1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = drm_of_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744 disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747 free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752 } 753 754 static void panel_simple_shutdown(struct device *dev) 755 { 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782 } 783 784 static void panel_simple_remove(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795 } 796 797 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808 }; 809 810 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821 }; 822 823 static const struct drm_display_mode ampire_am_1280800w8tzqw_t00h_mode = { 824 .clock = 72400, 825 .hdisplay = 1280, 826 .hsync_start = 1280 + 40, 827 .hsync_end = 1280 + 40 + 80, 828 .htotal = 1280 + 40 + 80 + 40, 829 .vdisplay = 800, 830 .vsync_start = 800 + 10, 831 .vsync_end = 800 + 10 + 18, 832 .vtotal = 800 + 10 + 18 + 10, 833 }; 834 835 static const struct panel_desc ampire_am_1280800w8tzqw_t00h = { 836 .modes = &ire_am_1280800w8tzqw_t00h_mode, 837 .num_modes = 1, 838 .bpc = 8, 839 .size = { 840 .width = 217, 841 .height = 136, 842 }, 843 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 845 .connector_type = DRM_MODE_CONNECTOR_LVDS, 846 }; 847 848 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 849 .clock = 9000, 850 .hdisplay = 480, 851 .hsync_start = 480 + 2, 852 .hsync_end = 480 + 2 + 41, 853 .htotal = 480 + 2 + 41 + 2, 854 .vdisplay = 272, 855 .vsync_start = 272 + 2, 856 .vsync_end = 272 + 2 + 10, 857 .vtotal = 272 + 2 + 10 + 2, 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 859 }; 860 861 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 862 .modes = &ire_am_480272h3tmqw_t01h_mode, 863 .num_modes = 1, 864 .bpc = 8, 865 .size = { 866 .width = 99, 867 .height = 58, 868 }, 869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 870 }; 871 872 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 873 .clock = 33333, 874 .hdisplay = 800, 875 .hsync_start = 800 + 0, 876 .hsync_end = 800 + 0 + 255, 877 .htotal = 800 + 0 + 255 + 0, 878 .vdisplay = 480, 879 .vsync_start = 480 + 2, 880 .vsync_end = 480 + 2 + 45, 881 .vtotal = 480 + 2 + 45 + 0, 882 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 883 }; 884 885 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 886 .pixelclock = { 29930000, 33260000, 36590000 }, 887 .hactive = { 800, 800, 800 }, 888 .hfront_porch = { 1, 40, 168 }, 889 .hback_porch = { 88, 88, 88 }, 890 .hsync_len = { 1, 128, 128 }, 891 .vactive = { 480, 480, 480 }, 892 .vfront_porch = { 1, 35, 37 }, 893 .vback_porch = { 8, 8, 8 }, 894 .vsync_len = { 1, 2, 2 }, 895 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 896 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 897 DISPLAY_FLAGS_SYNC_POSEDGE, 898 }; 899 900 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 901 .timings = &ire_am_800480l1tmqw_t00h_timing, 902 .num_timings = 1, 903 .bpc = 8, 904 .size = { 905 .width = 111, 906 .height = 67, 907 }, 908 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 909 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 910 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 911 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 912 .connector_type = DRM_MODE_CONNECTOR_DPI, 913 }; 914 915 static const struct display_timing ampire_am_800480n3tzqw_00h_timing = { 916 .pixelclock = {23000000, 25000000, 27000000}, 917 .hactive = { 800, 800, 800 }, 918 .hfront_porch = { 4, 8, 48 }, 919 .hback_porch = { 4, 8, 48 }, 920 .hsync_len = { 2, 8, 8 }, 921 .vactive = { 480, 480, 480 }, 922 .vfront_porch = { 4, 8, 12 }, 923 .vback_porch = { 4, 8, 12 }, 924 .vsync_len = { 2, 4, 8 }, 925 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 926 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 927 DISPLAY_FLAGS_SYNC_POSEDGE, 928 }; 929 930 static const struct panel_desc ampire_am_800480n3tzqw_00h = { 931 .timings = &ire_am_800480n3tzqw_00h_timing, 932 .num_timings = 1, 933 .bpc = 8, 934 .size = { 935 .width = 108, 936 .height = 65, 937 }, 938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 939 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 940 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 941 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 942 .connector_type = DRM_MODE_CONNECTOR_DPI, 943 }; 944 945 static const struct panel_desc ampire_am800480r3tmqwa1h = { 946 .modes = &ire_am800480r3tmqwa1h_mode, 947 .num_modes = 1, 948 .bpc = 6, 949 .size = { 950 .width = 152, 951 .height = 91, 952 }, 953 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 954 }; 955 956 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 957 .pixelclock = { 34500000, 39600000, 50400000 }, 958 .hactive = { 800, 800, 800 }, 959 .hfront_porch = { 12, 112, 312 }, 960 .hback_porch = { 87, 87, 48 }, 961 .hsync_len = { 1, 1, 40 }, 962 .vactive = { 600, 600, 600 }, 963 .vfront_porch = { 1, 21, 61 }, 964 .vback_porch = { 38, 38, 19 }, 965 .vsync_len = { 1, 1, 20 }, 966 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 967 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 968 DISPLAY_FLAGS_SYNC_POSEDGE, 969 }; 970 971 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 972 .timings = &ire_am800600p5tmqw_tb8h_timing, 973 .num_timings = 1, 974 .bpc = 6, 975 .size = { 976 .width = 162, 977 .height = 122, 978 }, 979 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 980 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 981 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 982 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 983 .connector_type = DRM_MODE_CONNECTOR_DPI, 984 }; 985 986 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 987 .pixelclock = { 26400000, 33300000, 46800000 }, 988 .hactive = { 800, 800, 800 }, 989 .hfront_porch = { 16, 210, 354 }, 990 .hback_porch = { 45, 36, 6 }, 991 .hsync_len = { 1, 10, 40 }, 992 .vactive = { 480, 480, 480 }, 993 .vfront_porch = { 7, 22, 147 }, 994 .vback_porch = { 22, 13, 3 }, 995 .vsync_len = { 1, 10, 20 }, 996 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 997 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 998 }; 999 1000 static const struct panel_desc armadeus_st0700_adapt = { 1001 .timings = &santek_st0700i5y_rbslw_f_timing, 1002 .num_timings = 1, 1003 .bpc = 6, 1004 .size = { 1005 .width = 154, 1006 .height = 86, 1007 }, 1008 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1010 }; 1011 1012 static const struct drm_display_mode auo_b101aw03_mode = { 1013 .clock = 51450, 1014 .hdisplay = 1024, 1015 .hsync_start = 1024 + 156, 1016 .hsync_end = 1024 + 156 + 8, 1017 .htotal = 1024 + 156 + 8 + 156, 1018 .vdisplay = 600, 1019 .vsync_start = 600 + 16, 1020 .vsync_end = 600 + 16 + 6, 1021 .vtotal = 600 + 16 + 6 + 16, 1022 }; 1023 1024 static const struct panel_desc auo_b101aw03 = { 1025 .modes = &auo_b101aw03_mode, 1026 .num_modes = 1, 1027 .bpc = 6, 1028 .size = { 1029 .width = 223, 1030 .height = 125, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1035 }; 1036 1037 static const struct drm_display_mode auo_b101xtn01_mode = { 1038 .clock = 72000, 1039 .hdisplay = 1366, 1040 .hsync_start = 1366 + 20, 1041 .hsync_end = 1366 + 20 + 70, 1042 .htotal = 1366 + 20 + 70, 1043 .vdisplay = 768, 1044 .vsync_start = 768 + 14, 1045 .vsync_end = 768 + 14 + 42, 1046 .vtotal = 768 + 14 + 42, 1047 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1048 }; 1049 1050 static const struct panel_desc auo_b101xtn01 = { 1051 .modes = &auo_b101xtn01_mode, 1052 .num_modes = 1, 1053 .bpc = 6, 1054 .size = { 1055 .width = 223, 1056 .height = 125, 1057 }, 1058 }; 1059 1060 static const struct drm_display_mode auo_b116xw03_mode = { 1061 .clock = 70589, 1062 .hdisplay = 1366, 1063 .hsync_start = 1366 + 40, 1064 .hsync_end = 1366 + 40 + 40, 1065 .htotal = 1366 + 40 + 40 + 32, 1066 .vdisplay = 768, 1067 .vsync_start = 768 + 10, 1068 .vsync_end = 768 + 10 + 12, 1069 .vtotal = 768 + 10 + 12 + 6, 1070 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1071 }; 1072 1073 static const struct panel_desc auo_b116xw03 = { 1074 .modes = &auo_b116xw03_mode, 1075 .num_modes = 1, 1076 .bpc = 6, 1077 .size = { 1078 .width = 256, 1079 .height = 144, 1080 }, 1081 .delay = { 1082 .prepare = 1, 1083 .enable = 200, 1084 .disable = 200, 1085 .unprepare = 500, 1086 }, 1087 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1088 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1089 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1090 }; 1091 1092 static const struct display_timing auo_g070vvn01_timings = { 1093 .pixelclock = { 33300000, 34209000, 45000000 }, 1094 .hactive = { 800, 800, 800 }, 1095 .hfront_porch = { 20, 40, 200 }, 1096 .hback_porch = { 87, 40, 1 }, 1097 .hsync_len = { 1, 48, 87 }, 1098 .vactive = { 480, 480, 480 }, 1099 .vfront_porch = { 5, 13, 200 }, 1100 .vback_porch = { 31, 31, 29 }, 1101 .vsync_len = { 1, 1, 3 }, 1102 }; 1103 1104 static const struct panel_desc auo_g070vvn01 = { 1105 .timings = &auo_g070vvn01_timings, 1106 .num_timings = 1, 1107 .bpc = 8, 1108 .size = { 1109 .width = 152, 1110 .height = 91, 1111 }, 1112 .delay = { 1113 .prepare = 200, 1114 .enable = 50, 1115 .disable = 50, 1116 .unprepare = 1000, 1117 }, 1118 }; 1119 1120 static const struct display_timing auo_g101evn010_timing = { 1121 .pixelclock = { 64000000, 68930000, 85000000 }, 1122 .hactive = { 1280, 1280, 1280 }, 1123 .hfront_porch = { 8, 64, 256 }, 1124 .hback_porch = { 8, 64, 256 }, 1125 .hsync_len = { 40, 168, 767 }, 1126 .vactive = { 800, 800, 800 }, 1127 .vfront_porch = { 4, 8, 100 }, 1128 .vback_porch = { 4, 8, 100 }, 1129 .vsync_len = { 8, 16, 223 }, 1130 }; 1131 1132 static const struct panel_desc auo_g101evn010 = { 1133 .timings = &auo_g101evn010_timing, 1134 .num_timings = 1, 1135 .bpc = 6, 1136 .size = { 1137 .width = 216, 1138 .height = 135, 1139 }, 1140 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1141 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1142 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1143 }; 1144 1145 static const struct drm_display_mode auo_g104sn02_mode = { 1146 .clock = 40000, 1147 .hdisplay = 800, 1148 .hsync_start = 800 + 40, 1149 .hsync_end = 800 + 40 + 216, 1150 .htotal = 800 + 40 + 216 + 128, 1151 .vdisplay = 600, 1152 .vsync_start = 600 + 10, 1153 .vsync_end = 600 + 10 + 35, 1154 .vtotal = 600 + 10 + 35 + 2, 1155 }; 1156 1157 static const struct panel_desc auo_g104sn02 = { 1158 .modes = &auo_g104sn02_mode, 1159 .num_modes = 1, 1160 .bpc = 8, 1161 .size = { 1162 .width = 211, 1163 .height = 158, 1164 }, 1165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1166 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1167 }; 1168 1169 static const struct drm_display_mode auo_g104stn01_mode = { 1170 .clock = 40000, 1171 .hdisplay = 800, 1172 .hsync_start = 800 + 40, 1173 .hsync_end = 800 + 40 + 88, 1174 .htotal = 800 + 40 + 88 + 128, 1175 .vdisplay = 600, 1176 .vsync_start = 600 + 1, 1177 .vsync_end = 600 + 1 + 23, 1178 .vtotal = 600 + 1 + 23 + 4, 1179 }; 1180 1181 static const struct panel_desc auo_g104stn01 = { 1182 .modes = &auo_g104stn01_mode, 1183 .num_modes = 1, 1184 .bpc = 8, 1185 .size = { 1186 .width = 211, 1187 .height = 158, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1191 }; 1192 1193 static const struct display_timing auo_g121ean01_timing = { 1194 .pixelclock = { 60000000, 74400000, 90000000 }, 1195 .hactive = { 1280, 1280, 1280 }, 1196 .hfront_porch = { 20, 50, 100 }, 1197 .hback_porch = { 20, 50, 100 }, 1198 .hsync_len = { 30, 100, 200 }, 1199 .vactive = { 800, 800, 800 }, 1200 .vfront_porch = { 2, 10, 25 }, 1201 .vback_porch = { 2, 10, 25 }, 1202 .vsync_len = { 4, 18, 50 }, 1203 }; 1204 1205 static const struct panel_desc auo_g121ean01 = { 1206 .timings = &auo_g121ean01_timing, 1207 .num_timings = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 261, 1211 .height = 163, 1212 }, 1213 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1214 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1215 }; 1216 1217 static const struct display_timing auo_g133han01_timings = { 1218 .pixelclock = { 134000000, 141200000, 149000000 }, 1219 .hactive = { 1920, 1920, 1920 }, 1220 .hfront_porch = { 39, 58, 77 }, 1221 .hback_porch = { 59, 88, 117 }, 1222 .hsync_len = { 28, 42, 56 }, 1223 .vactive = { 1080, 1080, 1080 }, 1224 .vfront_porch = { 3, 8, 11 }, 1225 .vback_porch = { 5, 14, 19 }, 1226 .vsync_len = { 4, 14, 19 }, 1227 }; 1228 1229 static const struct panel_desc auo_g133han01 = { 1230 .timings = &auo_g133han01_timings, 1231 .num_timings = 1, 1232 .bpc = 8, 1233 .size = { 1234 .width = 293, 1235 .height = 165, 1236 }, 1237 .delay = { 1238 .prepare = 200, 1239 .enable = 50, 1240 .disable = 50, 1241 .unprepare = 1000, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245 }; 1246 1247 static const struct display_timing auo_g156han04_timings = { 1248 .pixelclock = { 137000000, 141000000, 146000000 }, 1249 .hactive = { 1920, 1920, 1920 }, 1250 .hfront_porch = { 60, 60, 60 }, 1251 .hback_porch = { 90, 92, 111 }, 1252 .hsync_len = { 32, 32, 32 }, 1253 .vactive = { 1080, 1080, 1080 }, 1254 .vfront_porch = { 12, 12, 12 }, 1255 .vback_porch = { 24, 36, 56 }, 1256 .vsync_len = { 8, 8, 8 }, 1257 }; 1258 1259 static const struct panel_desc auo_g156han04 = { 1260 .timings = &auo_g156han04_timings, 1261 .num_timings = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 344, 1265 .height = 194, 1266 }, 1267 .delay = { 1268 .prepare = 50, /* T2 */ 1269 .enable = 200, /* T3 */ 1270 .disable = 110, /* T10 */ 1271 .unprepare = 1000, /* T13 */ 1272 }, 1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1274 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct drm_display_mode auo_g156xtn01_mode = { 1279 .clock = 76000, 1280 .hdisplay = 1366, 1281 .hsync_start = 1366 + 33, 1282 .hsync_end = 1366 + 33 + 67, 1283 .htotal = 1560, 1284 .vdisplay = 768, 1285 .vsync_start = 768 + 4, 1286 .vsync_end = 768 + 4 + 4, 1287 .vtotal = 806, 1288 }; 1289 1290 static const struct panel_desc auo_g156xtn01 = { 1291 .modes = &auo_g156xtn01_mode, 1292 .num_modes = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 344, 1296 .height = 194, 1297 }, 1298 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1299 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1300 }; 1301 1302 static const struct display_timing auo_g185han01_timings = { 1303 .pixelclock = { 120000000, 144000000, 175000000 }, 1304 .hactive = { 1920, 1920, 1920 }, 1305 .hfront_porch = { 36, 120, 148 }, 1306 .hback_porch = { 24, 88, 108 }, 1307 .hsync_len = { 20, 48, 64 }, 1308 .vactive = { 1080, 1080, 1080 }, 1309 .vfront_porch = { 6, 10, 40 }, 1310 .vback_porch = { 2, 5, 20 }, 1311 .vsync_len = { 2, 5, 20 }, 1312 }; 1313 1314 static const struct panel_desc auo_g185han01 = { 1315 .timings = &auo_g185han01_timings, 1316 .num_timings = 1, 1317 .bpc = 8, 1318 .size = { 1319 .width = 409, 1320 .height = 230, 1321 }, 1322 .delay = { 1323 .prepare = 50, 1324 .enable = 200, 1325 .disable = 110, 1326 .unprepare = 1000, 1327 }, 1328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1329 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1330 }; 1331 1332 static const struct display_timing auo_g190ean01_timings = { 1333 .pixelclock = { 90000000, 108000000, 135000000 }, 1334 .hactive = { 1280, 1280, 1280 }, 1335 .hfront_porch = { 126, 184, 1266 }, 1336 .hback_porch = { 84, 122, 844 }, 1337 .hsync_len = { 70, 102, 704 }, 1338 .vactive = { 1024, 1024, 1024 }, 1339 .vfront_porch = { 4, 26, 76 }, 1340 .vback_porch = { 2, 8, 25 }, 1341 .vsync_len = { 2, 8, 25 }, 1342 }; 1343 1344 static const struct panel_desc auo_g190ean01 = { 1345 .timings = &auo_g190ean01_timings, 1346 .num_timings = 1, 1347 .bpc = 8, 1348 .size = { 1349 .width = 376, 1350 .height = 301, 1351 }, 1352 .delay = { 1353 .prepare = 30, 1354 .enable = 200, 1355 .disable = 110, 1356 .unprepare = 1000, 1357 }, 1358 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1359 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1360 }; 1361 1362 static const struct display_timing auo_p238han01_timings = { 1363 .pixelclock = { 107400000, 142400000, 180000000 }, 1364 .hactive = { 1920, 1920, 1920 }, 1365 .hfront_porch = { 30, 70, 650 }, 1366 .hback_porch = { 30, 70, 650 }, 1367 .hsync_len = { 20, 40, 136 }, 1368 .vactive = { 1080, 1080, 1080 }, 1369 .vfront_porch = { 5, 19, 318 }, 1370 .vback_porch = { 5, 19, 318 }, 1371 .vsync_len = { 4, 12, 120 }, 1372 }; 1373 1374 static const struct panel_desc auo_p238han01 = { 1375 .timings = &auo_p238han01_timings, 1376 .num_timings = 1, 1377 .bpc = 8, 1378 .size = { 1379 .width = 527, 1380 .height = 296, 1381 }, 1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1383 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1384 }; 1385 1386 static const struct display_timing auo_p320hvn03_timings = { 1387 .pixelclock = { 106000000, 148500000, 164000000 }, 1388 .hactive = { 1920, 1920, 1920 }, 1389 .hfront_porch = { 25, 50, 130 }, 1390 .hback_porch = { 25, 50, 130 }, 1391 .hsync_len = { 20, 40, 105 }, 1392 .vactive = { 1080, 1080, 1080 }, 1393 .vfront_porch = { 8, 17, 150 }, 1394 .vback_porch = { 8, 17, 150 }, 1395 .vsync_len = { 4, 11, 100 }, 1396 }; 1397 1398 static const struct panel_desc auo_p320hvn03 = { 1399 .timings = &auo_p320hvn03_timings, 1400 .num_timings = 1, 1401 .bpc = 8, 1402 .size = { 1403 .width = 698, 1404 .height = 393, 1405 }, 1406 .delay = { 1407 .prepare = 1, 1408 .enable = 450, 1409 .unprepare = 500, 1410 }, 1411 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1412 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1413 }; 1414 1415 static const struct drm_display_mode auo_t215hvn01_mode = { 1416 .clock = 148800, 1417 .hdisplay = 1920, 1418 .hsync_start = 1920 + 88, 1419 .hsync_end = 1920 + 88 + 44, 1420 .htotal = 1920 + 88 + 44 + 148, 1421 .vdisplay = 1080, 1422 .vsync_start = 1080 + 4, 1423 .vsync_end = 1080 + 4 + 5, 1424 .vtotal = 1080 + 4 + 5 + 36, 1425 }; 1426 1427 static const struct panel_desc auo_t215hvn01 = { 1428 .modes = &auo_t215hvn01_mode, 1429 .num_modes = 1, 1430 .bpc = 8, 1431 .size = { 1432 .width = 430, 1433 .height = 270, 1434 }, 1435 .delay = { 1436 .disable = 5, 1437 .unprepare = 1000, 1438 }, 1439 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1440 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1441 }; 1442 1443 static const struct drm_display_mode avic_tm070ddh03_mode = { 1444 .clock = 51200, 1445 .hdisplay = 1024, 1446 .hsync_start = 1024 + 160, 1447 .hsync_end = 1024 + 160 + 4, 1448 .htotal = 1024 + 160 + 4 + 156, 1449 .vdisplay = 600, 1450 .vsync_start = 600 + 17, 1451 .vsync_end = 600 + 17 + 1, 1452 .vtotal = 600 + 17 + 1 + 17, 1453 }; 1454 1455 static const struct panel_desc avic_tm070ddh03 = { 1456 .modes = &avic_tm070ddh03_mode, 1457 .num_modes = 1, 1458 .bpc = 8, 1459 .size = { 1460 .width = 154, 1461 .height = 90, 1462 }, 1463 .delay = { 1464 .prepare = 20, 1465 .enable = 200, 1466 .disable = 200, 1467 }, 1468 }; 1469 1470 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1471 .clock = 30000, 1472 .hdisplay = 800, 1473 .hsync_start = 800 + 40, 1474 .hsync_end = 800 + 40 + 48, 1475 .htotal = 800 + 40 + 48 + 40, 1476 .vdisplay = 480, 1477 .vsync_start = 480 + 13, 1478 .vsync_end = 480 + 13 + 3, 1479 .vtotal = 480 + 13 + 3 + 29, 1480 }; 1481 1482 static const struct panel_desc bananapi_s070wv20_ct16 = { 1483 .modes = &bananapi_s070wv20_ct16_mode, 1484 .num_modes = 1, 1485 .bpc = 6, 1486 .size = { 1487 .width = 154, 1488 .height = 86, 1489 }, 1490 }; 1491 1492 static const struct display_timing boe_av101hdt_a10_timing = { 1493 .pixelclock = { 74210000, 75330000, 76780000, }, 1494 .hactive = { 1280, 1280, 1280, }, 1495 .hfront_porch = { 10, 42, 33, }, 1496 .hback_porch = { 10, 18, 33, }, 1497 .hsync_len = { 30, 10, 30, }, 1498 .vactive = { 720, 720, 720, }, 1499 .vfront_porch = { 200, 183, 200, }, 1500 .vback_porch = { 8, 8, 8, }, 1501 .vsync_len = { 2, 19, 2, }, 1502 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1503 }; 1504 1505 static const struct panel_desc boe_av101hdt_a10 = { 1506 .timings = &boe_av101hdt_a10_timing, 1507 .num_timings = 1, 1508 .bpc = 8, 1509 .size = { 1510 .width = 224, 1511 .height = 126, 1512 }, 1513 .delay = { 1514 .enable = 50, 1515 .disable = 50, 1516 }, 1517 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1518 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1519 }; 1520 1521 static const struct display_timing boe_av123z7m_n17_timing = { 1522 .pixelclock = { 86600000, 88000000, 90800000, }, 1523 .hactive = { 1920, 1920, 1920, }, 1524 .hfront_porch = { 10, 10, 10, }, 1525 .hback_porch = { 10, 10, 10, }, 1526 .hsync_len = { 9, 12, 25, }, 1527 .vactive = { 720, 720, 720, }, 1528 .vfront_porch = { 7, 10, 13, }, 1529 .vback_porch = { 7, 10, 13, }, 1530 .vsync_len = { 7, 11, 14, }, 1531 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1532 }; 1533 1534 static const struct panel_desc boe_av123z7m_n17 = { 1535 .timings = &boe_av123z7m_n17_timing, 1536 .bpc = 8, 1537 .num_timings = 1, 1538 .size = { 1539 .width = 292, 1540 .height = 110, 1541 }, 1542 .delay = { 1543 .prepare = 50, 1544 .disable = 50, 1545 }, 1546 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1547 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1548 }; 1549 1550 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1551 .clock = 78945, 1552 .hdisplay = 1280, 1553 .hsync_start = 1280 + 0, 1554 .hsync_end = 1280 + 0 + 2, 1555 .htotal = 1280 + 62 + 0 + 2, 1556 .vdisplay = 800, 1557 .vsync_start = 800 + 8, 1558 .vsync_end = 800 + 8 + 2, 1559 .vtotal = 800 + 6 + 8 + 2, 1560 }; 1561 1562 static const struct panel_desc boe_bp082wx1_100 = { 1563 .modes = &boe_bp101wx1_100_mode, 1564 .num_modes = 1, 1565 .bpc = 8, 1566 .size = { 1567 .width = 177, 1568 .height = 110, 1569 }, 1570 .delay = { 1571 .enable = 50, 1572 .disable = 50, 1573 }, 1574 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1575 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1577 }; 1578 1579 static const struct panel_desc boe_bp101wx1_100 = { 1580 .modes = &boe_bp101wx1_100_mode, 1581 .num_modes = 1, 1582 .bpc = 8, 1583 .size = { 1584 .width = 217, 1585 .height = 136, 1586 }, 1587 .delay = { 1588 .enable = 50, 1589 .disable = 50, 1590 }, 1591 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1592 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1593 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1594 }; 1595 1596 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1597 .pixelclock = { 69922000, 71000000, 72293000 }, 1598 .hactive = { 1280, 1280, 1280 }, 1599 .hfront_porch = { 48, 48, 48 }, 1600 .hback_porch = { 80, 80, 80 }, 1601 .hsync_len = { 32, 32, 32 }, 1602 .vactive = { 800, 800, 800 }, 1603 .vfront_porch = { 3, 3, 3 }, 1604 .vback_porch = { 14, 14, 14 }, 1605 .vsync_len = { 6, 6, 6 }, 1606 }; 1607 1608 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1609 .timings = &boe_ev121wxm_n10_1850_timing, 1610 .num_timings = 1, 1611 .bpc = 8, 1612 .size = { 1613 .width = 261, 1614 .height = 163, 1615 }, 1616 .delay = { 1617 .prepare = 9, 1618 .enable = 300, 1619 .unprepare = 300, 1620 .disable = 560, 1621 }, 1622 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1623 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1624 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1625 }; 1626 1627 static const struct drm_display_mode boe_hv070wsa_mode = { 1628 .clock = 42105, 1629 .hdisplay = 1024, 1630 .hsync_start = 1024 + 30, 1631 .hsync_end = 1024 + 30 + 30, 1632 .htotal = 1024 + 30 + 30 + 30, 1633 .vdisplay = 600, 1634 .vsync_start = 600 + 10, 1635 .vsync_end = 600 + 10 + 10, 1636 .vtotal = 600 + 10 + 10 + 10, 1637 }; 1638 1639 static const struct panel_desc boe_hv070wsa = { 1640 .modes = &boe_hv070wsa_mode, 1641 .num_modes = 1, 1642 .bpc = 8, 1643 .size = { 1644 .width = 154, 1645 .height = 90, 1646 }, 1647 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1648 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1649 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1650 }; 1651 1652 static const struct display_timing cct_cmt430b19n00_timing = { 1653 .pixelclock = { 8000000, 9000000, 12000000 }, 1654 .hactive = { 480, 480, 480 }, 1655 .hfront_porch = { 2, 8, 75 }, 1656 .hback_porch = { 3, 43, 43 }, 1657 .hsync_len = { 2, 4, 75 }, 1658 .vactive = { 272, 272, 272 }, 1659 .vfront_porch = { 2, 8, 37 }, 1660 .vback_porch = { 2, 12, 12 }, 1661 .vsync_len = { 2, 4, 37 }, 1662 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1663 }; 1664 1665 static const struct panel_desc cct_cmt430b19n00 = { 1666 .timings = &cct_cmt430b19n00_timing, 1667 .num_timings = 1, 1668 .bpc = 8, 1669 .size = { 1670 .width = 95, 1671 .height = 53, 1672 }, 1673 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1674 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1675 .connector_type = DRM_MODE_CONNECTOR_DPI, 1676 }; 1677 1678 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1679 .clock = 9000, 1680 .hdisplay = 480, 1681 .hsync_start = 480 + 5, 1682 .hsync_end = 480 + 5 + 5, 1683 .htotal = 480 + 5 + 5 + 40, 1684 .vdisplay = 272, 1685 .vsync_start = 272 + 8, 1686 .vsync_end = 272 + 8 + 8, 1687 .vtotal = 272 + 8 + 8 + 8, 1688 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1689 }; 1690 1691 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1692 .modes = &cdtech_s043wq26h_ct7_mode, 1693 .num_modes = 1, 1694 .bpc = 8, 1695 .size = { 1696 .width = 95, 1697 .height = 54, 1698 }, 1699 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1700 }; 1701 1702 /* S070PWS19HP-FC21 2017/04/22 */ 1703 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1704 .clock = 51200, 1705 .hdisplay = 1024, 1706 .hsync_start = 1024 + 160, 1707 .hsync_end = 1024 + 160 + 20, 1708 .htotal = 1024 + 160 + 20 + 140, 1709 .vdisplay = 600, 1710 .vsync_start = 600 + 12, 1711 .vsync_end = 600 + 12 + 3, 1712 .vtotal = 600 + 12 + 3 + 20, 1713 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1714 }; 1715 1716 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1717 .modes = &cdtech_s070pws19hp_fc21_mode, 1718 .num_modes = 1, 1719 .bpc = 6, 1720 .size = { 1721 .width = 154, 1722 .height = 86, 1723 }, 1724 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1725 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1726 .connector_type = DRM_MODE_CONNECTOR_DPI, 1727 }; 1728 1729 /* S070SWV29HG-DC44 2017/09/21 */ 1730 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1731 .clock = 33300, 1732 .hdisplay = 800, 1733 .hsync_start = 800 + 210, 1734 .hsync_end = 800 + 210 + 2, 1735 .htotal = 800 + 210 + 2 + 44, 1736 .vdisplay = 480, 1737 .vsync_start = 480 + 22, 1738 .vsync_end = 480 + 22 + 2, 1739 .vtotal = 480 + 22 + 2 + 21, 1740 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1741 }; 1742 1743 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1744 .modes = &cdtech_s070swv29hg_dc44_mode, 1745 .num_modes = 1, 1746 .bpc = 6, 1747 .size = { 1748 .width = 154, 1749 .height = 86, 1750 }, 1751 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1752 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1753 .connector_type = DRM_MODE_CONNECTOR_DPI, 1754 }; 1755 1756 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1757 .clock = 35000, 1758 .hdisplay = 800, 1759 .hsync_start = 800 + 40, 1760 .hsync_end = 800 + 40 + 40, 1761 .htotal = 800 + 40 + 40 + 48, 1762 .vdisplay = 480, 1763 .vsync_start = 480 + 29, 1764 .vsync_end = 480 + 29 + 13, 1765 .vtotal = 480 + 29 + 13 + 3, 1766 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1767 }; 1768 1769 static const struct panel_desc cdtech_s070wv95_ct16 = { 1770 .modes = &cdtech_s070wv95_ct16_mode, 1771 .num_modes = 1, 1772 .bpc = 8, 1773 .size = { 1774 .width = 154, 1775 .height = 85, 1776 }, 1777 }; 1778 1779 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1780 .pixelclock = { 68900000, 71100000, 73400000 }, 1781 .hactive = { 1280, 1280, 1280 }, 1782 .hfront_porch = { 65, 80, 95 }, 1783 .hback_porch = { 64, 79, 94 }, 1784 .hsync_len = { 1, 1, 1 }, 1785 .vactive = { 800, 800, 800 }, 1786 .vfront_porch = { 7, 11, 14 }, 1787 .vback_porch = { 7, 11, 14 }, 1788 .vsync_len = { 1, 1, 1 }, 1789 .flags = DISPLAY_FLAGS_DE_HIGH, 1790 }; 1791 1792 static const struct panel_desc chefree_ch101olhlwh_002 = { 1793 .timings = &chefree_ch101olhlwh_002_timing, 1794 .num_timings = 1, 1795 .bpc = 8, 1796 .size = { 1797 .width = 217, 1798 .height = 135, 1799 }, 1800 .delay = { 1801 .enable = 200, 1802 .disable = 200, 1803 }, 1804 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1805 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1806 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1807 }; 1808 1809 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1810 .clock = 66770, 1811 .hdisplay = 800, 1812 .hsync_start = 800 + 49, 1813 .hsync_end = 800 + 49 + 33, 1814 .htotal = 800 + 49 + 33 + 17, 1815 .vdisplay = 1280, 1816 .vsync_start = 1280 + 1, 1817 .vsync_end = 1280 + 1 + 7, 1818 .vtotal = 1280 + 1 + 7 + 15, 1819 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1820 }; 1821 1822 static const struct panel_desc chunghwa_claa070wp03xg = { 1823 .modes = &chunghwa_claa070wp03xg_mode, 1824 .num_modes = 1, 1825 .bpc = 6, 1826 .size = { 1827 .width = 94, 1828 .height = 150, 1829 }, 1830 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1831 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1832 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1833 }; 1834 1835 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1836 .clock = 72070, 1837 .hdisplay = 1366, 1838 .hsync_start = 1366 + 58, 1839 .hsync_end = 1366 + 58 + 58, 1840 .htotal = 1366 + 58 + 58 + 58, 1841 .vdisplay = 768, 1842 .vsync_start = 768 + 4, 1843 .vsync_end = 768 + 4 + 4, 1844 .vtotal = 768 + 4 + 4 + 4, 1845 }; 1846 1847 static const struct panel_desc chunghwa_claa101wa01a = { 1848 .modes = &chunghwa_claa101wa01a_mode, 1849 .num_modes = 1, 1850 .bpc = 6, 1851 .size = { 1852 .width = 220, 1853 .height = 120, 1854 }, 1855 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1856 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1857 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1858 }; 1859 1860 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1861 .clock = 69300, 1862 .hdisplay = 1366, 1863 .hsync_start = 1366 + 48, 1864 .hsync_end = 1366 + 48 + 32, 1865 .htotal = 1366 + 48 + 32 + 20, 1866 .vdisplay = 768, 1867 .vsync_start = 768 + 16, 1868 .vsync_end = 768 + 16 + 8, 1869 .vtotal = 768 + 16 + 8 + 16, 1870 }; 1871 1872 static const struct panel_desc chunghwa_claa101wb01 = { 1873 .modes = &chunghwa_claa101wb01_mode, 1874 .num_modes = 1, 1875 .bpc = 6, 1876 .size = { 1877 .width = 223, 1878 .height = 125, 1879 }, 1880 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1881 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1882 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1883 }; 1884 1885 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1886 .pixelclock = { 5000000, 9000000, 12000000 }, 1887 .hactive = { 480, 480, 480 }, 1888 .hfront_porch = { 12, 12, 12 }, 1889 .hback_porch = { 12, 12, 12 }, 1890 .hsync_len = { 21, 21, 21 }, 1891 .vactive = { 272, 272, 272 }, 1892 .vfront_porch = { 4, 4, 4 }, 1893 .vback_porch = { 4, 4, 4 }, 1894 .vsync_len = { 8, 8, 8 }, 1895 }; 1896 1897 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1898 .timings = &dataimage_fg040346dsswbg04_timing, 1899 .num_timings = 1, 1900 .bpc = 8, 1901 .size = { 1902 .width = 95, 1903 .height = 54, 1904 }, 1905 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1906 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1907 .connector_type = DRM_MODE_CONNECTOR_DPI, 1908 }; 1909 1910 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1911 .pixelclock = { 68900000, 71110000, 73400000 }, 1912 .hactive = { 1280, 1280, 1280 }, 1913 .vactive = { 800, 800, 800 }, 1914 .hback_porch = { 100, 100, 100 }, 1915 .hfront_porch = { 100, 100, 100 }, 1916 .vback_porch = { 5, 5, 5 }, 1917 .vfront_porch = { 5, 5, 5 }, 1918 .hsync_len = { 24, 24, 24 }, 1919 .vsync_len = { 3, 3, 3 }, 1920 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1921 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1922 }; 1923 1924 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1925 .timings = &dataimage_fg1001l0dsswmg01_timing, 1926 .num_timings = 1, 1927 .bpc = 8, 1928 .size = { 1929 .width = 217, 1930 .height = 136, 1931 }, 1932 }; 1933 1934 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1935 .clock = 33260, 1936 .hdisplay = 800, 1937 .hsync_start = 800 + 40, 1938 .hsync_end = 800 + 40 + 128, 1939 .htotal = 800 + 40 + 128 + 88, 1940 .vdisplay = 480, 1941 .vsync_start = 480 + 10, 1942 .vsync_end = 480 + 10 + 2, 1943 .vtotal = 480 + 10 + 2 + 33, 1944 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1945 }; 1946 1947 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1948 .modes = &dataimage_scf0700c48ggu18_mode, 1949 .num_modes = 1, 1950 .bpc = 8, 1951 .size = { 1952 .width = 152, 1953 .height = 91, 1954 }, 1955 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1956 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1957 .connector_type = DRM_MODE_CONNECTOR_DPI, 1958 }; 1959 1960 static const struct display_timing displaytech_dt050btft_pts_timing = { 1961 /* The TYP pixel clock are recalculated from tV * tH * 60 Hz */ 1962 .pixelclock = { 30000000, 33264000, 50000000 }, 1963 .hactive = { 800, 800, 800 }, 1964 .hfront_porch = { 16, 210, 354 }, 1965 /* Datasheet Figure 3 indicates, that tHPW is part of tHBP */ 1966 .hback_porch = { 41, 26, 6 }, 1967 .hsync_len = { 1, 20, 40 }, 1968 .vactive = { 480, 480, 480 }, 1969 .vfront_porch = { 7, 22, 147 }, 1970 /* Datasheet Figure 2 indicates, that tVPW is part of tVBP */ 1971 .vback_porch = { 22, 13, 3 }, 1972 .vsync_len = { 1, 10, 20 }, 1973 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1974 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1975 DISPLAY_FLAGS_SYNC_POSEDGE, 1976 }; 1977 1978 static const struct panel_desc displaytech_dt050btft_pts = { 1979 .timings = &displaytech_dt050btft_pts_timing, 1980 .num_timings = 1, 1981 .bpc = 8, 1982 .size = { 1983 .width = 108, 1984 .height = 65, 1985 }, 1986 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1987 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 1988 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 1989 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 1990 .connector_type = DRM_MODE_CONNECTOR_DPI, 1991 }; 1992 1993 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1994 .pixelclock = { 45000000, 51200000, 57000000 }, 1995 .hactive = { 1024, 1024, 1024 }, 1996 .hfront_porch = { 100, 106, 113 }, 1997 .hback_porch = { 100, 106, 113 }, 1998 .hsync_len = { 100, 108, 114 }, 1999 .vactive = { 600, 600, 600 }, 2000 .vfront_porch = { 8, 11, 15 }, 2001 .vback_porch = { 8, 11, 15 }, 2002 .vsync_len = { 9, 13, 15 }, 2003 .flags = DISPLAY_FLAGS_DE_HIGH, 2004 }; 2005 2006 static const struct panel_desc dlc_dlc0700yzg_1 = { 2007 .timings = &dlc_dlc0700yzg_1_timing, 2008 .num_timings = 1, 2009 .bpc = 6, 2010 .size = { 2011 .width = 154, 2012 .height = 86, 2013 }, 2014 .delay = { 2015 .prepare = 30, 2016 .enable = 200, 2017 .disable = 200, 2018 }, 2019 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2020 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2021 }; 2022 2023 static const struct display_timing dlc_dlc1010gig_timing = { 2024 .pixelclock = { 68900000, 71100000, 73400000 }, 2025 .hactive = { 1280, 1280, 1280 }, 2026 .hfront_porch = { 43, 53, 63 }, 2027 .hback_porch = { 43, 53, 63 }, 2028 .hsync_len = { 44, 54, 64 }, 2029 .vactive = { 800, 800, 800 }, 2030 .vfront_porch = { 5, 8, 11 }, 2031 .vback_porch = { 5, 8, 11 }, 2032 .vsync_len = { 5, 7, 11 }, 2033 .flags = DISPLAY_FLAGS_DE_HIGH, 2034 }; 2035 2036 static const struct panel_desc dlc_dlc1010gig = { 2037 .timings = &dlc_dlc1010gig_timing, 2038 .num_timings = 1, 2039 .bpc = 8, 2040 .size = { 2041 .width = 216, 2042 .height = 135, 2043 }, 2044 .delay = { 2045 .prepare = 60, 2046 .enable = 150, 2047 .disable = 100, 2048 .unprepare = 60, 2049 }, 2050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2052 }; 2053 2054 static const struct drm_display_mode edt_et035012dm6_mode = { 2055 .clock = 6500, 2056 .hdisplay = 320, 2057 .hsync_start = 320 + 20, 2058 .hsync_end = 320 + 20 + 30, 2059 .htotal = 320 + 20 + 68, 2060 .vdisplay = 240, 2061 .vsync_start = 240 + 4, 2062 .vsync_end = 240 + 4 + 4, 2063 .vtotal = 240 + 4 + 4 + 14, 2064 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2065 }; 2066 2067 static const struct panel_desc edt_et035012dm6 = { 2068 .modes = &edt_et035012dm6_mode, 2069 .num_modes = 1, 2070 .bpc = 8, 2071 .size = { 2072 .width = 70, 2073 .height = 52, 2074 }, 2075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2076 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2077 }; 2078 2079 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 2080 .clock = 6520, 2081 .hdisplay = 320, 2082 .hsync_start = 320 + 20, 2083 .hsync_end = 320 + 20 + 68, 2084 .htotal = 320 + 20 + 68, 2085 .vdisplay = 240, 2086 .vsync_start = 240 + 4, 2087 .vsync_end = 240 + 4 + 18, 2088 .vtotal = 240 + 4 + 18, 2089 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2090 }; 2091 2092 static const struct panel_desc edt_etm0350g0dh6 = { 2093 .modes = &edt_etm0350g0dh6_mode, 2094 .num_modes = 1, 2095 .bpc = 6, 2096 .size = { 2097 .width = 70, 2098 .height = 53, 2099 }, 2100 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2101 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2102 .connector_type = DRM_MODE_CONNECTOR_DPI, 2103 }; 2104 2105 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2106 .clock = 10870, 2107 .hdisplay = 480, 2108 .hsync_start = 480 + 8, 2109 .hsync_end = 480 + 8 + 4, 2110 .htotal = 480 + 8 + 4 + 41, 2111 2112 /* 2113 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2114 * fb_align 2115 */ 2116 2117 .vdisplay = 288, 2118 .vsync_start = 288 + 2, 2119 .vsync_end = 288 + 2 + 4, 2120 .vtotal = 288 + 2 + 4 + 10, 2121 }; 2122 2123 static const struct panel_desc edt_etm043080dh6gp = { 2124 .modes = &edt_etm043080dh6gp_mode, 2125 .num_modes = 1, 2126 .bpc = 8, 2127 .size = { 2128 .width = 100, 2129 .height = 65, 2130 }, 2131 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2132 .connector_type = DRM_MODE_CONNECTOR_DPI, 2133 }; 2134 2135 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2136 .clock = 9000, 2137 .hdisplay = 480, 2138 .hsync_start = 480 + 2, 2139 .hsync_end = 480 + 2 + 41, 2140 .htotal = 480 + 2 + 41 + 2, 2141 .vdisplay = 272, 2142 .vsync_start = 272 + 2, 2143 .vsync_end = 272 + 2 + 10, 2144 .vtotal = 272 + 2 + 10 + 2, 2145 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2146 }; 2147 2148 static const struct panel_desc edt_etm0430g0dh6 = { 2149 .modes = &edt_etm0430g0dh6_mode, 2150 .num_modes = 1, 2151 .bpc = 6, 2152 .size = { 2153 .width = 95, 2154 .height = 54, 2155 }, 2156 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2157 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2158 .connector_type = DRM_MODE_CONNECTOR_DPI, 2159 }; 2160 2161 static const struct drm_display_mode edt_et057090dhu_mode = { 2162 .clock = 25175, 2163 .hdisplay = 640, 2164 .hsync_start = 640 + 16, 2165 .hsync_end = 640 + 16 + 30, 2166 .htotal = 640 + 16 + 30 + 114, 2167 .vdisplay = 480, 2168 .vsync_start = 480 + 10, 2169 .vsync_end = 480 + 10 + 3, 2170 .vtotal = 480 + 10 + 3 + 32, 2171 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2172 }; 2173 2174 static const struct panel_desc edt_et057090dhu = { 2175 .modes = &edt_et057090dhu_mode, 2176 .num_modes = 1, 2177 .bpc = 6, 2178 .size = { 2179 .width = 115, 2180 .height = 86, 2181 }, 2182 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2183 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2184 .connector_type = DRM_MODE_CONNECTOR_DPI, 2185 }; 2186 2187 static const struct display_timing edt_et057023udba_timing = { 2188 .pixelclock = { 23200000, 24190000, 39640000 }, 2189 .hactive = { 640, 640, 640 }, 2190 .hfront_porch = { 20, 40, 200 }, 2191 .hback_porch = { 87, 40, 1 }, 2192 .hsync_len = { 1, 48, 87 }, 2193 .vactive = { 480, 480, 480 }, 2194 .vfront_porch = { 5, 13, 200 }, 2195 .vback_porch = { 31, 31, 29 }, 2196 .vsync_len = { 1, 1, 3 }, 2197 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2198 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2199 DISPLAY_FLAGS_SYNC_POSEDGE, 2200 }; 2201 2202 static const struct panel_desc edt_et057023udba = { 2203 .timings = &edt_et057023udba_timing, 2204 .num_timings = 1, 2205 .bpc = 8, 2206 .size = { 2207 .width = 115, 2208 .height = 86, 2209 }, 2210 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2211 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2212 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2213 .connector_type = DRM_MODE_CONNECTOR_DPI, 2214 }; 2215 2216 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2217 .clock = 33260, 2218 .hdisplay = 800, 2219 .hsync_start = 800 + 40, 2220 .hsync_end = 800 + 40 + 128, 2221 .htotal = 800 + 40 + 128 + 88, 2222 .vdisplay = 480, 2223 .vsync_start = 480 + 10, 2224 .vsync_end = 480 + 10 + 2, 2225 .vtotal = 480 + 10 + 2 + 33, 2226 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2227 }; 2228 2229 static const struct panel_desc edt_etm0700g0dh6 = { 2230 .modes = &edt_etm0700g0dh6_mode, 2231 .num_modes = 1, 2232 .bpc = 6, 2233 .size = { 2234 .width = 152, 2235 .height = 91, 2236 }, 2237 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2238 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2239 .connector_type = DRM_MODE_CONNECTOR_DPI, 2240 }; 2241 2242 static const struct panel_desc edt_etm0700g0bdh6 = { 2243 .modes = &edt_etm0700g0dh6_mode, 2244 .num_modes = 1, 2245 .bpc = 6, 2246 .size = { 2247 .width = 152, 2248 .height = 91, 2249 }, 2250 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2251 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2252 .connector_type = DRM_MODE_CONNECTOR_DPI, 2253 }; 2254 2255 static const struct display_timing edt_etml0700y5dha_timing = { 2256 .pixelclock = { 40800000, 51200000, 67200000 }, 2257 .hactive = { 1024, 1024, 1024 }, 2258 .hfront_porch = { 30, 106, 125 }, 2259 .hback_porch = { 30, 106, 125 }, 2260 .hsync_len = { 30, 108, 126 }, 2261 .vactive = { 600, 600, 600 }, 2262 .vfront_porch = { 3, 12, 67}, 2263 .vback_porch = { 3, 12, 67 }, 2264 .vsync_len = { 4, 11, 66 }, 2265 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2266 DISPLAY_FLAGS_DE_HIGH, 2267 }; 2268 2269 static const struct panel_desc edt_etml0700y5dha = { 2270 .timings = &edt_etml0700y5dha_timing, 2271 .num_timings = 1, 2272 .bpc = 8, 2273 .size = { 2274 .width = 155, 2275 .height = 86, 2276 }, 2277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2279 }; 2280 2281 static const struct display_timing edt_etml1010g3dra_timing = { 2282 .pixelclock = { 66300000, 72400000, 78900000 }, 2283 .hactive = { 1280, 1280, 1280 }, 2284 .hfront_porch = { 12, 72, 132 }, 2285 .hback_porch = { 86, 86, 86 }, 2286 .hsync_len = { 2, 2, 2 }, 2287 .vactive = { 800, 800, 800 }, 2288 .vfront_porch = { 1, 15, 49 }, 2289 .vback_porch = { 21, 21, 21 }, 2290 .vsync_len = { 2, 2, 2 }, 2291 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2292 DISPLAY_FLAGS_DE_HIGH, 2293 }; 2294 2295 static const struct panel_desc edt_etml1010g3dra = { 2296 .timings = &edt_etml1010g3dra_timing, 2297 .num_timings = 1, 2298 .bpc = 8, 2299 .size = { 2300 .width = 216, 2301 .height = 135, 2302 }, 2303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2304 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2305 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2306 }; 2307 2308 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2309 .clock = 25175, 2310 .hdisplay = 640, 2311 .hsync_start = 640, 2312 .hsync_end = 640 + 16, 2313 .htotal = 640 + 16 + 30 + 114, 2314 .vdisplay = 480, 2315 .vsync_start = 480 + 10, 2316 .vsync_end = 480 + 10 + 3, 2317 .vtotal = 480 + 10 + 3 + 35, 2318 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2319 }; 2320 2321 static const struct panel_desc edt_etmv570g2dhu = { 2322 .modes = &edt_etmv570g2dhu_mode, 2323 .num_modes = 1, 2324 .bpc = 6, 2325 .size = { 2326 .width = 115, 2327 .height = 86, 2328 }, 2329 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2330 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2331 .connector_type = DRM_MODE_CONNECTOR_DPI, 2332 }; 2333 2334 static const struct display_timing eink_vb3300_kca_timing = { 2335 .pixelclock = { 40000000, 40000000, 40000000 }, 2336 .hactive = { 334, 334, 334 }, 2337 .hfront_porch = { 1, 1, 1 }, 2338 .hback_porch = { 1, 1, 1 }, 2339 .hsync_len = { 1, 1, 1 }, 2340 .vactive = { 1405, 1405, 1405 }, 2341 .vfront_porch = { 1, 1, 1 }, 2342 .vback_porch = { 1, 1, 1 }, 2343 .vsync_len = { 1, 1, 1 }, 2344 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2345 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2346 }; 2347 2348 static const struct panel_desc eink_vb3300_kca = { 2349 .timings = &eink_vb3300_kca_timing, 2350 .num_timings = 1, 2351 .bpc = 6, 2352 .size = { 2353 .width = 157, 2354 .height = 209, 2355 }, 2356 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2357 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2358 .connector_type = DRM_MODE_CONNECTOR_DPI, 2359 }; 2360 2361 static const struct display_timing evervision_vgg644804_timing = { 2362 .pixelclock = { 25175000, 25175000, 25175000 }, 2363 .hactive = { 640, 640, 640 }, 2364 .hfront_porch = { 16, 16, 16 }, 2365 .hback_porch = { 82, 114, 170 }, 2366 .hsync_len = { 5, 30, 30 }, 2367 .vactive = { 480, 480, 480 }, 2368 .vfront_porch = { 10, 10, 10 }, 2369 .vback_porch = { 30, 32, 34 }, 2370 .vsync_len = { 1, 3, 5 }, 2371 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2372 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2373 DISPLAY_FLAGS_SYNC_POSEDGE, 2374 }; 2375 2376 static const struct panel_desc evervision_vgg644804 = { 2377 .timings = &evervision_vgg644804_timing, 2378 .num_timings = 1, 2379 .bpc = 6, 2380 .size = { 2381 .width = 115, 2382 .height = 86, 2383 }, 2384 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2385 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2386 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2387 }; 2388 2389 static const struct display_timing evervision_vgg804821_timing = { 2390 .pixelclock = { 27600000, 33300000, 50000000 }, 2391 .hactive = { 800, 800, 800 }, 2392 .hfront_porch = { 40, 66, 70 }, 2393 .hback_porch = { 40, 67, 70 }, 2394 .hsync_len = { 40, 67, 70 }, 2395 .vactive = { 480, 480, 480 }, 2396 .vfront_porch = { 6, 10, 10 }, 2397 .vback_porch = { 7, 11, 11 }, 2398 .vsync_len = { 7, 11, 11 }, 2399 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2400 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2401 DISPLAY_FLAGS_SYNC_NEGEDGE, 2402 }; 2403 2404 static const struct panel_desc evervision_vgg804821 = { 2405 .timings = &evervision_vgg804821_timing, 2406 .num_timings = 1, 2407 .bpc = 8, 2408 .size = { 2409 .width = 108, 2410 .height = 64, 2411 }, 2412 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2413 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2414 }; 2415 2416 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2417 .clock = 32260, 2418 .hdisplay = 800, 2419 .hsync_start = 800 + 168, 2420 .hsync_end = 800 + 168 + 64, 2421 .htotal = 800 + 168 + 64 + 88, 2422 .vdisplay = 480, 2423 .vsync_start = 480 + 37, 2424 .vsync_end = 480 + 37 + 2, 2425 .vtotal = 480 + 37 + 2 + 8, 2426 }; 2427 2428 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2429 .modes = &foxlink_fl500wvr00_a0t_mode, 2430 .num_modes = 1, 2431 .bpc = 8, 2432 .size = { 2433 .width = 108, 2434 .height = 65, 2435 }, 2436 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2437 }; 2438 2439 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2440 { /* 60 Hz */ 2441 .clock = 6000, 2442 .hdisplay = 320, 2443 .hsync_start = 320 + 44, 2444 .hsync_end = 320 + 44 + 16, 2445 .htotal = 320 + 44 + 16 + 20, 2446 .vdisplay = 240, 2447 .vsync_start = 240 + 2, 2448 .vsync_end = 240 + 2 + 6, 2449 .vtotal = 240 + 2 + 6 + 2, 2450 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2451 }, 2452 { /* 50 Hz */ 2453 .clock = 5400, 2454 .hdisplay = 320, 2455 .hsync_start = 320 + 56, 2456 .hsync_end = 320 + 56 + 16, 2457 .htotal = 320 + 56 + 16 + 40, 2458 .vdisplay = 240, 2459 .vsync_start = 240 + 2, 2460 .vsync_end = 240 + 2 + 6, 2461 .vtotal = 240 + 2 + 6 + 2, 2462 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2463 }, 2464 }; 2465 2466 static const struct panel_desc frida_frd350h54004 = { 2467 .modes = frida_frd350h54004_modes, 2468 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2469 .bpc = 8, 2470 .size = { 2471 .width = 77, 2472 .height = 64, 2473 }, 2474 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2475 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2476 .connector_type = DRM_MODE_CONNECTOR_DPI, 2477 }; 2478 2479 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2480 .clock = 9000, 2481 .hdisplay = 480, 2482 .hsync_start = 480 + 5, 2483 .hsync_end = 480 + 5 + 1, 2484 .htotal = 480 + 5 + 1 + 40, 2485 .vdisplay = 272, 2486 .vsync_start = 272 + 8, 2487 .vsync_end = 272 + 8 + 1, 2488 .vtotal = 272 + 8 + 1 + 8, 2489 }; 2490 2491 static const struct panel_desc giantplus_gpg482739qs5 = { 2492 .modes = &giantplus_gpg482739qs5_mode, 2493 .num_modes = 1, 2494 .bpc = 8, 2495 .size = { 2496 .width = 95, 2497 .height = 54, 2498 }, 2499 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2500 }; 2501 2502 static const struct display_timing giantplus_gpm940b0_timing = { 2503 .pixelclock = { 13500000, 27000000, 27500000 }, 2504 .hactive = { 320, 320, 320 }, 2505 .hfront_porch = { 14, 686, 718 }, 2506 .hback_porch = { 50, 70, 255 }, 2507 .hsync_len = { 1, 1, 1 }, 2508 .vactive = { 240, 240, 240 }, 2509 .vfront_porch = { 1, 1, 179 }, 2510 .vback_porch = { 1, 21, 31 }, 2511 .vsync_len = { 1, 1, 6 }, 2512 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2513 }; 2514 2515 static const struct panel_desc giantplus_gpm940b0 = { 2516 .timings = &giantplus_gpm940b0_timing, 2517 .num_timings = 1, 2518 .bpc = 8, 2519 .size = { 2520 .width = 60, 2521 .height = 45, 2522 }, 2523 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2524 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2525 }; 2526 2527 static const struct display_timing hannstar_hsd070pww1_timing = { 2528 .pixelclock = { 64300000, 71100000, 82000000 }, 2529 .hactive = { 1280, 1280, 1280 }, 2530 .hfront_porch = { 1, 1, 10 }, 2531 .hback_porch = { 1, 1, 10 }, 2532 /* 2533 * According to the data sheet, the minimum horizontal blanking interval 2534 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2535 * minimum working horizontal blanking interval to be 60 clocks. 2536 */ 2537 .hsync_len = { 58, 158, 661 }, 2538 .vactive = { 800, 800, 800 }, 2539 .vfront_porch = { 1, 1, 10 }, 2540 .vback_porch = { 1, 1, 10 }, 2541 .vsync_len = { 1, 21, 203 }, 2542 .flags = DISPLAY_FLAGS_DE_HIGH, 2543 }; 2544 2545 static const struct panel_desc hannstar_hsd070pww1 = { 2546 .timings = &hannstar_hsd070pww1_timing, 2547 .num_timings = 1, 2548 .bpc = 6, 2549 .size = { 2550 .width = 151, 2551 .height = 94, 2552 }, 2553 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2554 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2555 }; 2556 2557 static const struct display_timing hannstar_hsd100pxn1_timing = { 2558 .pixelclock = { 55000000, 65000000, 75000000 }, 2559 .hactive = { 1024, 1024, 1024 }, 2560 .hfront_porch = { 40, 40, 40 }, 2561 .hback_porch = { 220, 220, 220 }, 2562 .hsync_len = { 20, 60, 100 }, 2563 .vactive = { 768, 768, 768 }, 2564 .vfront_porch = { 7, 7, 7 }, 2565 .vback_porch = { 21, 21, 21 }, 2566 .vsync_len = { 10, 10, 10 }, 2567 .flags = DISPLAY_FLAGS_DE_HIGH, 2568 }; 2569 2570 static const struct panel_desc hannstar_hsd100pxn1 = { 2571 .timings = &hannstar_hsd100pxn1_timing, 2572 .num_timings = 1, 2573 .bpc = 6, 2574 .size = { 2575 .width = 203, 2576 .height = 152, 2577 }, 2578 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2579 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2580 }; 2581 2582 static const struct display_timing hannstar_hsd101pww2_timing = { 2583 .pixelclock = { 64300000, 71100000, 82000000 }, 2584 .hactive = { 1280, 1280, 1280 }, 2585 .hfront_porch = { 1, 1, 10 }, 2586 .hback_porch = { 1, 1, 10 }, 2587 .hsync_len = { 58, 158, 661 }, 2588 .vactive = { 800, 800, 800 }, 2589 .vfront_porch = { 1, 1, 10 }, 2590 .vback_porch = { 1, 1, 10 }, 2591 .vsync_len = { 1, 21, 203 }, 2592 .flags = DISPLAY_FLAGS_DE_HIGH, 2593 }; 2594 2595 static const struct panel_desc hannstar_hsd101pww2 = { 2596 .timings = &hannstar_hsd101pww2_timing, 2597 .num_timings = 1, 2598 .bpc = 8, 2599 .size = { 2600 .width = 217, 2601 .height = 136, 2602 }, 2603 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2604 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2605 }; 2606 2607 static const struct display_timing hannstar_hsd156juw2_timing = { 2608 .pixelclock = { 66000000, 72800000, 80500000 }, 2609 .hactive = { 1920, 1920, 1920 }, 2610 .hfront_porch = { 20, 30, 30 }, 2611 .hback_porch = { 20, 30, 30 }, 2612 .hsync_len = { 50, 60, 90 }, 2613 .vactive = { 1080, 1080, 1080 }, 2614 .vfront_porch = { 1, 2, 4 }, 2615 .vback_porch = { 1, 2, 4 }, 2616 .vsync_len = { 3, 40, 80 }, 2617 .flags = DISPLAY_FLAGS_DE_HIGH, 2618 }; 2619 2620 static const struct panel_desc hannstar_hsd156juw2 = { 2621 .timings = &hannstar_hsd156juw2_timing, 2622 .num_timings = 1, 2623 .bpc = 8, 2624 .size = { 2625 .width = 344, 2626 .height = 194, 2627 }, 2628 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2629 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2630 }; 2631 2632 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2633 .clock = 33333, 2634 .hdisplay = 800, 2635 .hsync_start = 800 + 85, 2636 .hsync_end = 800 + 85 + 86, 2637 .htotal = 800 + 85 + 86 + 85, 2638 .vdisplay = 480, 2639 .vsync_start = 480 + 16, 2640 .vsync_end = 480 + 16 + 13, 2641 .vtotal = 480 + 16 + 13 + 16, 2642 }; 2643 2644 static const struct panel_desc hitachi_tx23d38vm0caa = { 2645 .modes = &hitachi_tx23d38vm0caa_mode, 2646 .num_modes = 1, 2647 .bpc = 6, 2648 .size = { 2649 .width = 195, 2650 .height = 117, 2651 }, 2652 .delay = { 2653 .enable = 160, 2654 .disable = 160, 2655 }, 2656 }; 2657 2658 static const struct drm_display_mode innolux_at043tn24_mode = { 2659 .clock = 9000, 2660 .hdisplay = 480, 2661 .hsync_start = 480 + 2, 2662 .hsync_end = 480 + 2 + 41, 2663 .htotal = 480 + 2 + 41 + 2, 2664 .vdisplay = 272, 2665 .vsync_start = 272 + 2, 2666 .vsync_end = 272 + 2 + 10, 2667 .vtotal = 272 + 2 + 10 + 2, 2668 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2669 }; 2670 2671 static const struct panel_desc innolux_at043tn24 = { 2672 .modes = &innolux_at043tn24_mode, 2673 .num_modes = 1, 2674 .bpc = 8, 2675 .size = { 2676 .width = 95, 2677 .height = 54, 2678 }, 2679 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2680 .connector_type = DRM_MODE_CONNECTOR_DPI, 2681 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2682 }; 2683 2684 static const struct drm_display_mode innolux_at070tn92_mode = { 2685 .clock = 33333, 2686 .hdisplay = 800, 2687 .hsync_start = 800 + 210, 2688 .hsync_end = 800 + 210 + 20, 2689 .htotal = 800 + 210 + 20 + 46, 2690 .vdisplay = 480, 2691 .vsync_start = 480 + 22, 2692 .vsync_end = 480 + 22 + 10, 2693 .vtotal = 480 + 22 + 23 + 10, 2694 }; 2695 2696 static const struct panel_desc innolux_at070tn92 = { 2697 .modes = &innolux_at070tn92_mode, 2698 .num_modes = 1, 2699 .size = { 2700 .width = 154, 2701 .height = 86, 2702 }, 2703 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2704 }; 2705 2706 static const struct display_timing innolux_g070ace_l01_timing = { 2707 .pixelclock = { 25200000, 35000000, 35700000 }, 2708 .hactive = { 800, 800, 800 }, 2709 .hfront_porch = { 30, 32, 87 }, 2710 .hback_porch = { 30, 32, 87 }, 2711 .hsync_len = { 1, 1, 1 }, 2712 .vactive = { 480, 480, 480 }, 2713 .vfront_porch = { 3, 3, 3 }, 2714 .vback_porch = { 13, 13, 13 }, 2715 .vsync_len = { 1, 1, 4 }, 2716 .flags = DISPLAY_FLAGS_DE_HIGH, 2717 }; 2718 2719 static const struct panel_desc innolux_g070ace_l01 = { 2720 .timings = &innolux_g070ace_l01_timing, 2721 .num_timings = 1, 2722 .bpc = 8, 2723 .size = { 2724 .width = 152, 2725 .height = 91, 2726 }, 2727 .delay = { 2728 .prepare = 10, 2729 .enable = 50, 2730 .disable = 50, 2731 .unprepare = 500, 2732 }, 2733 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2734 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2735 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2736 }; 2737 2738 static const struct display_timing innolux_g070y2_l01_timing = { 2739 .pixelclock = { 28000000, 29500000, 32000000 }, 2740 .hactive = { 800, 800, 800 }, 2741 .hfront_porch = { 61, 91, 141 }, 2742 .hback_porch = { 60, 90, 140 }, 2743 .hsync_len = { 12, 12, 12 }, 2744 .vactive = { 480, 480, 480 }, 2745 .vfront_porch = { 4, 9, 30 }, 2746 .vback_porch = { 4, 8, 28 }, 2747 .vsync_len = { 2, 2, 2 }, 2748 .flags = DISPLAY_FLAGS_DE_HIGH, 2749 }; 2750 2751 static const struct panel_desc innolux_g070y2_l01 = { 2752 .timings = &innolux_g070y2_l01_timing, 2753 .num_timings = 1, 2754 .bpc = 8, 2755 .size = { 2756 .width = 152, 2757 .height = 91, 2758 }, 2759 .delay = { 2760 .prepare = 10, 2761 .enable = 100, 2762 .disable = 100, 2763 .unprepare = 800, 2764 }, 2765 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2766 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2767 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2768 }; 2769 2770 static const struct display_timing innolux_g070ace_lh3_timing = { 2771 .pixelclock = { 25200000, 25400000, 35700000 }, 2772 .hactive = { 800, 800, 800 }, 2773 .hfront_porch = { 30, 32, 87 }, 2774 .hback_porch = { 29, 31, 86 }, 2775 .hsync_len = { 1, 1, 1 }, 2776 .vactive = { 480, 480, 480 }, 2777 .vfront_porch = { 4, 5, 65 }, 2778 .vback_porch = { 3, 4, 65 }, 2779 .vsync_len = { 1, 1, 1 }, 2780 .flags = DISPLAY_FLAGS_DE_HIGH, 2781 }; 2782 2783 static const struct panel_desc innolux_g070ace_lh3 = { 2784 .timings = &innolux_g070ace_lh3_timing, 2785 .num_timings = 1, 2786 .bpc = 8, 2787 .size = { 2788 .width = 152, 2789 .height = 91, 2790 }, 2791 .delay = { 2792 .prepare = 10, 2793 .enable = 450, 2794 .disable = 200, 2795 .unprepare = 510, 2796 }, 2797 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2798 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2799 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2800 }; 2801 2802 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2803 .clock = 33333, 2804 .hdisplay = 800, 2805 .hsync_start = 800 + 210, 2806 .hsync_end = 800 + 210 + 20, 2807 .htotal = 800 + 210 + 20 + 46, 2808 .vdisplay = 480, 2809 .vsync_start = 480 + 22, 2810 .vsync_end = 480 + 22 + 10, 2811 .vtotal = 480 + 22 + 23 + 10, 2812 }; 2813 2814 static const struct panel_desc innolux_g070y2_t02 = { 2815 .modes = &innolux_g070y2_t02_mode, 2816 .num_modes = 1, 2817 .bpc = 8, 2818 .size = { 2819 .width = 152, 2820 .height = 92, 2821 }, 2822 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2823 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2824 .connector_type = DRM_MODE_CONNECTOR_DPI, 2825 }; 2826 2827 static const struct display_timing innolux_g101ice_l01_timing = { 2828 .pixelclock = { 60400000, 71100000, 74700000 }, 2829 .hactive = { 1280, 1280, 1280 }, 2830 .hfront_porch = { 30, 60, 70 }, 2831 .hback_porch = { 30, 60, 70 }, 2832 .hsync_len = { 22, 40, 60 }, 2833 .vactive = { 800, 800, 800 }, 2834 .vfront_porch = { 3, 8, 14 }, 2835 .vback_porch = { 3, 8, 14 }, 2836 .vsync_len = { 4, 7, 12 }, 2837 .flags = DISPLAY_FLAGS_DE_HIGH, 2838 }; 2839 2840 static const struct panel_desc innolux_g101ice_l01 = { 2841 .timings = &innolux_g101ice_l01_timing, 2842 .num_timings = 1, 2843 .bpc = 8, 2844 .size = { 2845 .width = 217, 2846 .height = 135, 2847 }, 2848 .delay = { 2849 .enable = 200, 2850 .disable = 200, 2851 }, 2852 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2853 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2854 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2855 }; 2856 2857 static const struct display_timing innolux_g121i1_l01_timing = { 2858 .pixelclock = { 67450000, 71000000, 74550000 }, 2859 .hactive = { 1280, 1280, 1280 }, 2860 .hfront_porch = { 40, 80, 160 }, 2861 .hback_porch = { 39, 79, 159 }, 2862 .hsync_len = { 1, 1, 1 }, 2863 .vactive = { 800, 800, 800 }, 2864 .vfront_porch = { 5, 11, 100 }, 2865 .vback_porch = { 4, 11, 99 }, 2866 .vsync_len = { 1, 1, 1 }, 2867 }; 2868 2869 static const struct panel_desc innolux_g121i1_l01 = { 2870 .timings = &innolux_g121i1_l01_timing, 2871 .num_timings = 1, 2872 .bpc = 6, 2873 .size = { 2874 .width = 261, 2875 .height = 163, 2876 }, 2877 .delay = { 2878 .enable = 200, 2879 .disable = 20, 2880 }, 2881 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2882 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2883 }; 2884 2885 static const struct display_timing innolux_g121x1_l03_timings = { 2886 .pixelclock = { 57500000, 64900000, 74400000 }, 2887 .hactive = { 1024, 1024, 1024 }, 2888 .hfront_porch = { 90, 140, 190 }, 2889 .hback_porch = { 90, 140, 190 }, 2890 .hsync_len = { 36, 40, 60 }, 2891 .vactive = { 768, 768, 768 }, 2892 .vfront_porch = { 2, 15, 30 }, 2893 .vback_porch = { 2, 15, 30 }, 2894 .vsync_len = { 2, 8, 20 }, 2895 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2896 }; 2897 2898 static const struct panel_desc innolux_g121x1_l03 = { 2899 .timings = &innolux_g121x1_l03_timings, 2900 .num_timings = 1, 2901 .bpc = 6, 2902 .size = { 2903 .width = 246, 2904 .height = 185, 2905 }, 2906 .delay = { 2907 .enable = 200, 2908 .unprepare = 200, 2909 .disable = 400, 2910 }, 2911 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2912 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2913 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2914 }; 2915 2916 static const struct panel_desc innolux_g121xce_l01 = { 2917 .timings = &innolux_g121x1_l03_timings, 2918 .num_timings = 1, 2919 .bpc = 8, 2920 .size = { 2921 .width = 246, 2922 .height = 185, 2923 }, 2924 .delay = { 2925 .enable = 200, 2926 .unprepare = 200, 2927 .disable = 400, 2928 }, 2929 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2930 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2931 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2932 }; 2933 2934 static const struct display_timing innolux_g150xge_l05_timing = { 2935 .pixelclock = { 53350000, 65000000, 80000000 }, 2936 .hactive = { 1024, 1024, 1024 }, 2937 .hfront_porch = { 58, 160, 288 }, 2938 .hback_porch = { 58, 160, 288 }, 2939 .hsync_len = { 1, 1, 1 }, 2940 .vactive = { 768, 768, 768 }, 2941 .vfront_porch = { 6, 19, 216 }, 2942 .vback_porch = { 6, 19, 216 }, 2943 .vsync_len = { 1, 1, 1 }, 2944 .flags = DISPLAY_FLAGS_DE_HIGH, 2945 }; 2946 2947 static const struct panel_desc innolux_g150xge_l05 = { 2948 .timings = &innolux_g150xge_l05_timing, 2949 .num_timings = 1, 2950 .bpc = 8, 2951 .size = { 2952 .width = 304, 2953 .height = 228, 2954 }, 2955 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2956 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2957 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2958 }; 2959 2960 static const struct display_timing innolux_g156hce_l01_timings = { 2961 .pixelclock = { 120000000, 141860000, 150000000 }, 2962 .hactive = { 1920, 1920, 1920 }, 2963 .hfront_porch = { 80, 90, 100 }, 2964 .hback_porch = { 80, 90, 100 }, 2965 .hsync_len = { 20, 30, 30 }, 2966 .vactive = { 1080, 1080, 1080 }, 2967 .vfront_porch = { 3, 10, 20 }, 2968 .vback_porch = { 3, 10, 20 }, 2969 .vsync_len = { 4, 10, 10 }, 2970 }; 2971 2972 static const struct panel_desc innolux_g156hce_l01 = { 2973 .timings = &innolux_g156hce_l01_timings, 2974 .num_timings = 1, 2975 .bpc = 8, 2976 .size = { 2977 .width = 344, 2978 .height = 194, 2979 }, 2980 .delay = { 2981 .prepare = 1, /* T1+T2 */ 2982 .enable = 450, /* T5 */ 2983 .disable = 200, /* T6 */ 2984 .unprepare = 10, /* T3+T7 */ 2985 }, 2986 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2987 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2988 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2989 }; 2990 2991 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2992 .clock = 69300, 2993 .hdisplay = 1366, 2994 .hsync_start = 1366 + 16, 2995 .hsync_end = 1366 + 16 + 34, 2996 .htotal = 1366 + 16 + 34 + 50, 2997 .vdisplay = 768, 2998 .vsync_start = 768 + 2, 2999 .vsync_end = 768 + 2 + 6, 3000 .vtotal = 768 + 2 + 6 + 12, 3001 }; 3002 3003 static const struct panel_desc innolux_n156bge_l21 = { 3004 .modes = &innolux_n156bge_l21_mode, 3005 .num_modes = 1, 3006 .bpc = 6, 3007 .size = { 3008 .width = 344, 3009 .height = 193, 3010 }, 3011 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3012 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3013 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3014 }; 3015 3016 static const struct drm_display_mode innolux_zj070na_01p_mode = { 3017 .clock = 51501, 3018 .hdisplay = 1024, 3019 .hsync_start = 1024 + 128, 3020 .hsync_end = 1024 + 128 + 64, 3021 .htotal = 1024 + 128 + 64 + 128, 3022 .vdisplay = 600, 3023 .vsync_start = 600 + 16, 3024 .vsync_end = 600 + 16 + 4, 3025 .vtotal = 600 + 16 + 4 + 16, 3026 }; 3027 3028 static const struct panel_desc innolux_zj070na_01p = { 3029 .modes = &innolux_zj070na_01p_mode, 3030 .num_modes = 1, 3031 .bpc = 6, 3032 .size = { 3033 .width = 154, 3034 .height = 90, 3035 }, 3036 }; 3037 3038 static const struct display_timing jutouch_jt070tm041_timing = { 3039 .pixelclock = { 40800000, 51200000, 67200000 }, 3040 .hactive = { 1024, 1024, 1024 }, 3041 .hfront_porch = { 16, 160, 216 }, 3042 .hback_porch = { 160, 160, 160 }, 3043 .hsync_len = { 1, 1, 140 }, 3044 .vactive = { 600, 600, 600 }, 3045 .vfront_porch = { 1, 12, 127 }, 3046 .vback_porch = { 23, 23, 23 }, 3047 .vsync_len = { 1, 1, 20 }, 3048 }; 3049 3050 static const struct panel_desc jutouch_jt070tm041 = { 3051 .timings = &jutouch_jt070tm041_timing, 3052 .num_timings = 1, 3053 .bpc = 8, 3054 .size = { 3055 .width = 154, 3056 .height = 86, 3057 }, 3058 .delay = { 3059 .enable = 50, 3060 .disable = 50, 3061 }, 3062 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3063 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3064 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3065 }; 3066 3067 static const struct display_timing jutouch_jt101tm023_timing = { 3068 .pixelclock = { 66300000, 72400000, 78900000 }, 3069 .hactive = { 1280, 1280, 1280 }, 3070 .hfront_porch = { 12, 72, 132 }, 3071 .hback_porch = { 88, 88, 88 }, 3072 .hsync_len = { 10, 10, 48 }, 3073 .vactive = { 800, 800, 800 }, 3074 .vfront_porch = { 1, 15, 49 }, 3075 .vback_porch = { 23, 23, 23 }, 3076 .vsync_len = { 5, 6, 13 }, 3077 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3078 DISPLAY_FLAGS_DE_HIGH, 3079 }; 3080 3081 static const struct panel_desc jutouch_jt101tm023 = { 3082 .timings = &jutouch_jt101tm023_timing, 3083 .num_timings = 1, 3084 .bpc = 8, 3085 .size = { 3086 .width = 217, 3087 .height = 136, 3088 }, 3089 .delay = { 3090 .enable = 50, 3091 .disable = 50, 3092 }, 3093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3094 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3095 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3096 }; 3097 3098 3099 static const struct display_timing koe_tx14d24vm1bpa_timing = { 3100 .pixelclock = { 5580000, 5850000, 6200000 }, 3101 .hactive = { 320, 320, 320 }, 3102 .hfront_porch = { 30, 30, 30 }, 3103 .hback_porch = { 30, 30, 30 }, 3104 .hsync_len = { 1, 5, 17 }, 3105 .vactive = { 240, 240, 240 }, 3106 .vfront_porch = { 6, 6, 6 }, 3107 .vback_porch = { 5, 5, 5 }, 3108 .vsync_len = { 1, 2, 11 }, 3109 .flags = DISPLAY_FLAGS_DE_HIGH, 3110 }; 3111 3112 static const struct panel_desc koe_tx14d24vm1bpa = { 3113 .timings = &koe_tx14d24vm1bpa_timing, 3114 .num_timings = 1, 3115 .bpc = 6, 3116 .size = { 3117 .width = 115, 3118 .height = 86, 3119 }, 3120 }; 3121 3122 static const struct display_timing koe_tx26d202vm0bwa_timing = { 3123 .pixelclock = { 151820000, 156720000, 159780000 }, 3124 .hactive = { 1920, 1920, 1920 }, 3125 .hfront_porch = { 105, 130, 142 }, 3126 .hback_porch = { 45, 70, 82 }, 3127 .hsync_len = { 30, 30, 30 }, 3128 .vactive = { 1200, 1200, 1200}, 3129 .vfront_porch = { 3, 5, 10 }, 3130 .vback_porch = { 2, 5, 10 }, 3131 .vsync_len = { 5, 5, 5 }, 3132 .flags = DISPLAY_FLAGS_DE_HIGH, 3133 }; 3134 3135 static const struct panel_desc koe_tx26d202vm0bwa = { 3136 .timings = &koe_tx26d202vm0bwa_timing, 3137 .num_timings = 1, 3138 .bpc = 8, 3139 .size = { 3140 .width = 217, 3141 .height = 136, 3142 }, 3143 .delay = { 3144 .prepare = 1000, 3145 .enable = 1000, 3146 .unprepare = 1000, 3147 .disable = 1000, 3148 }, 3149 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3150 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3151 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3152 }; 3153 3154 static const struct display_timing koe_tx31d200vm0baa_timing = { 3155 .pixelclock = { 39600000, 43200000, 48000000 }, 3156 .hactive = { 1280, 1280, 1280 }, 3157 .hfront_porch = { 16, 36, 56 }, 3158 .hback_porch = { 16, 36, 56 }, 3159 .hsync_len = { 8, 8, 8 }, 3160 .vactive = { 480, 480, 480 }, 3161 .vfront_porch = { 6, 21, 33 }, 3162 .vback_porch = { 6, 21, 33 }, 3163 .vsync_len = { 8, 8, 8 }, 3164 .flags = DISPLAY_FLAGS_DE_HIGH, 3165 }; 3166 3167 static const struct panel_desc koe_tx31d200vm0baa = { 3168 .timings = &koe_tx31d200vm0baa_timing, 3169 .num_timings = 1, 3170 .bpc = 6, 3171 .size = { 3172 .width = 292, 3173 .height = 109, 3174 }, 3175 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3177 }; 3178 3179 static const struct display_timing kyo_tcg121xglp_timing = { 3180 .pixelclock = { 52000000, 65000000, 71000000 }, 3181 .hactive = { 1024, 1024, 1024 }, 3182 .hfront_porch = { 2, 2, 2 }, 3183 .hback_porch = { 2, 2, 2 }, 3184 .hsync_len = { 86, 124, 244 }, 3185 .vactive = { 768, 768, 768 }, 3186 .vfront_porch = { 2, 2, 2 }, 3187 .vback_porch = { 2, 2, 2 }, 3188 .vsync_len = { 6, 34, 73 }, 3189 .flags = DISPLAY_FLAGS_DE_HIGH, 3190 }; 3191 3192 static const struct panel_desc kyo_tcg121xglp = { 3193 .timings = &kyo_tcg121xglp_timing, 3194 .num_timings = 1, 3195 .bpc = 8, 3196 .size = { 3197 .width = 246, 3198 .height = 184, 3199 }, 3200 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3201 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3202 }; 3203 3204 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3205 .clock = 7000, 3206 .hdisplay = 320, 3207 .hsync_start = 320 + 20, 3208 .hsync_end = 320 + 20 + 30, 3209 .htotal = 320 + 20 + 30 + 38, 3210 .vdisplay = 240, 3211 .vsync_start = 240 + 4, 3212 .vsync_end = 240 + 4 + 3, 3213 .vtotal = 240 + 4 + 3 + 15, 3214 }; 3215 3216 static const struct panel_desc lemaker_bl035_rgb_002 = { 3217 .modes = &lemaker_bl035_rgb_002_mode, 3218 .num_modes = 1, 3219 .size = { 3220 .width = 70, 3221 .height = 52, 3222 }, 3223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3224 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3225 }; 3226 3227 static const struct display_timing lg_lb070wv8_timing = { 3228 .pixelclock = { 31950000, 33260000, 34600000 }, 3229 .hactive = { 800, 800, 800 }, 3230 .hfront_porch = { 88, 88, 88 }, 3231 .hback_porch = { 88, 88, 88 }, 3232 .hsync_len = { 80, 80, 80 }, 3233 .vactive = { 480, 480, 480 }, 3234 .vfront_porch = { 10, 10, 10 }, 3235 .vback_porch = { 10, 10, 10 }, 3236 .vsync_len = { 25, 25, 25 }, 3237 }; 3238 3239 static const struct panel_desc lg_lb070wv8 = { 3240 .timings = &lg_lb070wv8_timing, 3241 .num_timings = 1, 3242 .bpc = 8, 3243 .size = { 3244 .width = 151, 3245 .height = 91, 3246 }, 3247 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3248 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3249 }; 3250 3251 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3252 .clock = 155127, 3253 .hdisplay = 1920, 3254 .hsync_start = 1920 + 128, 3255 .hsync_end = 1920 + 128 + 20, 3256 .htotal = 1920 + 128 + 20 + 12, 3257 .vdisplay = 1200, 3258 .vsync_start = 1200 + 19, 3259 .vsync_end = 1200 + 19 + 4, 3260 .vtotal = 1200 + 19 + 4 + 20, 3261 }; 3262 3263 static const struct panel_desc lincolntech_lcd185_101ct = { 3264 .modes = &lincolntech_lcd185_101ct_mode, 3265 .bpc = 8, 3266 .num_modes = 1, 3267 .size = { 3268 .width = 217, 3269 .height = 136, 3270 }, 3271 .delay = { 3272 .prepare = 50, 3273 .disable = 50, 3274 }, 3275 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3277 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3278 }; 3279 3280 static const struct display_timing logictechno_lt161010_2nh_timing = { 3281 .pixelclock = { 26400000, 33300000, 46800000 }, 3282 .hactive = { 800, 800, 800 }, 3283 .hfront_porch = { 16, 210, 354 }, 3284 .hback_porch = { 46, 46, 46 }, 3285 .hsync_len = { 1, 20, 40 }, 3286 .vactive = { 480, 480, 480 }, 3287 .vfront_porch = { 7, 22, 147 }, 3288 .vback_porch = { 23, 23, 23 }, 3289 .vsync_len = { 1, 10, 20 }, 3290 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3291 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3292 DISPLAY_FLAGS_SYNC_POSEDGE, 3293 }; 3294 3295 static const struct panel_desc logictechno_lt161010_2nh = { 3296 .timings = &logictechno_lt161010_2nh_timing, 3297 .num_timings = 1, 3298 .bpc = 6, 3299 .size = { 3300 .width = 154, 3301 .height = 86, 3302 }, 3303 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3304 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3305 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3306 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3307 .connector_type = DRM_MODE_CONNECTOR_DPI, 3308 }; 3309 3310 static const struct display_timing logictechno_lt170410_2whc_timing = { 3311 .pixelclock = { 68900000, 71100000, 73400000 }, 3312 .hactive = { 1280, 1280, 1280 }, 3313 .hfront_porch = { 23, 60, 71 }, 3314 .hback_porch = { 23, 60, 71 }, 3315 .hsync_len = { 15, 40, 47 }, 3316 .vactive = { 800, 800, 800 }, 3317 .vfront_porch = { 5, 7, 10 }, 3318 .vback_porch = { 5, 7, 10 }, 3319 .vsync_len = { 6, 9, 12 }, 3320 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3321 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3322 DISPLAY_FLAGS_SYNC_POSEDGE, 3323 }; 3324 3325 static const struct panel_desc logictechno_lt170410_2whc = { 3326 .timings = &logictechno_lt170410_2whc_timing, 3327 .num_timings = 1, 3328 .bpc = 8, 3329 .size = { 3330 .width = 217, 3331 .height = 136, 3332 }, 3333 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3334 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3335 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3336 }; 3337 3338 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3339 .clock = 33000, 3340 .hdisplay = 800, 3341 .hsync_start = 800 + 112, 3342 .hsync_end = 800 + 112 + 3, 3343 .htotal = 800 + 112 + 3 + 85, 3344 .vdisplay = 480, 3345 .vsync_start = 480 + 38, 3346 .vsync_end = 480 + 38 + 3, 3347 .vtotal = 480 + 38 + 3 + 29, 3348 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3349 }; 3350 3351 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3352 .modes = &logictechno_lttd800480070_l2rt_mode, 3353 .num_modes = 1, 3354 .bpc = 8, 3355 .size = { 3356 .width = 154, 3357 .height = 86, 3358 }, 3359 .delay = { 3360 .prepare = 45, 3361 .enable = 100, 3362 .disable = 100, 3363 .unprepare = 45 3364 }, 3365 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3366 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3367 .connector_type = DRM_MODE_CONNECTOR_DPI, 3368 }; 3369 3370 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3371 .clock = 33000, 3372 .hdisplay = 800, 3373 .hsync_start = 800 + 154, 3374 .hsync_end = 800 + 154 + 3, 3375 .htotal = 800 + 154 + 3 + 43, 3376 .vdisplay = 480, 3377 .vsync_start = 480 + 47, 3378 .vsync_end = 480 + 47 + 3, 3379 .vtotal = 480 + 47 + 3 + 20, 3380 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3381 }; 3382 3383 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3384 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3385 .num_modes = 1, 3386 .bpc = 8, 3387 .size = { 3388 .width = 154, 3389 .height = 86, 3390 }, 3391 .delay = { 3392 .prepare = 45, 3393 .enable = 100, 3394 .disable = 100, 3395 .unprepare = 45 3396 }, 3397 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3398 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3399 .connector_type = DRM_MODE_CONNECTOR_DPI, 3400 }; 3401 3402 static const struct drm_display_mode logicpd_type_28_mode = { 3403 .clock = 9107, 3404 .hdisplay = 480, 3405 .hsync_start = 480 + 3, 3406 .hsync_end = 480 + 3 + 42, 3407 .htotal = 480 + 3 + 42 + 2, 3408 3409 .vdisplay = 272, 3410 .vsync_start = 272 + 2, 3411 .vsync_end = 272 + 2 + 11, 3412 .vtotal = 272 + 2 + 11 + 3, 3413 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3414 }; 3415 3416 static const struct panel_desc logicpd_type_28 = { 3417 .modes = &logicpd_type_28_mode, 3418 .num_modes = 1, 3419 .bpc = 8, 3420 .size = { 3421 .width = 105, 3422 .height = 67, 3423 }, 3424 .delay = { 3425 .prepare = 200, 3426 .enable = 200, 3427 .unprepare = 200, 3428 .disable = 200, 3429 }, 3430 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3431 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3432 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3433 .connector_type = DRM_MODE_CONNECTOR_DPI, 3434 }; 3435 3436 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3437 .clock = 150275, 3438 .hdisplay = 1920, 3439 .hsync_start = 1920 + 32, 3440 .hsync_end = 1920 + 32 + 52, 3441 .htotal = 1920 + 32 + 52 + 24, 3442 .vdisplay = 1200, 3443 .vsync_start = 1200 + 24, 3444 .vsync_end = 1200 + 24 + 8, 3445 .vtotal = 1200 + 24 + 8 + 3, 3446 }; 3447 3448 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3449 .modes = µtips_mf_101hiebcaf0_c_mode, 3450 .bpc = 8, 3451 .num_modes = 1, 3452 .size = { 3453 .width = 217, 3454 .height = 136, 3455 }, 3456 .delay = { 3457 .prepare = 50, 3458 .disable = 50, 3459 }, 3460 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3461 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3462 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3463 }; 3464 3465 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3466 .clock = 93301, 3467 .hdisplay = 1920, 3468 .hsync_start = 1920 + 72, 3469 .hsync_end = 1920 + 72 + 72, 3470 .htotal = 1920 + 72 + 72 + 72, 3471 .vdisplay = 720, 3472 .vsync_start = 720 + 3, 3473 .vsync_end = 720 + 3 + 3, 3474 .vtotal = 720 + 3 + 3 + 2, 3475 }; 3476 3477 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3478 .modes = µtips_mf_103hieb0ga0_mode, 3479 .bpc = 8, 3480 .num_modes = 1, 3481 .size = { 3482 .width = 244, 3483 .height = 92, 3484 }, 3485 .delay = { 3486 .prepare = 50, 3487 .disable = 50, 3488 }, 3489 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3490 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3491 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3492 }; 3493 3494 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3495 .clock = 30400, 3496 .hdisplay = 800, 3497 .hsync_start = 800 + 0, 3498 .hsync_end = 800 + 1, 3499 .htotal = 800 + 0 + 1 + 160, 3500 .vdisplay = 480, 3501 .vsync_start = 480 + 0, 3502 .vsync_end = 480 + 48 + 1, 3503 .vtotal = 480 + 48 + 1 + 0, 3504 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3505 }; 3506 3507 static const struct panel_desc mitsubishi_aa070mc01 = { 3508 .modes = &mitsubishi_aa070mc01_mode, 3509 .num_modes = 1, 3510 .bpc = 8, 3511 .size = { 3512 .width = 152, 3513 .height = 91, 3514 }, 3515 3516 .delay = { 3517 .enable = 200, 3518 .unprepare = 200, 3519 .disable = 400, 3520 }, 3521 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3522 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3523 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3524 }; 3525 3526 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3527 .clock = 56234, 3528 .hdisplay = 1024, 3529 .hsync_start = 1024 + 24, 3530 .hsync_end = 1024 + 24 + 63, 3531 .htotal = 1024 + 24 + 63 + 1, 3532 .vdisplay = 768, 3533 .vsync_start = 768 + 3, 3534 .vsync_end = 768 + 3 + 6, 3535 .vtotal = 768 + 3 + 6 + 1, 3536 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3537 }; 3538 3539 static const struct panel_desc mitsubishi_aa084xe01 = { 3540 .modes = &mitsubishi_aa084xe01_mode, 3541 .num_modes = 1, 3542 .bpc = 8, 3543 .size = { 3544 .width = 1024, 3545 .height = 768, 3546 }, 3547 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3548 .connector_type = DRM_MODE_CONNECTOR_DPI, 3549 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3550 }; 3551 3552 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3553 .pixelclock = { 26400000, 33000000, 46800000 }, 3554 .hactive = { 800, 800, 800 }, 3555 .hfront_porch = { 16, 204, 354 }, 3556 .hback_porch = { 46, 46, 46 }, 3557 .hsync_len = { 1, 6, 40 }, 3558 .vactive = { 480, 480, 480 }, 3559 .vfront_porch = { 7, 22, 147 }, 3560 .vback_porch = { 23, 23, 23 }, 3561 .vsync_len = { 1, 3, 20 }, 3562 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3563 DISPLAY_FLAGS_DE_HIGH, 3564 }; 3565 3566 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3567 .timings = &multi_inno_mi0700a2t_30_timing, 3568 .num_timings = 1, 3569 .bpc = 6, 3570 .size = { 3571 .width = 153, 3572 .height = 92, 3573 }, 3574 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3575 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3577 }; 3578 3579 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3580 .pixelclock = { 29000000, 33000000, 38000000 }, 3581 .hactive = { 800, 800, 800 }, 3582 .hfront_porch = { 180, 210, 240 }, 3583 .hback_porch = { 16, 16, 16 }, 3584 .hsync_len = { 30, 30, 30 }, 3585 .vactive = { 480, 480, 480 }, 3586 .vfront_porch = { 12, 22, 32 }, 3587 .vback_porch = { 10, 10, 10 }, 3588 .vsync_len = { 13, 13, 13 }, 3589 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3590 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3591 DISPLAY_FLAGS_SYNC_POSEDGE, 3592 }; 3593 3594 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3595 .timings = &multi_inno_mi0700s4t_6_timing, 3596 .num_timings = 1, 3597 .bpc = 8, 3598 .size = { 3599 .width = 154, 3600 .height = 86, 3601 }, 3602 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3603 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3604 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3605 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3606 .connector_type = DRM_MODE_CONNECTOR_DPI, 3607 }; 3608 3609 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3610 .pixelclock = { 32000000, 40000000, 50000000 }, 3611 .hactive = { 800, 800, 800 }, 3612 .hfront_porch = { 16, 210, 354 }, 3613 .hback_porch = { 6, 26, 45 }, 3614 .hsync_len = { 1, 20, 40 }, 3615 .vactive = { 600, 600, 600 }, 3616 .vfront_porch = { 1, 12, 77 }, 3617 .vback_porch = { 3, 13, 22 }, 3618 .vsync_len = { 1, 10, 20 }, 3619 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3620 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3621 DISPLAY_FLAGS_SYNC_POSEDGE, 3622 }; 3623 3624 static const struct panel_desc multi_inno_mi0800ft_9 = { 3625 .timings = &multi_inno_mi0800ft_9_timing, 3626 .num_timings = 1, 3627 .bpc = 8, 3628 .size = { 3629 .width = 162, 3630 .height = 122, 3631 }, 3632 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3633 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3634 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3635 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3636 .connector_type = DRM_MODE_CONNECTOR_DPI, 3637 }; 3638 3639 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3640 .pixelclock = { 68900000, 70000000, 73400000 }, 3641 .hactive = { 1280, 1280, 1280 }, 3642 .hfront_porch = { 30, 60, 71 }, 3643 .hback_porch = { 30, 60, 71 }, 3644 .hsync_len = { 10, 10, 48 }, 3645 .vactive = { 800, 800, 800 }, 3646 .vfront_porch = { 5, 10, 10 }, 3647 .vback_porch = { 5, 10, 10 }, 3648 .vsync_len = { 5, 6, 13 }, 3649 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3650 DISPLAY_FLAGS_DE_HIGH, 3651 }; 3652 3653 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3654 .timings = &multi_inno_mi1010ait_1cp_timing, 3655 .num_timings = 1, 3656 .bpc = 8, 3657 .size = { 3658 .width = 217, 3659 .height = 136, 3660 }, 3661 .delay = { 3662 .enable = 50, 3663 .disable = 50, 3664 }, 3665 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3666 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3667 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3668 }; 3669 3670 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3671 .pixelclock = { 40800000, 51200000, 67200000 }, 3672 .hactive = { 1024, 1024, 1024 }, 3673 .hfront_porch = { 30, 110, 130 }, 3674 .hback_porch = { 30, 110, 130 }, 3675 .hsync_len = { 30, 100, 116 }, 3676 .vactive = { 600, 600, 600 }, 3677 .vfront_porch = { 4, 13, 80 }, 3678 .vback_porch = { 4, 13, 80 }, 3679 .vsync_len = { 2, 9, 40 }, 3680 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3681 DISPLAY_FLAGS_DE_HIGH, 3682 }; 3683 3684 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3685 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3686 .num_timings = 1, 3687 .bpc = 6, 3688 .size = { 3689 .width = 260, 3690 .height = 162, 3691 }, 3692 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3693 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3694 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3695 }; 3696 3697 static const struct display_timing nec_nl12880bc20_05_timing = { 3698 .pixelclock = { 67000000, 71000000, 75000000 }, 3699 .hactive = { 1280, 1280, 1280 }, 3700 .hfront_porch = { 2, 30, 30 }, 3701 .hback_porch = { 6, 100, 100 }, 3702 .hsync_len = { 2, 30, 30 }, 3703 .vactive = { 800, 800, 800 }, 3704 .vfront_porch = { 5, 5, 5 }, 3705 .vback_porch = { 11, 11, 11 }, 3706 .vsync_len = { 7, 7, 7 }, 3707 }; 3708 3709 static const struct panel_desc nec_nl12880bc20_05 = { 3710 .timings = &nec_nl12880bc20_05_timing, 3711 .num_timings = 1, 3712 .bpc = 8, 3713 .size = { 3714 .width = 261, 3715 .height = 163, 3716 }, 3717 .delay = { 3718 .enable = 50, 3719 .disable = 50, 3720 }, 3721 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3722 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3723 }; 3724 3725 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3726 .clock = 10870, 3727 .hdisplay = 480, 3728 .hsync_start = 480 + 2, 3729 .hsync_end = 480 + 2 + 41, 3730 .htotal = 480 + 2 + 41 + 2, 3731 .vdisplay = 272, 3732 .vsync_start = 272 + 2, 3733 .vsync_end = 272 + 2 + 4, 3734 .vtotal = 272 + 2 + 4 + 2, 3735 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3736 }; 3737 3738 static const struct panel_desc nec_nl4827hc19_05b = { 3739 .modes = &nec_nl4827hc19_05b_mode, 3740 .num_modes = 1, 3741 .bpc = 8, 3742 .size = { 3743 .width = 95, 3744 .height = 54, 3745 }, 3746 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3747 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3748 }; 3749 3750 static const struct drm_display_mode nec_nl6448bc33_70c_mode = { 3751 .clock = 25175, 3752 .hdisplay = 640, 3753 .hsync_start = 640 + 16, 3754 .hsync_end = 640 + 16 + 48, 3755 .htotal = 640 + 16 + 48 + 96, 3756 .vdisplay = 480, 3757 .vsync_start = 480 + 2, 3758 .vsync_end = 480 + 2 + 31, 3759 .vtotal = 480 + 2 + 31 + 31, 3760 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 3761 }; 3762 3763 static const struct panel_desc nec_nl6448bc33_70c = { 3764 .modes = &nec_nl6448bc33_70c_mode, 3765 .num_modes = 1, 3766 .bpc = 6, 3767 .size = { 3768 .width = 211, 3769 .height = 158, 3770 }, 3771 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3772 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3773 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3774 }; 3775 3776 static const struct drm_display_mode netron_dy_e231732_mode = { 3777 .clock = 66000, 3778 .hdisplay = 1024, 3779 .hsync_start = 1024 + 160, 3780 .hsync_end = 1024 + 160 + 70, 3781 .htotal = 1024 + 160 + 70 + 90, 3782 .vdisplay = 600, 3783 .vsync_start = 600 + 127, 3784 .vsync_end = 600 + 127 + 20, 3785 .vtotal = 600 + 127 + 20 + 3, 3786 }; 3787 3788 static const struct panel_desc netron_dy_e231732 = { 3789 .modes = &netron_dy_e231732_mode, 3790 .num_modes = 1, 3791 .size = { 3792 .width = 154, 3793 .height = 87, 3794 }, 3795 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3796 }; 3797 3798 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3799 .clock = 9000, 3800 .hdisplay = 480, 3801 .hsync_start = 480 + 2, 3802 .hsync_end = 480 + 2 + 41, 3803 .htotal = 480 + 2 + 41 + 2, 3804 .vdisplay = 272, 3805 .vsync_start = 272 + 2, 3806 .vsync_end = 272 + 2 + 10, 3807 .vtotal = 272 + 2 + 10 + 2, 3808 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3809 }; 3810 3811 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3812 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3813 .num_modes = 1, 3814 .bpc = 8, 3815 .size = { 3816 .width = 95, 3817 .height = 54, 3818 }, 3819 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3820 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3821 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3822 .connector_type = DRM_MODE_CONNECTOR_DPI, 3823 }; 3824 3825 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3826 .clock = 75400, 3827 .hdisplay = 1366, 3828 .hsync_start = 1366 + 14, 3829 .hsync_end = 1366 + 14 + 56, 3830 .htotal = 1366 + 14 + 56 + 64, 3831 .vdisplay = 768, 3832 .vsync_start = 768 + 1, 3833 .vsync_end = 768 + 1 + 3, 3834 .vtotal = 768 + 1 + 3 + 22, 3835 }; 3836 3837 static const struct panel_desc nlt_nl13676bc25_03f = { 3838 .modes = &nlt_nl13676bc25_03f_mode, 3839 .num_modes = 1, 3840 .bpc = 8, 3841 .size = { 3842 .width = 363, 3843 .height = 215, 3844 }, 3845 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3846 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3847 }; 3848 3849 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3850 .pixelclock = { 130000000, 148350000, 163000000 }, 3851 .hactive = { 1920, 1920, 1920 }, 3852 .hfront_porch = { 80, 100, 100 }, 3853 .hback_porch = { 100, 120, 120 }, 3854 .hsync_len = { 50, 60, 60 }, 3855 .vactive = { 1080, 1080, 1080 }, 3856 .vfront_porch = { 12, 30, 30 }, 3857 .vback_porch = { 4, 10, 10 }, 3858 .vsync_len = { 4, 5, 5 }, 3859 }; 3860 3861 static const struct panel_desc nlt_nl192108ac18_02d = { 3862 .timings = &nlt_nl192108ac18_02d_timing, 3863 .num_timings = 1, 3864 .bpc = 8, 3865 .size = { 3866 .width = 344, 3867 .height = 194, 3868 }, 3869 .delay = { 3870 .unprepare = 500, 3871 }, 3872 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3873 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3874 }; 3875 3876 static const struct drm_display_mode nvd_9128_mode = { 3877 .clock = 29500, 3878 .hdisplay = 800, 3879 .hsync_start = 800 + 130, 3880 .hsync_end = 800 + 130 + 98, 3881 .htotal = 800 + 0 + 130 + 98, 3882 .vdisplay = 480, 3883 .vsync_start = 480 + 10, 3884 .vsync_end = 480 + 10 + 50, 3885 .vtotal = 480 + 0 + 10 + 50, 3886 }; 3887 3888 static const struct panel_desc nvd_9128 = { 3889 .modes = &nvd_9128_mode, 3890 .num_modes = 1, 3891 .bpc = 8, 3892 .size = { 3893 .width = 156, 3894 .height = 88, 3895 }, 3896 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3897 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3898 }; 3899 3900 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3901 .pixelclock = { 30000000, 30000000, 40000000 }, 3902 .hactive = { 800, 800, 800 }, 3903 .hfront_porch = { 40, 40, 40 }, 3904 .hback_porch = { 40, 40, 40 }, 3905 .hsync_len = { 1, 48, 48 }, 3906 .vactive = { 480, 480, 480 }, 3907 .vfront_porch = { 13, 13, 13 }, 3908 .vback_porch = { 29, 29, 29 }, 3909 .vsync_len = { 3, 3, 3 }, 3910 .flags = DISPLAY_FLAGS_DE_HIGH, 3911 }; 3912 3913 static const struct panel_desc okaya_rs800480t_7x0gp = { 3914 .timings = &okaya_rs800480t_7x0gp_timing, 3915 .num_timings = 1, 3916 .bpc = 6, 3917 .size = { 3918 .width = 154, 3919 .height = 87, 3920 }, 3921 .delay = { 3922 .prepare = 41, 3923 .enable = 50, 3924 .unprepare = 41, 3925 .disable = 50, 3926 }, 3927 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3928 }; 3929 3930 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3931 .clock = 9000, 3932 .hdisplay = 480, 3933 .hsync_start = 480 + 5, 3934 .hsync_end = 480 + 5 + 30, 3935 .htotal = 480 + 5 + 30 + 10, 3936 .vdisplay = 272, 3937 .vsync_start = 272 + 8, 3938 .vsync_end = 272 + 8 + 5, 3939 .vtotal = 272 + 8 + 5 + 3, 3940 }; 3941 3942 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3943 .modes = &olimex_lcd_olinuxino_43ts_mode, 3944 .num_modes = 1, 3945 .size = { 3946 .width = 95, 3947 .height = 54, 3948 }, 3949 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3950 }; 3951 3952 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3953 .clock = 33300, 3954 .hdisplay = 800, 3955 .hsync_start = 800 + 210, 3956 .hsync_end = 800 + 210 + 20, 3957 .htotal = 800 + 210 + 20 + 26, 3958 .vdisplay = 480, 3959 .vsync_start = 480 + 22, 3960 .vsync_end = 480 + 22 + 10, 3961 .vtotal = 480 + 22 + 10 + 13, 3962 }; 3963 3964 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3965 .modes = &olimex_lcd_olinuxino_5cts_mode, 3966 .num_modes = 1, 3967 .size = { 3968 .width = 154, 3969 .height = 86, 3970 }, 3971 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3972 }; 3973 3974 3975 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3976 .pixelclock = { 30000000, 30000000, 50000000 }, 3977 .hactive = { 800, 800, 800 }, 3978 .hfront_porch = { 1, 40, 255 }, 3979 .hback_porch = { 1, 40, 87 }, 3980 .hsync_len = { 1, 48, 87 }, 3981 .vactive = { 480, 480, 480 }, 3982 .vfront_porch = { 1, 13, 255 }, 3983 .vback_porch = { 1, 29, 29 }, 3984 .vsync_len = { 3, 3, 31 }, 3985 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3986 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3987 }; 3988 3989 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3990 .timings = &ontat_kd50g21_40nt_a1_timing, 3991 .num_timings = 1, 3992 .bpc = 8, 3993 .size = { 3994 .width = 108, 3995 .height = 65, 3996 }, 3997 .delay = { 3998 .prepare = 147, /* 5 VSDs */ 3999 .enable = 147, /* 5 VSDs */ 4000 .disable = 88, /* 3 VSDs */ 4001 .unprepare = 117, /* 4 VSDs */ 4002 }, 4003 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4004 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4005 .connector_type = DRM_MODE_CONNECTOR_DPI, 4006 }; 4007 4008 /* 4009 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 4010 * pixel clocks, but this is the timing that was being used in the Adafruit 4011 * installation instructions. 4012 */ 4013 static const struct drm_display_mode ontat_yx700wv03_mode = { 4014 .clock = 29500, 4015 .hdisplay = 800, 4016 .hsync_start = 824, 4017 .hsync_end = 896, 4018 .htotal = 992, 4019 .vdisplay = 480, 4020 .vsync_start = 483, 4021 .vsync_end = 493, 4022 .vtotal = 500, 4023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4024 }; 4025 4026 /* 4027 * Specification at: 4028 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 4029 */ 4030 static const struct panel_desc ontat_yx700wv03 = { 4031 .modes = &ontat_yx700wv03_mode, 4032 .num_modes = 1, 4033 .bpc = 8, 4034 .size = { 4035 .width = 154, 4036 .height = 83, 4037 }, 4038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4039 }; 4040 4041 static const struct drm_display_mode ortustech_com37h3m_mode = { 4042 .clock = 22230, 4043 .hdisplay = 480, 4044 .hsync_start = 480 + 40, 4045 .hsync_end = 480 + 40 + 10, 4046 .htotal = 480 + 40 + 10 + 40, 4047 .vdisplay = 640, 4048 .vsync_start = 640 + 4, 4049 .vsync_end = 640 + 4 + 2, 4050 .vtotal = 640 + 4 + 2 + 4, 4051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4052 }; 4053 4054 static const struct panel_desc ortustech_com37h3m = { 4055 .modes = &ortustech_com37h3m_mode, 4056 .num_modes = 1, 4057 .bpc = 8, 4058 .size = { 4059 .width = 56, /* 56.16mm */ 4060 .height = 75, /* 74.88mm */ 4061 }, 4062 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4063 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4064 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4065 }; 4066 4067 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 4068 .clock = 25000, 4069 .hdisplay = 480, 4070 .hsync_start = 480 + 10, 4071 .hsync_end = 480 + 10 + 10, 4072 .htotal = 480 + 10 + 10 + 15, 4073 .vdisplay = 800, 4074 .vsync_start = 800 + 3, 4075 .vsync_end = 800 + 3 + 3, 4076 .vtotal = 800 + 3 + 3 + 3, 4077 }; 4078 4079 static const struct panel_desc ortustech_com43h4m85ulc = { 4080 .modes = &ortustech_com43h4m85ulc_mode, 4081 .num_modes = 1, 4082 .bpc = 6, 4083 .size = { 4084 .width = 56, 4085 .height = 93, 4086 }, 4087 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4088 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4089 .connector_type = DRM_MODE_CONNECTOR_DPI, 4090 }; 4091 4092 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 4093 .clock = 33000, 4094 .hdisplay = 800, 4095 .hsync_start = 800 + 210, 4096 .hsync_end = 800 + 210 + 30, 4097 .htotal = 800 + 210 + 30 + 16, 4098 .vdisplay = 480, 4099 .vsync_start = 480 + 22, 4100 .vsync_end = 480 + 22 + 13, 4101 .vtotal = 480 + 22 + 13 + 10, 4102 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4103 }; 4104 4105 static const struct panel_desc osddisplays_osd070t1718_19ts = { 4106 .modes = &osddisplays_osd070t1718_19ts_mode, 4107 .num_modes = 1, 4108 .bpc = 8, 4109 .size = { 4110 .width = 152, 4111 .height = 91, 4112 }, 4113 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4114 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 4115 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4116 .connector_type = DRM_MODE_CONNECTOR_DPI, 4117 }; 4118 4119 static const struct drm_display_mode pda_91_00156_a0_mode = { 4120 .clock = 33300, 4121 .hdisplay = 800, 4122 .hsync_start = 800 + 1, 4123 .hsync_end = 800 + 1 + 64, 4124 .htotal = 800 + 1 + 64 + 64, 4125 .vdisplay = 480, 4126 .vsync_start = 480 + 1, 4127 .vsync_end = 480 + 1 + 23, 4128 .vtotal = 480 + 1 + 23 + 22, 4129 }; 4130 4131 static const struct panel_desc pda_91_00156_a0 = { 4132 .modes = &pda_91_00156_a0_mode, 4133 .num_modes = 1, 4134 .size = { 4135 .width = 152, 4136 .height = 91, 4137 }, 4138 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4139 }; 4140 4141 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 4142 .clock = 71150, 4143 .hdisplay = 1280, 4144 .hsync_start = 1280 + 48, 4145 .hsync_end = 1280 + 48 + 32, 4146 .htotal = 1280 + 48 + 32 + 80, 4147 .vdisplay = 800, 4148 .vsync_start = 800 + 9, 4149 .vsync_end = 800 + 9 + 8, 4150 .vtotal = 800 + 9 + 8 + 6, 4151 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4152 }; 4153 4154 static const struct panel_desc powertip_ph128800t004_zza01 = { 4155 .modes = &powertip_ph128800t004_zza01_mode, 4156 .num_modes = 1, 4157 .bpc = 8, 4158 .size = { 4159 .width = 216, 4160 .height = 135, 4161 }, 4162 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4163 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4164 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4165 }; 4166 4167 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 4168 .clock = 66500, 4169 .hdisplay = 1280, 4170 .hsync_start = 1280 + 12, 4171 .hsync_end = 1280 + 12 + 20, 4172 .htotal = 1280 + 12 + 20 + 56, 4173 .vdisplay = 800, 4174 .vsync_start = 800 + 1, 4175 .vsync_end = 800 + 1 + 3, 4176 .vtotal = 800 + 1 + 3 + 20, 4177 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4178 }; 4179 4180 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4181 .modes = &powertip_ph128800t006_zhc01_mode, 4182 .num_modes = 1, 4183 .bpc = 8, 4184 .size = { 4185 .width = 216, 4186 .height = 135, 4187 }, 4188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4189 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4191 }; 4192 4193 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4194 .clock = 24750, 4195 .hdisplay = 800, 4196 .hsync_start = 800 + 54, 4197 .hsync_end = 800 + 54 + 2, 4198 .htotal = 800 + 54 + 2 + 44, 4199 .vdisplay = 480, 4200 .vsync_start = 480 + 49, 4201 .vsync_end = 480 + 49 + 2, 4202 .vtotal = 480 + 49 + 2 + 22, 4203 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4204 }; 4205 4206 static const struct panel_desc powertip_ph800480t013_idf02 = { 4207 .modes = &powertip_ph800480t013_idf02_mode, 4208 .num_modes = 1, 4209 .bpc = 8, 4210 .size = { 4211 .width = 152, 4212 .height = 91, 4213 }, 4214 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4215 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4216 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4217 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4218 .connector_type = DRM_MODE_CONNECTOR_DPI, 4219 }; 4220 4221 static const struct drm_display_mode powertip_ph800480t032_zhc19_mode = { 4222 .clock = 27200, 4223 .hdisplay = 800, 4224 .hsync_start = 800 + 52, 4225 .hsync_end = 800 + 52 + 2, 4226 .htotal = 800 + 52 + 2 + 44, 4227 .vdisplay = 480, 4228 .vsync_start = 480 + 7, 4229 .vsync_end = 480 + 7 + 2, 4230 .vtotal = 480 + 7 + 2 + 2, 4231 }; 4232 4233 static const struct panel_desc powertip_ph800480t032_zhc19 = { 4234 .modes = &powertip_ph800480t032_zhc19_mode, 4235 .num_modes = 1, 4236 .bpc = 8, 4237 .size = { 4238 .width = 152, 4239 .height = 91, 4240 }, 4241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4242 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4243 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4244 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4245 .connector_type = DRM_MODE_CONNECTOR_DPI, 4246 }; 4247 4248 static const struct drm_display_mode primeview_pm070wl4_mode = { 4249 .clock = 32000, 4250 .hdisplay = 800, 4251 .hsync_start = 800 + 42, 4252 .hsync_end = 800 + 42 + 128, 4253 .htotal = 800 + 42 + 128 + 86, 4254 .vdisplay = 480, 4255 .vsync_start = 480 + 10, 4256 .vsync_end = 480 + 10 + 2, 4257 .vtotal = 480 + 10 + 2 + 33, 4258 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4259 }; 4260 4261 static const struct panel_desc primeview_pm070wl4 = { 4262 .modes = &primeview_pm070wl4_mode, 4263 .num_modes = 1, 4264 .bpc = 6, 4265 .size = { 4266 .width = 152, 4267 .height = 91, 4268 }, 4269 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4270 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4271 .connector_type = DRM_MODE_CONNECTOR_DPI, 4272 }; 4273 4274 static const struct drm_display_mode qd43003c0_40_mode = { 4275 .clock = 9000, 4276 .hdisplay = 480, 4277 .hsync_start = 480 + 8, 4278 .hsync_end = 480 + 8 + 4, 4279 .htotal = 480 + 8 + 4 + 39, 4280 .vdisplay = 272, 4281 .vsync_start = 272 + 4, 4282 .vsync_end = 272 + 4 + 10, 4283 .vtotal = 272 + 4 + 10 + 2, 4284 }; 4285 4286 static const struct panel_desc qd43003c0_40 = { 4287 .modes = &qd43003c0_40_mode, 4288 .num_modes = 1, 4289 .bpc = 8, 4290 .size = { 4291 .width = 95, 4292 .height = 53, 4293 }, 4294 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4295 }; 4296 4297 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4298 { /* 60 Hz */ 4299 .clock = 10800, 4300 .hdisplay = 480, 4301 .hsync_start = 480 + 77, 4302 .hsync_end = 480 + 77 + 41, 4303 .htotal = 480 + 77 + 41 + 2, 4304 .vdisplay = 272, 4305 .vsync_start = 272 + 16, 4306 .vsync_end = 272 + 16 + 10, 4307 .vtotal = 272 + 16 + 10 + 2, 4308 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4309 }, 4310 { /* 50 Hz */ 4311 .clock = 10800, 4312 .hdisplay = 480, 4313 .hsync_start = 480 + 17, 4314 .hsync_end = 480 + 17 + 41, 4315 .htotal = 480 + 17 + 41 + 2, 4316 .vdisplay = 272, 4317 .vsync_start = 272 + 116, 4318 .vsync_end = 272 + 116 + 10, 4319 .vtotal = 272 + 116 + 10 + 2, 4320 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4321 }, 4322 }; 4323 4324 static const struct panel_desc qishenglong_gopher2b_lcd = { 4325 .modes = qishenglong_gopher2b_lcd_modes, 4326 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4327 .bpc = 8, 4328 .size = { 4329 .width = 95, 4330 .height = 54, 4331 }, 4332 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4333 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4334 .connector_type = DRM_MODE_CONNECTOR_DPI, 4335 }; 4336 4337 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4338 .pixelclock = { 23000000, 25000000, 27000000 }, 4339 .hactive = { 800, 800, 800 }, 4340 .hback_porch = { 4, 8, 48 }, 4341 .hfront_porch = { 4, 8, 48 }, 4342 .hsync_len = { 2, 4, 8 }, 4343 .vactive = { 480, 480, 480 }, 4344 .vback_porch = { 4, 8, 12 }, 4345 .vfront_porch = { 4, 8, 12 }, 4346 .vsync_len = { 2, 4, 8 }, 4347 }; 4348 4349 static const struct panel_desc raystar_rff500f_awh_dnn = { 4350 .timings = &raystar_rff500f_awh_dnn_timing, 4351 .num_timings = 1, 4352 .bpc = 8, 4353 .size = { 4354 .width = 108, 4355 .height = 65, 4356 }, 4357 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4358 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4359 }; 4360 4361 static const struct display_timing rocktech_rk043fn48h_timing = { 4362 .pixelclock = { 6000000, 9000000, 12000000 }, 4363 .hactive = { 480, 480, 480 }, 4364 .hback_porch = { 8, 43, 43 }, 4365 .hfront_porch = { 2, 8, 10 }, 4366 .hsync_len = { 1, 1, 1 }, 4367 .vactive = { 272, 272, 272 }, 4368 .vback_porch = { 2, 12, 26 }, 4369 .vfront_porch = { 1, 4, 4 }, 4370 .vsync_len = { 1, 10, 10 }, 4371 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4372 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4373 DISPLAY_FLAGS_SYNC_POSEDGE, 4374 }; 4375 4376 static const struct panel_desc rocktech_rk043fn48h = { 4377 .timings = &rocktech_rk043fn48h_timing, 4378 .num_timings = 1, 4379 .bpc = 8, 4380 .size = { 4381 .width = 95, 4382 .height = 54, 4383 }, 4384 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4385 .connector_type = DRM_MODE_CONNECTOR_DPI, 4386 }; 4387 4388 static const struct display_timing rocktech_rk070er9427_timing = { 4389 .pixelclock = { 26400000, 33300000, 46800000 }, 4390 .hactive = { 800, 800, 800 }, 4391 .hfront_porch = { 16, 210, 354 }, 4392 .hback_porch = { 46, 46, 46 }, 4393 .hsync_len = { 1, 1, 1 }, 4394 .vactive = { 480, 480, 480 }, 4395 .vfront_porch = { 7, 22, 147 }, 4396 .vback_porch = { 23, 23, 23 }, 4397 .vsync_len = { 1, 1, 1 }, 4398 .flags = DISPLAY_FLAGS_DE_HIGH, 4399 }; 4400 4401 static const struct panel_desc rocktech_rk070er9427 = { 4402 .timings = &rocktech_rk070er9427_timing, 4403 .num_timings = 1, 4404 .bpc = 6, 4405 .size = { 4406 .width = 154, 4407 .height = 86, 4408 }, 4409 .delay = { 4410 .prepare = 41, 4411 .enable = 50, 4412 .unprepare = 41, 4413 .disable = 50, 4414 }, 4415 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4416 }; 4417 4418 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4419 .clock = 71100, 4420 .hdisplay = 1280, 4421 .hsync_start = 1280 + 48, 4422 .hsync_end = 1280 + 48 + 32, 4423 .htotal = 1280 + 48 + 32 + 80, 4424 .vdisplay = 800, 4425 .vsync_start = 800 + 2, 4426 .vsync_end = 800 + 2 + 5, 4427 .vtotal = 800 + 2 + 5 + 16, 4428 }; 4429 4430 static const struct panel_desc rocktech_rk101ii01d_ct = { 4431 .modes = &rocktech_rk101ii01d_ct_mode, 4432 .bpc = 8, 4433 .num_modes = 1, 4434 .size = { 4435 .width = 217, 4436 .height = 136, 4437 }, 4438 .delay = { 4439 .prepare = 50, 4440 .disable = 50, 4441 }, 4442 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4443 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4444 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4445 }; 4446 4447 static const struct display_timing samsung_ltl101al01_timing = { 4448 .pixelclock = { 66663000, 66663000, 66663000 }, 4449 .hactive = { 1280, 1280, 1280 }, 4450 .hfront_porch = { 18, 18, 18 }, 4451 .hback_porch = { 36, 36, 36 }, 4452 .hsync_len = { 16, 16, 16 }, 4453 .vactive = { 800, 800, 800 }, 4454 .vfront_porch = { 4, 4, 4 }, 4455 .vback_porch = { 16, 16, 16 }, 4456 .vsync_len = { 3, 3, 3 }, 4457 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4458 }; 4459 4460 static const struct panel_desc samsung_ltl101al01 = { 4461 .timings = &samsung_ltl101al01_timing, 4462 .num_timings = 1, 4463 .bpc = 8, 4464 .size = { 4465 .width = 217, 4466 .height = 135, 4467 }, 4468 .delay = { 4469 .prepare = 40, 4470 .enable = 300, 4471 .disable = 200, 4472 .unprepare = 600, 4473 }, 4474 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4475 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4476 }; 4477 4478 static const struct display_timing samsung_ltl106al01_timing = { 4479 .pixelclock = { 71980000, 71980000, 71980000 }, 4480 .hactive = { 1366, 1366, 1366 }, 4481 .hfront_porch = { 56, 56, 56 }, 4482 .hback_porch = { 106, 106, 106 }, 4483 .hsync_len = { 14, 14, 14 }, 4484 .vactive = { 768, 768, 768 }, 4485 .vfront_porch = { 3, 3, 3 }, 4486 .vback_porch = { 6, 6, 6 }, 4487 .vsync_len = { 1, 1, 1 }, 4488 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4489 }; 4490 4491 static const struct panel_desc samsung_ltl106al01 = { 4492 .timings = &samsung_ltl106al01_timing, 4493 .num_timings = 1, 4494 .bpc = 8, 4495 .size = { 4496 .width = 235, 4497 .height = 132, 4498 }, 4499 .delay = { 4500 .prepare = 5, 4501 .enable = 10, 4502 .disable = 10, 4503 .unprepare = 5, 4504 }, 4505 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4506 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4507 }; 4508 4509 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4510 .clock = 54030, 4511 .hdisplay = 1024, 4512 .hsync_start = 1024 + 24, 4513 .hsync_end = 1024 + 24 + 136, 4514 .htotal = 1024 + 24 + 136 + 160, 4515 .vdisplay = 600, 4516 .vsync_start = 600 + 3, 4517 .vsync_end = 600 + 3 + 6, 4518 .vtotal = 600 + 3 + 6 + 61, 4519 }; 4520 4521 static const struct panel_desc samsung_ltn101nt05 = { 4522 .modes = &samsung_ltn101nt05_mode, 4523 .num_modes = 1, 4524 .bpc = 6, 4525 .size = { 4526 .width = 223, 4527 .height = 125, 4528 }, 4529 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4530 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4531 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4532 }; 4533 4534 static const struct display_timing satoz_sat050at40h12r2_timing = { 4535 .pixelclock = {33300000, 33300000, 50000000}, 4536 .hactive = {800, 800, 800}, 4537 .hfront_porch = {16, 210, 354}, 4538 .hback_porch = {46, 46, 46}, 4539 .hsync_len = {1, 1, 40}, 4540 .vactive = {480, 480, 480}, 4541 .vfront_porch = {7, 22, 147}, 4542 .vback_porch = {23, 23, 23}, 4543 .vsync_len = {1, 1, 20}, 4544 }; 4545 4546 static const struct panel_desc satoz_sat050at40h12r2 = { 4547 .timings = &satoz_sat050at40h12r2_timing, 4548 .num_timings = 1, 4549 .bpc = 8, 4550 .size = { 4551 .width = 108, 4552 .height = 65, 4553 }, 4554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4555 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4556 }; 4557 4558 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4559 .clock = 33260, 4560 .hdisplay = 800, 4561 .hsync_start = 800 + 64, 4562 .hsync_end = 800 + 64 + 128, 4563 .htotal = 800 + 64 + 128 + 64, 4564 .vdisplay = 480, 4565 .vsync_start = 480 + 8, 4566 .vsync_end = 480 + 8 + 2, 4567 .vtotal = 480 + 8 + 2 + 35, 4568 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4569 }; 4570 4571 static const struct panel_desc sharp_lq070y3dg3b = { 4572 .modes = &sharp_lq070y3dg3b_mode, 4573 .num_modes = 1, 4574 .bpc = 8, 4575 .size = { 4576 .width = 152, /* 152.4mm */ 4577 .height = 91, /* 91.4mm */ 4578 }, 4579 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4580 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4581 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4582 }; 4583 4584 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4585 .clock = 5500, 4586 .hdisplay = 240, 4587 .hsync_start = 240 + 16, 4588 .hsync_end = 240 + 16 + 7, 4589 .htotal = 240 + 16 + 7 + 5, 4590 .vdisplay = 320, 4591 .vsync_start = 320 + 9, 4592 .vsync_end = 320 + 9 + 1, 4593 .vtotal = 320 + 9 + 1 + 7, 4594 }; 4595 4596 static const struct panel_desc sharp_lq035q7db03 = { 4597 .modes = &sharp_lq035q7db03_mode, 4598 .num_modes = 1, 4599 .bpc = 6, 4600 .size = { 4601 .width = 54, 4602 .height = 72, 4603 }, 4604 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4605 }; 4606 4607 static const struct display_timing sharp_lq101k1ly04_timing = { 4608 .pixelclock = { 60000000, 65000000, 80000000 }, 4609 .hactive = { 1280, 1280, 1280 }, 4610 .hfront_porch = { 20, 20, 20 }, 4611 .hback_porch = { 20, 20, 20 }, 4612 .hsync_len = { 10, 10, 10 }, 4613 .vactive = { 800, 800, 800 }, 4614 .vfront_porch = { 4, 4, 4 }, 4615 .vback_porch = { 4, 4, 4 }, 4616 .vsync_len = { 4, 4, 4 }, 4617 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4618 }; 4619 4620 static const struct panel_desc sharp_lq101k1ly04 = { 4621 .timings = &sharp_lq101k1ly04_timing, 4622 .num_timings = 1, 4623 .bpc = 8, 4624 .size = { 4625 .width = 217, 4626 .height = 136, 4627 }, 4628 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4629 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4630 }; 4631 4632 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4633 { /* 50 Hz */ 4634 .clock = 3000, 4635 .hdisplay = 240, 4636 .hsync_start = 240 + 58, 4637 .hsync_end = 240 + 58 + 1, 4638 .htotal = 240 + 58 + 1 + 1, 4639 .vdisplay = 160, 4640 .vsync_start = 160 + 24, 4641 .vsync_end = 160 + 24 + 10, 4642 .vtotal = 160 + 24 + 10 + 6, 4643 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4644 }, 4645 { /* 60 Hz */ 4646 .clock = 3000, 4647 .hdisplay = 240, 4648 .hsync_start = 240 + 8, 4649 .hsync_end = 240 + 8 + 1, 4650 .htotal = 240 + 8 + 1 + 1, 4651 .vdisplay = 160, 4652 .vsync_start = 160 + 24, 4653 .vsync_end = 160 + 24 + 10, 4654 .vtotal = 160 + 24 + 10 + 6, 4655 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4656 }, 4657 }; 4658 4659 static const struct panel_desc sharp_ls020b1dd01d = { 4660 .modes = sharp_ls020b1dd01d_modes, 4661 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4662 .bpc = 6, 4663 .size = { 4664 .width = 42, 4665 .height = 28, 4666 }, 4667 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4668 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4669 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4670 | DRM_BUS_FLAG_SHARP_SIGNALS, 4671 }; 4672 4673 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4674 .clock = 33300, 4675 .hdisplay = 800, 4676 .hsync_start = 800 + 1, 4677 .hsync_end = 800 + 1 + 64, 4678 .htotal = 800 + 1 + 64 + 64, 4679 .vdisplay = 480, 4680 .vsync_start = 480 + 1, 4681 .vsync_end = 480 + 1 + 23, 4682 .vtotal = 480 + 1 + 23 + 22, 4683 }; 4684 4685 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4686 .modes = &shelly_sca07010_bfn_lnn_mode, 4687 .num_modes = 1, 4688 .size = { 4689 .width = 152, 4690 .height = 91, 4691 }, 4692 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4693 }; 4694 4695 static const struct drm_display_mode starry_kr070pe2t_mode = { 4696 .clock = 33000, 4697 .hdisplay = 800, 4698 .hsync_start = 800 + 209, 4699 .hsync_end = 800 + 209 + 1, 4700 .htotal = 800 + 209 + 1 + 45, 4701 .vdisplay = 480, 4702 .vsync_start = 480 + 22, 4703 .vsync_end = 480 + 22 + 1, 4704 .vtotal = 480 + 22 + 1 + 22, 4705 }; 4706 4707 static const struct panel_desc starry_kr070pe2t = { 4708 .modes = &starry_kr070pe2t_mode, 4709 .num_modes = 1, 4710 .bpc = 8, 4711 .size = { 4712 .width = 152, 4713 .height = 86, 4714 }, 4715 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4716 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4717 .connector_type = DRM_MODE_CONNECTOR_DPI, 4718 }; 4719 4720 static const struct display_timing startek_kd070hdfld092_timing = { 4721 .pixelclock = { 40800000, 51200000, 67200000 }, 4722 .hactive = { 1024, 1024, 1024 }, 4723 .hfront_porch = { 40, 160, 216 }, 4724 .hback_porch = { 30, 140, 140 }, 4725 .hsync_len = { 20, 20, 20 }, 4726 .vactive = { 600, 600, 600 }, 4727 .vfront_porch = { 2, 12, 177 }, 4728 .vback_porch = { 5, 20, 20 }, 4729 .vsync_len = { 3, 3, 3 }, 4730 .flags = DISPLAY_FLAGS_DE_HIGH, 4731 }; 4732 4733 static const struct panel_desc startek_kd070hdfld092 = { 4734 .timings = &startek_kd070hdfld092_timing, 4735 .num_timings = 1, 4736 .bpc = 8, 4737 .size = { 4738 .width = 154, 4739 .height = 86, 4740 }, 4741 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4742 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4743 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4744 }; 4745 4746 static const struct display_timing startek_kd070wvfpa_mode = { 4747 .pixelclock = { 25200000, 27200000, 30500000 }, 4748 .hactive = { 800, 800, 800 }, 4749 .hfront_porch = { 19, 44, 115 }, 4750 .hback_porch = { 5, 16, 101 }, 4751 .hsync_len = { 1, 2, 100 }, 4752 .vactive = { 480, 480, 480 }, 4753 .vfront_porch = { 5, 43, 67 }, 4754 .vback_porch = { 5, 5, 67 }, 4755 .vsync_len = { 1, 2, 66 }, 4756 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4757 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4758 DISPLAY_FLAGS_SYNC_POSEDGE, 4759 }; 4760 4761 static const struct panel_desc startek_kd070wvfpa = { 4762 .timings = &startek_kd070wvfpa_mode, 4763 .num_timings = 1, 4764 .bpc = 8, 4765 .size = { 4766 .width = 152, 4767 .height = 91, 4768 }, 4769 .delay = { 4770 .prepare = 20, 4771 .enable = 200, 4772 .disable = 200, 4773 }, 4774 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4775 .connector_type = DRM_MODE_CONNECTOR_DPI, 4776 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4777 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4778 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4779 }; 4780 4781 static const struct display_timing tsd_tst043015cmhx_timing = { 4782 .pixelclock = { 5000000, 9000000, 12000000 }, 4783 .hactive = { 480, 480, 480 }, 4784 .hfront_porch = { 4, 5, 65 }, 4785 .hback_porch = { 36, 40, 255 }, 4786 .hsync_len = { 1, 1, 1 }, 4787 .vactive = { 272, 272, 272 }, 4788 .vfront_porch = { 2, 8, 97 }, 4789 .vback_porch = { 3, 8, 31 }, 4790 .vsync_len = { 1, 1, 1 }, 4791 4792 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4793 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4794 }; 4795 4796 static const struct panel_desc tsd_tst043015cmhx = { 4797 .timings = &tsd_tst043015cmhx_timing, 4798 .num_timings = 1, 4799 .bpc = 8, 4800 .size = { 4801 .width = 105, 4802 .height = 67, 4803 }, 4804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4805 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4806 }; 4807 4808 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4809 .clock = 30000, 4810 .hdisplay = 800, 4811 .hsync_start = 800 + 39, 4812 .hsync_end = 800 + 39 + 47, 4813 .htotal = 800 + 39 + 47 + 39, 4814 .vdisplay = 480, 4815 .vsync_start = 480 + 13, 4816 .vsync_end = 480 + 13 + 2, 4817 .vtotal = 480 + 13 + 2 + 29, 4818 }; 4819 4820 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4821 .modes = &tfc_s9700rtwv43tr_01b_mode, 4822 .num_modes = 1, 4823 .bpc = 8, 4824 .size = { 4825 .width = 155, 4826 .height = 90, 4827 }, 4828 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4829 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4830 }; 4831 4832 static const struct display_timing tianma_tm070jdhg30_timing = { 4833 .pixelclock = { 62600000, 68200000, 78100000 }, 4834 .hactive = { 1280, 1280, 1280 }, 4835 .hfront_porch = { 15, 64, 159 }, 4836 .hback_porch = { 5, 5, 5 }, 4837 .hsync_len = { 1, 1, 256 }, 4838 .vactive = { 800, 800, 800 }, 4839 .vfront_porch = { 3, 40, 99 }, 4840 .vback_porch = { 2, 2, 2 }, 4841 .vsync_len = { 1, 1, 128 }, 4842 .flags = DISPLAY_FLAGS_DE_HIGH, 4843 }; 4844 4845 static const struct panel_desc tianma_tm070jdhg30 = { 4846 .timings = &tianma_tm070jdhg30_timing, 4847 .num_timings = 1, 4848 .bpc = 8, 4849 .size = { 4850 .width = 151, 4851 .height = 95, 4852 }, 4853 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4854 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4855 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4856 }; 4857 4858 static const struct panel_desc tianma_tm070jvhg33 = { 4859 .timings = &tianma_tm070jdhg30_timing, 4860 .num_timings = 1, 4861 .bpc = 8, 4862 .size = { 4863 .width = 150, 4864 .height = 94, 4865 }, 4866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4868 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4869 }; 4870 4871 /* 4872 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4873 * front porch, not including sync pulse width. This is for both H and 4874 * V. To make the total blanking and period correct, subtract the pulse 4875 * width from the front porch. 4876 * 4877 * This works well for the Min and Typ values, but for Max values the sync 4878 * pulse width is higher than back porch + front porch, so work around that 4879 * by reducing the Max sync length value to 1 and then treating the Max 4880 * porches as in the Min and Typ cases. 4881 * 4882 * Exact datasheet values are added as a comment where they differ from the 4883 * ones implemented for the above reason. 4884 * 4885 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4886 * and total blanking time, however the resulting values are the same as 4887 * the TM070JDHG34-00. 4888 */ 4889 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4890 .pixelclock = { 68400000, 71900000, 78100000 }, 4891 .hactive = { 1280, 1280, 1280 }, 4892 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4893 .hback_porch = { 5, 5, 5 }, 4894 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4895 .vactive = { 800, 800, 800 }, 4896 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4897 .vback_porch = { 2, 2, 2 }, 4898 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4899 .flags = DISPLAY_FLAGS_DE_HIGH, 4900 }; 4901 4902 static const struct panel_desc tianma_tm070jdhg34_00 = { 4903 .timings = &tianma_tm070jdhg34_00_timing, 4904 .num_timings = 1, 4905 .bpc = 8, 4906 .size = { 4907 .width = 150, /* 149.76 */ 4908 .height = 94, /* 93.60 */ 4909 }, 4910 .delay = { 4911 .prepare = 15, /* Tp1 */ 4912 .enable = 150, /* Tp2 */ 4913 .disable = 150, /* Tp4 */ 4914 .unprepare = 120, /* Tp3 */ 4915 }, 4916 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4917 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4918 }; 4919 4920 static const struct panel_desc tianma_p0700wxf1mbaa = { 4921 .timings = &tianma_tm070jdhg34_00_timing, 4922 .num_timings = 1, 4923 .bpc = 8, 4924 .size = { 4925 .width = 150, /* 149.76 */ 4926 .height = 94, /* 93.60 */ 4927 }, 4928 .delay = { 4929 .prepare = 18, /* Tr + Tp1 */ 4930 .enable = 152, /* Tp2 + Tp5 */ 4931 .disable = 152, /* Tp6 + Tp4 */ 4932 .unprepare = 120, /* Tp3 */ 4933 }, 4934 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4935 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4936 }; 4937 4938 static const struct display_timing tianma_tm070rvhg71_timing = { 4939 .pixelclock = { 27700000, 29200000, 39600000 }, 4940 .hactive = { 800, 800, 800 }, 4941 .hfront_porch = { 12, 40, 212 }, 4942 .hback_porch = { 88, 88, 88 }, 4943 .hsync_len = { 1, 1, 40 }, 4944 .vactive = { 480, 480, 480 }, 4945 .vfront_porch = { 1, 13, 88 }, 4946 .vback_porch = { 32, 32, 32 }, 4947 .vsync_len = { 1, 1, 3 }, 4948 .flags = DISPLAY_FLAGS_DE_HIGH, 4949 }; 4950 4951 static const struct panel_desc tianma_tm070rvhg71 = { 4952 .timings = &tianma_tm070rvhg71_timing, 4953 .num_timings = 1, 4954 .bpc = 8, 4955 .size = { 4956 .width = 154, 4957 .height = 86, 4958 }, 4959 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4960 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4961 }; 4962 4963 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4964 { 4965 .clock = 10000, 4966 .hdisplay = 320, 4967 .hsync_start = 320 + 50, 4968 .hsync_end = 320 + 50 + 6, 4969 .htotal = 320 + 50 + 6 + 38, 4970 .vdisplay = 240, 4971 .vsync_start = 240 + 3, 4972 .vsync_end = 240 + 3 + 1, 4973 .vtotal = 240 + 3 + 1 + 17, 4974 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4975 }, 4976 }; 4977 4978 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4979 .modes = ti_nspire_cx_lcd_mode, 4980 .num_modes = 1, 4981 .bpc = 8, 4982 .size = { 4983 .width = 65, 4984 .height = 49, 4985 }, 4986 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4987 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4988 }; 4989 4990 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4991 { 4992 .clock = 10000, 4993 .hdisplay = 320, 4994 .hsync_start = 320 + 6, 4995 .hsync_end = 320 + 6 + 6, 4996 .htotal = 320 + 6 + 6 + 6, 4997 .vdisplay = 240, 4998 .vsync_start = 240 + 0, 4999 .vsync_end = 240 + 0 + 1, 5000 .vtotal = 240 + 0 + 1 + 0, 5001 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5002 }, 5003 }; 5004 5005 static const struct panel_desc ti_nspire_classic_lcd_panel = { 5006 .modes = ti_nspire_classic_lcd_mode, 5007 .num_modes = 1, 5008 /* The grayscale panel has 8 bit for the color .. Y (black) */ 5009 .bpc = 8, 5010 .size = { 5011 .width = 71, 5012 .height = 53, 5013 }, 5014 /* This is the grayscale bus format */ 5015 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 5016 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5017 }; 5018 5019 static const struct display_timing topland_tian_g07017_01_timing = { 5020 .pixelclock = { 44900000, 51200000, 63000000 }, 5021 .hactive = { 1024, 1024, 1024 }, 5022 .hfront_porch = { 16, 160, 216 }, 5023 .hback_porch = { 160, 160, 160 }, 5024 .hsync_len = { 1, 1, 140 }, 5025 .vactive = { 600, 600, 600 }, 5026 .vfront_porch = { 1, 12, 127 }, 5027 .vback_porch = { 23, 23, 23 }, 5028 .vsync_len = { 1, 1, 20 }, 5029 }; 5030 5031 static const struct panel_desc topland_tian_g07017_01 = { 5032 .timings = &topland_tian_g07017_01_timing, 5033 .num_timings = 1, 5034 .bpc = 8, 5035 .size = { 5036 .width = 154, 5037 .height = 86, 5038 }, 5039 .delay = { 5040 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 5041 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 5042 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 5043 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 5044 }, 5045 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5046 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5047 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5048 }; 5049 5050 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 5051 .clock = 79500, 5052 .hdisplay = 1280, 5053 .hsync_start = 1280 + 192, 5054 .hsync_end = 1280 + 192 + 128, 5055 .htotal = 1280 + 192 + 128 + 64, 5056 .vdisplay = 768, 5057 .vsync_start = 768 + 20, 5058 .vsync_end = 768 + 20 + 7, 5059 .vtotal = 768 + 20 + 7 + 3, 5060 }; 5061 5062 static const struct panel_desc toshiba_lt089ac29000 = { 5063 .modes = &toshiba_lt089ac29000_mode, 5064 .num_modes = 1, 5065 .size = { 5066 .width = 194, 5067 .height = 116, 5068 }, 5069 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5070 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5071 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5072 }; 5073 5074 static const struct drm_display_mode tpk_f07a_0102_mode = { 5075 .clock = 33260, 5076 .hdisplay = 800, 5077 .hsync_start = 800 + 40, 5078 .hsync_end = 800 + 40 + 128, 5079 .htotal = 800 + 40 + 128 + 88, 5080 .vdisplay = 480, 5081 .vsync_start = 480 + 10, 5082 .vsync_end = 480 + 10 + 2, 5083 .vtotal = 480 + 10 + 2 + 33, 5084 }; 5085 5086 static const struct panel_desc tpk_f07a_0102 = { 5087 .modes = &tpk_f07a_0102_mode, 5088 .num_modes = 1, 5089 .size = { 5090 .width = 152, 5091 .height = 91, 5092 }, 5093 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 5094 }; 5095 5096 static const struct drm_display_mode tpk_f10a_0102_mode = { 5097 .clock = 45000, 5098 .hdisplay = 1024, 5099 .hsync_start = 1024 + 176, 5100 .hsync_end = 1024 + 176 + 5, 5101 .htotal = 1024 + 176 + 5 + 88, 5102 .vdisplay = 600, 5103 .vsync_start = 600 + 20, 5104 .vsync_end = 600 + 20 + 5, 5105 .vtotal = 600 + 20 + 5 + 25, 5106 }; 5107 5108 static const struct panel_desc tpk_f10a_0102 = { 5109 .modes = &tpk_f10a_0102_mode, 5110 .num_modes = 1, 5111 .size = { 5112 .width = 223, 5113 .height = 125, 5114 }, 5115 }; 5116 5117 static const struct display_timing urt_umsh_8596md_timing = { 5118 .pixelclock = { 33260000, 33260000, 33260000 }, 5119 .hactive = { 800, 800, 800 }, 5120 .hfront_porch = { 41, 41, 41 }, 5121 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 5122 .hsync_len = { 71, 128, 128 }, 5123 .vactive = { 480, 480, 480 }, 5124 .vfront_porch = { 10, 10, 10 }, 5125 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 5126 .vsync_len = { 2, 2, 2 }, 5127 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 5128 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 5129 }; 5130 5131 static const struct panel_desc urt_umsh_8596md_lvds = { 5132 .timings = &urt_umsh_8596md_timing, 5133 .num_timings = 1, 5134 .bpc = 6, 5135 .size = { 5136 .width = 152, 5137 .height = 91, 5138 }, 5139 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5140 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5141 }; 5142 5143 static const struct panel_desc urt_umsh_8596md_parallel = { 5144 .timings = &urt_umsh_8596md_timing, 5145 .num_timings = 1, 5146 .bpc = 6, 5147 .size = { 5148 .width = 152, 5149 .height = 91, 5150 }, 5151 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 5152 }; 5153 5154 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 5155 .clock = 60000, 5156 .hdisplay = 1024, 5157 .hsync_start = 1024 + 160, 5158 .hsync_end = 1024 + 160 + 100, 5159 .htotal = 1024 + 160 + 100 + 60, 5160 .vdisplay = 600, 5161 .vsync_start = 600 + 12, 5162 .vsync_end = 600 + 12 + 10, 5163 .vtotal = 600 + 12 + 10 + 13, 5164 }; 5165 5166 static const struct panel_desc vivax_tpc9150_panel = { 5167 .modes = &vivax_tpc9150_panel_mode, 5168 .num_modes = 1, 5169 .bpc = 6, 5170 .size = { 5171 .width = 200, 5172 .height = 115, 5173 }, 5174 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5175 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5177 }; 5178 5179 static const struct drm_display_mode vl050_8048nt_c01_mode = { 5180 .clock = 33333, 5181 .hdisplay = 800, 5182 .hsync_start = 800 + 210, 5183 .hsync_end = 800 + 210 + 20, 5184 .htotal = 800 + 210 + 20 + 46, 5185 .vdisplay = 480, 5186 .vsync_start = 480 + 22, 5187 .vsync_end = 480 + 22 + 10, 5188 .vtotal = 480 + 22 + 10 + 23, 5189 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5190 }; 5191 5192 static const struct panel_desc vl050_8048nt_c01 = { 5193 .modes = &vl050_8048nt_c01_mode, 5194 .num_modes = 1, 5195 .bpc = 8, 5196 .size = { 5197 .width = 120, 5198 .height = 76, 5199 }, 5200 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5201 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5202 }; 5203 5204 static const struct drm_display_mode waveshare_28_lcd_mode = { 5205 .clock = 50000, 5206 .hdisplay = 480, 5207 .hsync_start = 480 + 150, 5208 .hsync_end = 480 + 150 + 50, 5209 .htotal = 480 + 150 + 50 + 150, 5210 .vdisplay = 640, 5211 .vsync_start = 640 + 150, 5212 .vsync_end = 640 + 150 + 50, 5213 .vtotal = 640 + 150 + 50 + 150, 5214 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5215 }; 5216 5217 static const struct panel_desc waveshare_28_lcd_panel = { 5218 .modes = &waveshare_28_lcd_mode, 5219 .num_modes = 1, 5220 .bpc = 8, 5221 .size = { 5222 .width = 44, 5223 .height = 58, 5224 }, 5225 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5226 .connector_type = DRM_MODE_CONNECTOR_DPI, 5227 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5228 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5229 }; 5230 5231 static const struct drm_display_mode waveshare_34_lcd_c_mode = { 5232 .clock = 50000, 5233 .hdisplay = 800, 5234 .hsync_start = 800 + 32, 5235 .hsync_end = 800 + 32 + 6, 5236 .htotal = 800 + 32 + 6 + 120, 5237 .vdisplay = 800, 5238 .vsync_start = 800 + 8, 5239 .vsync_end = 800 + 8 + 4, 5240 .vtotal = 800 + 8 + 4 + 16, 5241 }; 5242 5243 static const struct panel_desc waveshare_34_lcd_c_panel = { 5244 .modes = &waveshare_34_lcd_c_mode, 5245 .num_modes = 1, 5246 .bpc = 8, 5247 .size = { 5248 .width = 88, 5249 .height = 88, 5250 }, 5251 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5252 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5253 }; 5254 5255 static const struct drm_display_mode waveshare_40_lcd_mode = { 5256 .clock = 50000, 5257 .hdisplay = 480, 5258 .hsync_start = 480 + 150, 5259 .hsync_end = 480 + 150 + 100, 5260 .htotal = 480 + 150 + 100 + 150, 5261 .vdisplay = 800, 5262 .vsync_start = 800 + 20, 5263 .vsync_end = 800 + 20 + 100, 5264 .vtotal = 800 + 20 + 100 + 20, 5265 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5266 }; 5267 5268 static const struct panel_desc waveshare_40_lcd_panel = { 5269 .modes = &waveshare_40_lcd_mode, 5270 .num_modes = 1, 5271 .bpc = 8, 5272 .size = { 5273 .width = 52, 5274 .height = 87, 5275 }, 5276 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5277 .connector_type = DRM_MODE_CONNECTOR_DPI, 5278 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5279 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5280 }; 5281 5282 static const struct drm_display_mode waveshare_40_lcd_c_mode = { 5283 .clock = 50000, 5284 .hdisplay = 720, 5285 .hsync_start = 720 + 32, 5286 .hsync_end = 720 + 32 + 200, 5287 .htotal = 720 + 32 + 200 + 120, 5288 .vdisplay = 720, 5289 .vsync_start = 720 + 8, 5290 .vsync_end = 720 + 8 + 4, 5291 .vtotal = 720 + 8 + 4 + 16, 5292 }; 5293 5294 static const struct panel_desc waveshare_40_lcd_c_panel = { 5295 .modes = &waveshare_40_lcd_c_mode, 5296 .num_modes = 1, 5297 .bpc = 8, 5298 .size = { 5299 .width = 102, 5300 .height = 102, 5301 }, 5302 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5303 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5304 }; 5305 5306 static const struct drm_display_mode waveshare_50_lcd_c_mode = { 5307 .clock = 50000, 5308 .hdisplay = 1024, 5309 .hsync_start = 1024 + 100, 5310 .hsync_end = 1024 + 100 + 100, 5311 .htotal = 1024 + 100 + 100 + 100, 5312 .vdisplay = 600, 5313 .vsync_start = 600 + 10, 5314 .vsync_end = 600 + 10 + 10, 5315 .vtotal = 600 + 10 + 10 + 10, 5316 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5317 }; 5318 5319 static const struct panel_desc waveshare_50_lcd_c_panel = { 5320 .modes = &waveshare_50_lcd_c_mode, 5321 .num_modes = 1, 5322 .bpc = 8, 5323 .size = { 5324 .width = 109, 5325 .height = 66, 5326 }, 5327 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5328 .connector_type = DRM_MODE_CONNECTOR_DPI, 5329 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5330 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5331 }; 5332 5333 static const struct drm_display_mode waveshare_50_lcd_d_mode = { 5334 .clock = 83333, 5335 .hdisplay = 720, 5336 .hsync_start = 720 + 100, 5337 .hsync_end = 720 + 100 + 80, 5338 .htotal = 720 + 100 + 80 + 100, 5339 .vdisplay = 1280, 5340 .vsync_start = 1280 + 20, 5341 .vsync_end = 1280 + 20 + 20, 5342 .vtotal = 1280 + 20 + 20 + 20, 5343 }; 5344 5345 static const struct panel_desc waveshare_50_lcd_d_panel = { 5346 .modes = &waveshare_50_lcd_d_mode, 5347 .num_modes = 1, 5348 .bpc = 8, 5349 .size = { 5350 .width = 62, 5351 .height = 110, 5352 }, 5353 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5354 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5355 }; 5356 5357 static const struct drm_display_mode waveshare_625_lcd_mode = { 5358 .clock = 83333, 5359 .hdisplay = 720, 5360 .hsync_start = 720 + 50, 5361 .hsync_end = 720 + 50 + 50, 5362 .htotal = 720 + 50 + 50 + 50, 5363 .vdisplay = 1560, 5364 .vsync_start = 1560 + 20, 5365 .vsync_end = 1560 + 20 + 20, 5366 .vtotal = 1560 + 20 + 20 + 20, 5367 }; 5368 5369 static const struct panel_desc waveshare_625_lcd_panel = { 5370 .modes = &waveshare_625_lcd_mode, 5371 .num_modes = 1, 5372 .bpc = 8, 5373 .size = { 5374 .width = 66, 5375 .height = 144, 5376 }, 5377 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5378 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5379 }; 5380 5381 static const struct panel_desc waveshare_70_lcd_c_panel = { 5382 .modes = &waveshare_50_lcd_c_mode, 5383 .num_modes = 1, 5384 .bpc = 8, 5385 .size = { 5386 .width = 155, 5387 .height = 87, 5388 }, 5389 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5390 .connector_type = DRM_MODE_CONNECTOR_DPI, 5391 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5392 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5393 }; 5394 5395 static const struct drm_display_mode waveshare_80_lcd_c_mode; 5396 static const struct panel_desc waveshare_70_lcd_e_panel = { 5397 .modes = &waveshare_80_lcd_c_mode, 5398 .num_modes = 1, 5399 .bpc = 8, 5400 .size = { 5401 .width = 152, 5402 .height = 95, 5403 }, 5404 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5405 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5406 }; 5407 5408 static const struct drm_display_mode waveshare_70_lcd_h_mode = { 5409 .clock = 83333, 5410 .hdisplay = 1280, 5411 .hsync_start = 1280 + 64, 5412 .hsync_end = 1280 + 64 + 64, 5413 .htotal = 1280 + 64 + 64 + 64, 5414 .vdisplay = 720, 5415 .vsync_start = 720 + 64, 5416 .vsync_end = 720 + 64 + 64, 5417 .vtotal = 720 + 64 + 64 + 64, 5418 }; 5419 5420 static const struct panel_desc waveshare_70_lcd_h_panel = { 5421 .modes = &waveshare_70_lcd_h_mode, 5422 .num_modes = 1, 5423 .bpc = 8, 5424 .size = { 5425 .width = 155, 5426 .height = 88, 5427 }, 5428 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5429 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5430 }; 5431 5432 static const struct drm_display_mode waveshare_79_lcd_mode = { 5433 .clock = 50000, 5434 .hdisplay = 400, 5435 .hsync_start = 400 + 40, 5436 .hsync_end = 400 + 40 + 30, 5437 .htotal = 400 + 40 + 30 + 40, 5438 .vdisplay = 1280, 5439 .vsync_start = 1280 + 20, 5440 .vsync_end = 1280 + 20 + 10, 5441 .vtotal = 1280 + 20 + 10 + 20, 5442 }; 5443 5444 static const struct panel_desc waveshare_79_lcd_panel = { 5445 .modes = &waveshare_79_lcd_mode, 5446 .num_modes = 1, 5447 .bpc = 8, 5448 .size = { 5449 .width = 60, 5450 .height = 191, 5451 }, 5452 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5453 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5454 }; 5455 5456 static const struct drm_display_mode waveshare_80_lcd_c_mode = { 5457 .clock = 83333, 5458 .hdisplay = 1280, 5459 .hsync_start = 1280 + 156, 5460 .hsync_end = 1280 + 156 + 20, 5461 .htotal = 1280 + 156 + 20 + 40, 5462 .vdisplay = 800, 5463 .vsync_start = 800 + 40, 5464 .vsync_end = 800 + 40 + 48, 5465 .vtotal = 800 + 40 + 48 + 40, 5466 }; 5467 5468 static const struct panel_desc waveshare_80_lcd_c_panel = { 5469 .modes = &waveshare_80_lcd_c_mode, 5470 .num_modes = 1, 5471 .bpc = 8, 5472 .size = { 5473 .width = 173, 5474 .height = 108, 5475 }, 5476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5477 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5478 }; 5479 5480 static const struct drm_display_mode waveshare_88_lcd_mode = { 5481 .clock = 83333, 5482 .hdisplay = 480, 5483 .hsync_start = 480 + 50, 5484 .hsync_end = 480 + 50 + 50, 5485 .htotal = 480 + 50 + 50 + 50, 5486 .vdisplay = 1920, 5487 .vsync_start = 1920 + 20, 5488 .vsync_end = 1920 + 20 + 20, 5489 .vtotal = 1920 + 20 + 20 + 20, 5490 }; 5491 5492 static const struct panel_desc waveshare_88_lcd_panel = { 5493 .modes = &waveshare_88_lcd_mode, 5494 .num_modes = 1, 5495 .bpc = 8, 5496 .size = { 5497 .width = 56, 5498 .height = 220, 5499 }, 5500 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5501 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5502 }; 5503 5504 static const struct panel_desc waveshare_101_lcd_c_panel = { 5505 .modes = &waveshare_80_lcd_c_mode, 5506 .num_modes = 1, 5507 .bpc = 8, 5508 .size = { 5509 .width = 217, 5510 .height = 136, 5511 }, 5512 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5513 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5514 }; 5515 5516 static const struct drm_display_mode waveshare_119_lcd_mode = { 5517 .clock = 50000, 5518 .hdisplay = 320, 5519 .hsync_start = 320 + 60, 5520 .hsync_end = 320 + 60 + 60, 5521 .htotal = 320 + 60 + 60 + 60, 5522 .vdisplay = 1480, 5523 .vsync_start = 1480 + 60, 5524 .vsync_end = 1480 + 60 + 60, 5525 .vtotal = 1480 + 60 + 60 + 60, 5526 }; 5527 5528 static const struct panel_desc waveshare_119_lcd_panel = { 5529 .modes = &waveshare_119_lcd_mode, 5530 .num_modes = 1, 5531 .bpc = 8, 5532 .size = { 5533 .width = 58, 5534 .height = 268, 5535 }, 5536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5537 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5538 }; 5539 5540 static const struct drm_display_mode waveshare_133inch_mode = { 5541 .clock = 148500, 5542 .hdisplay = 1920, 5543 .hsync_start = 1920 + 88, 5544 .hsync_end = 1920 + 88 + 44, 5545 .htotal = 1920 + 88 + 44 + 148, 5546 .vdisplay = 1080, 5547 .vsync_start = 1080 + 4, 5548 .vsync_end = 1080 + 4 + 5, 5549 .vtotal = 1080 + 4 + 5 + 36, 5550 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5551 }; 5552 5553 static const struct panel_desc waveshare_133inch = { 5554 .modes = &waveshare_133inch_mode, 5555 .num_modes = 1, 5556 .bpc = 8, 5557 .size = { 5558 .width = 293, 5559 .height = 163, 5560 }, 5561 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5562 .connector_type = DRM_MODE_CONNECTOR_DPI, 5563 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5564 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5565 }; 5566 5567 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 5568 .clock = 6410, 5569 .hdisplay = 320, 5570 .hsync_start = 320 + 20, 5571 .hsync_end = 320 + 20 + 30, 5572 .htotal = 320 + 20 + 30 + 38, 5573 .vdisplay = 240, 5574 .vsync_start = 240 + 4, 5575 .vsync_end = 240 + 4 + 3, 5576 .vtotal = 240 + 4 + 3 + 15, 5577 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5578 }; 5579 5580 static const struct panel_desc winstar_wf35ltiacd = { 5581 .modes = &winstar_wf35ltiacd_mode, 5582 .num_modes = 1, 5583 .bpc = 8, 5584 .size = { 5585 .width = 70, 5586 .height = 53, 5587 }, 5588 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5589 }; 5590 5591 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5592 .clock = 51200, 5593 .hdisplay = 1024, 5594 .hsync_start = 1024 + 100, 5595 .hsync_end = 1024 + 100 + 100, 5596 .htotal = 1024 + 100 + 100 + 120, 5597 .vdisplay = 600, 5598 .vsync_start = 600 + 10, 5599 .vsync_end = 600 + 10 + 10, 5600 .vtotal = 600 + 10 + 10 + 15, 5601 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5602 }; 5603 5604 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5605 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5606 .num_modes = 1, 5607 .bpc = 8, 5608 .size = { 5609 .width = 154, 5610 .height = 90, 5611 }, 5612 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5613 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5614 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5615 }; 5616 5617 static const struct drm_display_mode mchp_ac69t88a_mode = { 5618 .clock = 25000, 5619 .hdisplay = 800, 5620 .hsync_start = 800 + 88, 5621 .hsync_end = 800 + 88 + 5, 5622 .htotal = 800 + 88 + 5 + 40, 5623 .vdisplay = 480, 5624 .vsync_start = 480 + 23, 5625 .vsync_end = 480 + 23 + 5, 5626 .vtotal = 480 + 23 + 5 + 1, 5627 }; 5628 5629 static const struct panel_desc mchp_ac69t88a = { 5630 .modes = &mchp_ac69t88a_mode, 5631 .num_modes = 1, 5632 .bpc = 8, 5633 .size = { 5634 .width = 108, 5635 .height = 65, 5636 }, 5637 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5639 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5640 }; 5641 5642 static const struct drm_display_mode arm_rtsm_mode[] = { 5643 { 5644 .clock = 65000, 5645 .hdisplay = 1024, 5646 .hsync_start = 1024 + 24, 5647 .hsync_end = 1024 + 24 + 136, 5648 .htotal = 1024 + 24 + 136 + 160, 5649 .vdisplay = 768, 5650 .vsync_start = 768 + 3, 5651 .vsync_end = 768 + 3 + 6, 5652 .vtotal = 768 + 3 + 6 + 29, 5653 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5654 }, 5655 }; 5656 5657 static const struct panel_desc arm_rtsm = { 5658 .modes = arm_rtsm_mode, 5659 .num_modes = 1, 5660 .bpc = 8, 5661 .size = { 5662 .width = 400, 5663 .height = 300, 5664 }, 5665 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5666 }; 5667 5668 static const struct of_device_id platform_of_match[] = { 5669 { 5670 .compatible = "ampire,am-1280800n3tzqw-t00h", 5671 .data = &ire_am_1280800n3tzqw_t00h, 5672 }, { 5673 .compatible = "ampire,am-1280800w8tzqw-t00h", 5674 .data = &ire_am_1280800w8tzqw_t00h, 5675 }, { 5676 .compatible = "ampire,am-480272h3tmqw-t01h", 5677 .data = &ire_am_480272h3tmqw_t01h, 5678 }, { 5679 .compatible = "ampire,am-800480l1tmqw-t00h", 5680 .data = &ire_am_800480l1tmqw_t00h, 5681 }, { 5682 .compatible = "ampire,am-800480n3tzqw-00h", 5683 .data = &ire_am_800480n3tzqw_00h, 5684 }, { 5685 .compatible = "ampire,am800480r3tmqwa1h", 5686 .data = &ire_am800480r3tmqwa1h, 5687 }, { 5688 .compatible = "ampire,am800600p5tmqw-tb8h", 5689 .data = &ire_am800600p5tmqwtb8h, 5690 }, { 5691 .compatible = "arm,rtsm-display", 5692 .data = &arm_rtsm, 5693 }, { 5694 .compatible = "armadeus,st0700-adapt", 5695 .data = &armadeus_st0700_adapt, 5696 }, { 5697 .compatible = "auo,b101aw03", 5698 .data = &auo_b101aw03, 5699 }, { 5700 .compatible = "auo,b101xtn01", 5701 .data = &auo_b101xtn01, 5702 }, { 5703 .compatible = "auo,b116xw03", 5704 .data = &auo_b116xw03, 5705 }, { 5706 .compatible = "auo,g070vvn01", 5707 .data = &auo_g070vvn01, 5708 }, { 5709 .compatible = "auo,g101evn010", 5710 .data = &auo_g101evn010, 5711 }, { 5712 .compatible = "auo,g104sn02", 5713 .data = &auo_g104sn02, 5714 }, { 5715 .compatible = "auo,g104stn01", 5716 .data = &auo_g104stn01, 5717 }, { 5718 .compatible = "auo,g121ean01", 5719 .data = &auo_g121ean01, 5720 }, { 5721 .compatible = "auo,g133han01", 5722 .data = &auo_g133han01, 5723 }, { 5724 .compatible = "auo,g156han04", 5725 .data = &auo_g156han04, 5726 }, { 5727 .compatible = "auo,g156xtn01", 5728 .data = &auo_g156xtn01, 5729 }, { 5730 .compatible = "auo,g185han01", 5731 .data = &auo_g185han01, 5732 }, { 5733 .compatible = "auo,g190ean01", 5734 .data = &auo_g190ean01, 5735 }, { 5736 .compatible = "auo,p238han01", 5737 .data = &auo_p238han01, 5738 }, { 5739 .compatible = "auo,p320hvn03", 5740 .data = &auo_p320hvn03, 5741 }, { 5742 .compatible = "auo,t215hvn01", 5743 .data = &auo_t215hvn01, 5744 }, { 5745 .compatible = "avic,tm070ddh03", 5746 .data = &avic_tm070ddh03, 5747 }, { 5748 .compatible = "bananapi,s070wv20-ct16", 5749 .data = &bananapi_s070wv20_ct16, 5750 }, { 5751 .compatible = "boe,av101hdt-a10", 5752 .data = &boe_av101hdt_a10, 5753 }, { 5754 .compatible = "boe,av123z7m-n17", 5755 .data = &boe_av123z7m_n17, 5756 }, { 5757 .compatible = "boe,bp082wx1-100", 5758 .data = &boe_bp082wx1_100, 5759 }, { 5760 .compatible = "boe,bp101wx1-100", 5761 .data = &boe_bp101wx1_100, 5762 }, { 5763 .compatible = "boe,ev121wxm-n10-1850", 5764 .data = &boe_ev121wxm_n10_1850, 5765 }, { 5766 .compatible = "boe,hv070wsa-100", 5767 .data = &boe_hv070wsa 5768 }, { 5769 .compatible = "cct,cmt430b19n00", 5770 .data = &cct_cmt430b19n00, 5771 }, { 5772 .compatible = "cdtech,s043wq26h-ct7", 5773 .data = &cdtech_s043wq26h_ct7, 5774 }, { 5775 .compatible = "cdtech,s070pws19hp-fc21", 5776 .data = &cdtech_s070pws19hp_fc21, 5777 }, { 5778 .compatible = "cdtech,s070swv29hg-dc44", 5779 .data = &cdtech_s070swv29hg_dc44, 5780 }, { 5781 .compatible = "cdtech,s070wv95-ct16", 5782 .data = &cdtech_s070wv95_ct16, 5783 }, { 5784 .compatible = "chefree,ch101olhlwh-002", 5785 .data = &chefree_ch101olhlwh_002, 5786 }, { 5787 .compatible = "chunghwa,claa070wp03xg", 5788 .data = &chunghwa_claa070wp03xg, 5789 }, { 5790 .compatible = "chunghwa,claa101wa01a", 5791 .data = &chunghwa_claa101wa01a 5792 }, { 5793 .compatible = "chunghwa,claa101wb01", 5794 .data = &chunghwa_claa101wb01 5795 }, { 5796 .compatible = "dataimage,fg040346dsswbg04", 5797 .data = &dataimage_fg040346dsswbg04, 5798 }, { 5799 .compatible = "dataimage,fg1001l0dsswmg01", 5800 .data = &dataimage_fg1001l0dsswmg01, 5801 }, { 5802 .compatible = "dataimage,scf0700c48ggu18", 5803 .data = &dataimage_scf0700c48ggu18, 5804 }, { 5805 .compatible = "displaytech,dt050btft-pts", 5806 .data = &displaytech_dt050btft_pts, 5807 }, { 5808 .compatible = "dlc,dlc0700yzg-1", 5809 .data = &dlc_dlc0700yzg_1, 5810 }, { 5811 .compatible = "dlc,dlc1010gig", 5812 .data = &dlc_dlc1010gig, 5813 }, { 5814 .compatible = "edt,et035012dm6", 5815 .data = &edt_et035012dm6, 5816 }, { 5817 .compatible = "edt,etm0350g0dh6", 5818 .data = &edt_etm0350g0dh6, 5819 }, { 5820 .compatible = "edt,etm043080dh6gp", 5821 .data = &edt_etm043080dh6gp, 5822 }, { 5823 .compatible = "edt,etm0430g0dh6", 5824 .data = &edt_etm0430g0dh6, 5825 }, { 5826 .compatible = "edt,et057023udba", 5827 .data = &edt_et057023udba, 5828 }, { 5829 .compatible = "edt,et057090dhu", 5830 .data = &edt_et057090dhu, 5831 }, { 5832 .compatible = "edt,et070080dh6", 5833 .data = &edt_etm0700g0dh6, 5834 }, { 5835 .compatible = "edt,etm0700g0dh6", 5836 .data = &edt_etm0700g0dh6, 5837 }, { 5838 .compatible = "edt,etm0700g0bdh6", 5839 .data = &edt_etm0700g0bdh6, 5840 }, { 5841 .compatible = "edt,etm0700g0edh6", 5842 .data = &edt_etm0700g0bdh6, 5843 }, { 5844 .compatible = "edt,etml0700y5dha", 5845 .data = &edt_etml0700y5dha, 5846 }, { 5847 .compatible = "edt,etml1010g3dra", 5848 .data = &edt_etml1010g3dra, 5849 }, { 5850 .compatible = "edt,etmv570g2dhu", 5851 .data = &edt_etmv570g2dhu, 5852 }, { 5853 .compatible = "eink,vb3300-kca", 5854 .data = &eink_vb3300_kca, 5855 }, { 5856 .compatible = "evervision,vgg644804", 5857 .data = &evervision_vgg644804, 5858 }, { 5859 .compatible = "evervision,vgg804821", 5860 .data = &evervision_vgg804821, 5861 }, { 5862 .compatible = "foxlink,fl500wvr00-a0t", 5863 .data = &foxlink_fl500wvr00_a0t, 5864 }, { 5865 .compatible = "frida,frd350h54004", 5866 .data = &frida_frd350h54004, 5867 }, { 5868 .compatible = "giantplus,gpg482739qs5", 5869 .data = &giantplus_gpg482739qs5 5870 }, { 5871 .compatible = "giantplus,gpm940b0", 5872 .data = &giantplus_gpm940b0, 5873 }, { 5874 .compatible = "hannstar,hsd070pww1", 5875 .data = &hannstar_hsd070pww1, 5876 }, { 5877 .compatible = "hannstar,hsd100pxn1", 5878 .data = &hannstar_hsd100pxn1, 5879 }, { 5880 .compatible = "hannstar,hsd101pww2", 5881 .data = &hannstar_hsd101pww2, 5882 }, { 5883 .compatible = "hannstar,hsd156juw2", 5884 .data = &hannstar_hsd156juw2, 5885 }, { 5886 .compatible = "hit,tx23d38vm0caa", 5887 .data = &hitachi_tx23d38vm0caa 5888 }, { 5889 .compatible = "innolux,at043tn24", 5890 .data = &innolux_at043tn24, 5891 }, { 5892 .compatible = "innolux,at070tn92", 5893 .data = &innolux_at070tn92, 5894 }, { 5895 .compatible = "innolux,g070ace-l01", 5896 .data = &innolux_g070ace_l01, 5897 }, { 5898 .compatible = "innolux,g070ace-lh3", 5899 .data = &innolux_g070ace_lh3, 5900 }, { 5901 .compatible = "innolux,g070y2-l01", 5902 .data = &innolux_g070y2_l01, 5903 }, { 5904 .compatible = "innolux,g070y2-t02", 5905 .data = &innolux_g070y2_t02, 5906 }, { 5907 .compatible = "innolux,g101ice-l01", 5908 .data = &innolux_g101ice_l01 5909 }, { 5910 .compatible = "innolux,g121i1-l01", 5911 .data = &innolux_g121i1_l01 5912 }, { 5913 .compatible = "innolux,g121x1-l03", 5914 .data = &innolux_g121x1_l03, 5915 }, { 5916 .compatible = "innolux,g121xce-l01", 5917 .data = &innolux_g121xce_l01, 5918 }, { 5919 .compatible = "innolux,g150xge-l05", 5920 .data = &innolux_g150xge_l05, 5921 }, { 5922 .compatible = "innolux,g156hce-l01", 5923 .data = &innolux_g156hce_l01, 5924 }, { 5925 .compatible = "innolux,n156bge-l21", 5926 .data = &innolux_n156bge_l21, 5927 }, { 5928 .compatible = "innolux,zj070na-01p", 5929 .data = &innolux_zj070na_01p, 5930 }, { 5931 .compatible = "jutouch,jt070tm041", 5932 .data = &jutouch_jt070tm041, 5933 }, { 5934 .compatible = "jutouch,jt101tm023", 5935 .data = &jutouch_jt101tm023, 5936 }, { 5937 .compatible = "koe,tx14d24vm1bpa", 5938 .data = &koe_tx14d24vm1bpa, 5939 }, { 5940 .compatible = "koe,tx26d202vm0bwa", 5941 .data = &koe_tx26d202vm0bwa, 5942 }, { 5943 .compatible = "koe,tx31d200vm0baa", 5944 .data = &koe_tx31d200vm0baa, 5945 }, { 5946 .compatible = "kyo,tcg070wvlq", 5947 .data = &lg_lb070wv8, 5948 }, { 5949 .compatible = "kyo,tcg121xglp", 5950 .data = &kyo_tcg121xglp, 5951 }, { 5952 .compatible = "lemaker,bl035-rgb-002", 5953 .data = &lemaker_bl035_rgb_002, 5954 }, { 5955 .compatible = "lg,lb070wv8", 5956 .data = &lg_lb070wv8, 5957 }, { 5958 .compatible = "lincolntech,lcd185-101ct", 5959 .data = &lincolntech_lcd185_101ct, 5960 }, { 5961 .compatible = "logicpd,type28", 5962 .data = &logicpd_type_28, 5963 }, { 5964 .compatible = "logictechno,lt161010-2nhc", 5965 .data = &logictechno_lt161010_2nh, 5966 }, { 5967 .compatible = "logictechno,lt161010-2nhr", 5968 .data = &logictechno_lt161010_2nh, 5969 }, { 5970 .compatible = "logictechno,lt170410-2whc", 5971 .data = &logictechno_lt170410_2whc, 5972 }, { 5973 .compatible = "logictechno,lttd800480070-l2rt", 5974 .data = &logictechno_lttd800480070_l2rt, 5975 }, { 5976 .compatible = "logictechno,lttd800480070-l6wh-rt", 5977 .data = &logictechno_lttd800480070_l6wh_rt, 5978 }, { 5979 .compatible = "microtips,mf-101hiebcaf0", 5980 .data = µtips_mf_101hiebcaf0_c, 5981 }, { 5982 .compatible = "microtips,mf-103hieb0ga0", 5983 .data = µtips_mf_103hieb0ga0, 5984 }, { 5985 .compatible = "mitsubishi,aa070mc01-ca1", 5986 .data = &mitsubishi_aa070mc01, 5987 }, { 5988 .compatible = "mitsubishi,aa084xe01", 5989 .data = &mitsubishi_aa084xe01, 5990 }, { 5991 .compatible = "multi-inno,mi0700a2t-30", 5992 .data = &multi_inno_mi0700a2t_30, 5993 }, { 5994 .compatible = "multi-inno,mi0700s4t-6", 5995 .data = &multi_inno_mi0700s4t_6, 5996 }, { 5997 .compatible = "multi-inno,mi0800ft-9", 5998 .data = &multi_inno_mi0800ft_9, 5999 }, { 6000 .compatible = "multi-inno,mi1010ait-1cp", 6001 .data = &multi_inno_mi1010ait_1cp, 6002 }, { 6003 .compatible = "multi-inno,mi1010z1t-1cp11", 6004 .data = &multi_inno_mi1010z1t_1cp11, 6005 }, { 6006 .compatible = "nec,nl12880bc20-05", 6007 .data = &nec_nl12880bc20_05, 6008 }, { 6009 .compatible = "nec,nl4827hc19-05b", 6010 .data = &nec_nl4827hc19_05b, 6011 }, { 6012 .compatible = "nec,nl6448bc33-70c", 6013 .data = &nec_nl6448bc33_70c, 6014 }, { 6015 .compatible = "netron-dy,e231732", 6016 .data = &netron_dy_e231732, 6017 }, { 6018 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 6019 .data = &newhaven_nhd_43_480272ef_atxl, 6020 }, { 6021 .compatible = "nlt,nl13676bc25-03f", 6022 .data = &nlt_nl13676bc25_03f, 6023 }, { 6024 .compatible = "nlt,nl192108ac18-02d", 6025 .data = &nlt_nl192108ac18_02d, 6026 }, { 6027 .compatible = "nvd,9128", 6028 .data = &nvd_9128, 6029 }, { 6030 .compatible = "okaya,rs800480t-7x0gp", 6031 .data = &okaya_rs800480t_7x0gp, 6032 }, { 6033 .compatible = "olimex,lcd-olinuxino-43-ts", 6034 .data = &olimex_lcd_olinuxino_43ts, 6035 }, { 6036 .compatible = "olimex,lcd-olinuxino-5-cts", 6037 .data = &olimex_lcd_olinuxino_5cts, 6038 }, { 6039 .compatible = "ontat,kd50g21-40nt-a1", 6040 .data = &ontat_kd50g21_40nt_a1, 6041 }, { 6042 .compatible = "ontat,yx700wv03", 6043 .data = &ontat_yx700wv03, 6044 }, { 6045 .compatible = "ortustech,com37h3m05dtc", 6046 .data = &ortustech_com37h3m, 6047 }, { 6048 .compatible = "ortustech,com37h3m99dtc", 6049 .data = &ortustech_com37h3m, 6050 }, { 6051 .compatible = "ortustech,com43h4m85ulc", 6052 .data = &ortustech_com43h4m85ulc, 6053 }, { 6054 .compatible = "osddisplays,osd070t1718-19ts", 6055 .data = &osddisplays_osd070t1718_19ts, 6056 }, { 6057 .compatible = "pda,91-00156-a0", 6058 .data = &pda_91_00156_a0, 6059 }, { 6060 .compatible = "powertip,ph128800t004-zza01", 6061 .data = &powertip_ph128800t004_zza01, 6062 }, { 6063 .compatible = "powertip,ph128800t006-zhc01", 6064 .data = &powertip_ph128800t006_zhc01, 6065 }, { 6066 .compatible = "powertip,ph800480t013-idf02", 6067 .data = &powertip_ph800480t013_idf02, 6068 }, { 6069 .compatible = "powertip,ph800480t032-zhc19", 6070 .data = &powertip_ph800480t032_zhc19, 6071 }, { 6072 .compatible = "primeview,pm070wl4", 6073 .data = &primeview_pm070wl4, 6074 }, { 6075 .compatible = "qiaodian,qd43003c0-40", 6076 .data = &qd43003c0_40, 6077 }, { 6078 .compatible = "qishenglong,gopher2b-lcd", 6079 .data = &qishenglong_gopher2b_lcd, 6080 }, { 6081 .compatible = "raystar,rff500f-awh-dnn", 6082 .data = &raystar_rff500f_awh_dnn, 6083 }, { 6084 .compatible = "rocktech,rk043fn48h", 6085 .data = &rocktech_rk043fn48h, 6086 }, { 6087 .compatible = "rocktech,rk070er9427", 6088 .data = &rocktech_rk070er9427, 6089 }, { 6090 .compatible = "rocktech,rk101ii01d-ct", 6091 .data = &rocktech_rk101ii01d_ct, 6092 }, { 6093 .compatible = "samsung,ltl101al01", 6094 .data = &samsung_ltl101al01, 6095 }, { 6096 .compatible = "samsung,ltl106al01", 6097 .data = &samsung_ltl106al01, 6098 }, { 6099 .compatible = "samsung,ltn101nt05", 6100 .data = &samsung_ltn101nt05, 6101 }, { 6102 .compatible = "satoz,sat050at40h12r2", 6103 .data = &satoz_sat050at40h12r2, 6104 }, { 6105 .compatible = "sharp,lq035q7db03", 6106 .data = &sharp_lq035q7db03, 6107 }, { 6108 .compatible = "sharp,lq070y3dg3b", 6109 .data = &sharp_lq070y3dg3b, 6110 }, { 6111 .compatible = "sharp,lq101k1ly04", 6112 .data = &sharp_lq101k1ly04, 6113 }, { 6114 .compatible = "sharp,ls020b1dd01d", 6115 .data = &sharp_ls020b1dd01d, 6116 }, { 6117 .compatible = "shelly,sca07010-bfn-lnn", 6118 .data = &shelly_sca07010_bfn_lnn, 6119 }, { 6120 .compatible = "starry,kr070pe2t", 6121 .data = &starry_kr070pe2t, 6122 }, { 6123 .compatible = "startek,kd070hdfld092", 6124 .data = &startek_kd070hdfld092, 6125 }, { 6126 .compatible = "startek,kd070wvfpa", 6127 .data = &startek_kd070wvfpa, 6128 }, { 6129 .compatible = "team-source-display,tst043015cmhx", 6130 .data = &tsd_tst043015cmhx, 6131 }, { 6132 .compatible = "tfc,s9700rtwv43tr-01b", 6133 .data = &tfc_s9700rtwv43tr_01b, 6134 }, { 6135 .compatible = "tianma,p0700wxf1mbaa", 6136 .data = &tianma_p0700wxf1mbaa, 6137 }, { 6138 .compatible = "tianma,tm050rdh03", 6139 .data = &ontat_kd50g21_40nt_a1, 6140 }, { 6141 .compatible = "tianma,tm070jdhg30", 6142 .data = &tianma_tm070jdhg30, 6143 }, { 6144 .compatible = "tianma,tm070jdhg34-00", 6145 .data = &tianma_tm070jdhg34_00, 6146 }, { 6147 .compatible = "tianma,tm070jvhg33", 6148 .data = &tianma_tm070jvhg33, 6149 }, { 6150 .compatible = "tianma,tm070rvhg71", 6151 .data = &tianma_tm070rvhg71, 6152 }, { 6153 .compatible = "ti,nspire-cx-lcd-panel", 6154 .data = &ti_nspire_cx_lcd_panel, 6155 }, { 6156 .compatible = "ti,nspire-classic-lcd-panel", 6157 .data = &ti_nspire_classic_lcd_panel, 6158 }, { 6159 .compatible = "toshiba,lt089ac29000", 6160 .data = &toshiba_lt089ac29000, 6161 }, { 6162 .compatible = "topland,tian-g07017-01", 6163 .data = &topland_tian_g07017_01, 6164 }, { 6165 .compatible = "tpk,f07a-0102", 6166 .data = &tpk_f07a_0102, 6167 }, { 6168 .compatible = "tpk,f10a-0102", 6169 .data = &tpk_f10a_0102, 6170 }, { 6171 .compatible = "urt,umsh-8596md-t", 6172 .data = &urt_umsh_8596md_parallel, 6173 }, { 6174 .compatible = "urt,umsh-8596md-1t", 6175 .data = &urt_umsh_8596md_parallel, 6176 }, { 6177 .compatible = "urt,umsh-8596md-7t", 6178 .data = &urt_umsh_8596md_parallel, 6179 }, { 6180 .compatible = "urt,umsh-8596md-11t", 6181 .data = &urt_umsh_8596md_lvds, 6182 }, { 6183 .compatible = "urt,umsh-8596md-19t", 6184 .data = &urt_umsh_8596md_lvds, 6185 }, { 6186 .compatible = "urt,umsh-8596md-20t", 6187 .data = &urt_umsh_8596md_parallel, 6188 }, { 6189 .compatible = "vivax,tpc9150-panel", 6190 .data = &vivax_tpc9150_panel, 6191 }, { 6192 .compatible = "vxt,vl050-8048nt-c01", 6193 .data = &vl050_8048nt_c01, 6194 }, { 6195 .compatible = "waveshare,2.8inch-panel", 6196 .data = &waveshare_28_lcd_panel 6197 }, { 6198 .compatible = "waveshare,3.4inch-c-panel", 6199 .data = &waveshare_34_lcd_c_panel 6200 }, { 6201 .compatible = "waveshare,4.0inch-panel", 6202 .data = &waveshare_40_lcd_panel 6203 }, { 6204 .compatible = "waveshare,4.0inch-c-panel", 6205 .data = &waveshare_40_lcd_c_panel 6206 }, { 6207 .compatible = "waveshare,5.0inch-c-panel", 6208 .data = &waveshare_50_lcd_c_panel 6209 }, { 6210 .compatible = "waveshare,5.0inch-d-panel", 6211 .data = &waveshare_50_lcd_d_panel 6212 }, { 6213 .compatible = "waveshare,6.25inch-panel", 6214 .data = &waveshare_625_lcd_panel 6215 }, { 6216 .compatible = "waveshare,7.0inch-c-panel", 6217 .data = &waveshare_70_lcd_c_panel 6218 }, { 6219 .compatible = "waveshare,7.0inch-e-panel", 6220 .data = &waveshare_70_lcd_e_panel 6221 }, { 6222 .compatible = "waveshare,7.0inch-h-panel", 6223 .data = &waveshare_70_lcd_h_panel 6224 }, { 6225 .compatible = "waveshare,7.9inch-panel", 6226 .data = &waveshare_79_lcd_panel 6227 }, { 6228 .compatible = "waveshare,8.0inch-c-panel", 6229 .data = &waveshare_80_lcd_c_panel 6230 }, { 6231 .compatible = "waveshare,8.8inch-panel", 6232 .data = &waveshare_88_lcd_panel 6233 }, { 6234 .compatible = "waveshare,10.1inch-c-panel", 6235 .data = &waveshare_101_lcd_c_panel 6236 }, { 6237 .compatible = "waveshare,11.9inch-panel", 6238 .data = &waveshare_119_lcd_panel 6239 }, { 6240 .compatible = "waveshare,13.3inch-panel", 6241 .data = &waveshare_133inch, 6242 }, { 6243 .compatible = "winstar,wf35ltiacd", 6244 .data = &winstar_wf35ltiacd, 6245 }, { 6246 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 6247 .data = &yes_optoelectronics_ytc700tlag_05_201c, 6248 }, { 6249 .compatible = "microchip,ac69t88a", 6250 .data = &mchp_ac69t88a, 6251 }, { 6252 /* Must be the last entry */ 6253 .compatible = "panel-dpi", 6254 6255 /* 6256 * Explicitly NULL, the panel_desc structure will be 6257 * allocated by panel_dpi_probe(). 6258 */ 6259 .data = NULL, 6260 }, { 6261 /* sentinel */ 6262 } 6263 }; 6264 MODULE_DEVICE_TABLE(of, platform_of_match); 6265 6266 static int panel_simple_platform_probe(struct platform_device *pdev) 6267 { 6268 struct panel_simple *panel; 6269 6270 panel = panel_simple_probe(&pdev->dev); 6271 if (IS_ERR(panel)) 6272 return PTR_ERR(panel); 6273 6274 return 0; 6275 } 6276 6277 static void panel_simple_platform_remove(struct platform_device *pdev) 6278 { 6279 panel_simple_remove(&pdev->dev); 6280 } 6281 6282 static void panel_simple_platform_shutdown(struct platform_device *pdev) 6283 { 6284 panel_simple_shutdown(&pdev->dev); 6285 } 6286 6287 static const struct dev_pm_ops panel_simple_pm_ops = { 6288 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 6289 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 6290 pm_runtime_force_resume) 6291 }; 6292 6293 static struct platform_driver panel_simple_platform_driver = { 6294 .driver = { 6295 .name = "panel-simple", 6296 .of_match_table = platform_of_match, 6297 .pm = &panel_simple_pm_ops, 6298 }, 6299 .probe = panel_simple_platform_probe, 6300 .remove = panel_simple_platform_remove, 6301 .shutdown = panel_simple_platform_shutdown, 6302 }; 6303 6304 static const struct drm_display_mode auo_b080uan01_mode = { 6305 .clock = 154500, 6306 .hdisplay = 1200, 6307 .hsync_start = 1200 + 62, 6308 .hsync_end = 1200 + 62 + 4, 6309 .htotal = 1200 + 62 + 4 + 62, 6310 .vdisplay = 1920, 6311 .vsync_start = 1920 + 9, 6312 .vsync_end = 1920 + 9 + 2, 6313 .vtotal = 1920 + 9 + 2 + 8, 6314 }; 6315 6316 static const struct panel_desc_dsi auo_b080uan01 = { 6317 .desc = { 6318 .modes = &auo_b080uan01_mode, 6319 .num_modes = 1, 6320 .bpc = 8, 6321 .size = { 6322 .width = 108, 6323 .height = 272, 6324 }, 6325 .connector_type = DRM_MODE_CONNECTOR_DSI, 6326 }, 6327 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 6328 .format = MIPI_DSI_FMT_RGB888, 6329 .lanes = 4, 6330 }; 6331 6332 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 6333 .clock = 160000, 6334 .hdisplay = 1200, 6335 .hsync_start = 1200 + 120, 6336 .hsync_end = 1200 + 120 + 20, 6337 .htotal = 1200 + 120 + 20 + 21, 6338 .vdisplay = 1920, 6339 .vsync_start = 1920 + 21, 6340 .vsync_end = 1920 + 21 + 3, 6341 .vtotal = 1920 + 21 + 3 + 18, 6342 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 6343 }; 6344 6345 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 6346 .desc = { 6347 .modes = &boe_tv080wum_nl0_mode, 6348 .num_modes = 1, 6349 .size = { 6350 .width = 107, 6351 .height = 172, 6352 }, 6353 .connector_type = DRM_MODE_CONNECTOR_DSI, 6354 }, 6355 .flags = MIPI_DSI_MODE_VIDEO | 6356 MIPI_DSI_MODE_VIDEO_BURST | 6357 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6358 .format = MIPI_DSI_FMT_RGB888, 6359 .lanes = 4, 6360 }; 6361 6362 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 6363 .clock = 67000, 6364 .hdisplay = 720, 6365 .hsync_start = 720 + 12, 6366 .hsync_end = 720 + 12 + 4, 6367 .htotal = 720 + 12 + 4 + 112, 6368 .vdisplay = 1280, 6369 .vsync_start = 1280 + 8, 6370 .vsync_end = 1280 + 8 + 4, 6371 .vtotal = 1280 + 8 + 4 + 12, 6372 }; 6373 6374 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 6375 .desc = { 6376 .modes = &lg_lh500wx1_sd03_mode, 6377 .num_modes = 1, 6378 .bpc = 8, 6379 .size = { 6380 .width = 62, 6381 .height = 110, 6382 }, 6383 .connector_type = DRM_MODE_CONNECTOR_DSI, 6384 }, 6385 .flags = MIPI_DSI_MODE_VIDEO, 6386 .format = MIPI_DSI_FMT_RGB888, 6387 .lanes = 4, 6388 }; 6389 6390 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 6391 .clock = 157200, 6392 .hdisplay = 1920, 6393 .hsync_start = 1920 + 154, 6394 .hsync_end = 1920 + 154 + 16, 6395 .htotal = 1920 + 154 + 16 + 32, 6396 .vdisplay = 1200, 6397 .vsync_start = 1200 + 17, 6398 .vsync_end = 1200 + 17 + 2, 6399 .vtotal = 1200 + 17 + 2 + 16, 6400 }; 6401 6402 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 6403 .desc = { 6404 .modes = &panasonic_vvx10f004b00_mode, 6405 .num_modes = 1, 6406 .bpc = 8, 6407 .size = { 6408 .width = 217, 6409 .height = 136, 6410 }, 6411 .connector_type = DRM_MODE_CONNECTOR_DSI, 6412 }, 6413 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6414 MIPI_DSI_CLOCK_NON_CONTINUOUS, 6415 .format = MIPI_DSI_FMT_RGB888, 6416 .lanes = 4, 6417 }; 6418 6419 static const struct drm_display_mode lg_acx467akm_7_mode = { 6420 .clock = 150000, 6421 .hdisplay = 1080, 6422 .hsync_start = 1080 + 2, 6423 .hsync_end = 1080 + 2 + 2, 6424 .htotal = 1080 + 2 + 2 + 2, 6425 .vdisplay = 1920, 6426 .vsync_start = 1920 + 2, 6427 .vsync_end = 1920 + 2 + 2, 6428 .vtotal = 1920 + 2 + 2 + 2, 6429 }; 6430 6431 static const struct panel_desc_dsi lg_acx467akm_7 = { 6432 .desc = { 6433 .modes = &lg_acx467akm_7_mode, 6434 .num_modes = 1, 6435 .bpc = 8, 6436 .size = { 6437 .width = 62, 6438 .height = 110, 6439 }, 6440 .connector_type = DRM_MODE_CONNECTOR_DSI, 6441 }, 6442 .flags = 0, 6443 .format = MIPI_DSI_FMT_RGB888, 6444 .lanes = 4, 6445 }; 6446 6447 static const struct drm_display_mode osd101t2045_53ts_mode = { 6448 .clock = 154500, 6449 .hdisplay = 1920, 6450 .hsync_start = 1920 + 112, 6451 .hsync_end = 1920 + 112 + 16, 6452 .htotal = 1920 + 112 + 16 + 32, 6453 .vdisplay = 1200, 6454 .vsync_start = 1200 + 16, 6455 .vsync_end = 1200 + 16 + 2, 6456 .vtotal = 1200 + 16 + 2 + 16, 6457 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 6458 }; 6459 6460 static const struct panel_desc_dsi osd101t2045_53ts = { 6461 .desc = { 6462 .modes = &osd101t2045_53ts_mode, 6463 .num_modes = 1, 6464 .bpc = 8, 6465 .size = { 6466 .width = 217, 6467 .height = 136, 6468 }, 6469 .connector_type = DRM_MODE_CONNECTOR_DSI, 6470 }, 6471 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 6472 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6473 MIPI_DSI_MODE_NO_EOT_PACKET, 6474 .format = MIPI_DSI_FMT_RGB888, 6475 .lanes = 4, 6476 }; 6477 6478 static const struct drm_display_mode tsd_tst070wsbe_196c_mode = { 6479 .clock = 52477, 6480 .hdisplay = 1024, 6481 .hsync_start = 1024 + 160, 6482 .hsync_end = 1024 + 160 + 12, 6483 .htotal = 1024 + 160 + 160 + 12, 6484 .vdisplay = 600, 6485 .vsync_start = 600 + 12, 6486 .vsync_end = 600 + 12 + 10, 6487 .vtotal = 600 + 12 + 10 + 23, 6488 }; 6489 6490 static const struct panel_desc_dsi tsd_tst070wsbe_196c = { 6491 .desc = { 6492 .modes = &tsd_tst070wsbe_196c_mode, 6493 .num_modes = 1, 6494 .bpc = 8, 6495 .size = { 6496 .width = 190, 6497 .height = 121, 6498 }, 6499 .delay = { 6500 .prepare = 20, 6501 }, 6502 .connector_type = DRM_MODE_CONNECTOR_DSI, 6503 }, 6504 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | 6505 MIPI_DSI_MODE_VIDEO_BURST | 6506 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6507 .format = MIPI_DSI_FMT_RGB888, 6508 .lanes = 4, 6509 }; 6510 6511 static const struct of_device_id dsi_of_match[] = { 6512 { 6513 .compatible = "auo,b080uan01", 6514 .data = &auo_b080uan01 6515 }, { 6516 .compatible = "boe,tv080wum-nl0", 6517 .data = &boe_tv080wum_nl0 6518 }, { 6519 .compatible = "lg,lh500wx1-sd03", 6520 .data = &lg_lh500wx1_sd03 6521 }, { 6522 .compatible = "panasonic,vvx10f004b00", 6523 .data = &panasonic_vvx10f004b00 6524 }, { 6525 .compatible = "lg,acx467akm-7", 6526 .data = &lg_acx467akm_7 6527 }, { 6528 .compatible = "osddisplays,osd101t2045-53ts", 6529 .data = &osd101t2045_53ts 6530 }, { 6531 .compatible = "team-source-display,tst070wsbe-196c", 6532 .data = &tsd_tst070wsbe_196c 6533 }, { 6534 /* sentinel */ 6535 } 6536 }; 6537 MODULE_DEVICE_TABLE(of, dsi_of_match); 6538 6539 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 6540 { 6541 const struct panel_desc_dsi *desc; 6542 struct panel_simple *panel; 6543 int err; 6544 6545 panel = panel_simple_probe(&dsi->dev); 6546 if (IS_ERR(panel)) 6547 return PTR_ERR(panel); 6548 6549 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 6550 dsi->mode_flags = desc->flags; 6551 dsi->format = desc->format; 6552 dsi->lanes = desc->lanes; 6553 6554 err = mipi_dsi_attach(dsi); 6555 if (err) { 6556 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 6557 6558 drm_panel_remove(&panel->base); 6559 } 6560 6561 return err; 6562 } 6563 6564 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 6565 { 6566 int err; 6567 6568 err = mipi_dsi_detach(dsi); 6569 if (err < 0) 6570 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 6571 6572 panel_simple_remove(&dsi->dev); 6573 } 6574 6575 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 6576 { 6577 panel_simple_shutdown(&dsi->dev); 6578 } 6579 6580 static struct mipi_dsi_driver panel_simple_dsi_driver = { 6581 .driver = { 6582 .name = "panel-simple-dsi", 6583 .of_match_table = dsi_of_match, 6584 .pm = &panel_simple_pm_ops, 6585 }, 6586 .probe = panel_simple_dsi_probe, 6587 .remove = panel_simple_dsi_remove, 6588 .shutdown = panel_simple_dsi_shutdown, 6589 }; 6590 6591 static int __init panel_simple_init(void) 6592 { 6593 int err; 6594 6595 err = platform_driver_register(&panel_simple_platform_driver); 6596 if (err < 0) 6597 return err; 6598 6599 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 6600 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 6601 if (err < 0) 6602 goto err_did_platform_register; 6603 } 6604 6605 return 0; 6606 6607 err_did_platform_register: 6608 platform_driver_unregister(&panel_simple_platform_driver); 6609 6610 return err; 6611 } 6612 module_init(panel_simple_init); 6613 6614 static void __exit panel_simple_exit(void) 6615 { 6616 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6617 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 6618 6619 platform_driver_unregister(&panel_simple_platform_driver); 6620 } 6621 module_exit(panel_simple_exit); 6622 6623 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 6624 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 6625 MODULE_LICENSE("GPL and additional rights"); 6626