1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 60 * Plug Detect isn't used. 61 * @enable: the time (in milliseconds) that it takes for the panel to 62 * display the first valid frame after starting to receive 63 * video data 64 * @disable: the time (in milliseconds) that it takes for the panel to 65 * turn the display off (no content is visible) 66 * @unprepare: the time (in milliseconds) that it takes for the panel 67 * to power itself down completely 68 */ 69 struct { 70 unsigned int prepare; 71 unsigned int hpd_absent_delay; 72 unsigned int enable; 73 unsigned int disable; 74 unsigned int unprepare; 75 } delay; 76 77 u32 bus_format; 78 u32 bus_flags; 79 }; 80 81 struct panel_simple { 82 struct drm_panel base; 83 bool prepared; 84 bool enabled; 85 bool no_hpd; 86 87 const struct panel_desc *desc; 88 89 struct backlight_device *backlight; 90 struct regulator *supply; 91 struct i2c_adapter *ddc; 92 93 struct gpio_desc *enable_gpio; 94 }; 95 96 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 97 { 98 return container_of(panel, struct panel_simple, base); 99 } 100 101 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 102 { 103 struct drm_connector *connector = panel->base.connector; 104 struct drm_device *drm = panel->base.drm; 105 struct drm_display_mode *mode; 106 unsigned int i, num = 0; 107 108 if (!panel->desc) 109 return 0; 110 111 for (i = 0; i < panel->desc->num_timings; i++) { 112 const struct display_timing *dt = &panel->desc->timings[i]; 113 struct videomode vm; 114 115 videomode_from_timing(dt, &vm); 116 mode = drm_mode_create(drm); 117 if (!mode) { 118 dev_err(drm->dev, "failed to add mode %ux%u\n", 119 dt->hactive.typ, dt->vactive.typ); 120 continue; 121 } 122 123 drm_display_mode_from_videomode(&vm, mode); 124 125 mode->type |= DRM_MODE_TYPE_DRIVER; 126 127 if (panel->desc->num_timings == 1) 128 mode->type |= DRM_MODE_TYPE_PREFERRED; 129 130 drm_mode_probed_add(connector, mode); 131 num++; 132 } 133 134 for (i = 0; i < panel->desc->num_modes; i++) { 135 const struct drm_display_mode *m = &panel->desc->modes[i]; 136 137 mode = drm_mode_duplicate(drm, m); 138 if (!mode) { 139 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 140 m->hdisplay, m->vdisplay, m->vrefresh); 141 continue; 142 } 143 144 mode->type |= DRM_MODE_TYPE_DRIVER; 145 146 if (panel->desc->num_modes == 1) 147 mode->type |= DRM_MODE_TYPE_PREFERRED; 148 149 drm_mode_set_name(mode); 150 151 drm_mode_probed_add(connector, mode); 152 num++; 153 } 154 155 connector->display_info.bpc = panel->desc->bpc; 156 connector->display_info.width_mm = panel->desc->size.width; 157 connector->display_info.height_mm = panel->desc->size.height; 158 if (panel->desc->bus_format) 159 drm_display_info_set_bus_formats(&connector->display_info, 160 &panel->desc->bus_format, 1); 161 connector->display_info.bus_flags = panel->desc->bus_flags; 162 163 return num; 164 } 165 166 static int panel_simple_disable(struct drm_panel *panel) 167 { 168 struct panel_simple *p = to_panel_simple(panel); 169 170 if (!p->enabled) 171 return 0; 172 173 if (p->backlight) { 174 p->backlight->props.power = FB_BLANK_POWERDOWN; 175 p->backlight->props.state |= BL_CORE_FBBLANK; 176 backlight_update_status(p->backlight); 177 } 178 179 if (p->desc->delay.disable) 180 msleep(p->desc->delay.disable); 181 182 p->enabled = false; 183 184 return 0; 185 } 186 187 static int panel_simple_unprepare(struct drm_panel *panel) 188 { 189 struct panel_simple *p = to_panel_simple(panel); 190 191 if (!p->prepared) 192 return 0; 193 194 gpiod_set_value_cansleep(p->enable_gpio, 0); 195 196 regulator_disable(p->supply); 197 198 if (p->desc->delay.unprepare) 199 msleep(p->desc->delay.unprepare); 200 201 p->prepared = false; 202 203 return 0; 204 } 205 206 static int panel_simple_prepare(struct drm_panel *panel) 207 { 208 struct panel_simple *p = to_panel_simple(panel); 209 unsigned int delay; 210 int err; 211 212 if (p->prepared) 213 return 0; 214 215 err = regulator_enable(p->supply); 216 if (err < 0) { 217 dev_err(panel->dev, "failed to enable supply: %d\n", err); 218 return err; 219 } 220 221 gpiod_set_value_cansleep(p->enable_gpio, 1); 222 223 delay = p->desc->delay.prepare; 224 if (p->no_hpd) 225 delay += p->desc->delay.hpd_absent_delay; 226 if (delay) 227 msleep(delay); 228 229 p->prepared = true; 230 231 return 0; 232 } 233 234 static int panel_simple_enable(struct drm_panel *panel) 235 { 236 struct panel_simple *p = to_panel_simple(panel); 237 238 if (p->enabled) 239 return 0; 240 241 if (p->desc->delay.enable) 242 msleep(p->desc->delay.enable); 243 244 if (p->backlight) { 245 p->backlight->props.state &= ~BL_CORE_FBBLANK; 246 p->backlight->props.power = FB_BLANK_UNBLANK; 247 backlight_update_status(p->backlight); 248 } 249 250 p->enabled = true; 251 252 return 0; 253 } 254 255 static int panel_simple_get_modes(struct drm_panel *panel) 256 { 257 struct panel_simple *p = to_panel_simple(panel); 258 int num = 0; 259 260 /* probe EDID if a DDC bus is available */ 261 if (p->ddc) { 262 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 263 drm_connector_update_edid_property(panel->connector, edid); 264 if (edid) { 265 num += drm_add_edid_modes(panel->connector, edid); 266 kfree(edid); 267 } 268 } 269 270 /* add hard-coded panel modes */ 271 num += panel_simple_get_fixed_modes(p); 272 273 return num; 274 } 275 276 static int panel_simple_get_timings(struct drm_panel *panel, 277 unsigned int num_timings, 278 struct display_timing *timings) 279 { 280 struct panel_simple *p = to_panel_simple(panel); 281 unsigned int i; 282 283 if (p->desc->num_timings < num_timings) 284 num_timings = p->desc->num_timings; 285 286 if (timings) 287 for (i = 0; i < num_timings; i++) 288 timings[i] = p->desc->timings[i]; 289 290 return p->desc->num_timings; 291 } 292 293 static const struct drm_panel_funcs panel_simple_funcs = { 294 .disable = panel_simple_disable, 295 .unprepare = panel_simple_unprepare, 296 .prepare = panel_simple_prepare, 297 .enable = panel_simple_enable, 298 .get_modes = panel_simple_get_modes, 299 .get_timings = panel_simple_get_timings, 300 }; 301 302 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 303 { 304 struct device_node *backlight, *ddc; 305 struct panel_simple *panel; 306 int err; 307 308 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 309 if (!panel) 310 return -ENOMEM; 311 312 panel->enabled = false; 313 panel->prepared = false; 314 panel->desc = desc; 315 316 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 317 318 panel->supply = devm_regulator_get(dev, "power"); 319 if (IS_ERR(panel->supply)) 320 return PTR_ERR(panel->supply); 321 322 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 323 GPIOD_OUT_LOW); 324 if (IS_ERR(panel->enable_gpio)) { 325 err = PTR_ERR(panel->enable_gpio); 326 if (err != -EPROBE_DEFER) 327 dev_err(dev, "failed to request GPIO: %d\n", err); 328 return err; 329 } 330 331 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 332 if (backlight) { 333 panel->backlight = of_find_backlight_by_node(backlight); 334 of_node_put(backlight); 335 336 if (!panel->backlight) 337 return -EPROBE_DEFER; 338 } 339 340 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 341 if (ddc) { 342 panel->ddc = of_find_i2c_adapter_by_node(ddc); 343 of_node_put(ddc); 344 345 if (!panel->ddc) { 346 err = -EPROBE_DEFER; 347 goto free_backlight; 348 } 349 } 350 351 drm_panel_init(&panel->base); 352 panel->base.dev = dev; 353 panel->base.funcs = &panel_simple_funcs; 354 355 err = drm_panel_add(&panel->base); 356 if (err < 0) 357 goto free_ddc; 358 359 dev_set_drvdata(dev, panel); 360 361 return 0; 362 363 free_ddc: 364 if (panel->ddc) 365 put_device(&panel->ddc->dev); 366 free_backlight: 367 if (panel->backlight) 368 put_device(&panel->backlight->dev); 369 370 return err; 371 } 372 373 static int panel_simple_remove(struct device *dev) 374 { 375 struct panel_simple *panel = dev_get_drvdata(dev); 376 377 drm_panel_remove(&panel->base); 378 379 panel_simple_disable(&panel->base); 380 panel_simple_unprepare(&panel->base); 381 382 if (panel->ddc) 383 put_device(&panel->ddc->dev); 384 385 if (panel->backlight) 386 put_device(&panel->backlight->dev); 387 388 return 0; 389 } 390 391 static void panel_simple_shutdown(struct device *dev) 392 { 393 struct panel_simple *panel = dev_get_drvdata(dev); 394 395 panel_simple_disable(&panel->base); 396 panel_simple_unprepare(&panel->base); 397 } 398 399 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 400 .clock = 9000, 401 .hdisplay = 480, 402 .hsync_start = 480 + 2, 403 .hsync_end = 480 + 2 + 41, 404 .htotal = 480 + 2 + 41 + 2, 405 .vdisplay = 272, 406 .vsync_start = 272 + 2, 407 .vsync_end = 272 + 2 + 10, 408 .vtotal = 272 + 2 + 10 + 2, 409 .vrefresh = 60, 410 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 411 }; 412 413 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 414 .modes = &ire_am_480272h3tmqw_t01h_mode, 415 .num_modes = 1, 416 .bpc = 8, 417 .size = { 418 .width = 105, 419 .height = 67, 420 }, 421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 422 }; 423 424 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 425 .clock = 33333, 426 .hdisplay = 800, 427 .hsync_start = 800 + 0, 428 .hsync_end = 800 + 0 + 255, 429 .htotal = 800 + 0 + 255 + 0, 430 .vdisplay = 480, 431 .vsync_start = 480 + 2, 432 .vsync_end = 480 + 2 + 45, 433 .vtotal = 480 + 2 + 45 + 0, 434 .vrefresh = 60, 435 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 436 }; 437 438 static const struct panel_desc ampire_am800480r3tmqwa1h = { 439 .modes = &ire_am800480r3tmqwa1h_mode, 440 .num_modes = 1, 441 .bpc = 6, 442 .size = { 443 .width = 152, 444 .height = 91, 445 }, 446 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 447 }; 448 449 static const struct drm_display_mode auo_b101aw03_mode = { 450 .clock = 51450, 451 .hdisplay = 1024, 452 .hsync_start = 1024 + 156, 453 .hsync_end = 1024 + 156 + 8, 454 .htotal = 1024 + 156 + 8 + 156, 455 .vdisplay = 600, 456 .vsync_start = 600 + 16, 457 .vsync_end = 600 + 16 + 6, 458 .vtotal = 600 + 16 + 6 + 16, 459 .vrefresh = 60, 460 }; 461 462 static const struct panel_desc auo_b101aw03 = { 463 .modes = &auo_b101aw03_mode, 464 .num_modes = 1, 465 .bpc = 6, 466 .size = { 467 .width = 223, 468 .height = 125, 469 }, 470 }; 471 472 static const struct drm_display_mode auo_b101ean01_mode = { 473 .clock = 72500, 474 .hdisplay = 1280, 475 .hsync_start = 1280 + 119, 476 .hsync_end = 1280 + 119 + 32, 477 .htotal = 1280 + 119 + 32 + 21, 478 .vdisplay = 800, 479 .vsync_start = 800 + 4, 480 .vsync_end = 800 + 4 + 20, 481 .vtotal = 800 + 4 + 20 + 8, 482 .vrefresh = 60, 483 }; 484 485 static const struct panel_desc auo_b101ean01 = { 486 .modes = &auo_b101ean01_mode, 487 .num_modes = 1, 488 .bpc = 6, 489 .size = { 490 .width = 217, 491 .height = 136, 492 }, 493 }; 494 495 static const struct drm_display_mode auo_b101xtn01_mode = { 496 .clock = 72000, 497 .hdisplay = 1366, 498 .hsync_start = 1366 + 20, 499 .hsync_end = 1366 + 20 + 70, 500 .htotal = 1366 + 20 + 70, 501 .vdisplay = 768, 502 .vsync_start = 768 + 14, 503 .vsync_end = 768 + 14 + 42, 504 .vtotal = 768 + 14 + 42, 505 .vrefresh = 60, 506 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 507 }; 508 509 static const struct panel_desc auo_b101xtn01 = { 510 .modes = &auo_b101xtn01_mode, 511 .num_modes = 1, 512 .bpc = 6, 513 .size = { 514 .width = 223, 515 .height = 125, 516 }, 517 }; 518 519 static const struct drm_display_mode auo_b116xw03_mode = { 520 .clock = 70589, 521 .hdisplay = 1366, 522 .hsync_start = 1366 + 40, 523 .hsync_end = 1366 + 40 + 40, 524 .htotal = 1366 + 40 + 40 + 32, 525 .vdisplay = 768, 526 .vsync_start = 768 + 10, 527 .vsync_end = 768 + 10 + 12, 528 .vtotal = 768 + 10 + 12 + 6, 529 .vrefresh = 60, 530 }; 531 532 static const struct panel_desc auo_b116xw03 = { 533 .modes = &auo_b116xw03_mode, 534 .num_modes = 1, 535 .bpc = 6, 536 .size = { 537 .width = 256, 538 .height = 144, 539 }, 540 }; 541 542 static const struct drm_display_mode auo_b133xtn01_mode = { 543 .clock = 69500, 544 .hdisplay = 1366, 545 .hsync_start = 1366 + 48, 546 .hsync_end = 1366 + 48 + 32, 547 .htotal = 1366 + 48 + 32 + 20, 548 .vdisplay = 768, 549 .vsync_start = 768 + 3, 550 .vsync_end = 768 + 3 + 6, 551 .vtotal = 768 + 3 + 6 + 13, 552 .vrefresh = 60, 553 }; 554 555 static const struct panel_desc auo_b133xtn01 = { 556 .modes = &auo_b133xtn01_mode, 557 .num_modes = 1, 558 .bpc = 6, 559 .size = { 560 .width = 293, 561 .height = 165, 562 }, 563 }; 564 565 static const struct drm_display_mode auo_b133htn01_mode = { 566 .clock = 150660, 567 .hdisplay = 1920, 568 .hsync_start = 1920 + 172, 569 .hsync_end = 1920 + 172 + 80, 570 .htotal = 1920 + 172 + 80 + 60, 571 .vdisplay = 1080, 572 .vsync_start = 1080 + 25, 573 .vsync_end = 1080 + 25 + 10, 574 .vtotal = 1080 + 25 + 10 + 10, 575 .vrefresh = 60, 576 }; 577 578 static const struct panel_desc auo_b133htn01 = { 579 .modes = &auo_b133htn01_mode, 580 .num_modes = 1, 581 .bpc = 6, 582 .size = { 583 .width = 293, 584 .height = 165, 585 }, 586 .delay = { 587 .prepare = 105, 588 .enable = 20, 589 .unprepare = 50, 590 }, 591 }; 592 593 static const struct display_timing auo_g070vvn01_timings = { 594 .pixelclock = { 33300000, 34209000, 45000000 }, 595 .hactive = { 800, 800, 800 }, 596 .hfront_porch = { 20, 40, 200 }, 597 .hback_porch = { 87, 40, 1 }, 598 .hsync_len = { 1, 48, 87 }, 599 .vactive = { 480, 480, 480 }, 600 .vfront_porch = { 5, 13, 200 }, 601 .vback_porch = { 31, 31, 29 }, 602 .vsync_len = { 1, 1, 3 }, 603 }; 604 605 static const struct panel_desc auo_g070vvn01 = { 606 .timings = &auo_g070vvn01_timings, 607 .num_timings = 1, 608 .bpc = 8, 609 .size = { 610 .width = 152, 611 .height = 91, 612 }, 613 .delay = { 614 .prepare = 200, 615 .enable = 50, 616 .disable = 50, 617 .unprepare = 1000, 618 }, 619 }; 620 621 static const struct drm_display_mode auo_g101evn010_mode = { 622 .clock = 68930, 623 .hdisplay = 1280, 624 .hsync_start = 1280 + 82, 625 .hsync_end = 1280 + 82 + 2, 626 .htotal = 1280 + 82 + 2 + 84, 627 .vdisplay = 800, 628 .vsync_start = 800 + 8, 629 .vsync_end = 800 + 8 + 2, 630 .vtotal = 800 + 8 + 2 + 6, 631 .vrefresh = 60, 632 }; 633 634 static const struct panel_desc auo_g101evn010 = { 635 .modes = &auo_g101evn010_mode, 636 .num_modes = 1, 637 .bpc = 6, 638 .size = { 639 .width = 216, 640 .height = 135, 641 }, 642 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 643 }; 644 645 static const struct drm_display_mode auo_g104sn02_mode = { 646 .clock = 40000, 647 .hdisplay = 800, 648 .hsync_start = 800 + 40, 649 .hsync_end = 800 + 40 + 216, 650 .htotal = 800 + 40 + 216 + 128, 651 .vdisplay = 600, 652 .vsync_start = 600 + 10, 653 .vsync_end = 600 + 10 + 35, 654 .vtotal = 600 + 10 + 35 + 2, 655 .vrefresh = 60, 656 }; 657 658 static const struct panel_desc auo_g104sn02 = { 659 .modes = &auo_g104sn02_mode, 660 .num_modes = 1, 661 .bpc = 8, 662 .size = { 663 .width = 211, 664 .height = 158, 665 }, 666 }; 667 668 static const struct display_timing auo_g133han01_timings = { 669 .pixelclock = { 134000000, 141200000, 149000000 }, 670 .hactive = { 1920, 1920, 1920 }, 671 .hfront_porch = { 39, 58, 77 }, 672 .hback_porch = { 59, 88, 117 }, 673 .hsync_len = { 28, 42, 56 }, 674 .vactive = { 1080, 1080, 1080 }, 675 .vfront_porch = { 3, 8, 11 }, 676 .vback_porch = { 5, 14, 19 }, 677 .vsync_len = { 4, 14, 19 }, 678 }; 679 680 static const struct panel_desc auo_g133han01 = { 681 .timings = &auo_g133han01_timings, 682 .num_timings = 1, 683 .bpc = 8, 684 .size = { 685 .width = 293, 686 .height = 165, 687 }, 688 .delay = { 689 .prepare = 200, 690 .enable = 50, 691 .disable = 50, 692 .unprepare = 1000, 693 }, 694 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 695 }; 696 697 static const struct display_timing auo_g185han01_timings = { 698 .pixelclock = { 120000000, 144000000, 175000000 }, 699 .hactive = { 1920, 1920, 1920 }, 700 .hfront_porch = { 18, 60, 74 }, 701 .hback_porch = { 12, 44, 54 }, 702 .hsync_len = { 10, 24, 32 }, 703 .vactive = { 1080, 1080, 1080 }, 704 .vfront_porch = { 6, 10, 40 }, 705 .vback_porch = { 2, 5, 20 }, 706 .vsync_len = { 2, 5, 20 }, 707 }; 708 709 static const struct panel_desc auo_g185han01 = { 710 .timings = &auo_g185han01_timings, 711 .num_timings = 1, 712 .bpc = 8, 713 .size = { 714 .width = 409, 715 .height = 230, 716 }, 717 .delay = { 718 .prepare = 50, 719 .enable = 200, 720 .disable = 110, 721 .unprepare = 1000, 722 }, 723 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 724 }; 725 726 static const struct display_timing auo_p320hvn03_timings = { 727 .pixelclock = { 106000000, 148500000, 164000000 }, 728 .hactive = { 1920, 1920, 1920 }, 729 .hfront_porch = { 25, 50, 130 }, 730 .hback_porch = { 25, 50, 130 }, 731 .hsync_len = { 20, 40, 105 }, 732 .vactive = { 1080, 1080, 1080 }, 733 .vfront_porch = { 8, 17, 150 }, 734 .vback_porch = { 8, 17, 150 }, 735 .vsync_len = { 4, 11, 100 }, 736 }; 737 738 static const struct panel_desc auo_p320hvn03 = { 739 .timings = &auo_p320hvn03_timings, 740 .num_timings = 1, 741 .bpc = 8, 742 .size = { 743 .width = 698, 744 .height = 393, 745 }, 746 .delay = { 747 .prepare = 1, 748 .enable = 450, 749 .unprepare = 500, 750 }, 751 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 752 }; 753 754 static const struct drm_display_mode auo_t215hvn01_mode = { 755 .clock = 148800, 756 .hdisplay = 1920, 757 .hsync_start = 1920 + 88, 758 .hsync_end = 1920 + 88 + 44, 759 .htotal = 1920 + 88 + 44 + 148, 760 .vdisplay = 1080, 761 .vsync_start = 1080 + 4, 762 .vsync_end = 1080 + 4 + 5, 763 .vtotal = 1080 + 4 + 5 + 36, 764 .vrefresh = 60, 765 }; 766 767 static const struct panel_desc auo_t215hvn01 = { 768 .modes = &auo_t215hvn01_mode, 769 .num_modes = 1, 770 .bpc = 8, 771 .size = { 772 .width = 430, 773 .height = 270, 774 }, 775 .delay = { 776 .disable = 5, 777 .unprepare = 1000, 778 } 779 }; 780 781 static const struct drm_display_mode avic_tm070ddh03_mode = { 782 .clock = 51200, 783 .hdisplay = 1024, 784 .hsync_start = 1024 + 160, 785 .hsync_end = 1024 + 160 + 4, 786 .htotal = 1024 + 160 + 4 + 156, 787 .vdisplay = 600, 788 .vsync_start = 600 + 17, 789 .vsync_end = 600 + 17 + 1, 790 .vtotal = 600 + 17 + 1 + 17, 791 .vrefresh = 60, 792 }; 793 794 static const struct panel_desc avic_tm070ddh03 = { 795 .modes = &avic_tm070ddh03_mode, 796 .num_modes = 1, 797 .bpc = 8, 798 .size = { 799 .width = 154, 800 .height = 90, 801 }, 802 .delay = { 803 .prepare = 20, 804 .enable = 200, 805 .disable = 200, 806 }, 807 }; 808 809 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 810 .clock = 30000, 811 .hdisplay = 800, 812 .hsync_start = 800 + 40, 813 .hsync_end = 800 + 40 + 48, 814 .htotal = 800 + 40 + 48 + 40, 815 .vdisplay = 480, 816 .vsync_start = 480 + 13, 817 .vsync_end = 480 + 13 + 3, 818 .vtotal = 480 + 13 + 3 + 29, 819 }; 820 821 static const struct panel_desc bananapi_s070wv20_ct16 = { 822 .modes = &bananapi_s070wv20_ct16_mode, 823 .num_modes = 1, 824 .bpc = 6, 825 .size = { 826 .width = 154, 827 .height = 86, 828 }, 829 }; 830 831 static const struct drm_display_mode boe_hv070wsa_mode = { 832 .clock = 42105, 833 .hdisplay = 1024, 834 .hsync_start = 1024 + 30, 835 .hsync_end = 1024 + 30 + 30, 836 .htotal = 1024 + 30 + 30 + 30, 837 .vdisplay = 600, 838 .vsync_start = 600 + 10, 839 .vsync_end = 600 + 10 + 10, 840 .vtotal = 600 + 10 + 10 + 10, 841 .vrefresh = 60, 842 }; 843 844 static const struct panel_desc boe_hv070wsa = { 845 .modes = &boe_hv070wsa_mode, 846 .num_modes = 1, 847 .size = { 848 .width = 154, 849 .height = 90, 850 }, 851 }; 852 853 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 854 { 855 .clock = 71900, 856 .hdisplay = 1280, 857 .hsync_start = 1280 + 48, 858 .hsync_end = 1280 + 48 + 32, 859 .htotal = 1280 + 48 + 32 + 80, 860 .vdisplay = 800, 861 .vsync_start = 800 + 3, 862 .vsync_end = 800 + 3 + 5, 863 .vtotal = 800 + 3 + 5 + 24, 864 .vrefresh = 60, 865 }, 866 { 867 .clock = 57500, 868 .hdisplay = 1280, 869 .hsync_start = 1280 + 48, 870 .hsync_end = 1280 + 48 + 32, 871 .htotal = 1280 + 48 + 32 + 80, 872 .vdisplay = 800, 873 .vsync_start = 800 + 3, 874 .vsync_end = 800 + 3 + 5, 875 .vtotal = 800 + 3 + 5 + 24, 876 .vrefresh = 48, 877 }, 878 }; 879 880 static const struct panel_desc boe_nv101wxmn51 = { 881 .modes = boe_nv101wxmn51_modes, 882 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 883 .bpc = 8, 884 .size = { 885 .width = 217, 886 .height = 136, 887 }, 888 .delay = { 889 .prepare = 210, 890 .enable = 50, 891 .unprepare = 160, 892 }, 893 }; 894 895 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 896 .clock = 9000, 897 .hdisplay = 480, 898 .hsync_start = 480 + 5, 899 .hsync_end = 480 + 5 + 5, 900 .htotal = 480 + 5 + 5 + 40, 901 .vdisplay = 272, 902 .vsync_start = 272 + 8, 903 .vsync_end = 272 + 8 + 8, 904 .vtotal = 272 + 8 + 8 + 8, 905 .vrefresh = 60, 906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 907 }; 908 909 static const struct panel_desc cdtech_s043wq26h_ct7 = { 910 .modes = &cdtech_s043wq26h_ct7_mode, 911 .num_modes = 1, 912 .bpc = 8, 913 .size = { 914 .width = 95, 915 .height = 54, 916 }, 917 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 918 }; 919 920 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 921 .clock = 35000, 922 .hdisplay = 800, 923 .hsync_start = 800 + 40, 924 .hsync_end = 800 + 40 + 40, 925 .htotal = 800 + 40 + 40 + 48, 926 .vdisplay = 480, 927 .vsync_start = 480 + 29, 928 .vsync_end = 480 + 29 + 13, 929 .vtotal = 480 + 29 + 13 + 3, 930 .vrefresh = 60, 931 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 932 }; 933 934 static const struct panel_desc cdtech_s070wv95_ct16 = { 935 .modes = &cdtech_s070wv95_ct16_mode, 936 .num_modes = 1, 937 .bpc = 8, 938 .size = { 939 .width = 154, 940 .height = 85, 941 }, 942 }; 943 944 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 945 .clock = 66770, 946 .hdisplay = 800, 947 .hsync_start = 800 + 49, 948 .hsync_end = 800 + 49 + 33, 949 .htotal = 800 + 49 + 33 + 17, 950 .vdisplay = 1280, 951 .vsync_start = 1280 + 1, 952 .vsync_end = 1280 + 1 + 7, 953 .vtotal = 1280 + 1 + 7 + 15, 954 .vrefresh = 60, 955 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 956 }; 957 958 static const struct panel_desc chunghwa_claa070wp03xg = { 959 .modes = &chunghwa_claa070wp03xg_mode, 960 .num_modes = 1, 961 .bpc = 6, 962 .size = { 963 .width = 94, 964 .height = 150, 965 }, 966 }; 967 968 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 969 .clock = 72070, 970 .hdisplay = 1366, 971 .hsync_start = 1366 + 58, 972 .hsync_end = 1366 + 58 + 58, 973 .htotal = 1366 + 58 + 58 + 58, 974 .vdisplay = 768, 975 .vsync_start = 768 + 4, 976 .vsync_end = 768 + 4 + 4, 977 .vtotal = 768 + 4 + 4 + 4, 978 .vrefresh = 60, 979 }; 980 981 static const struct panel_desc chunghwa_claa101wa01a = { 982 .modes = &chunghwa_claa101wa01a_mode, 983 .num_modes = 1, 984 .bpc = 6, 985 .size = { 986 .width = 220, 987 .height = 120, 988 }, 989 }; 990 991 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 992 .clock = 69300, 993 .hdisplay = 1366, 994 .hsync_start = 1366 + 48, 995 .hsync_end = 1366 + 48 + 32, 996 .htotal = 1366 + 48 + 32 + 20, 997 .vdisplay = 768, 998 .vsync_start = 768 + 16, 999 .vsync_end = 768 + 16 + 8, 1000 .vtotal = 768 + 16 + 8 + 16, 1001 .vrefresh = 60, 1002 }; 1003 1004 static const struct panel_desc chunghwa_claa101wb01 = { 1005 .modes = &chunghwa_claa101wb01_mode, 1006 .num_modes = 1, 1007 .bpc = 6, 1008 .size = { 1009 .width = 223, 1010 .height = 125, 1011 }, 1012 }; 1013 1014 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1015 .clock = 33260, 1016 .hdisplay = 800, 1017 .hsync_start = 800 + 40, 1018 .hsync_end = 800 + 40 + 128, 1019 .htotal = 800 + 40 + 128 + 88, 1020 .vdisplay = 480, 1021 .vsync_start = 480 + 10, 1022 .vsync_end = 480 + 10 + 2, 1023 .vtotal = 480 + 10 + 2 + 33, 1024 .vrefresh = 60, 1025 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1026 }; 1027 1028 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1029 .modes = &dataimage_scf0700c48ggu18_mode, 1030 .num_modes = 1, 1031 .bpc = 8, 1032 .size = { 1033 .width = 152, 1034 .height = 91, 1035 }, 1036 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1037 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1038 }; 1039 1040 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1041 .pixelclock = { 45000000, 51200000, 57000000 }, 1042 .hactive = { 1024, 1024, 1024 }, 1043 .hfront_porch = { 100, 106, 113 }, 1044 .hback_porch = { 100, 106, 113 }, 1045 .hsync_len = { 100, 108, 114 }, 1046 .vactive = { 600, 600, 600 }, 1047 .vfront_porch = { 8, 11, 15 }, 1048 .vback_porch = { 8, 11, 15 }, 1049 .vsync_len = { 9, 13, 15 }, 1050 .flags = DISPLAY_FLAGS_DE_HIGH, 1051 }; 1052 1053 static const struct panel_desc dlc_dlc0700yzg_1 = { 1054 .timings = &dlc_dlc0700yzg_1_timing, 1055 .num_timings = 1, 1056 .bpc = 6, 1057 .size = { 1058 .width = 154, 1059 .height = 86, 1060 }, 1061 .delay = { 1062 .prepare = 30, 1063 .enable = 200, 1064 .disable = 200, 1065 }, 1066 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1067 }; 1068 1069 static const struct display_timing dlc_dlc1010gig_timing = { 1070 .pixelclock = { 68900000, 71100000, 73400000 }, 1071 .hactive = { 1280, 1280, 1280 }, 1072 .hfront_porch = { 43, 53, 63 }, 1073 .hback_porch = { 43, 53, 63 }, 1074 .hsync_len = { 44, 54, 64 }, 1075 .vactive = { 800, 800, 800 }, 1076 .vfront_porch = { 5, 8, 11 }, 1077 .vback_porch = { 5, 8, 11 }, 1078 .vsync_len = { 5, 7, 11 }, 1079 .flags = DISPLAY_FLAGS_DE_HIGH, 1080 }; 1081 1082 static const struct panel_desc dlc_dlc1010gig = { 1083 .timings = &dlc_dlc1010gig_timing, 1084 .num_timings = 1, 1085 .bpc = 8, 1086 .size = { 1087 .width = 216, 1088 .height = 135, 1089 }, 1090 .delay = { 1091 .prepare = 60, 1092 .enable = 150, 1093 .disable = 100, 1094 .unprepare = 60, 1095 }, 1096 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1097 }; 1098 1099 static const struct drm_display_mode edt_et057090dhu_mode = { 1100 .clock = 25175, 1101 .hdisplay = 640, 1102 .hsync_start = 640 + 16, 1103 .hsync_end = 640 + 16 + 30, 1104 .htotal = 640 + 16 + 30 + 114, 1105 .vdisplay = 480, 1106 .vsync_start = 480 + 10, 1107 .vsync_end = 480 + 10 + 3, 1108 .vtotal = 480 + 10 + 3 + 32, 1109 .vrefresh = 60, 1110 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1111 }; 1112 1113 static const struct panel_desc edt_et057090dhu = { 1114 .modes = &edt_et057090dhu_mode, 1115 .num_modes = 1, 1116 .bpc = 6, 1117 .size = { 1118 .width = 115, 1119 .height = 86, 1120 }, 1121 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1122 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1123 }; 1124 1125 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1126 .clock = 33260, 1127 .hdisplay = 800, 1128 .hsync_start = 800 + 40, 1129 .hsync_end = 800 + 40 + 128, 1130 .htotal = 800 + 40 + 128 + 88, 1131 .vdisplay = 480, 1132 .vsync_start = 480 + 10, 1133 .vsync_end = 480 + 10 + 2, 1134 .vtotal = 480 + 10 + 2 + 33, 1135 .vrefresh = 60, 1136 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1137 }; 1138 1139 static const struct panel_desc edt_etm0700g0dh6 = { 1140 .modes = &edt_etm0700g0dh6_mode, 1141 .num_modes = 1, 1142 .bpc = 6, 1143 .size = { 1144 .width = 152, 1145 .height = 91, 1146 }, 1147 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1148 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1149 }; 1150 1151 static const struct panel_desc edt_etm0700g0bdh6 = { 1152 .modes = &edt_etm0700g0dh6_mode, 1153 .num_modes = 1, 1154 .bpc = 6, 1155 .size = { 1156 .width = 152, 1157 .height = 91, 1158 }, 1159 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1160 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1161 }; 1162 1163 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1164 .clock = 32260, 1165 .hdisplay = 800, 1166 .hsync_start = 800 + 168, 1167 .hsync_end = 800 + 168 + 64, 1168 .htotal = 800 + 168 + 64 + 88, 1169 .vdisplay = 480, 1170 .vsync_start = 480 + 37, 1171 .vsync_end = 480 + 37 + 2, 1172 .vtotal = 480 + 37 + 2 + 8, 1173 .vrefresh = 60, 1174 }; 1175 1176 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1177 .modes = &foxlink_fl500wvr00_a0t_mode, 1178 .num_modes = 1, 1179 .bpc = 8, 1180 .size = { 1181 .width = 108, 1182 .height = 65, 1183 }, 1184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1185 }; 1186 1187 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1188 .clock = 9000, 1189 .hdisplay = 480, 1190 .hsync_start = 480 + 5, 1191 .hsync_end = 480 + 5 + 1, 1192 .htotal = 480 + 5 + 1 + 40, 1193 .vdisplay = 272, 1194 .vsync_start = 272 + 8, 1195 .vsync_end = 272 + 8 + 1, 1196 .vtotal = 272 + 8 + 1 + 8, 1197 .vrefresh = 60, 1198 }; 1199 1200 static const struct panel_desc giantplus_gpg482739qs5 = { 1201 .modes = &giantplus_gpg482739qs5_mode, 1202 .num_modes = 1, 1203 .bpc = 8, 1204 .size = { 1205 .width = 95, 1206 .height = 54, 1207 }, 1208 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1209 }; 1210 1211 static const struct display_timing hannstar_hsd070pww1_timing = { 1212 .pixelclock = { 64300000, 71100000, 82000000 }, 1213 .hactive = { 1280, 1280, 1280 }, 1214 .hfront_porch = { 1, 1, 10 }, 1215 .hback_porch = { 1, 1, 10 }, 1216 /* 1217 * According to the data sheet, the minimum horizontal blanking interval 1218 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1219 * minimum working horizontal blanking interval to be 60 clocks. 1220 */ 1221 .hsync_len = { 58, 158, 661 }, 1222 .vactive = { 800, 800, 800 }, 1223 .vfront_porch = { 1, 1, 10 }, 1224 .vback_porch = { 1, 1, 10 }, 1225 .vsync_len = { 1, 21, 203 }, 1226 .flags = DISPLAY_FLAGS_DE_HIGH, 1227 }; 1228 1229 static const struct panel_desc hannstar_hsd070pww1 = { 1230 .timings = &hannstar_hsd070pww1_timing, 1231 .num_timings = 1, 1232 .bpc = 6, 1233 .size = { 1234 .width = 151, 1235 .height = 94, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1238 }; 1239 1240 static const struct display_timing hannstar_hsd100pxn1_timing = { 1241 .pixelclock = { 55000000, 65000000, 75000000 }, 1242 .hactive = { 1024, 1024, 1024 }, 1243 .hfront_porch = { 40, 40, 40 }, 1244 .hback_porch = { 220, 220, 220 }, 1245 .hsync_len = { 20, 60, 100 }, 1246 .vactive = { 768, 768, 768 }, 1247 .vfront_porch = { 7, 7, 7 }, 1248 .vback_porch = { 21, 21, 21 }, 1249 .vsync_len = { 10, 10, 10 }, 1250 .flags = DISPLAY_FLAGS_DE_HIGH, 1251 }; 1252 1253 static const struct panel_desc hannstar_hsd100pxn1 = { 1254 .timings = &hannstar_hsd100pxn1_timing, 1255 .num_timings = 1, 1256 .bpc = 6, 1257 .size = { 1258 .width = 203, 1259 .height = 152, 1260 }, 1261 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1262 }; 1263 1264 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1265 .clock = 33333, 1266 .hdisplay = 800, 1267 .hsync_start = 800 + 85, 1268 .hsync_end = 800 + 85 + 86, 1269 .htotal = 800 + 85 + 86 + 85, 1270 .vdisplay = 480, 1271 .vsync_start = 480 + 16, 1272 .vsync_end = 480 + 16 + 13, 1273 .vtotal = 480 + 16 + 13 + 16, 1274 .vrefresh = 60, 1275 }; 1276 1277 static const struct panel_desc hitachi_tx23d38vm0caa = { 1278 .modes = &hitachi_tx23d38vm0caa_mode, 1279 .num_modes = 1, 1280 .bpc = 6, 1281 .size = { 1282 .width = 195, 1283 .height = 117, 1284 }, 1285 .delay = { 1286 .enable = 160, 1287 .disable = 160, 1288 }, 1289 }; 1290 1291 static const struct drm_display_mode innolux_at043tn24_mode = { 1292 .clock = 9000, 1293 .hdisplay = 480, 1294 .hsync_start = 480 + 2, 1295 .hsync_end = 480 + 2 + 41, 1296 .htotal = 480 + 2 + 41 + 2, 1297 .vdisplay = 272, 1298 .vsync_start = 272 + 2, 1299 .vsync_end = 272 + 2 + 10, 1300 .vtotal = 272 + 2 + 10 + 2, 1301 .vrefresh = 60, 1302 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1303 }; 1304 1305 static const struct panel_desc innolux_at043tn24 = { 1306 .modes = &innolux_at043tn24_mode, 1307 .num_modes = 1, 1308 .bpc = 8, 1309 .size = { 1310 .width = 95, 1311 .height = 54, 1312 }, 1313 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1314 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1315 }; 1316 1317 static const struct drm_display_mode innolux_at070tn92_mode = { 1318 .clock = 33333, 1319 .hdisplay = 800, 1320 .hsync_start = 800 + 210, 1321 .hsync_end = 800 + 210 + 20, 1322 .htotal = 800 + 210 + 20 + 46, 1323 .vdisplay = 480, 1324 .vsync_start = 480 + 22, 1325 .vsync_end = 480 + 22 + 10, 1326 .vtotal = 480 + 22 + 23 + 10, 1327 .vrefresh = 60, 1328 }; 1329 1330 static const struct panel_desc innolux_at070tn92 = { 1331 .modes = &innolux_at070tn92_mode, 1332 .num_modes = 1, 1333 .size = { 1334 .width = 154, 1335 .height = 86, 1336 }, 1337 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1338 }; 1339 1340 static const struct display_timing innolux_g070y2_l01_timing = { 1341 .pixelclock = { 28000000, 29500000, 32000000 }, 1342 .hactive = { 800, 800, 800 }, 1343 .hfront_porch = { 61, 91, 141 }, 1344 .hback_porch = { 60, 90, 140 }, 1345 .hsync_len = { 12, 12, 12 }, 1346 .vactive = { 480, 480, 480 }, 1347 .vfront_porch = { 4, 9, 30 }, 1348 .vback_porch = { 4, 8, 28 }, 1349 .vsync_len = { 2, 2, 2 }, 1350 .flags = DISPLAY_FLAGS_DE_HIGH, 1351 }; 1352 1353 static const struct panel_desc innolux_g070y2_l01 = { 1354 .timings = &innolux_g070y2_l01_timing, 1355 .num_timings = 1, 1356 .bpc = 6, 1357 .size = { 1358 .width = 152, 1359 .height = 91, 1360 }, 1361 .delay = { 1362 .prepare = 10, 1363 .enable = 100, 1364 .disable = 100, 1365 .unprepare = 800, 1366 }, 1367 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1368 }; 1369 1370 static const struct display_timing innolux_g101ice_l01_timing = { 1371 .pixelclock = { 60400000, 71100000, 74700000 }, 1372 .hactive = { 1280, 1280, 1280 }, 1373 .hfront_porch = { 41, 80, 100 }, 1374 .hback_porch = { 40, 79, 99 }, 1375 .hsync_len = { 1, 1, 1 }, 1376 .vactive = { 800, 800, 800 }, 1377 .vfront_porch = { 5, 11, 14 }, 1378 .vback_porch = { 4, 11, 14 }, 1379 .vsync_len = { 1, 1, 1 }, 1380 .flags = DISPLAY_FLAGS_DE_HIGH, 1381 }; 1382 1383 static const struct panel_desc innolux_g101ice_l01 = { 1384 .timings = &innolux_g101ice_l01_timing, 1385 .num_timings = 1, 1386 .bpc = 8, 1387 .size = { 1388 .width = 217, 1389 .height = 135, 1390 }, 1391 .delay = { 1392 .enable = 200, 1393 .disable = 200, 1394 }, 1395 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1396 }; 1397 1398 static const struct display_timing innolux_g121i1_l01_timing = { 1399 .pixelclock = { 67450000, 71000000, 74550000 }, 1400 .hactive = { 1280, 1280, 1280 }, 1401 .hfront_porch = { 40, 80, 160 }, 1402 .hback_porch = { 39, 79, 159 }, 1403 .hsync_len = { 1, 1, 1 }, 1404 .vactive = { 800, 800, 800 }, 1405 .vfront_porch = { 5, 11, 100 }, 1406 .vback_porch = { 4, 11, 99 }, 1407 .vsync_len = { 1, 1, 1 }, 1408 }; 1409 1410 static const struct panel_desc innolux_g121i1_l01 = { 1411 .timings = &innolux_g121i1_l01_timing, 1412 .num_timings = 1, 1413 .bpc = 6, 1414 .size = { 1415 .width = 261, 1416 .height = 163, 1417 }, 1418 .delay = { 1419 .enable = 200, 1420 .disable = 20, 1421 }, 1422 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1423 }; 1424 1425 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1426 .clock = 65000, 1427 .hdisplay = 1024, 1428 .hsync_start = 1024 + 0, 1429 .hsync_end = 1024 + 1, 1430 .htotal = 1024 + 0 + 1 + 320, 1431 .vdisplay = 768, 1432 .vsync_start = 768 + 38, 1433 .vsync_end = 768 + 38 + 1, 1434 .vtotal = 768 + 38 + 1 + 0, 1435 .vrefresh = 60, 1436 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1437 }; 1438 1439 static const struct panel_desc innolux_g121x1_l03 = { 1440 .modes = &innolux_g121x1_l03_mode, 1441 .num_modes = 1, 1442 .bpc = 6, 1443 .size = { 1444 .width = 246, 1445 .height = 185, 1446 }, 1447 .delay = { 1448 .enable = 200, 1449 .unprepare = 200, 1450 .disable = 400, 1451 }, 1452 }; 1453 1454 static const struct drm_display_mode innolux_n116bge_mode = { 1455 .clock = 76420, 1456 .hdisplay = 1366, 1457 .hsync_start = 1366 + 136, 1458 .hsync_end = 1366 + 136 + 30, 1459 .htotal = 1366 + 136 + 30 + 60, 1460 .vdisplay = 768, 1461 .vsync_start = 768 + 8, 1462 .vsync_end = 768 + 8 + 12, 1463 .vtotal = 768 + 8 + 12 + 12, 1464 .vrefresh = 60, 1465 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1466 }; 1467 1468 static const struct panel_desc innolux_n116bge = { 1469 .modes = &innolux_n116bge_mode, 1470 .num_modes = 1, 1471 .bpc = 6, 1472 .size = { 1473 .width = 256, 1474 .height = 144, 1475 }, 1476 }; 1477 1478 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1479 .clock = 69300, 1480 .hdisplay = 1366, 1481 .hsync_start = 1366 + 16, 1482 .hsync_end = 1366 + 16 + 34, 1483 .htotal = 1366 + 16 + 34 + 50, 1484 .vdisplay = 768, 1485 .vsync_start = 768 + 2, 1486 .vsync_end = 768 + 2 + 6, 1487 .vtotal = 768 + 2 + 6 + 12, 1488 .vrefresh = 60, 1489 }; 1490 1491 static const struct panel_desc innolux_n156bge_l21 = { 1492 .modes = &innolux_n156bge_l21_mode, 1493 .num_modes = 1, 1494 .bpc = 6, 1495 .size = { 1496 .width = 344, 1497 .height = 193, 1498 }, 1499 }; 1500 1501 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 1502 .clock = 206016, 1503 .hdisplay = 2160, 1504 .hsync_start = 2160 + 48, 1505 .hsync_end = 2160 + 48 + 32, 1506 .htotal = 2160 + 48 + 32 + 80, 1507 .vdisplay = 1440, 1508 .vsync_start = 1440 + 3, 1509 .vsync_end = 1440 + 3 + 10, 1510 .vtotal = 1440 + 3 + 10 + 27, 1511 .vrefresh = 60, 1512 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1513 }; 1514 1515 static const struct panel_desc innolux_p120zdg_bf1 = { 1516 .modes = &innolux_p120zdg_bf1_mode, 1517 .num_modes = 1, 1518 .bpc = 8, 1519 .size = { 1520 .width = 254, 1521 .height = 169, 1522 }, 1523 .delay = { 1524 .hpd_absent_delay = 200, 1525 .unprepare = 500, 1526 }, 1527 }; 1528 1529 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1530 .clock = 51501, 1531 .hdisplay = 1024, 1532 .hsync_start = 1024 + 128, 1533 .hsync_end = 1024 + 128 + 64, 1534 .htotal = 1024 + 128 + 64 + 128, 1535 .vdisplay = 600, 1536 .vsync_start = 600 + 16, 1537 .vsync_end = 600 + 16 + 4, 1538 .vtotal = 600 + 16 + 4 + 16, 1539 .vrefresh = 60, 1540 }; 1541 1542 static const struct panel_desc innolux_zj070na_01p = { 1543 .modes = &innolux_zj070na_01p_mode, 1544 .num_modes = 1, 1545 .bpc = 6, 1546 .size = { 1547 .width = 154, 1548 .height = 90, 1549 }, 1550 }; 1551 1552 static const struct display_timing koe_tx31d200vm0baa_timing = { 1553 .pixelclock = { 39600000, 43200000, 48000000 }, 1554 .hactive = { 1280, 1280, 1280 }, 1555 .hfront_porch = { 16, 36, 56 }, 1556 .hback_porch = { 16, 36, 56 }, 1557 .hsync_len = { 8, 8, 8 }, 1558 .vactive = { 480, 480, 480 }, 1559 .vfront_porch = { 6, 21, 33 }, 1560 .vback_porch = { 6, 21, 33 }, 1561 .vsync_len = { 8, 8, 8 }, 1562 .flags = DISPLAY_FLAGS_DE_HIGH, 1563 }; 1564 1565 static const struct panel_desc koe_tx31d200vm0baa = { 1566 .timings = &koe_tx31d200vm0baa_timing, 1567 .num_timings = 1, 1568 .bpc = 6, 1569 .size = { 1570 .width = 292, 1571 .height = 109, 1572 }, 1573 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1574 }; 1575 1576 static const struct display_timing kyo_tcg121xglp_timing = { 1577 .pixelclock = { 52000000, 65000000, 71000000 }, 1578 .hactive = { 1024, 1024, 1024 }, 1579 .hfront_porch = { 2, 2, 2 }, 1580 .hback_porch = { 2, 2, 2 }, 1581 .hsync_len = { 86, 124, 244 }, 1582 .vactive = { 768, 768, 768 }, 1583 .vfront_porch = { 2, 2, 2 }, 1584 .vback_porch = { 2, 2, 2 }, 1585 .vsync_len = { 6, 34, 73 }, 1586 .flags = DISPLAY_FLAGS_DE_HIGH, 1587 }; 1588 1589 static const struct panel_desc kyo_tcg121xglp = { 1590 .timings = &kyo_tcg121xglp_timing, 1591 .num_timings = 1, 1592 .bpc = 8, 1593 .size = { 1594 .width = 246, 1595 .height = 184, 1596 }, 1597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1598 }; 1599 1600 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 1601 .clock = 7000, 1602 .hdisplay = 320, 1603 .hsync_start = 320 + 20, 1604 .hsync_end = 320 + 20 + 30, 1605 .htotal = 320 + 20 + 30 + 38, 1606 .vdisplay = 240, 1607 .vsync_start = 240 + 4, 1608 .vsync_end = 240 + 4 + 3, 1609 .vtotal = 240 + 4 + 3 + 15, 1610 .vrefresh = 60, 1611 }; 1612 1613 static const struct panel_desc lemaker_bl035_rgb_002 = { 1614 .modes = &lemaker_bl035_rgb_002_mode, 1615 .num_modes = 1, 1616 .size = { 1617 .width = 70, 1618 .height = 52, 1619 }, 1620 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1621 .bus_flags = DRM_BUS_FLAG_DE_LOW, 1622 }; 1623 1624 static const struct drm_display_mode lg_lb070wv8_mode = { 1625 .clock = 33246, 1626 .hdisplay = 800, 1627 .hsync_start = 800 + 88, 1628 .hsync_end = 800 + 88 + 80, 1629 .htotal = 800 + 88 + 80 + 88, 1630 .vdisplay = 480, 1631 .vsync_start = 480 + 10, 1632 .vsync_end = 480 + 10 + 25, 1633 .vtotal = 480 + 10 + 25 + 10, 1634 .vrefresh = 60, 1635 }; 1636 1637 static const struct panel_desc lg_lb070wv8 = { 1638 .modes = &lg_lb070wv8_mode, 1639 .num_modes = 1, 1640 .bpc = 16, 1641 .size = { 1642 .width = 151, 1643 .height = 91, 1644 }, 1645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1646 }; 1647 1648 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1649 .clock = 200000, 1650 .hdisplay = 1536, 1651 .hsync_start = 1536 + 12, 1652 .hsync_end = 1536 + 12 + 16, 1653 .htotal = 1536 + 12 + 16 + 48, 1654 .vdisplay = 2048, 1655 .vsync_start = 2048 + 8, 1656 .vsync_end = 2048 + 8 + 4, 1657 .vtotal = 2048 + 8 + 4 + 8, 1658 .vrefresh = 60, 1659 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1660 }; 1661 1662 static const struct panel_desc lg_lp079qx1_sp0v = { 1663 .modes = &lg_lp079qx1_sp0v_mode, 1664 .num_modes = 1, 1665 .size = { 1666 .width = 129, 1667 .height = 171, 1668 }, 1669 }; 1670 1671 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1672 .clock = 205210, 1673 .hdisplay = 2048, 1674 .hsync_start = 2048 + 150, 1675 .hsync_end = 2048 + 150 + 5, 1676 .htotal = 2048 + 150 + 5 + 5, 1677 .vdisplay = 1536, 1678 .vsync_start = 1536 + 3, 1679 .vsync_end = 1536 + 3 + 1, 1680 .vtotal = 1536 + 3 + 1 + 9, 1681 .vrefresh = 60, 1682 }; 1683 1684 static const struct panel_desc lg_lp097qx1_spa1 = { 1685 .modes = &lg_lp097qx1_spa1_mode, 1686 .num_modes = 1, 1687 .size = { 1688 .width = 208, 1689 .height = 147, 1690 }, 1691 }; 1692 1693 static const struct drm_display_mode lg_lp120up1_mode = { 1694 .clock = 162300, 1695 .hdisplay = 1920, 1696 .hsync_start = 1920 + 40, 1697 .hsync_end = 1920 + 40 + 40, 1698 .htotal = 1920 + 40 + 40+ 80, 1699 .vdisplay = 1280, 1700 .vsync_start = 1280 + 4, 1701 .vsync_end = 1280 + 4 + 4, 1702 .vtotal = 1280 + 4 + 4 + 12, 1703 .vrefresh = 60, 1704 }; 1705 1706 static const struct panel_desc lg_lp120up1 = { 1707 .modes = &lg_lp120up1_mode, 1708 .num_modes = 1, 1709 .bpc = 8, 1710 .size = { 1711 .width = 267, 1712 .height = 183, 1713 }, 1714 }; 1715 1716 static const struct drm_display_mode lg_lp129qe_mode = { 1717 .clock = 285250, 1718 .hdisplay = 2560, 1719 .hsync_start = 2560 + 48, 1720 .hsync_end = 2560 + 48 + 32, 1721 .htotal = 2560 + 48 + 32 + 80, 1722 .vdisplay = 1700, 1723 .vsync_start = 1700 + 3, 1724 .vsync_end = 1700 + 3 + 10, 1725 .vtotal = 1700 + 3 + 10 + 36, 1726 .vrefresh = 60, 1727 }; 1728 1729 static const struct panel_desc lg_lp129qe = { 1730 .modes = &lg_lp129qe_mode, 1731 .num_modes = 1, 1732 .bpc = 8, 1733 .size = { 1734 .width = 272, 1735 .height = 181, 1736 }, 1737 }; 1738 1739 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 1740 .clock = 30400, 1741 .hdisplay = 800, 1742 .hsync_start = 800 + 0, 1743 .hsync_end = 800 + 1, 1744 .htotal = 800 + 0 + 1 + 160, 1745 .vdisplay = 480, 1746 .vsync_start = 480 + 0, 1747 .vsync_end = 480 + 48 + 1, 1748 .vtotal = 480 + 48 + 1 + 0, 1749 .vrefresh = 60, 1750 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1751 }; 1752 1753 static const struct panel_desc mitsubishi_aa070mc01 = { 1754 .modes = &mitsubishi_aa070mc01_mode, 1755 .num_modes = 1, 1756 .bpc = 8, 1757 .size = { 1758 .width = 152, 1759 .height = 91, 1760 }, 1761 1762 .delay = { 1763 .enable = 200, 1764 .unprepare = 200, 1765 .disable = 400, 1766 }, 1767 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1768 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1769 }; 1770 1771 static const struct display_timing nec_nl12880bc20_05_timing = { 1772 .pixelclock = { 67000000, 71000000, 75000000 }, 1773 .hactive = { 1280, 1280, 1280 }, 1774 .hfront_porch = { 2, 30, 30 }, 1775 .hback_porch = { 6, 100, 100 }, 1776 .hsync_len = { 2, 30, 30 }, 1777 .vactive = { 800, 800, 800 }, 1778 .vfront_porch = { 5, 5, 5 }, 1779 .vback_porch = { 11, 11, 11 }, 1780 .vsync_len = { 7, 7, 7 }, 1781 }; 1782 1783 static const struct panel_desc nec_nl12880bc20_05 = { 1784 .timings = &nec_nl12880bc20_05_timing, 1785 .num_timings = 1, 1786 .bpc = 8, 1787 .size = { 1788 .width = 261, 1789 .height = 163, 1790 }, 1791 .delay = { 1792 .enable = 50, 1793 .disable = 50, 1794 }, 1795 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1796 }; 1797 1798 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1799 .clock = 10870, 1800 .hdisplay = 480, 1801 .hsync_start = 480 + 2, 1802 .hsync_end = 480 + 2 + 41, 1803 .htotal = 480 + 2 + 41 + 2, 1804 .vdisplay = 272, 1805 .vsync_start = 272 + 2, 1806 .vsync_end = 272 + 2 + 4, 1807 .vtotal = 272 + 2 + 4 + 2, 1808 .vrefresh = 74, 1809 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1810 }; 1811 1812 static const struct panel_desc nec_nl4827hc19_05b = { 1813 .modes = &nec_nl4827hc19_05b_mode, 1814 .num_modes = 1, 1815 .bpc = 8, 1816 .size = { 1817 .width = 95, 1818 .height = 54, 1819 }, 1820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1821 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1822 }; 1823 1824 static const struct drm_display_mode netron_dy_e231732_mode = { 1825 .clock = 66000, 1826 .hdisplay = 1024, 1827 .hsync_start = 1024 + 160, 1828 .hsync_end = 1024 + 160 + 70, 1829 .htotal = 1024 + 160 + 70 + 90, 1830 .vdisplay = 600, 1831 .vsync_start = 600 + 127, 1832 .vsync_end = 600 + 127 + 20, 1833 .vtotal = 600 + 127 + 20 + 3, 1834 .vrefresh = 60, 1835 }; 1836 1837 static const struct panel_desc netron_dy_e231732 = { 1838 .modes = &netron_dy_e231732_mode, 1839 .num_modes = 1, 1840 .size = { 1841 .width = 154, 1842 .height = 87, 1843 }, 1844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1845 }; 1846 1847 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 1848 .clock = 9000, 1849 .hdisplay = 480, 1850 .hsync_start = 480 + 2, 1851 .hsync_end = 480 + 2 + 41, 1852 .htotal = 480 + 2 + 41 + 2, 1853 .vdisplay = 272, 1854 .vsync_start = 272 + 2, 1855 .vsync_end = 272 + 2 + 10, 1856 .vtotal = 272 + 2 + 10 + 2, 1857 .vrefresh = 60, 1858 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1859 }; 1860 1861 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 1862 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 1863 .num_modes = 1, 1864 .bpc = 8, 1865 .size = { 1866 .width = 95, 1867 .height = 54, 1868 }, 1869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1870 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 1871 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 1872 }; 1873 1874 static const struct display_timing nlt_nl192108ac18_02d_timing = { 1875 .pixelclock = { 130000000, 148350000, 163000000 }, 1876 .hactive = { 1920, 1920, 1920 }, 1877 .hfront_porch = { 80, 100, 100 }, 1878 .hback_porch = { 100, 120, 120 }, 1879 .hsync_len = { 50, 60, 60 }, 1880 .vactive = { 1080, 1080, 1080 }, 1881 .vfront_porch = { 12, 30, 30 }, 1882 .vback_porch = { 4, 10, 10 }, 1883 .vsync_len = { 4, 5, 5 }, 1884 }; 1885 1886 static const struct panel_desc nlt_nl192108ac18_02d = { 1887 .timings = &nlt_nl192108ac18_02d_timing, 1888 .num_timings = 1, 1889 .bpc = 8, 1890 .size = { 1891 .width = 344, 1892 .height = 194, 1893 }, 1894 .delay = { 1895 .unprepare = 500, 1896 }, 1897 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1898 }; 1899 1900 static const struct drm_display_mode nvd_9128_mode = { 1901 .clock = 29500, 1902 .hdisplay = 800, 1903 .hsync_start = 800 + 130, 1904 .hsync_end = 800 + 130 + 98, 1905 .htotal = 800 + 0 + 130 + 98, 1906 .vdisplay = 480, 1907 .vsync_start = 480 + 10, 1908 .vsync_end = 480 + 10 + 50, 1909 .vtotal = 480 + 0 + 10 + 50, 1910 }; 1911 1912 static const struct panel_desc nvd_9128 = { 1913 .modes = &nvd_9128_mode, 1914 .num_modes = 1, 1915 .bpc = 8, 1916 .size = { 1917 .width = 156, 1918 .height = 88, 1919 }, 1920 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1921 }; 1922 1923 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1924 .pixelclock = { 30000000, 30000000, 40000000 }, 1925 .hactive = { 800, 800, 800 }, 1926 .hfront_porch = { 40, 40, 40 }, 1927 .hback_porch = { 40, 40, 40 }, 1928 .hsync_len = { 1, 48, 48 }, 1929 .vactive = { 480, 480, 480 }, 1930 .vfront_porch = { 13, 13, 13 }, 1931 .vback_porch = { 29, 29, 29 }, 1932 .vsync_len = { 3, 3, 3 }, 1933 .flags = DISPLAY_FLAGS_DE_HIGH, 1934 }; 1935 1936 static const struct panel_desc okaya_rs800480t_7x0gp = { 1937 .timings = &okaya_rs800480t_7x0gp_timing, 1938 .num_timings = 1, 1939 .bpc = 6, 1940 .size = { 1941 .width = 154, 1942 .height = 87, 1943 }, 1944 .delay = { 1945 .prepare = 41, 1946 .enable = 50, 1947 .unprepare = 41, 1948 .disable = 50, 1949 }, 1950 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1951 }; 1952 1953 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1954 .clock = 9000, 1955 .hdisplay = 480, 1956 .hsync_start = 480 + 5, 1957 .hsync_end = 480 + 5 + 30, 1958 .htotal = 480 + 5 + 30 + 10, 1959 .vdisplay = 272, 1960 .vsync_start = 272 + 8, 1961 .vsync_end = 272 + 8 + 5, 1962 .vtotal = 272 + 8 + 5 + 3, 1963 .vrefresh = 60, 1964 }; 1965 1966 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1967 .modes = &olimex_lcd_olinuxino_43ts_mode, 1968 .num_modes = 1, 1969 .size = { 1970 .width = 95, 1971 .height = 54, 1972 }, 1973 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1974 }; 1975 1976 /* 1977 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1978 * pixel clocks, but this is the timing that was being used in the Adafruit 1979 * installation instructions. 1980 */ 1981 static const struct drm_display_mode ontat_yx700wv03_mode = { 1982 .clock = 29500, 1983 .hdisplay = 800, 1984 .hsync_start = 824, 1985 .hsync_end = 896, 1986 .htotal = 992, 1987 .vdisplay = 480, 1988 .vsync_start = 483, 1989 .vsync_end = 493, 1990 .vtotal = 500, 1991 .vrefresh = 60, 1992 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1993 }; 1994 1995 /* 1996 * Specification at: 1997 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1998 */ 1999 static const struct panel_desc ontat_yx700wv03 = { 2000 .modes = &ontat_yx700wv03_mode, 2001 .num_modes = 1, 2002 .bpc = 8, 2003 .size = { 2004 .width = 154, 2005 .height = 83, 2006 }, 2007 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2008 }; 2009 2010 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2011 .clock = 25000, 2012 .hdisplay = 480, 2013 .hsync_start = 480 + 10, 2014 .hsync_end = 480 + 10 + 10, 2015 .htotal = 480 + 10 + 10 + 15, 2016 .vdisplay = 800, 2017 .vsync_start = 800 + 3, 2018 .vsync_end = 800 + 3 + 3, 2019 .vtotal = 800 + 3 + 3 + 3, 2020 .vrefresh = 60, 2021 }; 2022 2023 static const struct panel_desc ortustech_com43h4m85ulc = { 2024 .modes = &ortustech_com43h4m85ulc_mode, 2025 .num_modes = 1, 2026 .bpc = 8, 2027 .size = { 2028 .width = 56, 2029 .height = 93, 2030 }, 2031 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2032 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2033 }; 2034 2035 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2036 .clock = 33000, 2037 .hdisplay = 800, 2038 .hsync_start = 800 + 210, 2039 .hsync_end = 800 + 210 + 30, 2040 .htotal = 800 + 210 + 30 + 16, 2041 .vdisplay = 480, 2042 .vsync_start = 480 + 22, 2043 .vsync_end = 480 + 22 + 13, 2044 .vtotal = 480 + 22 + 13 + 10, 2045 .vrefresh = 60, 2046 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2047 }; 2048 2049 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2050 .modes = &osddisplays_osd070t1718_19ts_mode, 2051 .num_modes = 1, 2052 .bpc = 8, 2053 .size = { 2054 .width = 152, 2055 .height = 91, 2056 }, 2057 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2058 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2059 }; 2060 2061 static const struct drm_display_mode pda_91_00156_a0_mode = { 2062 .clock = 33300, 2063 .hdisplay = 800, 2064 .hsync_start = 800 + 1, 2065 .hsync_end = 800 + 1 + 64, 2066 .htotal = 800 + 1 + 64 + 64, 2067 .vdisplay = 480, 2068 .vsync_start = 480 + 1, 2069 .vsync_end = 480 + 1 + 23, 2070 .vtotal = 480 + 1 + 23 + 22, 2071 .vrefresh = 60, 2072 }; 2073 2074 static const struct panel_desc pda_91_00156_a0 = { 2075 .modes = &pda_91_00156_a0_mode, 2076 .num_modes = 1, 2077 .size = { 2078 .width = 152, 2079 .height = 91, 2080 }, 2081 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2082 }; 2083 2084 2085 static const struct drm_display_mode qd43003c0_40_mode = { 2086 .clock = 9000, 2087 .hdisplay = 480, 2088 .hsync_start = 480 + 8, 2089 .hsync_end = 480 + 8 + 4, 2090 .htotal = 480 + 8 + 4 + 39, 2091 .vdisplay = 272, 2092 .vsync_start = 272 + 4, 2093 .vsync_end = 272 + 4 + 10, 2094 .vtotal = 272 + 4 + 10 + 2, 2095 .vrefresh = 60, 2096 }; 2097 2098 static const struct panel_desc qd43003c0_40 = { 2099 .modes = &qd43003c0_40_mode, 2100 .num_modes = 1, 2101 .bpc = 8, 2102 .size = { 2103 .width = 95, 2104 .height = 53, 2105 }, 2106 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2107 }; 2108 2109 static const struct display_timing rocktech_rk070er9427_timing = { 2110 .pixelclock = { 26400000, 33300000, 46800000 }, 2111 .hactive = { 800, 800, 800 }, 2112 .hfront_porch = { 16, 210, 354 }, 2113 .hback_porch = { 46, 46, 46 }, 2114 .hsync_len = { 1, 1, 1 }, 2115 .vactive = { 480, 480, 480 }, 2116 .vfront_porch = { 7, 22, 147 }, 2117 .vback_porch = { 23, 23, 23 }, 2118 .vsync_len = { 1, 1, 1 }, 2119 .flags = DISPLAY_FLAGS_DE_HIGH, 2120 }; 2121 2122 static const struct panel_desc rocktech_rk070er9427 = { 2123 .timings = &rocktech_rk070er9427_timing, 2124 .num_timings = 1, 2125 .bpc = 6, 2126 .size = { 2127 .width = 154, 2128 .height = 86, 2129 }, 2130 .delay = { 2131 .prepare = 41, 2132 .enable = 50, 2133 .unprepare = 41, 2134 .disable = 50, 2135 }, 2136 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2137 }; 2138 2139 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2140 .clock = 271560, 2141 .hdisplay = 2560, 2142 .hsync_start = 2560 + 48, 2143 .hsync_end = 2560 + 48 + 32, 2144 .htotal = 2560 + 48 + 32 + 80, 2145 .vdisplay = 1600, 2146 .vsync_start = 1600 + 2, 2147 .vsync_end = 1600 + 2 + 5, 2148 .vtotal = 1600 + 2 + 5 + 57, 2149 .vrefresh = 60, 2150 }; 2151 2152 static const struct panel_desc samsung_lsn122dl01_c01 = { 2153 .modes = &samsung_lsn122dl01_c01_mode, 2154 .num_modes = 1, 2155 .size = { 2156 .width = 263, 2157 .height = 164, 2158 }, 2159 }; 2160 2161 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2162 .clock = 54030, 2163 .hdisplay = 1024, 2164 .hsync_start = 1024 + 24, 2165 .hsync_end = 1024 + 24 + 136, 2166 .htotal = 1024 + 24 + 136 + 160, 2167 .vdisplay = 600, 2168 .vsync_start = 600 + 3, 2169 .vsync_end = 600 + 3 + 6, 2170 .vtotal = 600 + 3 + 6 + 61, 2171 .vrefresh = 60, 2172 }; 2173 2174 static const struct panel_desc samsung_ltn101nt05 = { 2175 .modes = &samsung_ltn101nt05_mode, 2176 .num_modes = 1, 2177 .bpc = 6, 2178 .size = { 2179 .width = 223, 2180 .height = 125, 2181 }, 2182 }; 2183 2184 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 2185 .clock = 76300, 2186 .hdisplay = 1366, 2187 .hsync_start = 1366 + 64, 2188 .hsync_end = 1366 + 64 + 48, 2189 .htotal = 1366 + 64 + 48 + 128, 2190 .vdisplay = 768, 2191 .vsync_start = 768 + 2, 2192 .vsync_end = 768 + 2 + 5, 2193 .vtotal = 768 + 2 + 5 + 17, 2194 .vrefresh = 60, 2195 }; 2196 2197 static const struct panel_desc samsung_ltn140at29_301 = { 2198 .modes = &samsung_ltn140at29_301_mode, 2199 .num_modes = 1, 2200 .bpc = 6, 2201 .size = { 2202 .width = 320, 2203 .height = 187, 2204 }, 2205 }; 2206 2207 static const struct drm_display_mode sharp_lq035q7db03_mode = { 2208 .clock = 5500, 2209 .hdisplay = 240, 2210 .hsync_start = 240 + 16, 2211 .hsync_end = 240 + 16 + 7, 2212 .htotal = 240 + 16 + 7 + 5, 2213 .vdisplay = 320, 2214 .vsync_start = 320 + 9, 2215 .vsync_end = 320 + 9 + 1, 2216 .vtotal = 320 + 9 + 1 + 7, 2217 .vrefresh = 60, 2218 }; 2219 2220 static const struct panel_desc sharp_lq035q7db03 = { 2221 .modes = &sharp_lq035q7db03_mode, 2222 .num_modes = 1, 2223 .bpc = 6, 2224 .size = { 2225 .width = 54, 2226 .height = 72, 2227 }, 2228 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2229 }; 2230 2231 static const struct display_timing sharp_lq101k1ly04_timing = { 2232 .pixelclock = { 60000000, 65000000, 80000000 }, 2233 .hactive = { 1280, 1280, 1280 }, 2234 .hfront_porch = { 20, 20, 20 }, 2235 .hback_porch = { 20, 20, 20 }, 2236 .hsync_len = { 10, 10, 10 }, 2237 .vactive = { 800, 800, 800 }, 2238 .vfront_porch = { 4, 4, 4 }, 2239 .vback_porch = { 4, 4, 4 }, 2240 .vsync_len = { 4, 4, 4 }, 2241 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2242 }; 2243 2244 static const struct panel_desc sharp_lq101k1ly04 = { 2245 .timings = &sharp_lq101k1ly04_timing, 2246 .num_timings = 1, 2247 .bpc = 8, 2248 .size = { 2249 .width = 217, 2250 .height = 136, 2251 }, 2252 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2253 }; 2254 2255 static const struct display_timing sharp_lq123p1jx31_timing = { 2256 .pixelclock = { 252750000, 252750000, 266604720 }, 2257 .hactive = { 2400, 2400, 2400 }, 2258 .hfront_porch = { 48, 48, 48 }, 2259 .hback_porch = { 80, 80, 84 }, 2260 .hsync_len = { 32, 32, 32 }, 2261 .vactive = { 1600, 1600, 1600 }, 2262 .vfront_porch = { 3, 3, 3 }, 2263 .vback_porch = { 33, 33, 120 }, 2264 .vsync_len = { 10, 10, 10 }, 2265 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2266 }; 2267 2268 static const struct panel_desc sharp_lq123p1jx31 = { 2269 .timings = &sharp_lq123p1jx31_timing, 2270 .num_timings = 1, 2271 .bpc = 8, 2272 .size = { 2273 .width = 259, 2274 .height = 173, 2275 }, 2276 .delay = { 2277 .prepare = 110, 2278 .enable = 50, 2279 .unprepare = 550, 2280 }, 2281 }; 2282 2283 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 2284 .clock = 71100, 2285 .hdisplay = 1024, 2286 .hsync_start = 1024 + 168, 2287 .hsync_end = 1024 + 168 + 64, 2288 .htotal = 1024 + 168 + 64 + 88, 2289 .vdisplay = 768, 2290 .vsync_start = 768 + 37, 2291 .vsync_end = 768 + 37 + 2, 2292 .vtotal = 768 + 37 + 2 + 8, 2293 .vrefresh = 60, 2294 }; 2295 2296 static const struct panel_desc sharp_lq150x1lg11 = { 2297 .modes = &sharp_lq150x1lg11_mode, 2298 .num_modes = 1, 2299 .bpc = 6, 2300 .size = { 2301 .width = 304, 2302 .height = 228, 2303 }, 2304 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2305 }; 2306 2307 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 2308 .clock = 33300, 2309 .hdisplay = 800, 2310 .hsync_start = 800 + 1, 2311 .hsync_end = 800 + 1 + 64, 2312 .htotal = 800 + 1 + 64 + 64, 2313 .vdisplay = 480, 2314 .vsync_start = 480 + 1, 2315 .vsync_end = 480 + 1 + 23, 2316 .vtotal = 480 + 1 + 23 + 22, 2317 .vrefresh = 60, 2318 }; 2319 2320 static const struct panel_desc shelly_sca07010_bfn_lnn = { 2321 .modes = &shelly_sca07010_bfn_lnn_mode, 2322 .num_modes = 1, 2323 .size = { 2324 .width = 152, 2325 .height = 91, 2326 }, 2327 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2328 }; 2329 2330 static const struct drm_display_mode starry_kr122ea0sra_mode = { 2331 .clock = 147000, 2332 .hdisplay = 1920, 2333 .hsync_start = 1920 + 16, 2334 .hsync_end = 1920 + 16 + 16, 2335 .htotal = 1920 + 16 + 16 + 32, 2336 .vdisplay = 1200, 2337 .vsync_start = 1200 + 15, 2338 .vsync_end = 1200 + 15 + 2, 2339 .vtotal = 1200 + 15 + 2 + 18, 2340 .vrefresh = 60, 2341 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2342 }; 2343 2344 static const struct panel_desc starry_kr122ea0sra = { 2345 .modes = &starry_kr122ea0sra_mode, 2346 .num_modes = 1, 2347 .size = { 2348 .width = 263, 2349 .height = 164, 2350 }, 2351 .delay = { 2352 .prepare = 10 + 200, 2353 .enable = 50, 2354 .unprepare = 10 + 500, 2355 }, 2356 }; 2357 2358 static const struct display_timing tianma_tm070jdhg30_timing = { 2359 .pixelclock = { 62600000, 68200000, 78100000 }, 2360 .hactive = { 1280, 1280, 1280 }, 2361 .hfront_porch = { 15, 64, 159 }, 2362 .hback_porch = { 5, 5, 5 }, 2363 .hsync_len = { 1, 1, 256 }, 2364 .vactive = { 800, 800, 800 }, 2365 .vfront_porch = { 3, 40, 99 }, 2366 .vback_porch = { 2, 2, 2 }, 2367 .vsync_len = { 1, 1, 128 }, 2368 .flags = DISPLAY_FLAGS_DE_HIGH, 2369 }; 2370 2371 static const struct panel_desc tianma_tm070jdhg30 = { 2372 .timings = &tianma_tm070jdhg30_timing, 2373 .num_timings = 1, 2374 .bpc = 8, 2375 .size = { 2376 .width = 151, 2377 .height = 95, 2378 }, 2379 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2380 }; 2381 2382 static const struct display_timing tianma_tm070rvhg71_timing = { 2383 .pixelclock = { 27700000, 29200000, 39600000 }, 2384 .hactive = { 800, 800, 800 }, 2385 .hfront_porch = { 12, 40, 212 }, 2386 .hback_porch = { 88, 88, 88 }, 2387 .hsync_len = { 1, 1, 40 }, 2388 .vactive = { 480, 480, 480 }, 2389 .vfront_porch = { 1, 13, 88 }, 2390 .vback_porch = { 32, 32, 32 }, 2391 .vsync_len = { 1, 1, 3 }, 2392 .flags = DISPLAY_FLAGS_DE_HIGH, 2393 }; 2394 2395 static const struct panel_desc tianma_tm070rvhg71 = { 2396 .timings = &tianma_tm070rvhg71_timing, 2397 .num_timings = 1, 2398 .bpc = 8, 2399 .size = { 2400 .width = 154, 2401 .height = 86, 2402 }, 2403 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2404 }; 2405 2406 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 2407 .clock = 79500, 2408 .hdisplay = 1280, 2409 .hsync_start = 1280 + 192, 2410 .hsync_end = 1280 + 192 + 128, 2411 .htotal = 1280 + 192 + 128 + 64, 2412 .vdisplay = 768, 2413 .vsync_start = 768 + 20, 2414 .vsync_end = 768 + 20 + 7, 2415 .vtotal = 768 + 20 + 7 + 3, 2416 .vrefresh = 60, 2417 }; 2418 2419 static const struct panel_desc toshiba_lt089ac29000 = { 2420 .modes = &toshiba_lt089ac29000_mode, 2421 .num_modes = 1, 2422 .size = { 2423 .width = 194, 2424 .height = 116, 2425 }, 2426 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2427 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2428 }; 2429 2430 static const struct drm_display_mode tpk_f07a_0102_mode = { 2431 .clock = 33260, 2432 .hdisplay = 800, 2433 .hsync_start = 800 + 40, 2434 .hsync_end = 800 + 40 + 128, 2435 .htotal = 800 + 40 + 128 + 88, 2436 .vdisplay = 480, 2437 .vsync_start = 480 + 10, 2438 .vsync_end = 480 + 10 + 2, 2439 .vtotal = 480 + 10 + 2 + 33, 2440 .vrefresh = 60, 2441 }; 2442 2443 static const struct panel_desc tpk_f07a_0102 = { 2444 .modes = &tpk_f07a_0102_mode, 2445 .num_modes = 1, 2446 .size = { 2447 .width = 152, 2448 .height = 91, 2449 }, 2450 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2451 }; 2452 2453 static const struct drm_display_mode tpk_f10a_0102_mode = { 2454 .clock = 45000, 2455 .hdisplay = 1024, 2456 .hsync_start = 1024 + 176, 2457 .hsync_end = 1024 + 176 + 5, 2458 .htotal = 1024 + 176 + 5 + 88, 2459 .vdisplay = 600, 2460 .vsync_start = 600 + 20, 2461 .vsync_end = 600 + 20 + 5, 2462 .vtotal = 600 + 20 + 5 + 25, 2463 .vrefresh = 60, 2464 }; 2465 2466 static const struct panel_desc tpk_f10a_0102 = { 2467 .modes = &tpk_f10a_0102_mode, 2468 .num_modes = 1, 2469 .size = { 2470 .width = 223, 2471 .height = 125, 2472 }, 2473 }; 2474 2475 static const struct display_timing urt_umsh_8596md_timing = { 2476 .pixelclock = { 33260000, 33260000, 33260000 }, 2477 .hactive = { 800, 800, 800 }, 2478 .hfront_porch = { 41, 41, 41 }, 2479 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 2480 .hsync_len = { 71, 128, 128 }, 2481 .vactive = { 480, 480, 480 }, 2482 .vfront_porch = { 10, 10, 10 }, 2483 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 2484 .vsync_len = { 2, 2, 2 }, 2485 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2486 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2487 }; 2488 2489 static const struct panel_desc urt_umsh_8596md_lvds = { 2490 .timings = &urt_umsh_8596md_timing, 2491 .num_timings = 1, 2492 .bpc = 6, 2493 .size = { 2494 .width = 152, 2495 .height = 91, 2496 }, 2497 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2498 }; 2499 2500 static const struct panel_desc urt_umsh_8596md_parallel = { 2501 .timings = &urt_umsh_8596md_timing, 2502 .num_timings = 1, 2503 .bpc = 6, 2504 .size = { 2505 .width = 152, 2506 .height = 91, 2507 }, 2508 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2509 }; 2510 2511 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 2512 .clock = 6410, 2513 .hdisplay = 320, 2514 .hsync_start = 320 + 20, 2515 .hsync_end = 320 + 20 + 30, 2516 .htotal = 320 + 20 + 30 + 38, 2517 .vdisplay = 240, 2518 .vsync_start = 240 + 4, 2519 .vsync_end = 240 + 4 + 3, 2520 .vtotal = 240 + 4 + 3 + 15, 2521 .vrefresh = 60, 2522 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2523 }; 2524 2525 static const struct panel_desc winstar_wf35ltiacd = { 2526 .modes = &winstar_wf35ltiacd_mode, 2527 .num_modes = 1, 2528 .bpc = 8, 2529 .size = { 2530 .width = 70, 2531 .height = 53, 2532 }, 2533 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2534 }; 2535 2536 static const struct drm_display_mode arm_rtsm_mode[] = { 2537 { 2538 .clock = 65000, 2539 .hdisplay = 1024, 2540 .hsync_start = 1024 + 24, 2541 .hsync_end = 1024 + 24 + 136, 2542 .htotal = 1024 + 24 + 136 + 160, 2543 .vdisplay = 768, 2544 .vsync_start = 768 + 3, 2545 .vsync_end = 768 + 3 + 6, 2546 .vtotal = 768 + 3 + 6 + 29, 2547 .vrefresh = 60, 2548 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2549 }, 2550 }; 2551 2552 static const struct panel_desc arm_rtsm = { 2553 .modes = arm_rtsm_mode, 2554 .num_modes = 1, 2555 .bpc = 8, 2556 .size = { 2557 .width = 400, 2558 .height = 300, 2559 }, 2560 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2561 }; 2562 2563 static const struct of_device_id platform_of_match[] = { 2564 { 2565 .compatible = "ampire,am-480272h3tmqw-t01h", 2566 .data = &ire_am_480272h3tmqw_t01h, 2567 }, { 2568 .compatible = "ampire,am800480r3tmqwa1h", 2569 .data = &ire_am800480r3tmqwa1h, 2570 }, { 2571 .compatible = "arm,rtsm-display", 2572 .data = &arm_rtsm, 2573 }, { 2574 .compatible = "auo,b101aw03", 2575 .data = &auo_b101aw03, 2576 }, { 2577 .compatible = "auo,b101ean01", 2578 .data = &auo_b101ean01, 2579 }, { 2580 .compatible = "auo,b101xtn01", 2581 .data = &auo_b101xtn01, 2582 }, { 2583 .compatible = "auo,b116xw03", 2584 .data = &auo_b116xw03, 2585 }, { 2586 .compatible = "auo,b133htn01", 2587 .data = &auo_b133htn01, 2588 }, { 2589 .compatible = "auo,b133xtn01", 2590 .data = &auo_b133xtn01, 2591 }, { 2592 .compatible = "auo,g070vvn01", 2593 .data = &auo_g070vvn01, 2594 }, { 2595 .compatible = "auo,g101evn010", 2596 .data = &auo_g101evn010, 2597 }, { 2598 .compatible = "auo,g104sn02", 2599 .data = &auo_g104sn02, 2600 }, { 2601 .compatible = "auo,g133han01", 2602 .data = &auo_g133han01, 2603 }, { 2604 .compatible = "auo,g185han01", 2605 .data = &auo_g185han01, 2606 }, { 2607 .compatible = "auo,p320hvn03", 2608 .data = &auo_p320hvn03, 2609 }, { 2610 .compatible = "auo,t215hvn01", 2611 .data = &auo_t215hvn01, 2612 }, { 2613 .compatible = "avic,tm070ddh03", 2614 .data = &avic_tm070ddh03, 2615 }, { 2616 .compatible = "bananapi,s070wv20-ct16", 2617 .data = &bananapi_s070wv20_ct16, 2618 }, { 2619 .compatible = "boe,hv070wsa-100", 2620 .data = &boe_hv070wsa 2621 }, { 2622 .compatible = "boe,nv101wxmn51", 2623 .data = &boe_nv101wxmn51, 2624 }, { 2625 .compatible = "cdtech,s043wq26h-ct7", 2626 .data = &cdtech_s043wq26h_ct7, 2627 }, { 2628 .compatible = "cdtech,s070wv95-ct16", 2629 .data = &cdtech_s070wv95_ct16, 2630 }, { 2631 .compatible = "chunghwa,claa070wp03xg", 2632 .data = &chunghwa_claa070wp03xg, 2633 }, { 2634 .compatible = "chunghwa,claa101wa01a", 2635 .data = &chunghwa_claa101wa01a 2636 }, { 2637 .compatible = "chunghwa,claa101wb01", 2638 .data = &chunghwa_claa101wb01 2639 }, { 2640 .compatible = "dataimage,scf0700c48ggu18", 2641 .data = &dataimage_scf0700c48ggu18, 2642 }, { 2643 .compatible = "dlc,dlc0700yzg-1", 2644 .data = &dlc_dlc0700yzg_1, 2645 }, { 2646 .compatible = "dlc,dlc1010gig", 2647 .data = &dlc_dlc1010gig, 2648 }, { 2649 .compatible = "edt,et057090dhu", 2650 .data = &edt_et057090dhu, 2651 }, { 2652 .compatible = "edt,et070080dh6", 2653 .data = &edt_etm0700g0dh6, 2654 }, { 2655 .compatible = "edt,etm0700g0dh6", 2656 .data = &edt_etm0700g0dh6, 2657 }, { 2658 .compatible = "edt,etm0700g0bdh6", 2659 .data = &edt_etm0700g0bdh6, 2660 }, { 2661 .compatible = "edt,etm0700g0edh6", 2662 .data = &edt_etm0700g0bdh6, 2663 }, { 2664 .compatible = "foxlink,fl500wvr00-a0t", 2665 .data = &foxlink_fl500wvr00_a0t, 2666 }, { 2667 .compatible = "giantplus,gpg482739qs5", 2668 .data = &giantplus_gpg482739qs5 2669 }, { 2670 .compatible = "hannstar,hsd070pww1", 2671 .data = &hannstar_hsd070pww1, 2672 }, { 2673 .compatible = "hannstar,hsd100pxn1", 2674 .data = &hannstar_hsd100pxn1, 2675 }, { 2676 .compatible = "hit,tx23d38vm0caa", 2677 .data = &hitachi_tx23d38vm0caa 2678 }, { 2679 .compatible = "innolux,at043tn24", 2680 .data = &innolux_at043tn24, 2681 }, { 2682 .compatible = "innolux,at070tn92", 2683 .data = &innolux_at070tn92, 2684 }, { 2685 .compatible = "innolux,g070y2-l01", 2686 .data = &innolux_g070y2_l01, 2687 }, { 2688 .compatible = "innolux,g101ice-l01", 2689 .data = &innolux_g101ice_l01 2690 }, { 2691 .compatible = "innolux,g121i1-l01", 2692 .data = &innolux_g121i1_l01 2693 }, { 2694 .compatible = "innolux,g121x1-l03", 2695 .data = &innolux_g121x1_l03, 2696 }, { 2697 .compatible = "innolux,n116bge", 2698 .data = &innolux_n116bge, 2699 }, { 2700 .compatible = "innolux,n156bge-l21", 2701 .data = &innolux_n156bge_l21, 2702 }, { 2703 .compatible = "innolux,p120zdg-bf1", 2704 .data = &innolux_p120zdg_bf1, 2705 }, { 2706 .compatible = "innolux,zj070na-01p", 2707 .data = &innolux_zj070na_01p, 2708 }, { 2709 .compatible = "koe,tx31d200vm0baa", 2710 .data = &koe_tx31d200vm0baa, 2711 }, { 2712 .compatible = "kyo,tcg121xglp", 2713 .data = &kyo_tcg121xglp, 2714 }, { 2715 .compatible = "lemaker,bl035-rgb-002", 2716 .data = &lemaker_bl035_rgb_002, 2717 }, { 2718 .compatible = "lg,lb070wv8", 2719 .data = &lg_lb070wv8, 2720 }, { 2721 .compatible = "lg,lp079qx1-sp0v", 2722 .data = &lg_lp079qx1_sp0v, 2723 }, { 2724 .compatible = "lg,lp097qx1-spa1", 2725 .data = &lg_lp097qx1_spa1, 2726 }, { 2727 .compatible = "lg,lp120up1", 2728 .data = &lg_lp120up1, 2729 }, { 2730 .compatible = "lg,lp129qe", 2731 .data = &lg_lp129qe, 2732 }, { 2733 .compatible = "mitsubishi,aa070mc01-ca1", 2734 .data = &mitsubishi_aa070mc01, 2735 }, { 2736 .compatible = "nec,nl12880bc20-05", 2737 .data = &nec_nl12880bc20_05, 2738 }, { 2739 .compatible = "nec,nl4827hc19-05b", 2740 .data = &nec_nl4827hc19_05b, 2741 }, { 2742 .compatible = "netron-dy,e231732", 2743 .data = &netron_dy_e231732, 2744 }, { 2745 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 2746 .data = &newhaven_nhd_43_480272ef_atxl, 2747 }, { 2748 .compatible = "nlt,nl192108ac18-02d", 2749 .data = &nlt_nl192108ac18_02d, 2750 }, { 2751 .compatible = "nvd,9128", 2752 .data = &nvd_9128, 2753 }, { 2754 .compatible = "okaya,rs800480t-7x0gp", 2755 .data = &okaya_rs800480t_7x0gp, 2756 }, { 2757 .compatible = "olimex,lcd-olinuxino-43-ts", 2758 .data = &olimex_lcd_olinuxino_43ts, 2759 }, { 2760 .compatible = "ontat,yx700wv03", 2761 .data = &ontat_yx700wv03, 2762 }, { 2763 .compatible = "ortustech,com43h4m85ulc", 2764 .data = &ortustech_com43h4m85ulc, 2765 }, { 2766 .compatible = "osddisplays,osd070t1718-19ts", 2767 .data = &osddisplays_osd070t1718_19ts, 2768 }, { 2769 .compatible = "pda,91-00156-a0", 2770 .data = &pda_91_00156_a0, 2771 }, { 2772 .compatible = "qiaodian,qd43003c0-40", 2773 .data = &qd43003c0_40, 2774 }, { 2775 .compatible = "rocktech,rk070er9427", 2776 .data = &rocktech_rk070er9427, 2777 }, { 2778 .compatible = "samsung,lsn122dl01-c01", 2779 .data = &samsung_lsn122dl01_c01, 2780 }, { 2781 .compatible = "samsung,ltn101nt05", 2782 .data = &samsung_ltn101nt05, 2783 }, { 2784 .compatible = "samsung,ltn140at29-301", 2785 .data = &samsung_ltn140at29_301, 2786 }, { 2787 .compatible = "sharp,lq035q7db03", 2788 .data = &sharp_lq035q7db03, 2789 }, { 2790 .compatible = "sharp,lq101k1ly04", 2791 .data = &sharp_lq101k1ly04, 2792 }, { 2793 .compatible = "sharp,lq123p1jx31", 2794 .data = &sharp_lq123p1jx31, 2795 }, { 2796 .compatible = "sharp,lq150x1lg11", 2797 .data = &sharp_lq150x1lg11, 2798 }, { 2799 .compatible = "shelly,sca07010-bfn-lnn", 2800 .data = &shelly_sca07010_bfn_lnn, 2801 }, { 2802 .compatible = "starry,kr122ea0sra", 2803 .data = &starry_kr122ea0sra, 2804 }, { 2805 .compatible = "tianma,tm070jdhg30", 2806 .data = &tianma_tm070jdhg30, 2807 }, { 2808 .compatible = "tianma,tm070rvhg71", 2809 .data = &tianma_tm070rvhg71, 2810 }, { 2811 .compatible = "toshiba,lt089ac29000", 2812 .data = &toshiba_lt089ac29000, 2813 }, { 2814 .compatible = "tpk,f07a-0102", 2815 .data = &tpk_f07a_0102, 2816 }, { 2817 .compatible = "tpk,f10a-0102", 2818 .data = &tpk_f10a_0102, 2819 }, { 2820 .compatible = "urt,umsh-8596md-t", 2821 .data = &urt_umsh_8596md_parallel, 2822 }, { 2823 .compatible = "urt,umsh-8596md-1t", 2824 .data = &urt_umsh_8596md_parallel, 2825 }, { 2826 .compatible = "urt,umsh-8596md-7t", 2827 .data = &urt_umsh_8596md_parallel, 2828 }, { 2829 .compatible = "urt,umsh-8596md-11t", 2830 .data = &urt_umsh_8596md_lvds, 2831 }, { 2832 .compatible = "urt,umsh-8596md-19t", 2833 .data = &urt_umsh_8596md_lvds, 2834 }, { 2835 .compatible = "urt,umsh-8596md-20t", 2836 .data = &urt_umsh_8596md_parallel, 2837 }, { 2838 .compatible = "winstar,wf35ltiacd", 2839 .data = &winstar_wf35ltiacd, 2840 }, { 2841 /* sentinel */ 2842 } 2843 }; 2844 MODULE_DEVICE_TABLE(of, platform_of_match); 2845 2846 static int panel_simple_platform_probe(struct platform_device *pdev) 2847 { 2848 const struct of_device_id *id; 2849 2850 id = of_match_node(platform_of_match, pdev->dev.of_node); 2851 if (!id) 2852 return -ENODEV; 2853 2854 return panel_simple_probe(&pdev->dev, id->data); 2855 } 2856 2857 static int panel_simple_platform_remove(struct platform_device *pdev) 2858 { 2859 return panel_simple_remove(&pdev->dev); 2860 } 2861 2862 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2863 { 2864 panel_simple_shutdown(&pdev->dev); 2865 } 2866 2867 static struct platform_driver panel_simple_platform_driver = { 2868 .driver = { 2869 .name = "panel-simple", 2870 .of_match_table = platform_of_match, 2871 }, 2872 .probe = panel_simple_platform_probe, 2873 .remove = panel_simple_platform_remove, 2874 .shutdown = panel_simple_platform_shutdown, 2875 }; 2876 2877 struct panel_desc_dsi { 2878 struct panel_desc desc; 2879 2880 unsigned long flags; 2881 enum mipi_dsi_pixel_format format; 2882 unsigned int lanes; 2883 }; 2884 2885 static const struct drm_display_mode auo_b080uan01_mode = { 2886 .clock = 154500, 2887 .hdisplay = 1200, 2888 .hsync_start = 1200 + 62, 2889 .hsync_end = 1200 + 62 + 4, 2890 .htotal = 1200 + 62 + 4 + 62, 2891 .vdisplay = 1920, 2892 .vsync_start = 1920 + 9, 2893 .vsync_end = 1920 + 9 + 2, 2894 .vtotal = 1920 + 9 + 2 + 8, 2895 .vrefresh = 60, 2896 }; 2897 2898 static const struct panel_desc_dsi auo_b080uan01 = { 2899 .desc = { 2900 .modes = &auo_b080uan01_mode, 2901 .num_modes = 1, 2902 .bpc = 8, 2903 .size = { 2904 .width = 108, 2905 .height = 272, 2906 }, 2907 }, 2908 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2909 .format = MIPI_DSI_FMT_RGB888, 2910 .lanes = 4, 2911 }; 2912 2913 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2914 .clock = 160000, 2915 .hdisplay = 1200, 2916 .hsync_start = 1200 + 120, 2917 .hsync_end = 1200 + 120 + 20, 2918 .htotal = 1200 + 120 + 20 + 21, 2919 .vdisplay = 1920, 2920 .vsync_start = 1920 + 21, 2921 .vsync_end = 1920 + 21 + 3, 2922 .vtotal = 1920 + 21 + 3 + 18, 2923 .vrefresh = 60, 2924 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2925 }; 2926 2927 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2928 .desc = { 2929 .modes = &boe_tv080wum_nl0_mode, 2930 .num_modes = 1, 2931 .size = { 2932 .width = 107, 2933 .height = 172, 2934 }, 2935 }, 2936 .flags = MIPI_DSI_MODE_VIDEO | 2937 MIPI_DSI_MODE_VIDEO_BURST | 2938 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2939 .format = MIPI_DSI_FMT_RGB888, 2940 .lanes = 4, 2941 }; 2942 2943 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2944 .clock = 71000, 2945 .hdisplay = 800, 2946 .hsync_start = 800 + 32, 2947 .hsync_end = 800 + 32 + 1, 2948 .htotal = 800 + 32 + 1 + 57, 2949 .vdisplay = 1280, 2950 .vsync_start = 1280 + 28, 2951 .vsync_end = 1280 + 28 + 1, 2952 .vtotal = 1280 + 28 + 1 + 14, 2953 .vrefresh = 60, 2954 }; 2955 2956 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2957 .desc = { 2958 .modes = &lg_ld070wx3_sl01_mode, 2959 .num_modes = 1, 2960 .bpc = 8, 2961 .size = { 2962 .width = 94, 2963 .height = 151, 2964 }, 2965 }, 2966 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2967 .format = MIPI_DSI_FMT_RGB888, 2968 .lanes = 4, 2969 }; 2970 2971 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2972 .clock = 67000, 2973 .hdisplay = 720, 2974 .hsync_start = 720 + 12, 2975 .hsync_end = 720 + 12 + 4, 2976 .htotal = 720 + 12 + 4 + 112, 2977 .vdisplay = 1280, 2978 .vsync_start = 1280 + 8, 2979 .vsync_end = 1280 + 8 + 4, 2980 .vtotal = 1280 + 8 + 4 + 12, 2981 .vrefresh = 60, 2982 }; 2983 2984 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2985 .desc = { 2986 .modes = &lg_lh500wx1_sd03_mode, 2987 .num_modes = 1, 2988 .bpc = 8, 2989 .size = { 2990 .width = 62, 2991 .height = 110, 2992 }, 2993 }, 2994 .flags = MIPI_DSI_MODE_VIDEO, 2995 .format = MIPI_DSI_FMT_RGB888, 2996 .lanes = 4, 2997 }; 2998 2999 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 3000 .clock = 157200, 3001 .hdisplay = 1920, 3002 .hsync_start = 1920 + 154, 3003 .hsync_end = 1920 + 154 + 16, 3004 .htotal = 1920 + 154 + 16 + 32, 3005 .vdisplay = 1200, 3006 .vsync_start = 1200 + 17, 3007 .vsync_end = 1200 + 17 + 2, 3008 .vtotal = 1200 + 17 + 2 + 16, 3009 .vrefresh = 60, 3010 }; 3011 3012 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 3013 .desc = { 3014 .modes = &panasonic_vvx10f004b00_mode, 3015 .num_modes = 1, 3016 .bpc = 8, 3017 .size = { 3018 .width = 217, 3019 .height = 136, 3020 }, 3021 }, 3022 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 3023 MIPI_DSI_CLOCK_NON_CONTINUOUS, 3024 .format = MIPI_DSI_FMT_RGB888, 3025 .lanes = 4, 3026 }; 3027 3028 static const struct drm_display_mode lg_acx467akm_7_mode = { 3029 .clock = 150000, 3030 .hdisplay = 1080, 3031 .hsync_start = 1080 + 2, 3032 .hsync_end = 1080 + 2 + 2, 3033 .htotal = 1080 + 2 + 2 + 2, 3034 .vdisplay = 1920, 3035 .vsync_start = 1920 + 2, 3036 .vsync_end = 1920 + 2 + 2, 3037 .vtotal = 1920 + 2 + 2 + 2, 3038 .vrefresh = 60, 3039 }; 3040 3041 static const struct panel_desc_dsi lg_acx467akm_7 = { 3042 .desc = { 3043 .modes = &lg_acx467akm_7_mode, 3044 .num_modes = 1, 3045 .bpc = 8, 3046 .size = { 3047 .width = 62, 3048 .height = 110, 3049 }, 3050 }, 3051 .flags = 0, 3052 .format = MIPI_DSI_FMT_RGB888, 3053 .lanes = 4, 3054 }; 3055 3056 static const struct of_device_id dsi_of_match[] = { 3057 { 3058 .compatible = "auo,b080uan01", 3059 .data = &auo_b080uan01 3060 }, { 3061 .compatible = "boe,tv080wum-nl0", 3062 .data = &boe_tv080wum_nl0 3063 }, { 3064 .compatible = "lg,ld070wx3-sl01", 3065 .data = &lg_ld070wx3_sl01 3066 }, { 3067 .compatible = "lg,lh500wx1-sd03", 3068 .data = &lg_lh500wx1_sd03 3069 }, { 3070 .compatible = "panasonic,vvx10f004b00", 3071 .data = &panasonic_vvx10f004b00 3072 }, { 3073 .compatible = "lg,acx467akm-7", 3074 .data = &lg_acx467akm_7 3075 }, { 3076 /* sentinel */ 3077 } 3078 }; 3079 MODULE_DEVICE_TABLE(of, dsi_of_match); 3080 3081 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 3082 { 3083 const struct panel_desc_dsi *desc; 3084 const struct of_device_id *id; 3085 int err; 3086 3087 id = of_match_node(dsi_of_match, dsi->dev.of_node); 3088 if (!id) 3089 return -ENODEV; 3090 3091 desc = id->data; 3092 3093 err = panel_simple_probe(&dsi->dev, &desc->desc); 3094 if (err < 0) 3095 return err; 3096 3097 dsi->mode_flags = desc->flags; 3098 dsi->format = desc->format; 3099 dsi->lanes = desc->lanes; 3100 3101 return mipi_dsi_attach(dsi); 3102 } 3103 3104 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 3105 { 3106 int err; 3107 3108 err = mipi_dsi_detach(dsi); 3109 if (err < 0) 3110 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 3111 3112 return panel_simple_remove(&dsi->dev); 3113 } 3114 3115 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 3116 { 3117 panel_simple_shutdown(&dsi->dev); 3118 } 3119 3120 static struct mipi_dsi_driver panel_simple_dsi_driver = { 3121 .driver = { 3122 .name = "panel-simple-dsi", 3123 .of_match_table = dsi_of_match, 3124 }, 3125 .probe = panel_simple_dsi_probe, 3126 .remove = panel_simple_dsi_remove, 3127 .shutdown = panel_simple_dsi_shutdown, 3128 }; 3129 3130 static int __init panel_simple_init(void) 3131 { 3132 int err; 3133 3134 err = platform_driver_register(&panel_simple_platform_driver); 3135 if (err < 0) 3136 return err; 3137 3138 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 3139 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 3140 if (err < 0) 3141 return err; 3142 } 3143 3144 return 0; 3145 } 3146 module_init(panel_simple_init); 3147 3148 static void __exit panel_simple_exit(void) 3149 { 3150 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 3151 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 3152 3153 platform_driver_unregister(&panel_simple_platform_driver); 3154 } 3155 module_exit(panel_simple_exit); 3156 3157 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 3158 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 3159 MODULE_LICENSE("GPL and additional rights"); 3160