1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 583 &panel_simple_funcs, desc->connector_type); 584 if (IS_ERR(panel)) 585 return PTR_ERR(panel); 586 587 panel->desc = desc; 588 589 panel->supply = devm_regulator_get(dev, "power"); 590 if (IS_ERR(panel->supply)) 591 return PTR_ERR(panel->supply); 592 593 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 594 GPIOD_OUT_LOW); 595 if (IS_ERR(panel->enable_gpio)) 596 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 597 "failed to request GPIO\n"); 598 599 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 600 if (err) { 601 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 602 return err; 603 } 604 605 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 606 if (ddc) { 607 panel->ddc = of_find_i2c_adapter_by_node(ddc); 608 of_node_put(ddc); 609 610 if (!panel->ddc) 611 return -EPROBE_DEFER; 612 } 613 614 if (desc == &panel_dpi) { 615 /* Handle the generic panel-dpi binding */ 616 err = panel_dpi_probe(dev, panel); 617 if (err) 618 goto free_ddc; 619 desc = panel->desc; 620 } else { 621 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 622 panel_simple_parse_panel_timing_node(dev, panel, &dt); 623 } 624 625 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 626 /* Optional data-mapping property for overriding bus format */ 627 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 628 if (err) 629 goto free_ddc; 630 } 631 632 connector_type = desc->connector_type; 633 /* Catch common mistakes for panels. */ 634 switch (connector_type) { 635 case 0: 636 dev_warn(dev, "Specify missing connector_type\n"); 637 connector_type = DRM_MODE_CONNECTOR_DPI; 638 break; 639 case DRM_MODE_CONNECTOR_LVDS: 640 WARN_ON(desc->bus_flags & 641 ~(DRM_BUS_FLAG_DE_LOW | 642 DRM_BUS_FLAG_DE_HIGH | 643 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 644 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 645 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 647 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 648 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 649 desc->bpc != 6); 650 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 651 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 652 desc->bpc != 8); 653 break; 654 case DRM_MODE_CONNECTOR_eDP: 655 dev_warn(dev, "eDP panels moved to panel-edp\n"); 656 err = -EINVAL; 657 goto free_ddc; 658 case DRM_MODE_CONNECTOR_DSI: 659 if (desc->bpc != 6 && desc->bpc != 8) 660 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 661 break; 662 case DRM_MODE_CONNECTOR_DPI: 663 bus_flags = DRM_BUS_FLAG_DE_LOW | 664 DRM_BUS_FLAG_DE_HIGH | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 666 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 667 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 668 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 669 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 670 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 671 if (desc->bus_flags & ~bus_flags) 672 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 673 if (!(desc->bus_flags & bus_flags)) 674 dev_warn(dev, "Specify missing bus_flags\n"); 675 if (desc->bus_format == 0) 676 dev_warn(dev, "Specify missing bus_format\n"); 677 if (desc->bpc != 6 && desc->bpc != 8) 678 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 679 break; 680 default: 681 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 682 connector_type = DRM_MODE_CONNECTOR_DPI; 683 break; 684 } 685 686 dev_set_drvdata(dev, panel); 687 688 /* 689 * We use runtime PM for prepare / unprepare since those power the panel 690 * on and off and those can be very slow operations. This is important 691 * to optimize powering the panel on briefly to read the EDID before 692 * fully enabling the panel. 693 */ 694 pm_runtime_enable(dev); 695 pm_runtime_set_autosuspend_delay(dev, 1000); 696 pm_runtime_use_autosuspend(dev); 697 698 err = drm_panel_of_backlight(&panel->base); 699 if (err) { 700 dev_err_probe(dev, err, "Could not find backlight\n"); 701 goto disable_pm_runtime; 702 } 703 704 drm_panel_add(&panel->base); 705 706 return 0; 707 708 disable_pm_runtime: 709 pm_runtime_dont_use_autosuspend(dev); 710 pm_runtime_disable(dev); 711 free_ddc: 712 if (panel->ddc) 713 put_device(&panel->ddc->dev); 714 715 return err; 716 } 717 718 static void panel_simple_shutdown(struct device *dev) 719 { 720 struct panel_simple *panel = dev_get_drvdata(dev); 721 722 /* 723 * NOTE: the following two calls don't really belong here. It is the 724 * responsibility of a correctly written DRM modeset driver to call 725 * drm_atomic_helper_shutdown() at shutdown time and that should 726 * cause the panel to be disabled / unprepared if needed. For now, 727 * however, we'll keep these calls due to the sheer number of 728 * different DRM modeset drivers used with panel-simple. Once we've 729 * confirmed that all DRM modeset drivers using this panel properly 730 * call drm_atomic_helper_shutdown() we can simply delete the two 731 * calls below. 732 * 733 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 734 * PANEL DRIVERS. 735 * 736 * FIXME: If we're still haven't figured out if all DRM modeset 737 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 738 * managed to make sure that DRM modeset drivers get their shutdown() 739 * callback before the panel's shutdown() callback (perhaps using 740 * device link), we could add a WARN_ON here to help move forward. 741 */ 742 if (panel->base.enabled) 743 drm_panel_disable(&panel->base); 744 if (panel->base.prepared) 745 drm_panel_unprepare(&panel->base); 746 } 747 748 static void panel_simple_remove(struct device *dev) 749 { 750 struct panel_simple *panel = dev_get_drvdata(dev); 751 752 drm_panel_remove(&panel->base); 753 panel_simple_shutdown(dev); 754 755 pm_runtime_dont_use_autosuspend(dev); 756 pm_runtime_disable(dev); 757 if (panel->ddc) 758 put_device(&panel->ddc->dev); 759 } 760 761 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 762 .clock = 71100, 763 .hdisplay = 1280, 764 .hsync_start = 1280 + 40, 765 .hsync_end = 1280 + 40 + 80, 766 .htotal = 1280 + 40 + 80 + 40, 767 .vdisplay = 800, 768 .vsync_start = 800 + 3, 769 .vsync_end = 800 + 3 + 10, 770 .vtotal = 800 + 3 + 10 + 10, 771 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 772 }; 773 774 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 775 .modes = &ire_am_1280800n3tzqw_t00h_mode, 776 .num_modes = 1, 777 .bpc = 8, 778 .size = { 779 .width = 217, 780 .height = 136, 781 }, 782 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 785 }; 786 787 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 788 .clock = 9000, 789 .hdisplay = 480, 790 .hsync_start = 480 + 2, 791 .hsync_end = 480 + 2 + 41, 792 .htotal = 480 + 2 + 41 + 2, 793 .vdisplay = 272, 794 .vsync_start = 272 + 2, 795 .vsync_end = 272 + 2 + 10, 796 .vtotal = 272 + 2 + 10 + 2, 797 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 798 }; 799 800 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 801 .modes = &ire_am_480272h3tmqw_t01h_mode, 802 .num_modes = 1, 803 .bpc = 8, 804 .size = { 805 .width = 99, 806 .height = 58, 807 }, 808 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 809 }; 810 811 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 812 .clock = 33333, 813 .hdisplay = 800, 814 .hsync_start = 800 + 0, 815 .hsync_end = 800 + 0 + 255, 816 .htotal = 800 + 0 + 255 + 0, 817 .vdisplay = 480, 818 .vsync_start = 480 + 2, 819 .vsync_end = 480 + 2 + 45, 820 .vtotal = 480 + 2 + 45 + 0, 821 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 822 }; 823 824 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 825 .pixelclock = { 29930000, 33260000, 36590000 }, 826 .hactive = { 800, 800, 800 }, 827 .hfront_porch = { 1, 40, 168 }, 828 .hback_porch = { 88, 88, 88 }, 829 .hsync_len = { 1, 128, 128 }, 830 .vactive = { 480, 480, 480 }, 831 .vfront_porch = { 1, 35, 37 }, 832 .vback_porch = { 8, 8, 8 }, 833 .vsync_len = { 1, 2, 2 }, 834 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 835 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 836 DISPLAY_FLAGS_SYNC_POSEDGE, 837 }; 838 839 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 840 .timings = &ire_am_800480l1tmqw_t00h_timing, 841 .num_timings = 1, 842 .bpc = 8, 843 .size = { 844 .width = 111, 845 .height = 67, 846 }, 847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 849 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 850 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 851 .connector_type = DRM_MODE_CONNECTOR_DPI, 852 }; 853 854 static const struct panel_desc ampire_am800480r3tmqwa1h = { 855 .modes = &ire_am800480r3tmqwa1h_mode, 856 .num_modes = 1, 857 .bpc = 6, 858 .size = { 859 .width = 152, 860 .height = 91, 861 }, 862 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 863 }; 864 865 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 866 .pixelclock = { 34500000, 39600000, 50400000 }, 867 .hactive = { 800, 800, 800 }, 868 .hfront_porch = { 12, 112, 312 }, 869 .hback_porch = { 87, 87, 48 }, 870 .hsync_len = { 1, 1, 40 }, 871 .vactive = { 600, 600, 600 }, 872 .vfront_porch = { 1, 21, 61 }, 873 .vback_porch = { 38, 38, 19 }, 874 .vsync_len = { 1, 1, 20 }, 875 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 876 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 877 DISPLAY_FLAGS_SYNC_POSEDGE, 878 }; 879 880 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 881 .timings = &ire_am800600p5tmqw_tb8h_timing, 882 .num_timings = 1, 883 .bpc = 6, 884 .size = { 885 .width = 162, 886 .height = 122, 887 }, 888 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 889 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 890 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 891 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 892 .connector_type = DRM_MODE_CONNECTOR_DPI, 893 }; 894 895 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 896 .pixelclock = { 26400000, 33300000, 46800000 }, 897 .hactive = { 800, 800, 800 }, 898 .hfront_porch = { 16, 210, 354 }, 899 .hback_porch = { 45, 36, 6 }, 900 .hsync_len = { 1, 10, 40 }, 901 .vactive = { 480, 480, 480 }, 902 .vfront_porch = { 7, 22, 147 }, 903 .vback_porch = { 22, 13, 3 }, 904 .vsync_len = { 1, 10, 20 }, 905 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 906 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 907 }; 908 909 static const struct panel_desc armadeus_st0700_adapt = { 910 .timings = &santek_st0700i5y_rbslw_f_timing, 911 .num_timings = 1, 912 .bpc = 6, 913 .size = { 914 .width = 154, 915 .height = 86, 916 }, 917 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 918 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 919 }; 920 921 static const struct drm_display_mode auo_b101aw03_mode = { 922 .clock = 51450, 923 .hdisplay = 1024, 924 .hsync_start = 1024 + 156, 925 .hsync_end = 1024 + 156 + 8, 926 .htotal = 1024 + 156 + 8 + 156, 927 .vdisplay = 600, 928 .vsync_start = 600 + 16, 929 .vsync_end = 600 + 16 + 6, 930 .vtotal = 600 + 16 + 6 + 16, 931 }; 932 933 static const struct panel_desc auo_b101aw03 = { 934 .modes = &auo_b101aw03_mode, 935 .num_modes = 1, 936 .bpc = 6, 937 .size = { 938 .width = 223, 939 .height = 125, 940 }, 941 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 942 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 943 .connector_type = DRM_MODE_CONNECTOR_LVDS, 944 }; 945 946 static const struct drm_display_mode auo_b101xtn01_mode = { 947 .clock = 72000, 948 .hdisplay = 1366, 949 .hsync_start = 1366 + 20, 950 .hsync_end = 1366 + 20 + 70, 951 .htotal = 1366 + 20 + 70, 952 .vdisplay = 768, 953 .vsync_start = 768 + 14, 954 .vsync_end = 768 + 14 + 42, 955 .vtotal = 768 + 14 + 42, 956 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 957 }; 958 959 static const struct panel_desc auo_b101xtn01 = { 960 .modes = &auo_b101xtn01_mode, 961 .num_modes = 1, 962 .bpc = 6, 963 .size = { 964 .width = 223, 965 .height = 125, 966 }, 967 }; 968 969 static const struct drm_display_mode auo_b116xw03_mode = { 970 .clock = 70589, 971 .hdisplay = 1366, 972 .hsync_start = 1366 + 40, 973 .hsync_end = 1366 + 40 + 40, 974 .htotal = 1366 + 40 + 40 + 32, 975 .vdisplay = 768, 976 .vsync_start = 768 + 10, 977 .vsync_end = 768 + 10 + 12, 978 .vtotal = 768 + 10 + 12 + 6, 979 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 980 }; 981 982 static const struct panel_desc auo_b116xw03 = { 983 .modes = &auo_b116xw03_mode, 984 .num_modes = 1, 985 .bpc = 6, 986 .size = { 987 .width = 256, 988 .height = 144, 989 }, 990 .delay = { 991 .prepare = 1, 992 .enable = 200, 993 .disable = 200, 994 .unprepare = 500, 995 }, 996 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 997 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 998 .connector_type = DRM_MODE_CONNECTOR_LVDS, 999 }; 1000 1001 static const struct display_timing auo_g070vvn01_timings = { 1002 .pixelclock = { 33300000, 34209000, 45000000 }, 1003 .hactive = { 800, 800, 800 }, 1004 .hfront_porch = { 20, 40, 200 }, 1005 .hback_porch = { 87, 40, 1 }, 1006 .hsync_len = { 1, 48, 87 }, 1007 .vactive = { 480, 480, 480 }, 1008 .vfront_porch = { 5, 13, 200 }, 1009 .vback_porch = { 31, 31, 29 }, 1010 .vsync_len = { 1, 1, 3 }, 1011 }; 1012 1013 static const struct panel_desc auo_g070vvn01 = { 1014 .timings = &auo_g070vvn01_timings, 1015 .num_timings = 1, 1016 .bpc = 8, 1017 .size = { 1018 .width = 152, 1019 .height = 91, 1020 }, 1021 .delay = { 1022 .prepare = 200, 1023 .enable = 50, 1024 .disable = 50, 1025 .unprepare = 1000, 1026 }, 1027 }; 1028 1029 static const struct display_timing auo_g101evn010_timing = { 1030 .pixelclock = { 64000000, 68930000, 85000000 }, 1031 .hactive = { 1280, 1280, 1280 }, 1032 .hfront_porch = { 8, 64, 256 }, 1033 .hback_porch = { 8, 64, 256 }, 1034 .hsync_len = { 40, 168, 767 }, 1035 .vactive = { 800, 800, 800 }, 1036 .vfront_porch = { 4, 8, 100 }, 1037 .vback_porch = { 4, 8, 100 }, 1038 .vsync_len = { 8, 16, 223 }, 1039 }; 1040 1041 static const struct panel_desc auo_g101evn010 = { 1042 .timings = &auo_g101evn010_timing, 1043 .num_timings = 1, 1044 .bpc = 6, 1045 .size = { 1046 .width = 216, 1047 .height = 135, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1050 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052 }; 1053 1054 static const struct drm_display_mode auo_g104sn02_mode = { 1055 .clock = 40000, 1056 .hdisplay = 800, 1057 .hsync_start = 800 + 40, 1058 .hsync_end = 800 + 40 + 216, 1059 .htotal = 800 + 40 + 216 + 128, 1060 .vdisplay = 600, 1061 .vsync_start = 600 + 10, 1062 .vsync_end = 600 + 10 + 35, 1063 .vtotal = 600 + 10 + 35 + 2, 1064 }; 1065 1066 static const struct panel_desc auo_g104sn02 = { 1067 .modes = &auo_g104sn02_mode, 1068 .num_modes = 1, 1069 .bpc = 8, 1070 .size = { 1071 .width = 211, 1072 .height = 158, 1073 }, 1074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1076 }; 1077 1078 static const struct drm_display_mode auo_g104stn01_mode = { 1079 .clock = 40000, 1080 .hdisplay = 800, 1081 .hsync_start = 800 + 40, 1082 .hsync_end = 800 + 40 + 88, 1083 .htotal = 800 + 40 + 88 + 128, 1084 .vdisplay = 600, 1085 .vsync_start = 600 + 1, 1086 .vsync_end = 600 + 1 + 23, 1087 .vtotal = 600 + 1 + 23 + 4, 1088 }; 1089 1090 static const struct panel_desc auo_g104stn01 = { 1091 .modes = &auo_g104stn01_mode, 1092 .num_modes = 1, 1093 .bpc = 8, 1094 .size = { 1095 .width = 211, 1096 .height = 158, 1097 }, 1098 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1100 }; 1101 1102 static const struct display_timing auo_g121ean01_timing = { 1103 .pixelclock = { 60000000, 74400000, 90000000 }, 1104 .hactive = { 1280, 1280, 1280 }, 1105 .hfront_porch = { 20, 50, 100 }, 1106 .hback_porch = { 20, 50, 100 }, 1107 .hsync_len = { 30, 100, 200 }, 1108 .vactive = { 800, 800, 800 }, 1109 .vfront_porch = { 2, 10, 25 }, 1110 .vback_porch = { 2, 10, 25 }, 1111 .vsync_len = { 4, 18, 50 }, 1112 }; 1113 1114 static const struct panel_desc auo_g121ean01 = { 1115 .timings = &auo_g121ean01_timing, 1116 .num_timings = 1, 1117 .bpc = 8, 1118 .size = { 1119 .width = 261, 1120 .height = 163, 1121 }, 1122 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1123 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1124 }; 1125 1126 static const struct display_timing auo_g133han01_timings = { 1127 .pixelclock = { 134000000, 141200000, 149000000 }, 1128 .hactive = { 1920, 1920, 1920 }, 1129 .hfront_porch = { 39, 58, 77 }, 1130 .hback_porch = { 59, 88, 117 }, 1131 .hsync_len = { 28, 42, 56 }, 1132 .vactive = { 1080, 1080, 1080 }, 1133 .vfront_porch = { 3, 8, 11 }, 1134 .vback_porch = { 5, 14, 19 }, 1135 .vsync_len = { 4, 14, 19 }, 1136 }; 1137 1138 static const struct panel_desc auo_g133han01 = { 1139 .timings = &auo_g133han01_timings, 1140 .num_timings = 1, 1141 .bpc = 8, 1142 .size = { 1143 .width = 293, 1144 .height = 165, 1145 }, 1146 .delay = { 1147 .prepare = 200, 1148 .enable = 50, 1149 .disable = 50, 1150 .unprepare = 1000, 1151 }, 1152 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1153 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1154 }; 1155 1156 static const struct display_timing auo_g156han04_timings = { 1157 .pixelclock = { 137000000, 141000000, 146000000 }, 1158 .hactive = { 1920, 1920, 1920 }, 1159 .hfront_porch = { 60, 60, 60 }, 1160 .hback_porch = { 90, 92, 111 }, 1161 .hsync_len = { 32, 32, 32 }, 1162 .vactive = { 1080, 1080, 1080 }, 1163 .vfront_porch = { 12, 12, 12 }, 1164 .vback_porch = { 24, 36, 56 }, 1165 .vsync_len = { 8, 8, 8 }, 1166 }; 1167 1168 static const struct panel_desc auo_g156han04 = { 1169 .timings = &auo_g156han04_timings, 1170 .num_timings = 1, 1171 .bpc = 8, 1172 .size = { 1173 .width = 344, 1174 .height = 194, 1175 }, 1176 .delay = { 1177 .prepare = 50, /* T2 */ 1178 .enable = 200, /* T3 */ 1179 .disable = 110, /* T10 */ 1180 .unprepare = 1000, /* T13 */ 1181 }, 1182 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1183 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1184 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1185 }; 1186 1187 static const struct drm_display_mode auo_g156xtn01_mode = { 1188 .clock = 76000, 1189 .hdisplay = 1366, 1190 .hsync_start = 1366 + 33, 1191 .hsync_end = 1366 + 33 + 67, 1192 .htotal = 1560, 1193 .vdisplay = 768, 1194 .vsync_start = 768 + 4, 1195 .vsync_end = 768 + 4 + 4, 1196 .vtotal = 806, 1197 }; 1198 1199 static const struct panel_desc auo_g156xtn01 = { 1200 .modes = &auo_g156xtn01_mode, 1201 .num_modes = 1, 1202 .bpc = 8, 1203 .size = { 1204 .width = 344, 1205 .height = 194, 1206 }, 1207 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1208 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1209 }; 1210 1211 static const struct display_timing auo_g185han01_timings = { 1212 .pixelclock = { 120000000, 144000000, 175000000 }, 1213 .hactive = { 1920, 1920, 1920 }, 1214 .hfront_porch = { 36, 120, 148 }, 1215 .hback_porch = { 24, 88, 108 }, 1216 .hsync_len = { 20, 48, 64 }, 1217 .vactive = { 1080, 1080, 1080 }, 1218 .vfront_porch = { 6, 10, 40 }, 1219 .vback_porch = { 2, 5, 20 }, 1220 .vsync_len = { 2, 5, 20 }, 1221 }; 1222 1223 static const struct panel_desc auo_g185han01 = { 1224 .timings = &auo_g185han01_timings, 1225 .num_timings = 1, 1226 .bpc = 8, 1227 .size = { 1228 .width = 409, 1229 .height = 230, 1230 }, 1231 .delay = { 1232 .prepare = 50, 1233 .enable = 200, 1234 .disable = 110, 1235 .unprepare = 1000, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1239 }; 1240 1241 static const struct display_timing auo_g190ean01_timings = { 1242 .pixelclock = { 90000000, 108000000, 135000000 }, 1243 .hactive = { 1280, 1280, 1280 }, 1244 .hfront_porch = { 126, 184, 1266 }, 1245 .hback_porch = { 84, 122, 844 }, 1246 .hsync_len = { 70, 102, 704 }, 1247 .vactive = { 1024, 1024, 1024 }, 1248 .vfront_porch = { 4, 26, 76 }, 1249 .vback_porch = { 2, 8, 25 }, 1250 .vsync_len = { 2, 8, 25 }, 1251 }; 1252 1253 static const struct panel_desc auo_g190ean01 = { 1254 .timings = &auo_g190ean01_timings, 1255 .num_timings = 1, 1256 .bpc = 8, 1257 .size = { 1258 .width = 376, 1259 .height = 301, 1260 }, 1261 .delay = { 1262 .prepare = 50, 1263 .enable = 200, 1264 .disable = 110, 1265 .unprepare = 1000, 1266 }, 1267 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1268 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1269 }; 1270 1271 static const struct display_timing auo_p238han01_timings = { 1272 .pixelclock = { 107400000, 142400000, 180000000 }, 1273 .hactive = { 1920, 1920, 1920 }, 1274 .hfront_porch = { 30, 70, 650 }, 1275 .hback_porch = { 30, 70, 650 }, 1276 .hsync_len = { 20, 40, 136 }, 1277 .vactive = { 1080, 1080, 1080 }, 1278 .vfront_porch = { 5, 19, 318 }, 1279 .vback_porch = { 5, 19, 318 }, 1280 .vsync_len = { 4, 12, 120 }, 1281 }; 1282 1283 static const struct panel_desc auo_p238han01 = { 1284 .timings = &auo_p238han01_timings, 1285 .num_timings = 1, 1286 .bpc = 8, 1287 .size = { 1288 .width = 527, 1289 .height = 296, 1290 }, 1291 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1292 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1293 }; 1294 1295 static const struct display_timing auo_p320hvn03_timings = { 1296 .pixelclock = { 106000000, 148500000, 164000000 }, 1297 .hactive = { 1920, 1920, 1920 }, 1298 .hfront_porch = { 25, 50, 130 }, 1299 .hback_porch = { 25, 50, 130 }, 1300 .hsync_len = { 20, 40, 105 }, 1301 .vactive = { 1080, 1080, 1080 }, 1302 .vfront_porch = { 8, 17, 150 }, 1303 .vback_porch = { 8, 17, 150 }, 1304 .vsync_len = { 4, 11, 100 }, 1305 }; 1306 1307 static const struct panel_desc auo_p320hvn03 = { 1308 .timings = &auo_p320hvn03_timings, 1309 .num_timings = 1, 1310 .bpc = 8, 1311 .size = { 1312 .width = 698, 1313 .height = 393, 1314 }, 1315 .delay = { 1316 .prepare = 1, 1317 .enable = 450, 1318 .unprepare = 500, 1319 }, 1320 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1321 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1322 }; 1323 1324 static const struct drm_display_mode auo_t215hvn01_mode = { 1325 .clock = 148800, 1326 .hdisplay = 1920, 1327 .hsync_start = 1920 + 88, 1328 .hsync_end = 1920 + 88 + 44, 1329 .htotal = 1920 + 88 + 44 + 148, 1330 .vdisplay = 1080, 1331 .vsync_start = 1080 + 4, 1332 .vsync_end = 1080 + 4 + 5, 1333 .vtotal = 1080 + 4 + 5 + 36, 1334 }; 1335 1336 static const struct panel_desc auo_t215hvn01 = { 1337 .modes = &auo_t215hvn01_mode, 1338 .num_modes = 1, 1339 .bpc = 8, 1340 .size = { 1341 .width = 430, 1342 .height = 270, 1343 }, 1344 .delay = { 1345 .disable = 5, 1346 .unprepare = 1000, 1347 }, 1348 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1349 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1350 }; 1351 1352 static const struct drm_display_mode avic_tm070ddh03_mode = { 1353 .clock = 51200, 1354 .hdisplay = 1024, 1355 .hsync_start = 1024 + 160, 1356 .hsync_end = 1024 + 160 + 4, 1357 .htotal = 1024 + 160 + 4 + 156, 1358 .vdisplay = 600, 1359 .vsync_start = 600 + 17, 1360 .vsync_end = 600 + 17 + 1, 1361 .vtotal = 600 + 17 + 1 + 17, 1362 }; 1363 1364 static const struct panel_desc avic_tm070ddh03 = { 1365 .modes = &avic_tm070ddh03_mode, 1366 .num_modes = 1, 1367 .bpc = 8, 1368 .size = { 1369 .width = 154, 1370 .height = 90, 1371 }, 1372 .delay = { 1373 .prepare = 20, 1374 .enable = 200, 1375 .disable = 200, 1376 }, 1377 }; 1378 1379 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1380 .clock = 30000, 1381 .hdisplay = 800, 1382 .hsync_start = 800 + 40, 1383 .hsync_end = 800 + 40 + 48, 1384 .htotal = 800 + 40 + 48 + 40, 1385 .vdisplay = 480, 1386 .vsync_start = 480 + 13, 1387 .vsync_end = 480 + 13 + 3, 1388 .vtotal = 480 + 13 + 3 + 29, 1389 }; 1390 1391 static const struct panel_desc bananapi_s070wv20_ct16 = { 1392 .modes = &bananapi_s070wv20_ct16_mode, 1393 .num_modes = 1, 1394 .bpc = 6, 1395 .size = { 1396 .width = 154, 1397 .height = 86, 1398 }, 1399 }; 1400 1401 static const struct display_timing boe_av101hdt_a10_timing = { 1402 .pixelclock = { 74210000, 75330000, 76780000, }, 1403 .hactive = { 1280, 1280, 1280, }, 1404 .hfront_porch = { 10, 42, 33, }, 1405 .hback_porch = { 10, 18, 33, }, 1406 .hsync_len = { 30, 10, 30, }, 1407 .vactive = { 720, 720, 720, }, 1408 .vfront_porch = { 200, 183, 200, }, 1409 .vback_porch = { 8, 8, 8, }, 1410 .vsync_len = { 2, 19, 2, }, 1411 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1412 }; 1413 1414 static const struct panel_desc boe_av101hdt_a10 = { 1415 .timings = &boe_av101hdt_a10_timing, 1416 .num_timings = 1, 1417 .bpc = 8, 1418 .size = { 1419 .width = 224, 1420 .height = 126, 1421 }, 1422 .delay = { 1423 .enable = 50, 1424 .disable = 50, 1425 }, 1426 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1427 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1428 }; 1429 1430 static const struct display_timing boe_av123z7m_n17_timing = { 1431 .pixelclock = { 86600000, 88000000, 90800000, }, 1432 .hactive = { 1920, 1920, 1920, }, 1433 .hfront_porch = { 10, 10, 10, }, 1434 .hback_porch = { 10, 10, 10, }, 1435 .hsync_len = { 9, 12, 25, }, 1436 .vactive = { 720, 720, 720, }, 1437 .vfront_porch = { 7, 10, 13, }, 1438 .vback_porch = { 7, 10, 13, }, 1439 .vsync_len = { 7, 11, 14, }, 1440 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1441 }; 1442 1443 static const struct panel_desc boe_av123z7m_n17 = { 1444 .timings = &boe_av123z7m_n17_timing, 1445 .bpc = 8, 1446 .num_timings = 1, 1447 .size = { 1448 .width = 292, 1449 .height = 110, 1450 }, 1451 .delay = { 1452 .prepare = 50, 1453 .disable = 50, 1454 }, 1455 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1456 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1457 }; 1458 1459 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1460 .clock = 78945, 1461 .hdisplay = 1280, 1462 .hsync_start = 1280 + 0, 1463 .hsync_end = 1280 + 0 + 2, 1464 .htotal = 1280 + 62 + 0 + 2, 1465 .vdisplay = 800, 1466 .vsync_start = 800 + 8, 1467 .vsync_end = 800 + 8 + 2, 1468 .vtotal = 800 + 6 + 8 + 2, 1469 }; 1470 1471 static const struct panel_desc boe_bp082wx1_100 = { 1472 .modes = &boe_bp101wx1_100_mode, 1473 .num_modes = 1, 1474 .bpc = 8, 1475 .size = { 1476 .width = 177, 1477 .height = 110, 1478 }, 1479 .delay = { 1480 .enable = 50, 1481 .disable = 50, 1482 }, 1483 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1484 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1485 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1486 }; 1487 1488 static const struct panel_desc boe_bp101wx1_100 = { 1489 .modes = &boe_bp101wx1_100_mode, 1490 .num_modes = 1, 1491 .bpc = 8, 1492 .size = { 1493 .width = 217, 1494 .height = 136, 1495 }, 1496 .delay = { 1497 .enable = 50, 1498 .disable = 50, 1499 }, 1500 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1501 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1502 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1503 }; 1504 1505 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1506 .pixelclock = { 69922000, 71000000, 72293000 }, 1507 .hactive = { 1280, 1280, 1280 }, 1508 .hfront_porch = { 48, 48, 48 }, 1509 .hback_porch = { 80, 80, 80 }, 1510 .hsync_len = { 32, 32, 32 }, 1511 .vactive = { 800, 800, 800 }, 1512 .vfront_porch = { 3, 3, 3 }, 1513 .vback_porch = { 14, 14, 14 }, 1514 .vsync_len = { 6, 6, 6 }, 1515 }; 1516 1517 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1518 .timings = &boe_ev121wxm_n10_1850_timing, 1519 .num_timings = 1, 1520 .bpc = 8, 1521 .size = { 1522 .width = 261, 1523 .height = 163, 1524 }, 1525 .delay = { 1526 .prepare = 9, 1527 .enable = 300, 1528 .unprepare = 300, 1529 .disable = 560, 1530 }, 1531 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1532 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1533 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1534 }; 1535 1536 static const struct drm_display_mode boe_hv070wsa_mode = { 1537 .clock = 42105, 1538 .hdisplay = 1024, 1539 .hsync_start = 1024 + 30, 1540 .hsync_end = 1024 + 30 + 30, 1541 .htotal = 1024 + 30 + 30 + 30, 1542 .vdisplay = 600, 1543 .vsync_start = 600 + 10, 1544 .vsync_end = 600 + 10 + 10, 1545 .vtotal = 600 + 10 + 10 + 10, 1546 }; 1547 1548 static const struct panel_desc boe_hv070wsa = { 1549 .modes = &boe_hv070wsa_mode, 1550 .num_modes = 1, 1551 .bpc = 8, 1552 .size = { 1553 .width = 154, 1554 .height = 90, 1555 }, 1556 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1557 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1558 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1559 }; 1560 1561 static const struct display_timing cct_cmt430b19n00_timing = { 1562 .pixelclock = { 8000000, 9000000, 12000000 }, 1563 .hactive = { 480, 480, 480 }, 1564 .hfront_porch = { 2, 8, 75 }, 1565 .hback_porch = { 3, 43, 43 }, 1566 .hsync_len = { 2, 4, 75 }, 1567 .vactive = { 272, 272, 272 }, 1568 .vfront_porch = { 2, 8, 37 }, 1569 .vback_porch = { 2, 12, 12 }, 1570 .vsync_len = { 2, 4, 37 }, 1571 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1572 }; 1573 1574 static const struct panel_desc cct_cmt430b19n00 = { 1575 .timings = &cct_cmt430b19n00_timing, 1576 .num_timings = 1, 1577 .bpc = 8, 1578 .size = { 1579 .width = 95, 1580 .height = 53, 1581 }, 1582 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1583 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1584 .connector_type = DRM_MODE_CONNECTOR_DPI, 1585 }; 1586 1587 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1588 .clock = 9000, 1589 .hdisplay = 480, 1590 .hsync_start = 480 + 5, 1591 .hsync_end = 480 + 5 + 5, 1592 .htotal = 480 + 5 + 5 + 40, 1593 .vdisplay = 272, 1594 .vsync_start = 272 + 8, 1595 .vsync_end = 272 + 8 + 8, 1596 .vtotal = 272 + 8 + 8 + 8, 1597 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1598 }; 1599 1600 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1601 .modes = &cdtech_s043wq26h_ct7_mode, 1602 .num_modes = 1, 1603 .bpc = 8, 1604 .size = { 1605 .width = 95, 1606 .height = 54, 1607 }, 1608 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1609 }; 1610 1611 /* S070PWS19HP-FC21 2017/04/22 */ 1612 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1613 .clock = 51200, 1614 .hdisplay = 1024, 1615 .hsync_start = 1024 + 160, 1616 .hsync_end = 1024 + 160 + 20, 1617 .htotal = 1024 + 160 + 20 + 140, 1618 .vdisplay = 600, 1619 .vsync_start = 600 + 12, 1620 .vsync_end = 600 + 12 + 3, 1621 .vtotal = 600 + 12 + 3 + 20, 1622 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1623 }; 1624 1625 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1626 .modes = &cdtech_s070pws19hp_fc21_mode, 1627 .num_modes = 1, 1628 .bpc = 6, 1629 .size = { 1630 .width = 154, 1631 .height = 86, 1632 }, 1633 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1634 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1635 .connector_type = DRM_MODE_CONNECTOR_DPI, 1636 }; 1637 1638 /* S070SWV29HG-DC44 2017/09/21 */ 1639 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1640 .clock = 33300, 1641 .hdisplay = 800, 1642 .hsync_start = 800 + 210, 1643 .hsync_end = 800 + 210 + 2, 1644 .htotal = 800 + 210 + 2 + 44, 1645 .vdisplay = 480, 1646 .vsync_start = 480 + 22, 1647 .vsync_end = 480 + 22 + 2, 1648 .vtotal = 480 + 22 + 2 + 21, 1649 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1650 }; 1651 1652 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1653 .modes = &cdtech_s070swv29hg_dc44_mode, 1654 .num_modes = 1, 1655 .bpc = 6, 1656 .size = { 1657 .width = 154, 1658 .height = 86, 1659 }, 1660 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1661 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1662 .connector_type = DRM_MODE_CONNECTOR_DPI, 1663 }; 1664 1665 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1666 .clock = 35000, 1667 .hdisplay = 800, 1668 .hsync_start = 800 + 40, 1669 .hsync_end = 800 + 40 + 40, 1670 .htotal = 800 + 40 + 40 + 48, 1671 .vdisplay = 480, 1672 .vsync_start = 480 + 29, 1673 .vsync_end = 480 + 29 + 13, 1674 .vtotal = 480 + 29 + 13 + 3, 1675 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1676 }; 1677 1678 static const struct panel_desc cdtech_s070wv95_ct16 = { 1679 .modes = &cdtech_s070wv95_ct16_mode, 1680 .num_modes = 1, 1681 .bpc = 8, 1682 .size = { 1683 .width = 154, 1684 .height = 85, 1685 }, 1686 }; 1687 1688 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1689 .pixelclock = { 68900000, 71100000, 73400000 }, 1690 .hactive = { 1280, 1280, 1280 }, 1691 .hfront_porch = { 65, 80, 95 }, 1692 .hback_porch = { 64, 79, 94 }, 1693 .hsync_len = { 1, 1, 1 }, 1694 .vactive = { 800, 800, 800 }, 1695 .vfront_porch = { 7, 11, 14 }, 1696 .vback_porch = { 7, 11, 14 }, 1697 .vsync_len = { 1, 1, 1 }, 1698 .flags = DISPLAY_FLAGS_DE_HIGH, 1699 }; 1700 1701 static const struct panel_desc chefree_ch101olhlwh_002 = { 1702 .timings = &chefree_ch101olhlwh_002_timing, 1703 .num_timings = 1, 1704 .bpc = 8, 1705 .size = { 1706 .width = 217, 1707 .height = 135, 1708 }, 1709 .delay = { 1710 .enable = 200, 1711 .disable = 200, 1712 }, 1713 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1714 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1715 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1716 }; 1717 1718 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1719 .clock = 66770, 1720 .hdisplay = 800, 1721 .hsync_start = 800 + 49, 1722 .hsync_end = 800 + 49 + 33, 1723 .htotal = 800 + 49 + 33 + 17, 1724 .vdisplay = 1280, 1725 .vsync_start = 1280 + 1, 1726 .vsync_end = 1280 + 1 + 7, 1727 .vtotal = 1280 + 1 + 7 + 15, 1728 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1729 }; 1730 1731 static const struct panel_desc chunghwa_claa070wp03xg = { 1732 .modes = &chunghwa_claa070wp03xg_mode, 1733 .num_modes = 1, 1734 .bpc = 6, 1735 .size = { 1736 .width = 94, 1737 .height = 150, 1738 }, 1739 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1740 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1741 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1742 }; 1743 1744 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1745 .clock = 72070, 1746 .hdisplay = 1366, 1747 .hsync_start = 1366 + 58, 1748 .hsync_end = 1366 + 58 + 58, 1749 .htotal = 1366 + 58 + 58 + 58, 1750 .vdisplay = 768, 1751 .vsync_start = 768 + 4, 1752 .vsync_end = 768 + 4 + 4, 1753 .vtotal = 768 + 4 + 4 + 4, 1754 }; 1755 1756 static const struct panel_desc chunghwa_claa101wa01a = { 1757 .modes = &chunghwa_claa101wa01a_mode, 1758 .num_modes = 1, 1759 .bpc = 6, 1760 .size = { 1761 .width = 220, 1762 .height = 120, 1763 }, 1764 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1765 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1766 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1767 }; 1768 1769 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1770 .clock = 69300, 1771 .hdisplay = 1366, 1772 .hsync_start = 1366 + 48, 1773 .hsync_end = 1366 + 48 + 32, 1774 .htotal = 1366 + 48 + 32 + 20, 1775 .vdisplay = 768, 1776 .vsync_start = 768 + 16, 1777 .vsync_end = 768 + 16 + 8, 1778 .vtotal = 768 + 16 + 8 + 16, 1779 }; 1780 1781 static const struct panel_desc chunghwa_claa101wb01 = { 1782 .modes = &chunghwa_claa101wb01_mode, 1783 .num_modes = 1, 1784 .bpc = 6, 1785 .size = { 1786 .width = 223, 1787 .height = 125, 1788 }, 1789 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1790 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1791 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1792 }; 1793 1794 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1795 .pixelclock = { 5000000, 9000000, 12000000 }, 1796 .hactive = { 480, 480, 480 }, 1797 .hfront_porch = { 12, 12, 12 }, 1798 .hback_porch = { 12, 12, 12 }, 1799 .hsync_len = { 21, 21, 21 }, 1800 .vactive = { 272, 272, 272 }, 1801 .vfront_porch = { 4, 4, 4 }, 1802 .vback_porch = { 4, 4, 4 }, 1803 .vsync_len = { 8, 8, 8 }, 1804 }; 1805 1806 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1807 .timings = &dataimage_fg040346dsswbg04_timing, 1808 .num_timings = 1, 1809 .bpc = 8, 1810 .size = { 1811 .width = 95, 1812 .height = 54, 1813 }, 1814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1815 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1816 .connector_type = DRM_MODE_CONNECTOR_DPI, 1817 }; 1818 1819 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1820 .pixelclock = { 68900000, 71110000, 73400000 }, 1821 .hactive = { 1280, 1280, 1280 }, 1822 .vactive = { 800, 800, 800 }, 1823 .hback_porch = { 100, 100, 100 }, 1824 .hfront_porch = { 100, 100, 100 }, 1825 .vback_porch = { 5, 5, 5 }, 1826 .vfront_porch = { 5, 5, 5 }, 1827 .hsync_len = { 24, 24, 24 }, 1828 .vsync_len = { 3, 3, 3 }, 1829 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1830 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1831 }; 1832 1833 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1834 .timings = &dataimage_fg1001l0dsswmg01_timing, 1835 .num_timings = 1, 1836 .bpc = 8, 1837 .size = { 1838 .width = 217, 1839 .height = 136, 1840 }, 1841 }; 1842 1843 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1844 .clock = 33260, 1845 .hdisplay = 800, 1846 .hsync_start = 800 + 40, 1847 .hsync_end = 800 + 40 + 128, 1848 .htotal = 800 + 40 + 128 + 88, 1849 .vdisplay = 480, 1850 .vsync_start = 480 + 10, 1851 .vsync_end = 480 + 10 + 2, 1852 .vtotal = 480 + 10 + 2 + 33, 1853 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1854 }; 1855 1856 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1857 .modes = &dataimage_scf0700c48ggu18_mode, 1858 .num_modes = 1, 1859 .bpc = 8, 1860 .size = { 1861 .width = 152, 1862 .height = 91, 1863 }, 1864 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1865 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1866 }; 1867 1868 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1869 .pixelclock = { 45000000, 51200000, 57000000 }, 1870 .hactive = { 1024, 1024, 1024 }, 1871 .hfront_porch = { 100, 106, 113 }, 1872 .hback_porch = { 100, 106, 113 }, 1873 .hsync_len = { 100, 108, 114 }, 1874 .vactive = { 600, 600, 600 }, 1875 .vfront_porch = { 8, 11, 15 }, 1876 .vback_porch = { 8, 11, 15 }, 1877 .vsync_len = { 9, 13, 15 }, 1878 .flags = DISPLAY_FLAGS_DE_HIGH, 1879 }; 1880 1881 static const struct panel_desc dlc_dlc0700yzg_1 = { 1882 .timings = &dlc_dlc0700yzg_1_timing, 1883 .num_timings = 1, 1884 .bpc = 6, 1885 .size = { 1886 .width = 154, 1887 .height = 86, 1888 }, 1889 .delay = { 1890 .prepare = 30, 1891 .enable = 200, 1892 .disable = 200, 1893 }, 1894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1895 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1896 }; 1897 1898 static const struct display_timing dlc_dlc1010gig_timing = { 1899 .pixelclock = { 68900000, 71100000, 73400000 }, 1900 .hactive = { 1280, 1280, 1280 }, 1901 .hfront_porch = { 43, 53, 63 }, 1902 .hback_porch = { 43, 53, 63 }, 1903 .hsync_len = { 44, 54, 64 }, 1904 .vactive = { 800, 800, 800 }, 1905 .vfront_porch = { 5, 8, 11 }, 1906 .vback_porch = { 5, 8, 11 }, 1907 .vsync_len = { 5, 7, 11 }, 1908 .flags = DISPLAY_FLAGS_DE_HIGH, 1909 }; 1910 1911 static const struct panel_desc dlc_dlc1010gig = { 1912 .timings = &dlc_dlc1010gig_timing, 1913 .num_timings = 1, 1914 .bpc = 8, 1915 .size = { 1916 .width = 216, 1917 .height = 135, 1918 }, 1919 .delay = { 1920 .prepare = 60, 1921 .enable = 150, 1922 .disable = 100, 1923 .unprepare = 60, 1924 }, 1925 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1926 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1927 }; 1928 1929 static const struct drm_display_mode edt_et035012dm6_mode = { 1930 .clock = 6500, 1931 .hdisplay = 320, 1932 .hsync_start = 320 + 20, 1933 .hsync_end = 320 + 20 + 30, 1934 .htotal = 320 + 20 + 68, 1935 .vdisplay = 240, 1936 .vsync_start = 240 + 4, 1937 .vsync_end = 240 + 4 + 4, 1938 .vtotal = 240 + 4 + 4 + 14, 1939 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1940 }; 1941 1942 static const struct panel_desc edt_et035012dm6 = { 1943 .modes = &edt_et035012dm6_mode, 1944 .num_modes = 1, 1945 .bpc = 8, 1946 .size = { 1947 .width = 70, 1948 .height = 52, 1949 }, 1950 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1951 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1952 }; 1953 1954 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1955 .clock = 6520, 1956 .hdisplay = 320, 1957 .hsync_start = 320 + 20, 1958 .hsync_end = 320 + 20 + 68, 1959 .htotal = 320 + 20 + 68, 1960 .vdisplay = 240, 1961 .vsync_start = 240 + 4, 1962 .vsync_end = 240 + 4 + 18, 1963 .vtotal = 240 + 4 + 18, 1964 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1965 }; 1966 1967 static const struct panel_desc edt_etm0350g0dh6 = { 1968 .modes = &edt_etm0350g0dh6_mode, 1969 .num_modes = 1, 1970 .bpc = 6, 1971 .size = { 1972 .width = 70, 1973 .height = 53, 1974 }, 1975 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1976 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1977 .connector_type = DRM_MODE_CONNECTOR_DPI, 1978 }; 1979 1980 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1981 .clock = 10870, 1982 .hdisplay = 480, 1983 .hsync_start = 480 + 8, 1984 .hsync_end = 480 + 8 + 4, 1985 .htotal = 480 + 8 + 4 + 41, 1986 1987 /* 1988 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1989 * fb_align 1990 */ 1991 1992 .vdisplay = 288, 1993 .vsync_start = 288 + 2, 1994 .vsync_end = 288 + 2 + 4, 1995 .vtotal = 288 + 2 + 4 + 10, 1996 }; 1997 1998 static const struct panel_desc edt_etm043080dh6gp = { 1999 .modes = &edt_etm043080dh6gp_mode, 2000 .num_modes = 1, 2001 .bpc = 8, 2002 .size = { 2003 .width = 100, 2004 .height = 65, 2005 }, 2006 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2007 .connector_type = DRM_MODE_CONNECTOR_DPI, 2008 }; 2009 2010 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2011 .clock = 9000, 2012 .hdisplay = 480, 2013 .hsync_start = 480 + 2, 2014 .hsync_end = 480 + 2 + 41, 2015 .htotal = 480 + 2 + 41 + 2, 2016 .vdisplay = 272, 2017 .vsync_start = 272 + 2, 2018 .vsync_end = 272 + 2 + 10, 2019 .vtotal = 272 + 2 + 10 + 2, 2020 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2021 }; 2022 2023 static const struct panel_desc edt_etm0430g0dh6 = { 2024 .modes = &edt_etm0430g0dh6_mode, 2025 .num_modes = 1, 2026 .bpc = 6, 2027 .size = { 2028 .width = 95, 2029 .height = 54, 2030 }, 2031 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2032 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2033 .connector_type = DRM_MODE_CONNECTOR_DPI, 2034 }; 2035 2036 static const struct drm_display_mode edt_et057090dhu_mode = { 2037 .clock = 25175, 2038 .hdisplay = 640, 2039 .hsync_start = 640 + 16, 2040 .hsync_end = 640 + 16 + 30, 2041 .htotal = 640 + 16 + 30 + 114, 2042 .vdisplay = 480, 2043 .vsync_start = 480 + 10, 2044 .vsync_end = 480 + 10 + 3, 2045 .vtotal = 480 + 10 + 3 + 32, 2046 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2047 }; 2048 2049 static const struct panel_desc edt_et057090dhu = { 2050 .modes = &edt_et057090dhu_mode, 2051 .num_modes = 1, 2052 .bpc = 6, 2053 .size = { 2054 .width = 115, 2055 .height = 86, 2056 }, 2057 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2058 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2059 .connector_type = DRM_MODE_CONNECTOR_DPI, 2060 }; 2061 2062 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2063 .clock = 33260, 2064 .hdisplay = 800, 2065 .hsync_start = 800 + 40, 2066 .hsync_end = 800 + 40 + 128, 2067 .htotal = 800 + 40 + 128 + 88, 2068 .vdisplay = 480, 2069 .vsync_start = 480 + 10, 2070 .vsync_end = 480 + 10 + 2, 2071 .vtotal = 480 + 10 + 2 + 33, 2072 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2073 }; 2074 2075 static const struct panel_desc edt_etm0700g0dh6 = { 2076 .modes = &edt_etm0700g0dh6_mode, 2077 .num_modes = 1, 2078 .bpc = 6, 2079 .size = { 2080 .width = 152, 2081 .height = 91, 2082 }, 2083 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2084 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2085 .connector_type = DRM_MODE_CONNECTOR_DPI, 2086 }; 2087 2088 static const struct panel_desc edt_etm0700g0bdh6 = { 2089 .modes = &edt_etm0700g0dh6_mode, 2090 .num_modes = 1, 2091 .bpc = 6, 2092 .size = { 2093 .width = 152, 2094 .height = 91, 2095 }, 2096 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2097 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2098 .connector_type = DRM_MODE_CONNECTOR_DPI, 2099 }; 2100 2101 static const struct display_timing edt_etml0700y5dha_timing = { 2102 .pixelclock = { 40800000, 51200000, 67200000 }, 2103 .hactive = { 1024, 1024, 1024 }, 2104 .hfront_porch = { 30, 106, 125 }, 2105 .hback_porch = { 30, 106, 125 }, 2106 .hsync_len = { 30, 108, 126 }, 2107 .vactive = { 600, 600, 600 }, 2108 .vfront_porch = { 3, 12, 67}, 2109 .vback_porch = { 3, 12, 67 }, 2110 .vsync_len = { 4, 11, 66 }, 2111 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2112 DISPLAY_FLAGS_DE_HIGH, 2113 }; 2114 2115 static const struct panel_desc edt_etml0700y5dha = { 2116 .timings = &edt_etml0700y5dha_timing, 2117 .num_timings = 1, 2118 .bpc = 8, 2119 .size = { 2120 .width = 155, 2121 .height = 86, 2122 }, 2123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2124 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2125 }; 2126 2127 static const struct display_timing edt_etml1010g3dra_timing = { 2128 .pixelclock = { 66300000, 72400000, 78900000 }, 2129 .hactive = { 1280, 1280, 1280 }, 2130 .hfront_porch = { 12, 72, 132 }, 2131 .hback_porch = { 86, 86, 86 }, 2132 .hsync_len = { 2, 2, 2 }, 2133 .vactive = { 800, 800, 800 }, 2134 .vfront_porch = { 1, 15, 49 }, 2135 .vback_porch = { 21, 21, 21 }, 2136 .vsync_len = { 2, 2, 2 }, 2137 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2138 DISPLAY_FLAGS_DE_HIGH, 2139 }; 2140 2141 static const struct panel_desc edt_etml1010g3dra = { 2142 .timings = &edt_etml1010g3dra_timing, 2143 .num_timings = 1, 2144 .bpc = 8, 2145 .size = { 2146 .width = 216, 2147 .height = 135, 2148 }, 2149 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2150 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2151 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2152 }; 2153 2154 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2155 .clock = 25175, 2156 .hdisplay = 640, 2157 .hsync_start = 640, 2158 .hsync_end = 640 + 16, 2159 .htotal = 640 + 16 + 30 + 114, 2160 .vdisplay = 480, 2161 .vsync_start = 480 + 10, 2162 .vsync_end = 480 + 10 + 3, 2163 .vtotal = 480 + 10 + 3 + 35, 2164 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2165 }; 2166 2167 static const struct panel_desc edt_etmv570g2dhu = { 2168 .modes = &edt_etmv570g2dhu_mode, 2169 .num_modes = 1, 2170 .bpc = 6, 2171 .size = { 2172 .width = 115, 2173 .height = 86, 2174 }, 2175 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2176 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2177 .connector_type = DRM_MODE_CONNECTOR_DPI, 2178 }; 2179 2180 static const struct display_timing eink_vb3300_kca_timing = { 2181 .pixelclock = { 40000000, 40000000, 40000000 }, 2182 .hactive = { 334, 334, 334 }, 2183 .hfront_porch = { 1, 1, 1 }, 2184 .hback_porch = { 1, 1, 1 }, 2185 .hsync_len = { 1, 1, 1 }, 2186 .vactive = { 1405, 1405, 1405 }, 2187 .vfront_porch = { 1, 1, 1 }, 2188 .vback_porch = { 1, 1, 1 }, 2189 .vsync_len = { 1, 1, 1 }, 2190 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2191 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2192 }; 2193 2194 static const struct panel_desc eink_vb3300_kca = { 2195 .timings = &eink_vb3300_kca_timing, 2196 .num_timings = 1, 2197 .bpc = 6, 2198 .size = { 2199 .width = 157, 2200 .height = 209, 2201 }, 2202 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2203 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2204 .connector_type = DRM_MODE_CONNECTOR_DPI, 2205 }; 2206 2207 static const struct display_timing evervision_vgg644804_timing = { 2208 .pixelclock = { 25175000, 25175000, 25175000 }, 2209 .hactive = { 640, 640, 640 }, 2210 .hfront_porch = { 16, 16, 16 }, 2211 .hback_porch = { 82, 114, 170 }, 2212 .hsync_len = { 5, 30, 30 }, 2213 .vactive = { 480, 480, 480 }, 2214 .vfront_porch = { 10, 10, 10 }, 2215 .vback_porch = { 30, 32, 34 }, 2216 .vsync_len = { 1, 3, 5 }, 2217 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2218 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2219 DISPLAY_FLAGS_SYNC_POSEDGE, 2220 }; 2221 2222 static const struct panel_desc evervision_vgg644804 = { 2223 .timings = &evervision_vgg644804_timing, 2224 .num_timings = 1, 2225 .bpc = 6, 2226 .size = { 2227 .width = 115, 2228 .height = 86, 2229 }, 2230 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2231 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2232 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2233 }; 2234 2235 static const struct display_timing evervision_vgg804821_timing = { 2236 .pixelclock = { 27600000, 33300000, 50000000 }, 2237 .hactive = { 800, 800, 800 }, 2238 .hfront_porch = { 40, 66, 70 }, 2239 .hback_porch = { 40, 67, 70 }, 2240 .hsync_len = { 40, 67, 70 }, 2241 .vactive = { 480, 480, 480 }, 2242 .vfront_porch = { 6, 10, 10 }, 2243 .vback_porch = { 7, 11, 11 }, 2244 .vsync_len = { 7, 11, 11 }, 2245 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2246 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2247 DISPLAY_FLAGS_SYNC_NEGEDGE, 2248 }; 2249 2250 static const struct panel_desc evervision_vgg804821 = { 2251 .timings = &evervision_vgg804821_timing, 2252 .num_timings = 1, 2253 .bpc = 8, 2254 .size = { 2255 .width = 108, 2256 .height = 64, 2257 }, 2258 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2259 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2260 }; 2261 2262 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2263 .clock = 32260, 2264 .hdisplay = 800, 2265 .hsync_start = 800 + 168, 2266 .hsync_end = 800 + 168 + 64, 2267 .htotal = 800 + 168 + 64 + 88, 2268 .vdisplay = 480, 2269 .vsync_start = 480 + 37, 2270 .vsync_end = 480 + 37 + 2, 2271 .vtotal = 480 + 37 + 2 + 8, 2272 }; 2273 2274 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2275 .modes = &foxlink_fl500wvr00_a0t_mode, 2276 .num_modes = 1, 2277 .bpc = 8, 2278 .size = { 2279 .width = 108, 2280 .height = 65, 2281 }, 2282 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2283 }; 2284 2285 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2286 { /* 60 Hz */ 2287 .clock = 6000, 2288 .hdisplay = 320, 2289 .hsync_start = 320 + 44, 2290 .hsync_end = 320 + 44 + 16, 2291 .htotal = 320 + 44 + 16 + 20, 2292 .vdisplay = 240, 2293 .vsync_start = 240 + 2, 2294 .vsync_end = 240 + 2 + 6, 2295 .vtotal = 240 + 2 + 6 + 2, 2296 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2297 }, 2298 { /* 50 Hz */ 2299 .clock = 5400, 2300 .hdisplay = 320, 2301 .hsync_start = 320 + 56, 2302 .hsync_end = 320 + 56 + 16, 2303 .htotal = 320 + 56 + 16 + 40, 2304 .vdisplay = 240, 2305 .vsync_start = 240 + 2, 2306 .vsync_end = 240 + 2 + 6, 2307 .vtotal = 240 + 2 + 6 + 2, 2308 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2309 }, 2310 }; 2311 2312 static const struct panel_desc frida_frd350h54004 = { 2313 .modes = frida_frd350h54004_modes, 2314 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2315 .bpc = 8, 2316 .size = { 2317 .width = 77, 2318 .height = 64, 2319 }, 2320 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2321 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2322 .connector_type = DRM_MODE_CONNECTOR_DPI, 2323 }; 2324 2325 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2326 .clock = 67185, 2327 .hdisplay = 800, 2328 .hsync_start = 800 + 20, 2329 .hsync_end = 800 + 20 + 24, 2330 .htotal = 800 + 20 + 24 + 20, 2331 .vdisplay = 1280, 2332 .vsync_start = 1280 + 4, 2333 .vsync_end = 1280 + 4 + 8, 2334 .vtotal = 1280 + 4 + 8 + 4, 2335 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2336 }; 2337 2338 static const struct panel_desc friendlyarm_hd702e = { 2339 .modes = &friendlyarm_hd702e_mode, 2340 .num_modes = 1, 2341 .size = { 2342 .width = 94, 2343 .height = 151, 2344 }, 2345 }; 2346 2347 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2348 .clock = 9000, 2349 .hdisplay = 480, 2350 .hsync_start = 480 + 5, 2351 .hsync_end = 480 + 5 + 1, 2352 .htotal = 480 + 5 + 1 + 40, 2353 .vdisplay = 272, 2354 .vsync_start = 272 + 8, 2355 .vsync_end = 272 + 8 + 1, 2356 .vtotal = 272 + 8 + 1 + 8, 2357 }; 2358 2359 static const struct panel_desc giantplus_gpg482739qs5 = { 2360 .modes = &giantplus_gpg482739qs5_mode, 2361 .num_modes = 1, 2362 .bpc = 8, 2363 .size = { 2364 .width = 95, 2365 .height = 54, 2366 }, 2367 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2368 }; 2369 2370 static const struct display_timing giantplus_gpm940b0_timing = { 2371 .pixelclock = { 13500000, 27000000, 27500000 }, 2372 .hactive = { 320, 320, 320 }, 2373 .hfront_porch = { 14, 686, 718 }, 2374 .hback_porch = { 50, 70, 255 }, 2375 .hsync_len = { 1, 1, 1 }, 2376 .vactive = { 240, 240, 240 }, 2377 .vfront_porch = { 1, 1, 179 }, 2378 .vback_porch = { 1, 21, 31 }, 2379 .vsync_len = { 1, 1, 6 }, 2380 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2381 }; 2382 2383 static const struct panel_desc giantplus_gpm940b0 = { 2384 .timings = &giantplus_gpm940b0_timing, 2385 .num_timings = 1, 2386 .bpc = 8, 2387 .size = { 2388 .width = 60, 2389 .height = 45, 2390 }, 2391 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2392 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2393 }; 2394 2395 static const struct display_timing hannstar_hsd070pww1_timing = { 2396 .pixelclock = { 64300000, 71100000, 82000000 }, 2397 .hactive = { 1280, 1280, 1280 }, 2398 .hfront_porch = { 1, 1, 10 }, 2399 .hback_porch = { 1, 1, 10 }, 2400 /* 2401 * According to the data sheet, the minimum horizontal blanking interval 2402 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2403 * minimum working horizontal blanking interval to be 60 clocks. 2404 */ 2405 .hsync_len = { 58, 158, 661 }, 2406 .vactive = { 800, 800, 800 }, 2407 .vfront_porch = { 1, 1, 10 }, 2408 .vback_porch = { 1, 1, 10 }, 2409 .vsync_len = { 1, 21, 203 }, 2410 .flags = DISPLAY_FLAGS_DE_HIGH, 2411 }; 2412 2413 static const struct panel_desc hannstar_hsd070pww1 = { 2414 .timings = &hannstar_hsd070pww1_timing, 2415 .num_timings = 1, 2416 .bpc = 6, 2417 .size = { 2418 .width = 151, 2419 .height = 94, 2420 }, 2421 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2422 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2423 }; 2424 2425 static const struct display_timing hannstar_hsd100pxn1_timing = { 2426 .pixelclock = { 55000000, 65000000, 75000000 }, 2427 .hactive = { 1024, 1024, 1024 }, 2428 .hfront_porch = { 40, 40, 40 }, 2429 .hback_porch = { 220, 220, 220 }, 2430 .hsync_len = { 20, 60, 100 }, 2431 .vactive = { 768, 768, 768 }, 2432 .vfront_porch = { 7, 7, 7 }, 2433 .vback_porch = { 21, 21, 21 }, 2434 .vsync_len = { 10, 10, 10 }, 2435 .flags = DISPLAY_FLAGS_DE_HIGH, 2436 }; 2437 2438 static const struct panel_desc hannstar_hsd100pxn1 = { 2439 .timings = &hannstar_hsd100pxn1_timing, 2440 .num_timings = 1, 2441 .bpc = 6, 2442 .size = { 2443 .width = 203, 2444 .height = 152, 2445 }, 2446 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2447 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2448 }; 2449 2450 static const struct display_timing hannstar_hsd101pww2_timing = { 2451 .pixelclock = { 64300000, 71100000, 82000000 }, 2452 .hactive = { 1280, 1280, 1280 }, 2453 .hfront_porch = { 1, 1, 10 }, 2454 .hback_porch = { 1, 1, 10 }, 2455 .hsync_len = { 58, 158, 661 }, 2456 .vactive = { 800, 800, 800 }, 2457 .vfront_porch = { 1, 1, 10 }, 2458 .vback_porch = { 1, 1, 10 }, 2459 .vsync_len = { 1, 21, 203 }, 2460 .flags = DISPLAY_FLAGS_DE_HIGH, 2461 }; 2462 2463 static const struct panel_desc hannstar_hsd101pww2 = { 2464 .timings = &hannstar_hsd101pww2_timing, 2465 .num_timings = 1, 2466 .bpc = 8, 2467 .size = { 2468 .width = 217, 2469 .height = 136, 2470 }, 2471 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2472 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2473 }; 2474 2475 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2476 .clock = 33333, 2477 .hdisplay = 800, 2478 .hsync_start = 800 + 85, 2479 .hsync_end = 800 + 85 + 86, 2480 .htotal = 800 + 85 + 86 + 85, 2481 .vdisplay = 480, 2482 .vsync_start = 480 + 16, 2483 .vsync_end = 480 + 16 + 13, 2484 .vtotal = 480 + 16 + 13 + 16, 2485 }; 2486 2487 static const struct panel_desc hitachi_tx23d38vm0caa = { 2488 .modes = &hitachi_tx23d38vm0caa_mode, 2489 .num_modes = 1, 2490 .bpc = 6, 2491 .size = { 2492 .width = 195, 2493 .height = 117, 2494 }, 2495 .delay = { 2496 .enable = 160, 2497 .disable = 160, 2498 }, 2499 }; 2500 2501 static const struct drm_display_mode innolux_at043tn24_mode = { 2502 .clock = 9000, 2503 .hdisplay = 480, 2504 .hsync_start = 480 + 2, 2505 .hsync_end = 480 + 2 + 41, 2506 .htotal = 480 + 2 + 41 + 2, 2507 .vdisplay = 272, 2508 .vsync_start = 272 + 2, 2509 .vsync_end = 272 + 2 + 10, 2510 .vtotal = 272 + 2 + 10 + 2, 2511 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2512 }; 2513 2514 static const struct panel_desc innolux_at043tn24 = { 2515 .modes = &innolux_at043tn24_mode, 2516 .num_modes = 1, 2517 .bpc = 8, 2518 .size = { 2519 .width = 95, 2520 .height = 54, 2521 }, 2522 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2523 .connector_type = DRM_MODE_CONNECTOR_DPI, 2524 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2525 }; 2526 2527 static const struct drm_display_mode innolux_at070tn92_mode = { 2528 .clock = 33333, 2529 .hdisplay = 800, 2530 .hsync_start = 800 + 210, 2531 .hsync_end = 800 + 210 + 20, 2532 .htotal = 800 + 210 + 20 + 46, 2533 .vdisplay = 480, 2534 .vsync_start = 480 + 22, 2535 .vsync_end = 480 + 22 + 10, 2536 .vtotal = 480 + 22 + 23 + 10, 2537 }; 2538 2539 static const struct panel_desc innolux_at070tn92 = { 2540 .modes = &innolux_at070tn92_mode, 2541 .num_modes = 1, 2542 .size = { 2543 .width = 154, 2544 .height = 86, 2545 }, 2546 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2547 }; 2548 2549 static const struct display_timing innolux_g070ace_l01_timing = { 2550 .pixelclock = { 25200000, 35000000, 35700000 }, 2551 .hactive = { 800, 800, 800 }, 2552 .hfront_porch = { 30, 32, 87 }, 2553 .hback_porch = { 30, 32, 87 }, 2554 .hsync_len = { 1, 1, 1 }, 2555 .vactive = { 480, 480, 480 }, 2556 .vfront_porch = { 3, 3, 3 }, 2557 .vback_porch = { 13, 13, 13 }, 2558 .vsync_len = { 1, 1, 4 }, 2559 .flags = DISPLAY_FLAGS_DE_HIGH, 2560 }; 2561 2562 static const struct panel_desc innolux_g070ace_l01 = { 2563 .timings = &innolux_g070ace_l01_timing, 2564 .num_timings = 1, 2565 .bpc = 8, 2566 .size = { 2567 .width = 152, 2568 .height = 91, 2569 }, 2570 .delay = { 2571 .prepare = 10, 2572 .enable = 50, 2573 .disable = 50, 2574 .unprepare = 500, 2575 }, 2576 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2577 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2578 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2579 }; 2580 2581 static const struct display_timing innolux_g070y2_l01_timing = { 2582 .pixelclock = { 28000000, 29500000, 32000000 }, 2583 .hactive = { 800, 800, 800 }, 2584 .hfront_porch = { 61, 91, 141 }, 2585 .hback_porch = { 60, 90, 140 }, 2586 .hsync_len = { 12, 12, 12 }, 2587 .vactive = { 480, 480, 480 }, 2588 .vfront_porch = { 4, 9, 30 }, 2589 .vback_porch = { 4, 8, 28 }, 2590 .vsync_len = { 2, 2, 2 }, 2591 .flags = DISPLAY_FLAGS_DE_HIGH, 2592 }; 2593 2594 static const struct panel_desc innolux_g070y2_l01 = { 2595 .timings = &innolux_g070y2_l01_timing, 2596 .num_timings = 1, 2597 .bpc = 8, 2598 .size = { 2599 .width = 152, 2600 .height = 91, 2601 }, 2602 .delay = { 2603 .prepare = 10, 2604 .enable = 100, 2605 .disable = 100, 2606 .unprepare = 800, 2607 }, 2608 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2609 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2610 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2611 }; 2612 2613 static const struct display_timing innolux_g070ace_lh3_timing = { 2614 .pixelclock = { 25200000, 25400000, 35700000 }, 2615 .hactive = { 800, 800, 800 }, 2616 .hfront_porch = { 30, 32, 87 }, 2617 .hback_porch = { 29, 31, 86 }, 2618 .hsync_len = { 1, 1, 1 }, 2619 .vactive = { 480, 480, 480 }, 2620 .vfront_porch = { 4, 5, 65 }, 2621 .vback_porch = { 3, 4, 65 }, 2622 .vsync_len = { 1, 1, 1 }, 2623 .flags = DISPLAY_FLAGS_DE_HIGH, 2624 }; 2625 2626 static const struct panel_desc innolux_g070ace_lh3 = { 2627 .timings = &innolux_g070ace_lh3_timing, 2628 .num_timings = 1, 2629 .bpc = 8, 2630 .size = { 2631 .width = 152, 2632 .height = 91, 2633 }, 2634 .delay = { 2635 .prepare = 10, 2636 .enable = 450, 2637 .disable = 200, 2638 .unprepare = 510, 2639 }, 2640 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2641 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2642 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2643 }; 2644 2645 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2646 .clock = 33333, 2647 .hdisplay = 800, 2648 .hsync_start = 800 + 210, 2649 .hsync_end = 800 + 210 + 20, 2650 .htotal = 800 + 210 + 20 + 46, 2651 .vdisplay = 480, 2652 .vsync_start = 480 + 22, 2653 .vsync_end = 480 + 22 + 10, 2654 .vtotal = 480 + 22 + 23 + 10, 2655 }; 2656 2657 static const struct panel_desc innolux_g070y2_t02 = { 2658 .modes = &innolux_g070y2_t02_mode, 2659 .num_modes = 1, 2660 .bpc = 8, 2661 .size = { 2662 .width = 152, 2663 .height = 92, 2664 }, 2665 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2666 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2667 .connector_type = DRM_MODE_CONNECTOR_DPI, 2668 }; 2669 2670 static const struct display_timing innolux_g101ice_l01_timing = { 2671 .pixelclock = { 60400000, 71100000, 74700000 }, 2672 .hactive = { 1280, 1280, 1280 }, 2673 .hfront_porch = { 30, 60, 70 }, 2674 .hback_porch = { 30, 60, 70 }, 2675 .hsync_len = { 22, 40, 60 }, 2676 .vactive = { 800, 800, 800 }, 2677 .vfront_porch = { 3, 8, 14 }, 2678 .vback_porch = { 3, 8, 14 }, 2679 .vsync_len = { 4, 7, 12 }, 2680 .flags = DISPLAY_FLAGS_DE_HIGH, 2681 }; 2682 2683 static const struct panel_desc innolux_g101ice_l01 = { 2684 .timings = &innolux_g101ice_l01_timing, 2685 .num_timings = 1, 2686 .bpc = 8, 2687 .size = { 2688 .width = 217, 2689 .height = 135, 2690 }, 2691 .delay = { 2692 .enable = 200, 2693 .disable = 200, 2694 }, 2695 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2696 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2697 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2698 }; 2699 2700 static const struct display_timing innolux_g121i1_l01_timing = { 2701 .pixelclock = { 67450000, 71000000, 74550000 }, 2702 .hactive = { 1280, 1280, 1280 }, 2703 .hfront_porch = { 40, 80, 160 }, 2704 .hback_porch = { 39, 79, 159 }, 2705 .hsync_len = { 1, 1, 1 }, 2706 .vactive = { 800, 800, 800 }, 2707 .vfront_porch = { 5, 11, 100 }, 2708 .vback_porch = { 4, 11, 99 }, 2709 .vsync_len = { 1, 1, 1 }, 2710 }; 2711 2712 static const struct panel_desc innolux_g121i1_l01 = { 2713 .timings = &innolux_g121i1_l01_timing, 2714 .num_timings = 1, 2715 .bpc = 6, 2716 .size = { 2717 .width = 261, 2718 .height = 163, 2719 }, 2720 .delay = { 2721 .enable = 200, 2722 .disable = 20, 2723 }, 2724 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2725 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2726 }; 2727 2728 static const struct display_timing innolux_g121x1_l03_timings = { 2729 .pixelclock = { 57500000, 64900000, 74400000 }, 2730 .hactive = { 1024, 1024, 1024 }, 2731 .hfront_porch = { 90, 140, 190 }, 2732 .hback_porch = { 90, 140, 190 }, 2733 .hsync_len = { 36, 40, 60 }, 2734 .vactive = { 768, 768, 768 }, 2735 .vfront_porch = { 2, 15, 30 }, 2736 .vback_porch = { 2, 15, 30 }, 2737 .vsync_len = { 2, 8, 20 }, 2738 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2739 }; 2740 2741 static const struct panel_desc innolux_g121x1_l03 = { 2742 .timings = &innolux_g121x1_l03_timings, 2743 .num_timings = 1, 2744 .bpc = 6, 2745 .size = { 2746 .width = 246, 2747 .height = 185, 2748 }, 2749 .delay = { 2750 .enable = 200, 2751 .unprepare = 200, 2752 .disable = 400, 2753 }, 2754 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2755 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2756 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2757 }; 2758 2759 static const struct panel_desc innolux_g121xce_l01 = { 2760 .timings = &innolux_g121x1_l03_timings, 2761 .num_timings = 1, 2762 .bpc = 8, 2763 .size = { 2764 .width = 246, 2765 .height = 185, 2766 }, 2767 .delay = { 2768 .enable = 200, 2769 .unprepare = 200, 2770 .disable = 400, 2771 }, 2772 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2773 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2774 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2775 }; 2776 2777 static const struct display_timing innolux_g156hce_l01_timings = { 2778 .pixelclock = { 120000000, 141860000, 150000000 }, 2779 .hactive = { 1920, 1920, 1920 }, 2780 .hfront_porch = { 80, 90, 100 }, 2781 .hback_porch = { 80, 90, 100 }, 2782 .hsync_len = { 20, 30, 30 }, 2783 .vactive = { 1080, 1080, 1080 }, 2784 .vfront_porch = { 3, 10, 20 }, 2785 .vback_porch = { 3, 10, 20 }, 2786 .vsync_len = { 4, 10, 10 }, 2787 }; 2788 2789 static const struct panel_desc innolux_g156hce_l01 = { 2790 .timings = &innolux_g156hce_l01_timings, 2791 .num_timings = 1, 2792 .bpc = 8, 2793 .size = { 2794 .width = 344, 2795 .height = 194, 2796 }, 2797 .delay = { 2798 .prepare = 1, /* T1+T2 */ 2799 .enable = 450, /* T5 */ 2800 .disable = 200, /* T6 */ 2801 .unprepare = 10, /* T3+T7 */ 2802 }, 2803 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2804 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2805 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2806 }; 2807 2808 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2809 .clock = 69300, 2810 .hdisplay = 1366, 2811 .hsync_start = 1366 + 16, 2812 .hsync_end = 1366 + 16 + 34, 2813 .htotal = 1366 + 16 + 34 + 50, 2814 .vdisplay = 768, 2815 .vsync_start = 768 + 2, 2816 .vsync_end = 768 + 2 + 6, 2817 .vtotal = 768 + 2 + 6 + 12, 2818 }; 2819 2820 static const struct panel_desc innolux_n156bge_l21 = { 2821 .modes = &innolux_n156bge_l21_mode, 2822 .num_modes = 1, 2823 .bpc = 6, 2824 .size = { 2825 .width = 344, 2826 .height = 193, 2827 }, 2828 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2829 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2830 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2831 }; 2832 2833 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2834 .clock = 51501, 2835 .hdisplay = 1024, 2836 .hsync_start = 1024 + 128, 2837 .hsync_end = 1024 + 128 + 64, 2838 .htotal = 1024 + 128 + 64 + 128, 2839 .vdisplay = 600, 2840 .vsync_start = 600 + 16, 2841 .vsync_end = 600 + 16 + 4, 2842 .vtotal = 600 + 16 + 4 + 16, 2843 }; 2844 2845 static const struct panel_desc innolux_zj070na_01p = { 2846 .modes = &innolux_zj070na_01p_mode, 2847 .num_modes = 1, 2848 .bpc = 6, 2849 .size = { 2850 .width = 154, 2851 .height = 90, 2852 }, 2853 }; 2854 2855 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2856 .pixelclock = { 5580000, 5850000, 6200000 }, 2857 .hactive = { 320, 320, 320 }, 2858 .hfront_porch = { 30, 30, 30 }, 2859 .hback_porch = { 30, 30, 30 }, 2860 .hsync_len = { 1, 5, 17 }, 2861 .vactive = { 240, 240, 240 }, 2862 .vfront_porch = { 6, 6, 6 }, 2863 .vback_porch = { 5, 5, 5 }, 2864 .vsync_len = { 1, 2, 11 }, 2865 .flags = DISPLAY_FLAGS_DE_HIGH, 2866 }; 2867 2868 static const struct panel_desc koe_tx14d24vm1bpa = { 2869 .timings = &koe_tx14d24vm1bpa_timing, 2870 .num_timings = 1, 2871 .bpc = 6, 2872 .size = { 2873 .width = 115, 2874 .height = 86, 2875 }, 2876 }; 2877 2878 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2879 .pixelclock = { 151820000, 156720000, 159780000 }, 2880 .hactive = { 1920, 1920, 1920 }, 2881 .hfront_porch = { 105, 130, 142 }, 2882 .hback_porch = { 45, 70, 82 }, 2883 .hsync_len = { 30, 30, 30 }, 2884 .vactive = { 1200, 1200, 1200}, 2885 .vfront_porch = { 3, 5, 10 }, 2886 .vback_porch = { 2, 5, 10 }, 2887 .vsync_len = { 5, 5, 5 }, 2888 .flags = DISPLAY_FLAGS_DE_HIGH, 2889 }; 2890 2891 static const struct panel_desc koe_tx26d202vm0bwa = { 2892 .timings = &koe_tx26d202vm0bwa_timing, 2893 .num_timings = 1, 2894 .bpc = 8, 2895 .size = { 2896 .width = 217, 2897 .height = 136, 2898 }, 2899 .delay = { 2900 .prepare = 1000, 2901 .enable = 1000, 2902 .unprepare = 1000, 2903 .disable = 1000, 2904 }, 2905 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2906 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2907 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2908 }; 2909 2910 static const struct display_timing koe_tx31d200vm0baa_timing = { 2911 .pixelclock = { 39600000, 43200000, 48000000 }, 2912 .hactive = { 1280, 1280, 1280 }, 2913 .hfront_porch = { 16, 36, 56 }, 2914 .hback_porch = { 16, 36, 56 }, 2915 .hsync_len = { 8, 8, 8 }, 2916 .vactive = { 480, 480, 480 }, 2917 .vfront_porch = { 6, 21, 33 }, 2918 .vback_porch = { 6, 21, 33 }, 2919 .vsync_len = { 8, 8, 8 }, 2920 .flags = DISPLAY_FLAGS_DE_HIGH, 2921 }; 2922 2923 static const struct panel_desc koe_tx31d200vm0baa = { 2924 .timings = &koe_tx31d200vm0baa_timing, 2925 .num_timings = 1, 2926 .bpc = 6, 2927 .size = { 2928 .width = 292, 2929 .height = 109, 2930 }, 2931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2933 }; 2934 2935 static const struct display_timing kyo_tcg121xglp_timing = { 2936 .pixelclock = { 52000000, 65000000, 71000000 }, 2937 .hactive = { 1024, 1024, 1024 }, 2938 .hfront_porch = { 2, 2, 2 }, 2939 .hback_porch = { 2, 2, 2 }, 2940 .hsync_len = { 86, 124, 244 }, 2941 .vactive = { 768, 768, 768 }, 2942 .vfront_porch = { 2, 2, 2 }, 2943 .vback_porch = { 2, 2, 2 }, 2944 .vsync_len = { 6, 34, 73 }, 2945 .flags = DISPLAY_FLAGS_DE_HIGH, 2946 }; 2947 2948 static const struct panel_desc kyo_tcg121xglp = { 2949 .timings = &kyo_tcg121xglp_timing, 2950 .num_timings = 1, 2951 .bpc = 8, 2952 .size = { 2953 .width = 246, 2954 .height = 184, 2955 }, 2956 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2957 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2958 }; 2959 2960 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2961 .clock = 7000, 2962 .hdisplay = 320, 2963 .hsync_start = 320 + 20, 2964 .hsync_end = 320 + 20 + 30, 2965 .htotal = 320 + 20 + 30 + 38, 2966 .vdisplay = 240, 2967 .vsync_start = 240 + 4, 2968 .vsync_end = 240 + 4 + 3, 2969 .vtotal = 240 + 4 + 3 + 15, 2970 }; 2971 2972 static const struct panel_desc lemaker_bl035_rgb_002 = { 2973 .modes = &lemaker_bl035_rgb_002_mode, 2974 .num_modes = 1, 2975 .size = { 2976 .width = 70, 2977 .height = 52, 2978 }, 2979 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2980 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2981 }; 2982 2983 static const struct display_timing lg_lb070wv8_timing = { 2984 .pixelclock = { 31950000, 33260000, 34600000 }, 2985 .hactive = { 800, 800, 800 }, 2986 .hfront_porch = { 88, 88, 88 }, 2987 .hback_porch = { 88, 88, 88 }, 2988 .hsync_len = { 80, 80, 80 }, 2989 .vactive = { 480, 480, 480 }, 2990 .vfront_porch = { 10, 10, 10 }, 2991 .vback_porch = { 10, 10, 10 }, 2992 .vsync_len = { 25, 25, 25 }, 2993 }; 2994 2995 static const struct panel_desc lg_lb070wv8 = { 2996 .timings = &lg_lb070wv8_timing, 2997 .num_timings = 1, 2998 .bpc = 8, 2999 .size = { 3000 .width = 151, 3001 .height = 91, 3002 }, 3003 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3005 }; 3006 3007 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3008 .clock = 155127, 3009 .hdisplay = 1920, 3010 .hsync_start = 1920 + 128, 3011 .hsync_end = 1920 + 128 + 20, 3012 .htotal = 1920 + 128 + 20 + 12, 3013 .vdisplay = 1200, 3014 .vsync_start = 1200 + 19, 3015 .vsync_end = 1200 + 19 + 4, 3016 .vtotal = 1200 + 19 + 4 + 20, 3017 }; 3018 3019 static const struct panel_desc lincolntech_lcd185_101ct = { 3020 .modes = &lincolntech_lcd185_101ct_mode, 3021 .bpc = 8, 3022 .num_modes = 1, 3023 .size = { 3024 .width = 217, 3025 .height = 136, 3026 }, 3027 .delay = { 3028 .prepare = 50, 3029 .disable = 50, 3030 }, 3031 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3033 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3034 }; 3035 3036 static const struct display_timing logictechno_lt161010_2nh_timing = { 3037 .pixelclock = { 26400000, 33300000, 46800000 }, 3038 .hactive = { 800, 800, 800 }, 3039 .hfront_porch = { 16, 210, 354 }, 3040 .hback_porch = { 46, 46, 46 }, 3041 .hsync_len = { 1, 20, 40 }, 3042 .vactive = { 480, 480, 480 }, 3043 .vfront_porch = { 7, 22, 147 }, 3044 .vback_porch = { 23, 23, 23 }, 3045 .vsync_len = { 1, 10, 20 }, 3046 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3047 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3048 DISPLAY_FLAGS_SYNC_POSEDGE, 3049 }; 3050 3051 static const struct panel_desc logictechno_lt161010_2nh = { 3052 .timings = &logictechno_lt161010_2nh_timing, 3053 .num_timings = 1, 3054 .bpc = 6, 3055 .size = { 3056 .width = 154, 3057 .height = 86, 3058 }, 3059 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3060 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3061 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3062 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3063 .connector_type = DRM_MODE_CONNECTOR_DPI, 3064 }; 3065 3066 static const struct display_timing logictechno_lt170410_2whc_timing = { 3067 .pixelclock = { 68900000, 71100000, 73400000 }, 3068 .hactive = { 1280, 1280, 1280 }, 3069 .hfront_porch = { 23, 60, 71 }, 3070 .hback_porch = { 23, 60, 71 }, 3071 .hsync_len = { 15, 40, 47 }, 3072 .vactive = { 800, 800, 800 }, 3073 .vfront_porch = { 5, 7, 10 }, 3074 .vback_porch = { 5, 7, 10 }, 3075 .vsync_len = { 6, 9, 12 }, 3076 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3077 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3078 DISPLAY_FLAGS_SYNC_POSEDGE, 3079 }; 3080 3081 static const struct panel_desc logictechno_lt170410_2whc = { 3082 .timings = &logictechno_lt170410_2whc_timing, 3083 .num_timings = 1, 3084 .bpc = 8, 3085 .size = { 3086 .width = 217, 3087 .height = 136, 3088 }, 3089 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3090 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3091 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3092 }; 3093 3094 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3095 .clock = 33000, 3096 .hdisplay = 800, 3097 .hsync_start = 800 + 112, 3098 .hsync_end = 800 + 112 + 3, 3099 .htotal = 800 + 112 + 3 + 85, 3100 .vdisplay = 480, 3101 .vsync_start = 480 + 38, 3102 .vsync_end = 480 + 38 + 3, 3103 .vtotal = 480 + 38 + 3 + 29, 3104 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3105 }; 3106 3107 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3108 .modes = &logictechno_lttd800480070_l2rt_mode, 3109 .num_modes = 1, 3110 .bpc = 8, 3111 .size = { 3112 .width = 154, 3113 .height = 86, 3114 }, 3115 .delay = { 3116 .prepare = 45, 3117 .enable = 100, 3118 .disable = 100, 3119 .unprepare = 45 3120 }, 3121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3122 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3123 .connector_type = DRM_MODE_CONNECTOR_DPI, 3124 }; 3125 3126 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3127 .clock = 33000, 3128 .hdisplay = 800, 3129 .hsync_start = 800 + 154, 3130 .hsync_end = 800 + 154 + 3, 3131 .htotal = 800 + 154 + 3 + 43, 3132 .vdisplay = 480, 3133 .vsync_start = 480 + 47, 3134 .vsync_end = 480 + 47 + 3, 3135 .vtotal = 480 + 47 + 3 + 20, 3136 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3137 }; 3138 3139 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3140 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3141 .num_modes = 1, 3142 .bpc = 8, 3143 .size = { 3144 .width = 154, 3145 .height = 86, 3146 }, 3147 .delay = { 3148 .prepare = 45, 3149 .enable = 100, 3150 .disable = 100, 3151 .unprepare = 45 3152 }, 3153 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3154 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3155 .connector_type = DRM_MODE_CONNECTOR_DPI, 3156 }; 3157 3158 static const struct drm_display_mode logicpd_type_28_mode = { 3159 .clock = 9107, 3160 .hdisplay = 480, 3161 .hsync_start = 480 + 3, 3162 .hsync_end = 480 + 3 + 42, 3163 .htotal = 480 + 3 + 42 + 2, 3164 3165 .vdisplay = 272, 3166 .vsync_start = 272 + 2, 3167 .vsync_end = 272 + 2 + 11, 3168 .vtotal = 272 + 2 + 11 + 3, 3169 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3170 }; 3171 3172 static const struct panel_desc logicpd_type_28 = { 3173 .modes = &logicpd_type_28_mode, 3174 .num_modes = 1, 3175 .bpc = 8, 3176 .size = { 3177 .width = 105, 3178 .height = 67, 3179 }, 3180 .delay = { 3181 .prepare = 200, 3182 .enable = 200, 3183 .unprepare = 200, 3184 .disable = 200, 3185 }, 3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3187 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3188 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3189 .connector_type = DRM_MODE_CONNECTOR_DPI, 3190 }; 3191 3192 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3193 .clock = 150275, 3194 .hdisplay = 1920, 3195 .hsync_start = 1920 + 32, 3196 .hsync_end = 1920 + 32 + 52, 3197 .htotal = 1920 + 32 + 52 + 24, 3198 .vdisplay = 1200, 3199 .vsync_start = 1200 + 24, 3200 .vsync_end = 1200 + 24 + 8, 3201 .vtotal = 1200 + 24 + 8 + 3, 3202 }; 3203 3204 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3205 .modes = µtips_mf_101hiebcaf0_c_mode, 3206 .bpc = 8, 3207 .num_modes = 1, 3208 .size = { 3209 .width = 217, 3210 .height = 136, 3211 }, 3212 .delay = { 3213 .prepare = 50, 3214 .disable = 50, 3215 }, 3216 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3217 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3218 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3219 }; 3220 3221 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3222 .clock = 93301, 3223 .hdisplay = 1920, 3224 .hsync_start = 1920 + 72, 3225 .hsync_end = 1920 + 72 + 72, 3226 .htotal = 1920 + 72 + 72 + 72, 3227 .vdisplay = 720, 3228 .vsync_start = 720 + 3, 3229 .vsync_end = 720 + 3 + 3, 3230 .vtotal = 720 + 3 + 3 + 2, 3231 }; 3232 3233 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3234 .modes = µtips_mf_103hieb0ga0_mode, 3235 .bpc = 8, 3236 .num_modes = 1, 3237 .size = { 3238 .width = 244, 3239 .height = 92, 3240 }, 3241 .delay = { 3242 .prepare = 50, 3243 .disable = 50, 3244 }, 3245 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3248 }; 3249 3250 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3251 .clock = 30400, 3252 .hdisplay = 800, 3253 .hsync_start = 800 + 0, 3254 .hsync_end = 800 + 1, 3255 .htotal = 800 + 0 + 1 + 160, 3256 .vdisplay = 480, 3257 .vsync_start = 480 + 0, 3258 .vsync_end = 480 + 48 + 1, 3259 .vtotal = 480 + 48 + 1 + 0, 3260 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3261 }; 3262 3263 static const struct panel_desc mitsubishi_aa070mc01 = { 3264 .modes = &mitsubishi_aa070mc01_mode, 3265 .num_modes = 1, 3266 .bpc = 8, 3267 .size = { 3268 .width = 152, 3269 .height = 91, 3270 }, 3271 3272 .delay = { 3273 .enable = 200, 3274 .unprepare = 200, 3275 .disable = 400, 3276 }, 3277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3279 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3280 }; 3281 3282 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3283 .clock = 56234, 3284 .hdisplay = 1024, 3285 .hsync_start = 1024 + 24, 3286 .hsync_end = 1024 + 24 + 63, 3287 .htotal = 1024 + 24 + 63 + 1, 3288 .vdisplay = 768, 3289 .vsync_start = 768 + 3, 3290 .vsync_end = 768 + 3 + 6, 3291 .vtotal = 768 + 3 + 6 + 1, 3292 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3293 }; 3294 3295 static const struct panel_desc mitsubishi_aa084xe01 = { 3296 .modes = &mitsubishi_aa084xe01_mode, 3297 .num_modes = 1, 3298 .bpc = 8, 3299 .size = { 3300 .width = 1024, 3301 .height = 768, 3302 }, 3303 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3304 .connector_type = DRM_MODE_CONNECTOR_DPI, 3305 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3306 }; 3307 3308 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3309 .pixelclock = { 26400000, 33000000, 46800000 }, 3310 .hactive = { 800, 800, 800 }, 3311 .hfront_porch = { 16, 204, 354 }, 3312 .hback_porch = { 46, 46, 46 }, 3313 .hsync_len = { 1, 6, 40 }, 3314 .vactive = { 480, 480, 480 }, 3315 .vfront_porch = { 7, 22, 147 }, 3316 .vback_porch = { 23, 23, 23 }, 3317 .vsync_len = { 1, 3, 20 }, 3318 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3319 DISPLAY_FLAGS_DE_HIGH, 3320 }; 3321 3322 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3323 .timings = &multi_inno_mi0700a2t_30_timing, 3324 .num_timings = 1, 3325 .bpc = 6, 3326 .size = { 3327 .width = 153, 3328 .height = 92, 3329 }, 3330 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3331 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3332 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3333 }; 3334 3335 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3336 .pixelclock = { 29000000, 33000000, 38000000 }, 3337 .hactive = { 800, 800, 800 }, 3338 .hfront_porch = { 180, 210, 240 }, 3339 .hback_porch = { 16, 16, 16 }, 3340 .hsync_len = { 30, 30, 30 }, 3341 .vactive = { 480, 480, 480 }, 3342 .vfront_porch = { 12, 22, 32 }, 3343 .vback_porch = { 10, 10, 10 }, 3344 .vsync_len = { 13, 13, 13 }, 3345 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3346 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3347 DISPLAY_FLAGS_SYNC_POSEDGE, 3348 }; 3349 3350 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3351 .timings = &multi_inno_mi0700s4t_6_timing, 3352 .num_timings = 1, 3353 .bpc = 8, 3354 .size = { 3355 .width = 154, 3356 .height = 86, 3357 }, 3358 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3359 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3360 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3361 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3362 .connector_type = DRM_MODE_CONNECTOR_DPI, 3363 }; 3364 3365 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3366 .pixelclock = { 32000000, 40000000, 50000000 }, 3367 .hactive = { 800, 800, 800 }, 3368 .hfront_porch = { 16, 210, 354 }, 3369 .hback_porch = { 6, 26, 45 }, 3370 .hsync_len = { 1, 20, 40 }, 3371 .vactive = { 600, 600, 600 }, 3372 .vfront_porch = { 1, 12, 77 }, 3373 .vback_porch = { 3, 13, 22 }, 3374 .vsync_len = { 1, 10, 20 }, 3375 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3376 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3377 DISPLAY_FLAGS_SYNC_POSEDGE, 3378 }; 3379 3380 static const struct panel_desc multi_inno_mi0800ft_9 = { 3381 .timings = &multi_inno_mi0800ft_9_timing, 3382 .num_timings = 1, 3383 .bpc = 8, 3384 .size = { 3385 .width = 162, 3386 .height = 122, 3387 }, 3388 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3389 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3390 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3391 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3392 .connector_type = DRM_MODE_CONNECTOR_DPI, 3393 }; 3394 3395 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3396 .pixelclock = { 68900000, 70000000, 73400000 }, 3397 .hactive = { 1280, 1280, 1280 }, 3398 .hfront_porch = { 30, 60, 71 }, 3399 .hback_porch = { 30, 60, 71 }, 3400 .hsync_len = { 10, 10, 48 }, 3401 .vactive = { 800, 800, 800 }, 3402 .vfront_porch = { 5, 10, 10 }, 3403 .vback_porch = { 5, 10, 10 }, 3404 .vsync_len = { 5, 6, 13 }, 3405 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3406 DISPLAY_FLAGS_DE_HIGH, 3407 }; 3408 3409 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3410 .timings = &multi_inno_mi1010ait_1cp_timing, 3411 .num_timings = 1, 3412 .bpc = 8, 3413 .size = { 3414 .width = 217, 3415 .height = 136, 3416 }, 3417 .delay = { 3418 .enable = 50, 3419 .disable = 50, 3420 }, 3421 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3422 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3423 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3424 }; 3425 3426 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3427 .pixelclock = { 40800000, 51200000, 67200000 }, 3428 .hactive = { 1024, 1024, 1024 }, 3429 .hfront_porch = { 30, 110, 130 }, 3430 .hback_porch = { 30, 110, 130 }, 3431 .hsync_len = { 30, 100, 116 }, 3432 .vactive = { 600, 600, 600 }, 3433 .vfront_porch = { 4, 13, 80 }, 3434 .vback_porch = { 4, 13, 80 }, 3435 .vsync_len = { 2, 9, 40 }, 3436 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3437 DISPLAY_FLAGS_DE_HIGH, 3438 }; 3439 3440 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3441 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3442 .num_timings = 1, 3443 .bpc = 6, 3444 .size = { 3445 .width = 260, 3446 .height = 162, 3447 }, 3448 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3449 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3450 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3451 }; 3452 3453 static const struct display_timing nec_nl12880bc20_05_timing = { 3454 .pixelclock = { 67000000, 71000000, 75000000 }, 3455 .hactive = { 1280, 1280, 1280 }, 3456 .hfront_porch = { 2, 30, 30 }, 3457 .hback_porch = { 6, 100, 100 }, 3458 .hsync_len = { 2, 30, 30 }, 3459 .vactive = { 800, 800, 800 }, 3460 .vfront_porch = { 5, 5, 5 }, 3461 .vback_porch = { 11, 11, 11 }, 3462 .vsync_len = { 7, 7, 7 }, 3463 }; 3464 3465 static const struct panel_desc nec_nl12880bc20_05 = { 3466 .timings = &nec_nl12880bc20_05_timing, 3467 .num_timings = 1, 3468 .bpc = 8, 3469 .size = { 3470 .width = 261, 3471 .height = 163, 3472 }, 3473 .delay = { 3474 .enable = 50, 3475 .disable = 50, 3476 }, 3477 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3478 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3479 }; 3480 3481 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3482 .clock = 10870, 3483 .hdisplay = 480, 3484 .hsync_start = 480 + 2, 3485 .hsync_end = 480 + 2 + 41, 3486 .htotal = 480 + 2 + 41 + 2, 3487 .vdisplay = 272, 3488 .vsync_start = 272 + 2, 3489 .vsync_end = 272 + 2 + 4, 3490 .vtotal = 272 + 2 + 4 + 2, 3491 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3492 }; 3493 3494 static const struct panel_desc nec_nl4827hc19_05b = { 3495 .modes = &nec_nl4827hc19_05b_mode, 3496 .num_modes = 1, 3497 .bpc = 8, 3498 .size = { 3499 .width = 95, 3500 .height = 54, 3501 }, 3502 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3503 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3504 }; 3505 3506 static const struct drm_display_mode netron_dy_e231732_mode = { 3507 .clock = 66000, 3508 .hdisplay = 1024, 3509 .hsync_start = 1024 + 160, 3510 .hsync_end = 1024 + 160 + 70, 3511 .htotal = 1024 + 160 + 70 + 90, 3512 .vdisplay = 600, 3513 .vsync_start = 600 + 127, 3514 .vsync_end = 600 + 127 + 20, 3515 .vtotal = 600 + 127 + 20 + 3, 3516 }; 3517 3518 static const struct panel_desc netron_dy_e231732 = { 3519 .modes = &netron_dy_e231732_mode, 3520 .num_modes = 1, 3521 .size = { 3522 .width = 154, 3523 .height = 87, 3524 }, 3525 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3526 }; 3527 3528 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3529 .clock = 9000, 3530 .hdisplay = 480, 3531 .hsync_start = 480 + 2, 3532 .hsync_end = 480 + 2 + 41, 3533 .htotal = 480 + 2 + 41 + 2, 3534 .vdisplay = 272, 3535 .vsync_start = 272 + 2, 3536 .vsync_end = 272 + 2 + 10, 3537 .vtotal = 272 + 2 + 10 + 2, 3538 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3539 }; 3540 3541 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3542 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3543 .num_modes = 1, 3544 .bpc = 8, 3545 .size = { 3546 .width = 95, 3547 .height = 54, 3548 }, 3549 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3550 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3551 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3552 .connector_type = DRM_MODE_CONNECTOR_DPI, 3553 }; 3554 3555 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3556 .clock = 75400, 3557 .hdisplay = 1366, 3558 .hsync_start = 1366 + 14, 3559 .hsync_end = 1366 + 14 + 56, 3560 .htotal = 1366 + 14 + 56 + 64, 3561 .vdisplay = 768, 3562 .vsync_start = 768 + 1, 3563 .vsync_end = 768 + 1 + 3, 3564 .vtotal = 768 + 1 + 3 + 22, 3565 }; 3566 3567 static const struct panel_desc nlt_nl13676bc25_03f = { 3568 .modes = &nlt_nl13676bc25_03f_mode, 3569 .num_modes = 1, 3570 .bpc = 8, 3571 .size = { 3572 .width = 363, 3573 .height = 215, 3574 }, 3575 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3577 }; 3578 3579 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3580 .pixelclock = { 130000000, 148350000, 163000000 }, 3581 .hactive = { 1920, 1920, 1920 }, 3582 .hfront_porch = { 80, 100, 100 }, 3583 .hback_porch = { 100, 120, 120 }, 3584 .hsync_len = { 50, 60, 60 }, 3585 .vactive = { 1080, 1080, 1080 }, 3586 .vfront_porch = { 12, 30, 30 }, 3587 .vback_porch = { 4, 10, 10 }, 3588 .vsync_len = { 4, 5, 5 }, 3589 }; 3590 3591 static const struct panel_desc nlt_nl192108ac18_02d = { 3592 .timings = &nlt_nl192108ac18_02d_timing, 3593 .num_timings = 1, 3594 .bpc = 8, 3595 .size = { 3596 .width = 344, 3597 .height = 194, 3598 }, 3599 .delay = { 3600 .unprepare = 500, 3601 }, 3602 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3603 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3604 }; 3605 3606 static const struct drm_display_mode nvd_9128_mode = { 3607 .clock = 29500, 3608 .hdisplay = 800, 3609 .hsync_start = 800 + 130, 3610 .hsync_end = 800 + 130 + 98, 3611 .htotal = 800 + 0 + 130 + 98, 3612 .vdisplay = 480, 3613 .vsync_start = 480 + 10, 3614 .vsync_end = 480 + 10 + 50, 3615 .vtotal = 480 + 0 + 10 + 50, 3616 }; 3617 3618 static const struct panel_desc nvd_9128 = { 3619 .modes = &nvd_9128_mode, 3620 .num_modes = 1, 3621 .bpc = 8, 3622 .size = { 3623 .width = 156, 3624 .height = 88, 3625 }, 3626 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3627 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3628 }; 3629 3630 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3631 .pixelclock = { 30000000, 30000000, 40000000 }, 3632 .hactive = { 800, 800, 800 }, 3633 .hfront_porch = { 40, 40, 40 }, 3634 .hback_porch = { 40, 40, 40 }, 3635 .hsync_len = { 1, 48, 48 }, 3636 .vactive = { 480, 480, 480 }, 3637 .vfront_porch = { 13, 13, 13 }, 3638 .vback_porch = { 29, 29, 29 }, 3639 .vsync_len = { 3, 3, 3 }, 3640 .flags = DISPLAY_FLAGS_DE_HIGH, 3641 }; 3642 3643 static const struct panel_desc okaya_rs800480t_7x0gp = { 3644 .timings = &okaya_rs800480t_7x0gp_timing, 3645 .num_timings = 1, 3646 .bpc = 6, 3647 .size = { 3648 .width = 154, 3649 .height = 87, 3650 }, 3651 .delay = { 3652 .prepare = 41, 3653 .enable = 50, 3654 .unprepare = 41, 3655 .disable = 50, 3656 }, 3657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3658 }; 3659 3660 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3661 .clock = 9000, 3662 .hdisplay = 480, 3663 .hsync_start = 480 + 5, 3664 .hsync_end = 480 + 5 + 30, 3665 .htotal = 480 + 5 + 30 + 10, 3666 .vdisplay = 272, 3667 .vsync_start = 272 + 8, 3668 .vsync_end = 272 + 8 + 5, 3669 .vtotal = 272 + 8 + 5 + 3, 3670 }; 3671 3672 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3673 .modes = &olimex_lcd_olinuxino_43ts_mode, 3674 .num_modes = 1, 3675 .size = { 3676 .width = 95, 3677 .height = 54, 3678 }, 3679 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3680 }; 3681 3682 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3683 .pixelclock = { 30000000, 30000000, 50000000 }, 3684 .hactive = { 800, 800, 800 }, 3685 .hfront_porch = { 1, 40, 255 }, 3686 .hback_porch = { 1, 40, 87 }, 3687 .hsync_len = { 1, 48, 87 }, 3688 .vactive = { 480, 480, 480 }, 3689 .vfront_porch = { 1, 13, 255 }, 3690 .vback_porch = { 1, 29, 29 }, 3691 .vsync_len = { 3, 3, 31 }, 3692 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3693 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3694 }; 3695 3696 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3697 .timings = &ontat_kd50g21_40nt_a1_timing, 3698 .num_timings = 1, 3699 .bpc = 8, 3700 .size = { 3701 .width = 108, 3702 .height = 65, 3703 }, 3704 .delay = { 3705 .prepare = 147, /* 5 VSDs */ 3706 .enable = 147, /* 5 VSDs */ 3707 .disable = 88, /* 3 VSDs */ 3708 .unprepare = 117, /* 4 VSDs */ 3709 }, 3710 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3711 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3712 .connector_type = DRM_MODE_CONNECTOR_DPI, 3713 }; 3714 3715 /* 3716 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3717 * pixel clocks, but this is the timing that was being used in the Adafruit 3718 * installation instructions. 3719 */ 3720 static const struct drm_display_mode ontat_yx700wv03_mode = { 3721 .clock = 29500, 3722 .hdisplay = 800, 3723 .hsync_start = 824, 3724 .hsync_end = 896, 3725 .htotal = 992, 3726 .vdisplay = 480, 3727 .vsync_start = 483, 3728 .vsync_end = 493, 3729 .vtotal = 500, 3730 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3731 }; 3732 3733 /* 3734 * Specification at: 3735 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3736 */ 3737 static const struct panel_desc ontat_yx700wv03 = { 3738 .modes = &ontat_yx700wv03_mode, 3739 .num_modes = 1, 3740 .bpc = 8, 3741 .size = { 3742 .width = 154, 3743 .height = 83, 3744 }, 3745 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3746 }; 3747 3748 static const struct drm_display_mode ortustech_com37h3m_mode = { 3749 .clock = 22230, 3750 .hdisplay = 480, 3751 .hsync_start = 480 + 40, 3752 .hsync_end = 480 + 40 + 10, 3753 .htotal = 480 + 40 + 10 + 40, 3754 .vdisplay = 640, 3755 .vsync_start = 640 + 4, 3756 .vsync_end = 640 + 4 + 2, 3757 .vtotal = 640 + 4 + 2 + 4, 3758 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3759 }; 3760 3761 static const struct panel_desc ortustech_com37h3m = { 3762 .modes = &ortustech_com37h3m_mode, 3763 .num_modes = 1, 3764 .bpc = 8, 3765 .size = { 3766 .width = 56, /* 56.16mm */ 3767 .height = 75, /* 74.88mm */ 3768 }, 3769 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3770 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3771 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3772 }; 3773 3774 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3775 .clock = 25000, 3776 .hdisplay = 480, 3777 .hsync_start = 480 + 10, 3778 .hsync_end = 480 + 10 + 10, 3779 .htotal = 480 + 10 + 10 + 15, 3780 .vdisplay = 800, 3781 .vsync_start = 800 + 3, 3782 .vsync_end = 800 + 3 + 3, 3783 .vtotal = 800 + 3 + 3 + 3, 3784 }; 3785 3786 static const struct panel_desc ortustech_com43h4m85ulc = { 3787 .modes = &ortustech_com43h4m85ulc_mode, 3788 .num_modes = 1, 3789 .bpc = 6, 3790 .size = { 3791 .width = 56, 3792 .height = 93, 3793 }, 3794 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3795 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3796 .connector_type = DRM_MODE_CONNECTOR_DPI, 3797 }; 3798 3799 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3800 .clock = 33000, 3801 .hdisplay = 800, 3802 .hsync_start = 800 + 210, 3803 .hsync_end = 800 + 210 + 30, 3804 .htotal = 800 + 210 + 30 + 16, 3805 .vdisplay = 480, 3806 .vsync_start = 480 + 22, 3807 .vsync_end = 480 + 22 + 13, 3808 .vtotal = 480 + 22 + 13 + 10, 3809 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3810 }; 3811 3812 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3813 .modes = &osddisplays_osd070t1718_19ts_mode, 3814 .num_modes = 1, 3815 .bpc = 8, 3816 .size = { 3817 .width = 152, 3818 .height = 91, 3819 }, 3820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3821 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3822 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3823 .connector_type = DRM_MODE_CONNECTOR_DPI, 3824 }; 3825 3826 static const struct drm_display_mode pda_91_00156_a0_mode = { 3827 .clock = 33300, 3828 .hdisplay = 800, 3829 .hsync_start = 800 + 1, 3830 .hsync_end = 800 + 1 + 64, 3831 .htotal = 800 + 1 + 64 + 64, 3832 .vdisplay = 480, 3833 .vsync_start = 480 + 1, 3834 .vsync_end = 480 + 1 + 23, 3835 .vtotal = 480 + 1 + 23 + 22, 3836 }; 3837 3838 static const struct panel_desc pda_91_00156_a0 = { 3839 .modes = &pda_91_00156_a0_mode, 3840 .num_modes = 1, 3841 .size = { 3842 .width = 152, 3843 .height = 91, 3844 }, 3845 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3846 }; 3847 3848 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3849 .clock = 71150, 3850 .hdisplay = 1280, 3851 .hsync_start = 1280 + 48, 3852 .hsync_end = 1280 + 48 + 32, 3853 .htotal = 1280 + 48 + 32 + 80, 3854 .vdisplay = 800, 3855 .vsync_start = 800 + 9, 3856 .vsync_end = 800 + 9 + 8, 3857 .vtotal = 800 + 9 + 8 + 6, 3858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3859 }; 3860 3861 static const struct panel_desc powertip_ph128800t004_zza01 = { 3862 .modes = &powertip_ph128800t004_zza01_mode, 3863 .num_modes = 1, 3864 .bpc = 8, 3865 .size = { 3866 .width = 216, 3867 .height = 135, 3868 }, 3869 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3870 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3872 }; 3873 3874 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3875 .clock = 66500, 3876 .hdisplay = 1280, 3877 .hsync_start = 1280 + 12, 3878 .hsync_end = 1280 + 12 + 20, 3879 .htotal = 1280 + 12 + 20 + 56, 3880 .vdisplay = 800, 3881 .vsync_start = 800 + 1, 3882 .vsync_end = 800 + 1 + 3, 3883 .vtotal = 800 + 1 + 3 + 20, 3884 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3885 }; 3886 3887 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3888 .modes = &powertip_ph128800t006_zhc01_mode, 3889 .num_modes = 1, 3890 .bpc = 8, 3891 .size = { 3892 .width = 216, 3893 .height = 135, 3894 }, 3895 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3896 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3897 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3898 }; 3899 3900 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3901 .clock = 24750, 3902 .hdisplay = 800, 3903 .hsync_start = 800 + 54, 3904 .hsync_end = 800 + 54 + 2, 3905 .htotal = 800 + 54 + 2 + 44, 3906 .vdisplay = 480, 3907 .vsync_start = 480 + 49, 3908 .vsync_end = 480 + 49 + 2, 3909 .vtotal = 480 + 49 + 2 + 22, 3910 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3911 }; 3912 3913 static const struct panel_desc powertip_ph800480t013_idf02 = { 3914 .modes = &powertip_ph800480t013_idf02_mode, 3915 .num_modes = 1, 3916 .bpc = 8, 3917 .size = { 3918 .width = 152, 3919 .height = 91, 3920 }, 3921 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3922 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3923 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3925 .connector_type = DRM_MODE_CONNECTOR_DPI, 3926 }; 3927 3928 static const struct drm_display_mode primeview_pm070wl4_mode = { 3929 .clock = 32000, 3930 .hdisplay = 800, 3931 .hsync_start = 800 + 42, 3932 .hsync_end = 800 + 42 + 128, 3933 .htotal = 800 + 42 + 128 + 86, 3934 .vdisplay = 480, 3935 .vsync_start = 480 + 10, 3936 .vsync_end = 480 + 10 + 2, 3937 .vtotal = 480 + 10 + 2 + 33, 3938 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3939 }; 3940 3941 static const struct panel_desc primeview_pm070wl4 = { 3942 .modes = &primeview_pm070wl4_mode, 3943 .num_modes = 1, 3944 .bpc = 6, 3945 .size = { 3946 .width = 152, 3947 .height = 91, 3948 }, 3949 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3950 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3951 .connector_type = DRM_MODE_CONNECTOR_DPI, 3952 }; 3953 3954 static const struct drm_display_mode qd43003c0_40_mode = { 3955 .clock = 9000, 3956 .hdisplay = 480, 3957 .hsync_start = 480 + 8, 3958 .hsync_end = 480 + 8 + 4, 3959 .htotal = 480 + 8 + 4 + 39, 3960 .vdisplay = 272, 3961 .vsync_start = 272 + 4, 3962 .vsync_end = 272 + 4 + 10, 3963 .vtotal = 272 + 4 + 10 + 2, 3964 }; 3965 3966 static const struct panel_desc qd43003c0_40 = { 3967 .modes = &qd43003c0_40_mode, 3968 .num_modes = 1, 3969 .bpc = 8, 3970 .size = { 3971 .width = 95, 3972 .height = 53, 3973 }, 3974 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3975 }; 3976 3977 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3978 { /* 60 Hz */ 3979 .clock = 10800, 3980 .hdisplay = 480, 3981 .hsync_start = 480 + 77, 3982 .hsync_end = 480 + 77 + 41, 3983 .htotal = 480 + 77 + 41 + 2, 3984 .vdisplay = 272, 3985 .vsync_start = 272 + 16, 3986 .vsync_end = 272 + 16 + 10, 3987 .vtotal = 272 + 16 + 10 + 2, 3988 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3989 }, 3990 { /* 50 Hz */ 3991 .clock = 10800, 3992 .hdisplay = 480, 3993 .hsync_start = 480 + 17, 3994 .hsync_end = 480 + 17 + 41, 3995 .htotal = 480 + 17 + 41 + 2, 3996 .vdisplay = 272, 3997 .vsync_start = 272 + 116, 3998 .vsync_end = 272 + 116 + 10, 3999 .vtotal = 272 + 116 + 10 + 2, 4000 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4001 }, 4002 }; 4003 4004 static const struct panel_desc qishenglong_gopher2b_lcd = { 4005 .modes = qishenglong_gopher2b_lcd_modes, 4006 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4007 .bpc = 8, 4008 .size = { 4009 .width = 95, 4010 .height = 54, 4011 }, 4012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4014 .connector_type = DRM_MODE_CONNECTOR_DPI, 4015 }; 4016 4017 static const struct display_timing rocktech_rk043fn48h_timing = { 4018 .pixelclock = { 6000000, 9000000, 12000000 }, 4019 .hactive = { 480, 480, 480 }, 4020 .hback_porch = { 8, 43, 43 }, 4021 .hfront_porch = { 2, 8, 10 }, 4022 .hsync_len = { 1, 1, 1 }, 4023 .vactive = { 272, 272, 272 }, 4024 .vback_porch = { 2, 12, 26 }, 4025 .vfront_porch = { 1, 4, 4 }, 4026 .vsync_len = { 1, 10, 10 }, 4027 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4028 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4029 DISPLAY_FLAGS_SYNC_POSEDGE, 4030 }; 4031 4032 static const struct panel_desc rocktech_rk043fn48h = { 4033 .timings = &rocktech_rk043fn48h_timing, 4034 .num_timings = 1, 4035 .bpc = 8, 4036 .size = { 4037 .width = 95, 4038 .height = 54, 4039 }, 4040 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4041 .connector_type = DRM_MODE_CONNECTOR_DPI, 4042 }; 4043 4044 static const struct display_timing rocktech_rk070er9427_timing = { 4045 .pixelclock = { 26400000, 33300000, 46800000 }, 4046 .hactive = { 800, 800, 800 }, 4047 .hfront_porch = { 16, 210, 354 }, 4048 .hback_porch = { 46, 46, 46 }, 4049 .hsync_len = { 1, 1, 1 }, 4050 .vactive = { 480, 480, 480 }, 4051 .vfront_porch = { 7, 22, 147 }, 4052 .vback_porch = { 23, 23, 23 }, 4053 .vsync_len = { 1, 1, 1 }, 4054 .flags = DISPLAY_FLAGS_DE_HIGH, 4055 }; 4056 4057 static const struct panel_desc rocktech_rk070er9427 = { 4058 .timings = &rocktech_rk070er9427_timing, 4059 .num_timings = 1, 4060 .bpc = 6, 4061 .size = { 4062 .width = 154, 4063 .height = 86, 4064 }, 4065 .delay = { 4066 .prepare = 41, 4067 .enable = 50, 4068 .unprepare = 41, 4069 .disable = 50, 4070 }, 4071 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4072 }; 4073 4074 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4075 .clock = 71100, 4076 .hdisplay = 1280, 4077 .hsync_start = 1280 + 48, 4078 .hsync_end = 1280 + 48 + 32, 4079 .htotal = 1280 + 48 + 32 + 80, 4080 .vdisplay = 800, 4081 .vsync_start = 800 + 2, 4082 .vsync_end = 800 + 2 + 5, 4083 .vtotal = 800 + 2 + 5 + 16, 4084 }; 4085 4086 static const struct panel_desc rocktech_rk101ii01d_ct = { 4087 .modes = &rocktech_rk101ii01d_ct_mode, 4088 .bpc = 8, 4089 .num_modes = 1, 4090 .size = { 4091 .width = 217, 4092 .height = 136, 4093 }, 4094 .delay = { 4095 .prepare = 50, 4096 .disable = 50, 4097 }, 4098 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4100 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4101 }; 4102 4103 static const struct display_timing samsung_ltl101al01_timing = { 4104 .pixelclock = { 66663000, 66663000, 66663000 }, 4105 .hactive = { 1280, 1280, 1280 }, 4106 .hfront_porch = { 18, 18, 18 }, 4107 .hback_porch = { 36, 36, 36 }, 4108 .hsync_len = { 16, 16, 16 }, 4109 .vactive = { 800, 800, 800 }, 4110 .vfront_porch = { 4, 4, 4 }, 4111 .vback_porch = { 16, 16, 16 }, 4112 .vsync_len = { 3, 3, 3 }, 4113 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4114 }; 4115 4116 static const struct panel_desc samsung_ltl101al01 = { 4117 .timings = &samsung_ltl101al01_timing, 4118 .num_timings = 1, 4119 .bpc = 8, 4120 .size = { 4121 .width = 217, 4122 .height = 135, 4123 }, 4124 .delay = { 4125 .prepare = 40, 4126 .enable = 300, 4127 .disable = 200, 4128 .unprepare = 600, 4129 }, 4130 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4131 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4132 }; 4133 4134 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4135 .clock = 54030, 4136 .hdisplay = 1024, 4137 .hsync_start = 1024 + 24, 4138 .hsync_end = 1024 + 24 + 136, 4139 .htotal = 1024 + 24 + 136 + 160, 4140 .vdisplay = 600, 4141 .vsync_start = 600 + 3, 4142 .vsync_end = 600 + 3 + 6, 4143 .vtotal = 600 + 3 + 6 + 61, 4144 }; 4145 4146 static const struct panel_desc samsung_ltn101nt05 = { 4147 .modes = &samsung_ltn101nt05_mode, 4148 .num_modes = 1, 4149 .bpc = 6, 4150 .size = { 4151 .width = 223, 4152 .height = 125, 4153 }, 4154 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4155 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4156 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4157 }; 4158 4159 static const struct display_timing satoz_sat050at40h12r2_timing = { 4160 .pixelclock = {33300000, 33300000, 50000000}, 4161 .hactive = {800, 800, 800}, 4162 .hfront_porch = {16, 210, 354}, 4163 .hback_porch = {46, 46, 46}, 4164 .hsync_len = {1, 1, 40}, 4165 .vactive = {480, 480, 480}, 4166 .vfront_porch = {7, 22, 147}, 4167 .vback_porch = {23, 23, 23}, 4168 .vsync_len = {1, 1, 20}, 4169 }; 4170 4171 static const struct panel_desc satoz_sat050at40h12r2 = { 4172 .timings = &satoz_sat050at40h12r2_timing, 4173 .num_timings = 1, 4174 .bpc = 8, 4175 .size = { 4176 .width = 108, 4177 .height = 65, 4178 }, 4179 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4180 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4181 }; 4182 4183 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4184 .clock = 33260, 4185 .hdisplay = 800, 4186 .hsync_start = 800 + 64, 4187 .hsync_end = 800 + 64 + 128, 4188 .htotal = 800 + 64 + 128 + 64, 4189 .vdisplay = 480, 4190 .vsync_start = 480 + 8, 4191 .vsync_end = 480 + 8 + 2, 4192 .vtotal = 480 + 8 + 2 + 35, 4193 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4194 }; 4195 4196 static const struct panel_desc sharp_lq070y3dg3b = { 4197 .modes = &sharp_lq070y3dg3b_mode, 4198 .num_modes = 1, 4199 .bpc = 8, 4200 .size = { 4201 .width = 152, /* 152.4mm */ 4202 .height = 91, /* 91.4mm */ 4203 }, 4204 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4205 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4206 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4207 }; 4208 4209 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4210 .clock = 5500, 4211 .hdisplay = 240, 4212 .hsync_start = 240 + 16, 4213 .hsync_end = 240 + 16 + 7, 4214 .htotal = 240 + 16 + 7 + 5, 4215 .vdisplay = 320, 4216 .vsync_start = 320 + 9, 4217 .vsync_end = 320 + 9 + 1, 4218 .vtotal = 320 + 9 + 1 + 7, 4219 }; 4220 4221 static const struct panel_desc sharp_lq035q7db03 = { 4222 .modes = &sharp_lq035q7db03_mode, 4223 .num_modes = 1, 4224 .bpc = 6, 4225 .size = { 4226 .width = 54, 4227 .height = 72, 4228 }, 4229 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4230 }; 4231 4232 static const struct display_timing sharp_lq101k1ly04_timing = { 4233 .pixelclock = { 60000000, 65000000, 80000000 }, 4234 .hactive = { 1280, 1280, 1280 }, 4235 .hfront_porch = { 20, 20, 20 }, 4236 .hback_porch = { 20, 20, 20 }, 4237 .hsync_len = { 10, 10, 10 }, 4238 .vactive = { 800, 800, 800 }, 4239 .vfront_porch = { 4, 4, 4 }, 4240 .vback_porch = { 4, 4, 4 }, 4241 .vsync_len = { 4, 4, 4 }, 4242 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4243 }; 4244 4245 static const struct panel_desc sharp_lq101k1ly04 = { 4246 .timings = &sharp_lq101k1ly04_timing, 4247 .num_timings = 1, 4248 .bpc = 8, 4249 .size = { 4250 .width = 217, 4251 .height = 136, 4252 }, 4253 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4254 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4255 }; 4256 4257 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4258 { /* 50 Hz */ 4259 .clock = 3000, 4260 .hdisplay = 240, 4261 .hsync_start = 240 + 58, 4262 .hsync_end = 240 + 58 + 1, 4263 .htotal = 240 + 58 + 1 + 1, 4264 .vdisplay = 160, 4265 .vsync_start = 160 + 24, 4266 .vsync_end = 160 + 24 + 10, 4267 .vtotal = 160 + 24 + 10 + 6, 4268 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4269 }, 4270 { /* 60 Hz */ 4271 .clock = 3000, 4272 .hdisplay = 240, 4273 .hsync_start = 240 + 8, 4274 .hsync_end = 240 + 8 + 1, 4275 .htotal = 240 + 8 + 1 + 1, 4276 .vdisplay = 160, 4277 .vsync_start = 160 + 24, 4278 .vsync_end = 160 + 24 + 10, 4279 .vtotal = 160 + 24 + 10 + 6, 4280 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4281 }, 4282 }; 4283 4284 static const struct panel_desc sharp_ls020b1dd01d = { 4285 .modes = sharp_ls020b1dd01d_modes, 4286 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4287 .bpc = 6, 4288 .size = { 4289 .width = 42, 4290 .height = 28, 4291 }, 4292 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4293 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4294 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4295 | DRM_BUS_FLAG_SHARP_SIGNALS, 4296 }; 4297 4298 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4299 .clock = 33300, 4300 .hdisplay = 800, 4301 .hsync_start = 800 + 1, 4302 .hsync_end = 800 + 1 + 64, 4303 .htotal = 800 + 1 + 64 + 64, 4304 .vdisplay = 480, 4305 .vsync_start = 480 + 1, 4306 .vsync_end = 480 + 1 + 23, 4307 .vtotal = 480 + 1 + 23 + 22, 4308 }; 4309 4310 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4311 .modes = &shelly_sca07010_bfn_lnn_mode, 4312 .num_modes = 1, 4313 .size = { 4314 .width = 152, 4315 .height = 91, 4316 }, 4317 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4318 }; 4319 4320 static const struct drm_display_mode starry_kr070pe2t_mode = { 4321 .clock = 33000, 4322 .hdisplay = 800, 4323 .hsync_start = 800 + 209, 4324 .hsync_end = 800 + 209 + 1, 4325 .htotal = 800 + 209 + 1 + 45, 4326 .vdisplay = 480, 4327 .vsync_start = 480 + 22, 4328 .vsync_end = 480 + 22 + 1, 4329 .vtotal = 480 + 22 + 1 + 22, 4330 }; 4331 4332 static const struct panel_desc starry_kr070pe2t = { 4333 .modes = &starry_kr070pe2t_mode, 4334 .num_modes = 1, 4335 .bpc = 8, 4336 .size = { 4337 .width = 152, 4338 .height = 86, 4339 }, 4340 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4341 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4342 .connector_type = DRM_MODE_CONNECTOR_DPI, 4343 }; 4344 4345 static const struct display_timing startek_kd070wvfpa_mode = { 4346 .pixelclock = { 25200000, 27200000, 30500000 }, 4347 .hactive = { 800, 800, 800 }, 4348 .hfront_porch = { 19, 44, 115 }, 4349 .hback_porch = { 5, 16, 101 }, 4350 .hsync_len = { 1, 2, 100 }, 4351 .vactive = { 480, 480, 480 }, 4352 .vfront_porch = { 5, 43, 67 }, 4353 .vback_porch = { 5, 5, 67 }, 4354 .vsync_len = { 1, 2, 66 }, 4355 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4356 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4357 DISPLAY_FLAGS_SYNC_POSEDGE, 4358 }; 4359 4360 static const struct panel_desc startek_kd070wvfpa = { 4361 .timings = &startek_kd070wvfpa_mode, 4362 .num_timings = 1, 4363 .bpc = 8, 4364 .size = { 4365 .width = 152, 4366 .height = 91, 4367 }, 4368 .delay = { 4369 .prepare = 20, 4370 .enable = 200, 4371 .disable = 200, 4372 }, 4373 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4374 .connector_type = DRM_MODE_CONNECTOR_DPI, 4375 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4376 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4377 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4378 }; 4379 4380 static const struct display_timing tsd_tst043015cmhx_timing = { 4381 .pixelclock = { 5000000, 9000000, 12000000 }, 4382 .hactive = { 480, 480, 480 }, 4383 .hfront_porch = { 4, 5, 65 }, 4384 .hback_porch = { 36, 40, 255 }, 4385 .hsync_len = { 1, 1, 1 }, 4386 .vactive = { 272, 272, 272 }, 4387 .vfront_porch = { 2, 8, 97 }, 4388 .vback_porch = { 3, 8, 31 }, 4389 .vsync_len = { 1, 1, 1 }, 4390 4391 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4392 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4393 }; 4394 4395 static const struct panel_desc tsd_tst043015cmhx = { 4396 .timings = &tsd_tst043015cmhx_timing, 4397 .num_timings = 1, 4398 .bpc = 8, 4399 .size = { 4400 .width = 105, 4401 .height = 67, 4402 }, 4403 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4404 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4405 }; 4406 4407 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4408 .clock = 30000, 4409 .hdisplay = 800, 4410 .hsync_start = 800 + 39, 4411 .hsync_end = 800 + 39 + 47, 4412 .htotal = 800 + 39 + 47 + 39, 4413 .vdisplay = 480, 4414 .vsync_start = 480 + 13, 4415 .vsync_end = 480 + 13 + 2, 4416 .vtotal = 480 + 13 + 2 + 29, 4417 }; 4418 4419 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4420 .modes = &tfc_s9700rtwv43tr_01b_mode, 4421 .num_modes = 1, 4422 .bpc = 8, 4423 .size = { 4424 .width = 155, 4425 .height = 90, 4426 }, 4427 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4428 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4429 }; 4430 4431 static const struct display_timing tianma_tm070jdhg30_timing = { 4432 .pixelclock = { 62600000, 68200000, 78100000 }, 4433 .hactive = { 1280, 1280, 1280 }, 4434 .hfront_porch = { 15, 64, 159 }, 4435 .hback_porch = { 5, 5, 5 }, 4436 .hsync_len = { 1, 1, 256 }, 4437 .vactive = { 800, 800, 800 }, 4438 .vfront_porch = { 3, 40, 99 }, 4439 .vback_porch = { 2, 2, 2 }, 4440 .vsync_len = { 1, 1, 128 }, 4441 .flags = DISPLAY_FLAGS_DE_HIGH, 4442 }; 4443 4444 static const struct panel_desc tianma_tm070jdhg30 = { 4445 .timings = &tianma_tm070jdhg30_timing, 4446 .num_timings = 1, 4447 .bpc = 8, 4448 .size = { 4449 .width = 151, 4450 .height = 95, 4451 }, 4452 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4453 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4454 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4455 }; 4456 4457 static const struct panel_desc tianma_tm070jvhg33 = { 4458 .timings = &tianma_tm070jdhg30_timing, 4459 .num_timings = 1, 4460 .bpc = 8, 4461 .size = { 4462 .width = 150, 4463 .height = 94, 4464 }, 4465 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4466 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4467 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4468 }; 4469 4470 /* 4471 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4472 * front porch, not including sync pulse width. This is for both H and 4473 * V. To make the total blanking and period correct, subtract the pulse 4474 * width from the front porch. 4475 * 4476 * This works well for the Min and Typ values, but for Max values the sync 4477 * pulse width is higher than back porch + front porch, so work around that 4478 * by reducing the Max sync length value to 1 and then treating the Max 4479 * porches as in the Min and Typ cases. 4480 * 4481 * Exact datasheet values are added as a comment where they differ from the 4482 * ones implemented for the above reason. 4483 * 4484 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4485 * and total blanking time, however the resulting values are the same as 4486 * the TM070JDHG34-00. 4487 */ 4488 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4489 .pixelclock = { 68400000, 71900000, 78100000 }, 4490 .hactive = { 1280, 1280, 1280 }, 4491 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4492 .hback_porch = { 5, 5, 5 }, 4493 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4494 .vactive = { 800, 800, 800 }, 4495 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4496 .vback_porch = { 2, 2, 2 }, 4497 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4498 .flags = DISPLAY_FLAGS_DE_HIGH, 4499 }; 4500 4501 static const struct panel_desc tianma_tm070jdhg34_00 = { 4502 .timings = &tianma_tm070jdhg34_00_timing, 4503 .num_timings = 1, 4504 .bpc = 8, 4505 .size = { 4506 .width = 150, /* 149.76 */ 4507 .height = 94, /* 93.60 */ 4508 }, 4509 .delay = { 4510 .prepare = 15, /* Tp1 */ 4511 .enable = 150, /* Tp2 */ 4512 .disable = 150, /* Tp4 */ 4513 .unprepare = 120, /* Tp3 */ 4514 }, 4515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4516 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4517 }; 4518 4519 static const struct panel_desc tianma_p0700wxf1mbaa = { 4520 .timings = &tianma_tm070jdhg34_00_timing, 4521 .num_timings = 1, 4522 .bpc = 8, 4523 .size = { 4524 .width = 150, /* 149.76 */ 4525 .height = 94, /* 93.60 */ 4526 }, 4527 .delay = { 4528 .prepare = 18, /* Tr + Tp1 */ 4529 .enable = 152, /* Tp2 + Tp5 */ 4530 .disable = 152, /* Tp6 + Tp4 */ 4531 .unprepare = 120, /* Tp3 */ 4532 }, 4533 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4535 }; 4536 4537 static const struct display_timing tianma_tm070rvhg71_timing = { 4538 .pixelclock = { 27700000, 29200000, 39600000 }, 4539 .hactive = { 800, 800, 800 }, 4540 .hfront_porch = { 12, 40, 212 }, 4541 .hback_porch = { 88, 88, 88 }, 4542 .hsync_len = { 1, 1, 40 }, 4543 .vactive = { 480, 480, 480 }, 4544 .vfront_porch = { 1, 13, 88 }, 4545 .vback_porch = { 32, 32, 32 }, 4546 .vsync_len = { 1, 1, 3 }, 4547 .flags = DISPLAY_FLAGS_DE_HIGH, 4548 }; 4549 4550 static const struct panel_desc tianma_tm070rvhg71 = { 4551 .timings = &tianma_tm070rvhg71_timing, 4552 .num_timings = 1, 4553 .bpc = 8, 4554 .size = { 4555 .width = 154, 4556 .height = 86, 4557 }, 4558 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4559 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4560 }; 4561 4562 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4563 { 4564 .clock = 10000, 4565 .hdisplay = 320, 4566 .hsync_start = 320 + 50, 4567 .hsync_end = 320 + 50 + 6, 4568 .htotal = 320 + 50 + 6 + 38, 4569 .vdisplay = 240, 4570 .vsync_start = 240 + 3, 4571 .vsync_end = 240 + 3 + 1, 4572 .vtotal = 240 + 3 + 1 + 17, 4573 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4574 }, 4575 }; 4576 4577 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4578 .modes = ti_nspire_cx_lcd_mode, 4579 .num_modes = 1, 4580 .bpc = 8, 4581 .size = { 4582 .width = 65, 4583 .height = 49, 4584 }, 4585 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4586 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4587 }; 4588 4589 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4590 { 4591 .clock = 10000, 4592 .hdisplay = 320, 4593 .hsync_start = 320 + 6, 4594 .hsync_end = 320 + 6 + 6, 4595 .htotal = 320 + 6 + 6 + 6, 4596 .vdisplay = 240, 4597 .vsync_start = 240 + 0, 4598 .vsync_end = 240 + 0 + 1, 4599 .vtotal = 240 + 0 + 1 + 0, 4600 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4601 }, 4602 }; 4603 4604 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4605 .modes = ti_nspire_classic_lcd_mode, 4606 .num_modes = 1, 4607 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4608 .bpc = 8, 4609 .size = { 4610 .width = 71, 4611 .height = 53, 4612 }, 4613 /* This is the grayscale bus format */ 4614 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4615 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4616 }; 4617 4618 static const struct display_timing topland_tian_g07017_01_timing = { 4619 .pixelclock = { 44900000, 51200000, 63000000 }, 4620 .hactive = { 1024, 1024, 1024 }, 4621 .hfront_porch = { 16, 160, 216 }, 4622 .hback_porch = { 160, 160, 160 }, 4623 .hsync_len = { 1, 1, 140 }, 4624 .vactive = { 600, 600, 600 }, 4625 .vfront_porch = { 1, 12, 127 }, 4626 .vback_porch = { 23, 23, 23 }, 4627 .vsync_len = { 1, 1, 20 }, 4628 }; 4629 4630 static const struct panel_desc topland_tian_g07017_01 = { 4631 .timings = &topland_tian_g07017_01_timing, 4632 .num_timings = 1, 4633 .bpc = 8, 4634 .size = { 4635 .width = 154, 4636 .height = 86, 4637 }, 4638 .delay = { 4639 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4640 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4641 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4642 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4643 }, 4644 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4645 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4646 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4647 }; 4648 4649 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4650 .clock = 79500, 4651 .hdisplay = 1280, 4652 .hsync_start = 1280 + 192, 4653 .hsync_end = 1280 + 192 + 128, 4654 .htotal = 1280 + 192 + 128 + 64, 4655 .vdisplay = 768, 4656 .vsync_start = 768 + 20, 4657 .vsync_end = 768 + 20 + 7, 4658 .vtotal = 768 + 20 + 7 + 3, 4659 }; 4660 4661 static const struct panel_desc toshiba_lt089ac29000 = { 4662 .modes = &toshiba_lt089ac29000_mode, 4663 .num_modes = 1, 4664 .size = { 4665 .width = 194, 4666 .height = 116, 4667 }, 4668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4669 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4670 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4671 }; 4672 4673 static const struct drm_display_mode tpk_f07a_0102_mode = { 4674 .clock = 33260, 4675 .hdisplay = 800, 4676 .hsync_start = 800 + 40, 4677 .hsync_end = 800 + 40 + 128, 4678 .htotal = 800 + 40 + 128 + 88, 4679 .vdisplay = 480, 4680 .vsync_start = 480 + 10, 4681 .vsync_end = 480 + 10 + 2, 4682 .vtotal = 480 + 10 + 2 + 33, 4683 }; 4684 4685 static const struct panel_desc tpk_f07a_0102 = { 4686 .modes = &tpk_f07a_0102_mode, 4687 .num_modes = 1, 4688 .size = { 4689 .width = 152, 4690 .height = 91, 4691 }, 4692 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4693 }; 4694 4695 static const struct drm_display_mode tpk_f10a_0102_mode = { 4696 .clock = 45000, 4697 .hdisplay = 1024, 4698 .hsync_start = 1024 + 176, 4699 .hsync_end = 1024 + 176 + 5, 4700 .htotal = 1024 + 176 + 5 + 88, 4701 .vdisplay = 600, 4702 .vsync_start = 600 + 20, 4703 .vsync_end = 600 + 20 + 5, 4704 .vtotal = 600 + 20 + 5 + 25, 4705 }; 4706 4707 static const struct panel_desc tpk_f10a_0102 = { 4708 .modes = &tpk_f10a_0102_mode, 4709 .num_modes = 1, 4710 .size = { 4711 .width = 223, 4712 .height = 125, 4713 }, 4714 }; 4715 4716 static const struct display_timing urt_umsh_8596md_timing = { 4717 .pixelclock = { 33260000, 33260000, 33260000 }, 4718 .hactive = { 800, 800, 800 }, 4719 .hfront_porch = { 41, 41, 41 }, 4720 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4721 .hsync_len = { 71, 128, 128 }, 4722 .vactive = { 480, 480, 480 }, 4723 .vfront_porch = { 10, 10, 10 }, 4724 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4725 .vsync_len = { 2, 2, 2 }, 4726 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4727 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4728 }; 4729 4730 static const struct panel_desc urt_umsh_8596md_lvds = { 4731 .timings = &urt_umsh_8596md_timing, 4732 .num_timings = 1, 4733 .bpc = 6, 4734 .size = { 4735 .width = 152, 4736 .height = 91, 4737 }, 4738 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4739 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4740 }; 4741 4742 static const struct panel_desc urt_umsh_8596md_parallel = { 4743 .timings = &urt_umsh_8596md_timing, 4744 .num_timings = 1, 4745 .bpc = 6, 4746 .size = { 4747 .width = 152, 4748 .height = 91, 4749 }, 4750 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4751 }; 4752 4753 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4754 .clock = 60000, 4755 .hdisplay = 1024, 4756 .hsync_start = 1024 + 160, 4757 .hsync_end = 1024 + 160 + 100, 4758 .htotal = 1024 + 160 + 100 + 60, 4759 .vdisplay = 600, 4760 .vsync_start = 600 + 12, 4761 .vsync_end = 600 + 12 + 10, 4762 .vtotal = 600 + 12 + 10 + 13, 4763 }; 4764 4765 static const struct panel_desc vivax_tpc9150_panel = { 4766 .modes = &vivax_tpc9150_panel_mode, 4767 .num_modes = 1, 4768 .bpc = 6, 4769 .size = { 4770 .width = 200, 4771 .height = 115, 4772 }, 4773 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4774 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4775 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4776 }; 4777 4778 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4779 .clock = 33333, 4780 .hdisplay = 800, 4781 .hsync_start = 800 + 210, 4782 .hsync_end = 800 + 210 + 20, 4783 .htotal = 800 + 210 + 20 + 46, 4784 .vdisplay = 480, 4785 .vsync_start = 480 + 22, 4786 .vsync_end = 480 + 22 + 10, 4787 .vtotal = 480 + 22 + 10 + 23, 4788 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4789 }; 4790 4791 static const struct panel_desc vl050_8048nt_c01 = { 4792 .modes = &vl050_8048nt_c01_mode, 4793 .num_modes = 1, 4794 .bpc = 8, 4795 .size = { 4796 .width = 120, 4797 .height = 76, 4798 }, 4799 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4800 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4801 }; 4802 4803 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4804 .clock = 6410, 4805 .hdisplay = 320, 4806 .hsync_start = 320 + 20, 4807 .hsync_end = 320 + 20 + 30, 4808 .htotal = 320 + 20 + 30 + 38, 4809 .vdisplay = 240, 4810 .vsync_start = 240 + 4, 4811 .vsync_end = 240 + 4 + 3, 4812 .vtotal = 240 + 4 + 3 + 15, 4813 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4814 }; 4815 4816 static const struct panel_desc winstar_wf35ltiacd = { 4817 .modes = &winstar_wf35ltiacd_mode, 4818 .num_modes = 1, 4819 .bpc = 8, 4820 .size = { 4821 .width = 70, 4822 .height = 53, 4823 }, 4824 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4825 }; 4826 4827 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4828 .clock = 51200, 4829 .hdisplay = 1024, 4830 .hsync_start = 1024 + 100, 4831 .hsync_end = 1024 + 100 + 100, 4832 .htotal = 1024 + 100 + 100 + 120, 4833 .vdisplay = 600, 4834 .vsync_start = 600 + 10, 4835 .vsync_end = 600 + 10 + 10, 4836 .vtotal = 600 + 10 + 10 + 15, 4837 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4838 }; 4839 4840 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4841 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4842 .num_modes = 1, 4843 .bpc = 8, 4844 .size = { 4845 .width = 154, 4846 .height = 90, 4847 }, 4848 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4849 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4850 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4851 }; 4852 4853 static const struct drm_display_mode mchp_ac69t88a_mode = { 4854 .clock = 25000, 4855 .hdisplay = 800, 4856 .hsync_start = 800 + 88, 4857 .hsync_end = 800 + 88 + 5, 4858 .htotal = 800 + 88 + 5 + 40, 4859 .vdisplay = 480, 4860 .vsync_start = 480 + 23, 4861 .vsync_end = 480 + 23 + 5, 4862 .vtotal = 480 + 23 + 5 + 1, 4863 }; 4864 4865 static const struct panel_desc mchp_ac69t88a = { 4866 .modes = &mchp_ac69t88a_mode, 4867 .num_modes = 1, 4868 .bpc = 8, 4869 .size = { 4870 .width = 108, 4871 .height = 65, 4872 }, 4873 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4874 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4875 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4876 }; 4877 4878 static const struct drm_display_mode arm_rtsm_mode[] = { 4879 { 4880 .clock = 65000, 4881 .hdisplay = 1024, 4882 .hsync_start = 1024 + 24, 4883 .hsync_end = 1024 + 24 + 136, 4884 .htotal = 1024 + 24 + 136 + 160, 4885 .vdisplay = 768, 4886 .vsync_start = 768 + 3, 4887 .vsync_end = 768 + 3 + 6, 4888 .vtotal = 768 + 3 + 6 + 29, 4889 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4890 }, 4891 }; 4892 4893 static const struct panel_desc arm_rtsm = { 4894 .modes = arm_rtsm_mode, 4895 .num_modes = 1, 4896 .bpc = 8, 4897 .size = { 4898 .width = 400, 4899 .height = 300, 4900 }, 4901 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4902 }; 4903 4904 static const struct of_device_id platform_of_match[] = { 4905 { 4906 .compatible = "ampire,am-1280800n3tzqw-t00h", 4907 .data = &ire_am_1280800n3tzqw_t00h, 4908 }, { 4909 .compatible = "ampire,am-480272h3tmqw-t01h", 4910 .data = &ire_am_480272h3tmqw_t01h, 4911 }, { 4912 .compatible = "ampire,am-800480l1tmqw-t00h", 4913 .data = &ire_am_800480l1tmqw_t00h, 4914 }, { 4915 .compatible = "ampire,am800480r3tmqwa1h", 4916 .data = &ire_am800480r3tmqwa1h, 4917 }, { 4918 .compatible = "ampire,am800600p5tmqw-tb8h", 4919 .data = &ire_am800600p5tmqwtb8h, 4920 }, { 4921 .compatible = "arm,rtsm-display", 4922 .data = &arm_rtsm, 4923 }, { 4924 .compatible = "armadeus,st0700-adapt", 4925 .data = &armadeus_st0700_adapt, 4926 }, { 4927 .compatible = "auo,b101aw03", 4928 .data = &auo_b101aw03, 4929 }, { 4930 .compatible = "auo,b101xtn01", 4931 .data = &auo_b101xtn01, 4932 }, { 4933 .compatible = "auo,b116xw03", 4934 .data = &auo_b116xw03, 4935 }, { 4936 .compatible = "auo,g070vvn01", 4937 .data = &auo_g070vvn01, 4938 }, { 4939 .compatible = "auo,g101evn010", 4940 .data = &auo_g101evn010, 4941 }, { 4942 .compatible = "auo,g104sn02", 4943 .data = &auo_g104sn02, 4944 }, { 4945 .compatible = "auo,g104stn01", 4946 .data = &auo_g104stn01, 4947 }, { 4948 .compatible = "auo,g121ean01", 4949 .data = &auo_g121ean01, 4950 }, { 4951 .compatible = "auo,g133han01", 4952 .data = &auo_g133han01, 4953 }, { 4954 .compatible = "auo,g156han04", 4955 .data = &auo_g156han04, 4956 }, { 4957 .compatible = "auo,g156xtn01", 4958 .data = &auo_g156xtn01, 4959 }, { 4960 .compatible = "auo,g185han01", 4961 .data = &auo_g185han01, 4962 }, { 4963 .compatible = "auo,g190ean01", 4964 .data = &auo_g190ean01, 4965 }, { 4966 .compatible = "auo,p238han01", 4967 .data = &auo_p238han01, 4968 }, { 4969 .compatible = "auo,p320hvn03", 4970 .data = &auo_p320hvn03, 4971 }, { 4972 .compatible = "auo,t215hvn01", 4973 .data = &auo_t215hvn01, 4974 }, { 4975 .compatible = "avic,tm070ddh03", 4976 .data = &avic_tm070ddh03, 4977 }, { 4978 .compatible = "bananapi,s070wv20-ct16", 4979 .data = &bananapi_s070wv20_ct16, 4980 }, { 4981 .compatible = "boe,av101hdt-a10", 4982 .data = &boe_av101hdt_a10, 4983 }, { 4984 .compatible = "boe,av123z7m-n17", 4985 .data = &boe_av123z7m_n17, 4986 }, { 4987 .compatible = "boe,bp082wx1-100", 4988 .data = &boe_bp082wx1_100, 4989 }, { 4990 .compatible = "boe,bp101wx1-100", 4991 .data = &boe_bp101wx1_100, 4992 }, { 4993 .compatible = "boe,ev121wxm-n10-1850", 4994 .data = &boe_ev121wxm_n10_1850, 4995 }, { 4996 .compatible = "boe,hv070wsa-100", 4997 .data = &boe_hv070wsa 4998 }, { 4999 .compatible = "cct,cmt430b19n00", 5000 .data = &cct_cmt430b19n00, 5001 }, { 5002 .compatible = "cdtech,s043wq26h-ct7", 5003 .data = &cdtech_s043wq26h_ct7, 5004 }, { 5005 .compatible = "cdtech,s070pws19hp-fc21", 5006 .data = &cdtech_s070pws19hp_fc21, 5007 }, { 5008 .compatible = "cdtech,s070swv29hg-dc44", 5009 .data = &cdtech_s070swv29hg_dc44, 5010 }, { 5011 .compatible = "cdtech,s070wv95-ct16", 5012 .data = &cdtech_s070wv95_ct16, 5013 }, { 5014 .compatible = "chefree,ch101olhlwh-002", 5015 .data = &chefree_ch101olhlwh_002, 5016 }, { 5017 .compatible = "chunghwa,claa070wp03xg", 5018 .data = &chunghwa_claa070wp03xg, 5019 }, { 5020 .compatible = "chunghwa,claa101wa01a", 5021 .data = &chunghwa_claa101wa01a 5022 }, { 5023 .compatible = "chunghwa,claa101wb01", 5024 .data = &chunghwa_claa101wb01 5025 }, { 5026 .compatible = "dataimage,fg040346dsswbg04", 5027 .data = &dataimage_fg040346dsswbg04, 5028 }, { 5029 .compatible = "dataimage,fg1001l0dsswmg01", 5030 .data = &dataimage_fg1001l0dsswmg01, 5031 }, { 5032 .compatible = "dataimage,scf0700c48ggu18", 5033 .data = &dataimage_scf0700c48ggu18, 5034 }, { 5035 .compatible = "dlc,dlc0700yzg-1", 5036 .data = &dlc_dlc0700yzg_1, 5037 }, { 5038 .compatible = "dlc,dlc1010gig", 5039 .data = &dlc_dlc1010gig, 5040 }, { 5041 .compatible = "edt,et035012dm6", 5042 .data = &edt_et035012dm6, 5043 }, { 5044 .compatible = "edt,etm0350g0dh6", 5045 .data = &edt_etm0350g0dh6, 5046 }, { 5047 .compatible = "edt,etm043080dh6gp", 5048 .data = &edt_etm043080dh6gp, 5049 }, { 5050 .compatible = "edt,etm0430g0dh6", 5051 .data = &edt_etm0430g0dh6, 5052 }, { 5053 .compatible = "edt,et057090dhu", 5054 .data = &edt_et057090dhu, 5055 }, { 5056 .compatible = "edt,et070080dh6", 5057 .data = &edt_etm0700g0dh6, 5058 }, { 5059 .compatible = "edt,etm0700g0dh6", 5060 .data = &edt_etm0700g0dh6, 5061 }, { 5062 .compatible = "edt,etm0700g0bdh6", 5063 .data = &edt_etm0700g0bdh6, 5064 }, { 5065 .compatible = "edt,etm0700g0edh6", 5066 .data = &edt_etm0700g0bdh6, 5067 }, { 5068 .compatible = "edt,etml0700y5dha", 5069 .data = &edt_etml0700y5dha, 5070 }, { 5071 .compatible = "edt,etml1010g3dra", 5072 .data = &edt_etml1010g3dra, 5073 }, { 5074 .compatible = "edt,etmv570g2dhu", 5075 .data = &edt_etmv570g2dhu, 5076 }, { 5077 .compatible = "eink,vb3300-kca", 5078 .data = &eink_vb3300_kca, 5079 }, { 5080 .compatible = "evervision,vgg644804", 5081 .data = &evervision_vgg644804, 5082 }, { 5083 .compatible = "evervision,vgg804821", 5084 .data = &evervision_vgg804821, 5085 }, { 5086 .compatible = "foxlink,fl500wvr00-a0t", 5087 .data = &foxlink_fl500wvr00_a0t, 5088 }, { 5089 .compatible = "frida,frd350h54004", 5090 .data = &frida_frd350h54004, 5091 }, { 5092 .compatible = "friendlyarm,hd702e", 5093 .data = &friendlyarm_hd702e, 5094 }, { 5095 .compatible = "giantplus,gpg482739qs5", 5096 .data = &giantplus_gpg482739qs5 5097 }, { 5098 .compatible = "giantplus,gpm940b0", 5099 .data = &giantplus_gpm940b0, 5100 }, { 5101 .compatible = "hannstar,hsd070pww1", 5102 .data = &hannstar_hsd070pww1, 5103 }, { 5104 .compatible = "hannstar,hsd100pxn1", 5105 .data = &hannstar_hsd100pxn1, 5106 }, { 5107 .compatible = "hannstar,hsd101pww2", 5108 .data = &hannstar_hsd101pww2, 5109 }, { 5110 .compatible = "hit,tx23d38vm0caa", 5111 .data = &hitachi_tx23d38vm0caa 5112 }, { 5113 .compatible = "innolux,at043tn24", 5114 .data = &innolux_at043tn24, 5115 }, { 5116 .compatible = "innolux,at070tn92", 5117 .data = &innolux_at070tn92, 5118 }, { 5119 .compatible = "innolux,g070ace-l01", 5120 .data = &innolux_g070ace_l01, 5121 }, { 5122 .compatible = "innolux,g070ace-lh3", 5123 .data = &innolux_g070ace_lh3, 5124 }, { 5125 .compatible = "innolux,g070y2-l01", 5126 .data = &innolux_g070y2_l01, 5127 }, { 5128 .compatible = "innolux,g070y2-t02", 5129 .data = &innolux_g070y2_t02, 5130 }, { 5131 .compatible = "innolux,g101ice-l01", 5132 .data = &innolux_g101ice_l01 5133 }, { 5134 .compatible = "innolux,g121i1-l01", 5135 .data = &innolux_g121i1_l01 5136 }, { 5137 .compatible = "innolux,g121x1-l03", 5138 .data = &innolux_g121x1_l03, 5139 }, { 5140 .compatible = "innolux,g121xce-l01", 5141 .data = &innolux_g121xce_l01, 5142 }, { 5143 .compatible = "innolux,g156hce-l01", 5144 .data = &innolux_g156hce_l01, 5145 }, { 5146 .compatible = "innolux,n156bge-l21", 5147 .data = &innolux_n156bge_l21, 5148 }, { 5149 .compatible = "innolux,zj070na-01p", 5150 .data = &innolux_zj070na_01p, 5151 }, { 5152 .compatible = "koe,tx14d24vm1bpa", 5153 .data = &koe_tx14d24vm1bpa, 5154 }, { 5155 .compatible = "koe,tx26d202vm0bwa", 5156 .data = &koe_tx26d202vm0bwa, 5157 }, { 5158 .compatible = "koe,tx31d200vm0baa", 5159 .data = &koe_tx31d200vm0baa, 5160 }, { 5161 .compatible = "kyo,tcg121xglp", 5162 .data = &kyo_tcg121xglp, 5163 }, { 5164 .compatible = "lemaker,bl035-rgb-002", 5165 .data = &lemaker_bl035_rgb_002, 5166 }, { 5167 .compatible = "lg,lb070wv8", 5168 .data = &lg_lb070wv8, 5169 }, { 5170 .compatible = "lincolntech,lcd185-101ct", 5171 .data = &lincolntech_lcd185_101ct, 5172 }, { 5173 .compatible = "logicpd,type28", 5174 .data = &logicpd_type_28, 5175 }, { 5176 .compatible = "logictechno,lt161010-2nhc", 5177 .data = &logictechno_lt161010_2nh, 5178 }, { 5179 .compatible = "logictechno,lt161010-2nhr", 5180 .data = &logictechno_lt161010_2nh, 5181 }, { 5182 .compatible = "logictechno,lt170410-2whc", 5183 .data = &logictechno_lt170410_2whc, 5184 }, { 5185 .compatible = "logictechno,lttd800480070-l2rt", 5186 .data = &logictechno_lttd800480070_l2rt, 5187 }, { 5188 .compatible = "logictechno,lttd800480070-l6wh-rt", 5189 .data = &logictechno_lttd800480070_l6wh_rt, 5190 }, { 5191 .compatible = "microtips,mf-101hiebcaf0", 5192 .data = µtips_mf_101hiebcaf0_c, 5193 }, { 5194 .compatible = "microtips,mf-103hieb0ga0", 5195 .data = µtips_mf_103hieb0ga0, 5196 }, { 5197 .compatible = "mitsubishi,aa070mc01-ca1", 5198 .data = &mitsubishi_aa070mc01, 5199 }, { 5200 .compatible = "mitsubishi,aa084xe01", 5201 .data = &mitsubishi_aa084xe01, 5202 }, { 5203 .compatible = "multi-inno,mi0700a2t-30", 5204 .data = &multi_inno_mi0700a2t_30, 5205 }, { 5206 .compatible = "multi-inno,mi0700s4t-6", 5207 .data = &multi_inno_mi0700s4t_6, 5208 }, { 5209 .compatible = "multi-inno,mi0800ft-9", 5210 .data = &multi_inno_mi0800ft_9, 5211 }, { 5212 .compatible = "multi-inno,mi1010ait-1cp", 5213 .data = &multi_inno_mi1010ait_1cp, 5214 }, { 5215 .compatible = "multi-inno,mi1010z1t-1cp11", 5216 .data = &multi_inno_mi1010z1t_1cp11, 5217 }, { 5218 .compatible = "nec,nl12880bc20-05", 5219 .data = &nec_nl12880bc20_05, 5220 }, { 5221 .compatible = "nec,nl4827hc19-05b", 5222 .data = &nec_nl4827hc19_05b, 5223 }, { 5224 .compatible = "netron-dy,e231732", 5225 .data = &netron_dy_e231732, 5226 }, { 5227 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5228 .data = &newhaven_nhd_43_480272ef_atxl, 5229 }, { 5230 .compatible = "nlt,nl13676bc25-03f", 5231 .data = &nlt_nl13676bc25_03f, 5232 }, { 5233 .compatible = "nlt,nl192108ac18-02d", 5234 .data = &nlt_nl192108ac18_02d, 5235 }, { 5236 .compatible = "nvd,9128", 5237 .data = &nvd_9128, 5238 }, { 5239 .compatible = "okaya,rs800480t-7x0gp", 5240 .data = &okaya_rs800480t_7x0gp, 5241 }, { 5242 .compatible = "olimex,lcd-olinuxino-43-ts", 5243 .data = &olimex_lcd_olinuxino_43ts, 5244 }, { 5245 .compatible = "ontat,kd50g21-40nt-a1", 5246 .data = &ontat_kd50g21_40nt_a1, 5247 }, { 5248 .compatible = "ontat,yx700wv03", 5249 .data = &ontat_yx700wv03, 5250 }, { 5251 .compatible = "ortustech,com37h3m05dtc", 5252 .data = &ortustech_com37h3m, 5253 }, { 5254 .compatible = "ortustech,com37h3m99dtc", 5255 .data = &ortustech_com37h3m, 5256 }, { 5257 .compatible = "ortustech,com43h4m85ulc", 5258 .data = &ortustech_com43h4m85ulc, 5259 }, { 5260 .compatible = "osddisplays,osd070t1718-19ts", 5261 .data = &osddisplays_osd070t1718_19ts, 5262 }, { 5263 .compatible = "pda,91-00156-a0", 5264 .data = &pda_91_00156_a0, 5265 }, { 5266 .compatible = "powertip,ph128800t004-zza01", 5267 .data = &powertip_ph128800t004_zza01, 5268 }, { 5269 .compatible = "powertip,ph128800t006-zhc01", 5270 .data = &powertip_ph128800t006_zhc01, 5271 }, { 5272 .compatible = "powertip,ph800480t013-idf02", 5273 .data = &powertip_ph800480t013_idf02, 5274 }, { 5275 .compatible = "primeview,pm070wl4", 5276 .data = &primeview_pm070wl4, 5277 }, { 5278 .compatible = "qiaodian,qd43003c0-40", 5279 .data = &qd43003c0_40, 5280 }, { 5281 .compatible = "qishenglong,gopher2b-lcd", 5282 .data = &qishenglong_gopher2b_lcd, 5283 }, { 5284 .compatible = "rocktech,rk043fn48h", 5285 .data = &rocktech_rk043fn48h, 5286 }, { 5287 .compatible = "rocktech,rk070er9427", 5288 .data = &rocktech_rk070er9427, 5289 }, { 5290 .compatible = "rocktech,rk101ii01d-ct", 5291 .data = &rocktech_rk101ii01d_ct, 5292 }, { 5293 .compatible = "samsung,ltl101al01", 5294 .data = &samsung_ltl101al01, 5295 }, { 5296 .compatible = "samsung,ltn101nt05", 5297 .data = &samsung_ltn101nt05, 5298 }, { 5299 .compatible = "satoz,sat050at40h12r2", 5300 .data = &satoz_sat050at40h12r2, 5301 }, { 5302 .compatible = "sharp,lq035q7db03", 5303 .data = &sharp_lq035q7db03, 5304 }, { 5305 .compatible = "sharp,lq070y3dg3b", 5306 .data = &sharp_lq070y3dg3b, 5307 }, { 5308 .compatible = "sharp,lq101k1ly04", 5309 .data = &sharp_lq101k1ly04, 5310 }, { 5311 .compatible = "sharp,ls020b1dd01d", 5312 .data = &sharp_ls020b1dd01d, 5313 }, { 5314 .compatible = "shelly,sca07010-bfn-lnn", 5315 .data = &shelly_sca07010_bfn_lnn, 5316 }, { 5317 .compatible = "starry,kr070pe2t", 5318 .data = &starry_kr070pe2t, 5319 }, { 5320 .compatible = "startek,kd070wvfpa", 5321 .data = &startek_kd070wvfpa, 5322 }, { 5323 .compatible = "team-source-display,tst043015cmhx", 5324 .data = &tsd_tst043015cmhx, 5325 }, { 5326 .compatible = "tfc,s9700rtwv43tr-01b", 5327 .data = &tfc_s9700rtwv43tr_01b, 5328 }, { 5329 .compatible = "tianma,p0700wxf1mbaa", 5330 .data = &tianma_p0700wxf1mbaa, 5331 }, { 5332 .compatible = "tianma,tm070jdhg30", 5333 .data = &tianma_tm070jdhg30, 5334 }, { 5335 .compatible = "tianma,tm070jdhg34-00", 5336 .data = &tianma_tm070jdhg34_00, 5337 }, { 5338 .compatible = "tianma,tm070jvhg33", 5339 .data = &tianma_tm070jvhg33, 5340 }, { 5341 .compatible = "tianma,tm070rvhg71", 5342 .data = &tianma_tm070rvhg71, 5343 }, { 5344 .compatible = "ti,nspire-cx-lcd-panel", 5345 .data = &ti_nspire_cx_lcd_panel, 5346 }, { 5347 .compatible = "ti,nspire-classic-lcd-panel", 5348 .data = &ti_nspire_classic_lcd_panel, 5349 }, { 5350 .compatible = "toshiba,lt089ac29000", 5351 .data = &toshiba_lt089ac29000, 5352 }, { 5353 .compatible = "topland,tian-g07017-01", 5354 .data = &topland_tian_g07017_01, 5355 }, { 5356 .compatible = "tpk,f07a-0102", 5357 .data = &tpk_f07a_0102, 5358 }, { 5359 .compatible = "tpk,f10a-0102", 5360 .data = &tpk_f10a_0102, 5361 }, { 5362 .compatible = "urt,umsh-8596md-t", 5363 .data = &urt_umsh_8596md_parallel, 5364 }, { 5365 .compatible = "urt,umsh-8596md-1t", 5366 .data = &urt_umsh_8596md_parallel, 5367 }, { 5368 .compatible = "urt,umsh-8596md-7t", 5369 .data = &urt_umsh_8596md_parallel, 5370 }, { 5371 .compatible = "urt,umsh-8596md-11t", 5372 .data = &urt_umsh_8596md_lvds, 5373 }, { 5374 .compatible = "urt,umsh-8596md-19t", 5375 .data = &urt_umsh_8596md_lvds, 5376 }, { 5377 .compatible = "urt,umsh-8596md-20t", 5378 .data = &urt_umsh_8596md_parallel, 5379 }, { 5380 .compatible = "vivax,tpc9150-panel", 5381 .data = &vivax_tpc9150_panel, 5382 }, { 5383 .compatible = "vxt,vl050-8048nt-c01", 5384 .data = &vl050_8048nt_c01, 5385 }, { 5386 .compatible = "winstar,wf35ltiacd", 5387 .data = &winstar_wf35ltiacd, 5388 }, { 5389 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5390 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5391 }, { 5392 .compatible = "microchip,ac69t88a", 5393 .data = &mchp_ac69t88a, 5394 }, { 5395 /* Must be the last entry */ 5396 .compatible = "panel-dpi", 5397 .data = &panel_dpi, 5398 }, { 5399 /* sentinel */ 5400 } 5401 }; 5402 MODULE_DEVICE_TABLE(of, platform_of_match); 5403 5404 static int panel_simple_platform_probe(struct platform_device *pdev) 5405 { 5406 const struct panel_desc *desc; 5407 5408 desc = of_device_get_match_data(&pdev->dev); 5409 if (!desc) 5410 return -ENODEV; 5411 5412 return panel_simple_probe(&pdev->dev, desc); 5413 } 5414 5415 static void panel_simple_platform_remove(struct platform_device *pdev) 5416 { 5417 panel_simple_remove(&pdev->dev); 5418 } 5419 5420 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5421 { 5422 panel_simple_shutdown(&pdev->dev); 5423 } 5424 5425 static const struct dev_pm_ops panel_simple_pm_ops = { 5426 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5427 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5428 pm_runtime_force_resume) 5429 }; 5430 5431 static struct platform_driver panel_simple_platform_driver = { 5432 .driver = { 5433 .name = "panel-simple", 5434 .of_match_table = platform_of_match, 5435 .pm = &panel_simple_pm_ops, 5436 }, 5437 .probe = panel_simple_platform_probe, 5438 .remove = panel_simple_platform_remove, 5439 .shutdown = panel_simple_platform_shutdown, 5440 }; 5441 5442 struct panel_desc_dsi { 5443 struct panel_desc desc; 5444 5445 unsigned long flags; 5446 enum mipi_dsi_pixel_format format; 5447 unsigned int lanes; 5448 }; 5449 5450 static const struct drm_display_mode auo_b080uan01_mode = { 5451 .clock = 154500, 5452 .hdisplay = 1200, 5453 .hsync_start = 1200 + 62, 5454 .hsync_end = 1200 + 62 + 4, 5455 .htotal = 1200 + 62 + 4 + 62, 5456 .vdisplay = 1920, 5457 .vsync_start = 1920 + 9, 5458 .vsync_end = 1920 + 9 + 2, 5459 .vtotal = 1920 + 9 + 2 + 8, 5460 }; 5461 5462 static const struct panel_desc_dsi auo_b080uan01 = { 5463 .desc = { 5464 .modes = &auo_b080uan01_mode, 5465 .num_modes = 1, 5466 .bpc = 8, 5467 .size = { 5468 .width = 108, 5469 .height = 272, 5470 }, 5471 .connector_type = DRM_MODE_CONNECTOR_DSI, 5472 }, 5473 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5474 .format = MIPI_DSI_FMT_RGB888, 5475 .lanes = 4, 5476 }; 5477 5478 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5479 .clock = 160000, 5480 .hdisplay = 1200, 5481 .hsync_start = 1200 + 120, 5482 .hsync_end = 1200 + 120 + 20, 5483 .htotal = 1200 + 120 + 20 + 21, 5484 .vdisplay = 1920, 5485 .vsync_start = 1920 + 21, 5486 .vsync_end = 1920 + 21 + 3, 5487 .vtotal = 1920 + 21 + 3 + 18, 5488 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5489 }; 5490 5491 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5492 .desc = { 5493 .modes = &boe_tv080wum_nl0_mode, 5494 .num_modes = 1, 5495 .size = { 5496 .width = 107, 5497 .height = 172, 5498 }, 5499 .connector_type = DRM_MODE_CONNECTOR_DSI, 5500 }, 5501 .flags = MIPI_DSI_MODE_VIDEO | 5502 MIPI_DSI_MODE_VIDEO_BURST | 5503 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5504 .format = MIPI_DSI_FMT_RGB888, 5505 .lanes = 4, 5506 }; 5507 5508 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5509 .clock = 71000, 5510 .hdisplay = 800, 5511 .hsync_start = 800 + 32, 5512 .hsync_end = 800 + 32 + 1, 5513 .htotal = 800 + 32 + 1 + 57, 5514 .vdisplay = 1280, 5515 .vsync_start = 1280 + 28, 5516 .vsync_end = 1280 + 28 + 1, 5517 .vtotal = 1280 + 28 + 1 + 14, 5518 }; 5519 5520 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5521 .desc = { 5522 .modes = &lg_ld070wx3_sl01_mode, 5523 .num_modes = 1, 5524 .bpc = 8, 5525 .size = { 5526 .width = 94, 5527 .height = 151, 5528 }, 5529 .connector_type = DRM_MODE_CONNECTOR_DSI, 5530 }, 5531 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5532 .format = MIPI_DSI_FMT_RGB888, 5533 .lanes = 4, 5534 }; 5535 5536 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5537 .clock = 67000, 5538 .hdisplay = 720, 5539 .hsync_start = 720 + 12, 5540 .hsync_end = 720 + 12 + 4, 5541 .htotal = 720 + 12 + 4 + 112, 5542 .vdisplay = 1280, 5543 .vsync_start = 1280 + 8, 5544 .vsync_end = 1280 + 8 + 4, 5545 .vtotal = 1280 + 8 + 4 + 12, 5546 }; 5547 5548 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5549 .desc = { 5550 .modes = &lg_lh500wx1_sd03_mode, 5551 .num_modes = 1, 5552 .bpc = 8, 5553 .size = { 5554 .width = 62, 5555 .height = 110, 5556 }, 5557 .connector_type = DRM_MODE_CONNECTOR_DSI, 5558 }, 5559 .flags = MIPI_DSI_MODE_VIDEO, 5560 .format = MIPI_DSI_FMT_RGB888, 5561 .lanes = 4, 5562 }; 5563 5564 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5565 .clock = 157200, 5566 .hdisplay = 1920, 5567 .hsync_start = 1920 + 154, 5568 .hsync_end = 1920 + 154 + 16, 5569 .htotal = 1920 + 154 + 16 + 32, 5570 .vdisplay = 1200, 5571 .vsync_start = 1200 + 17, 5572 .vsync_end = 1200 + 17 + 2, 5573 .vtotal = 1200 + 17 + 2 + 16, 5574 }; 5575 5576 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5577 .desc = { 5578 .modes = &panasonic_vvx10f004b00_mode, 5579 .num_modes = 1, 5580 .bpc = 8, 5581 .size = { 5582 .width = 217, 5583 .height = 136, 5584 }, 5585 .connector_type = DRM_MODE_CONNECTOR_DSI, 5586 }, 5587 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5588 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5589 .format = MIPI_DSI_FMT_RGB888, 5590 .lanes = 4, 5591 }; 5592 5593 static const struct drm_display_mode lg_acx467akm_7_mode = { 5594 .clock = 150000, 5595 .hdisplay = 1080, 5596 .hsync_start = 1080 + 2, 5597 .hsync_end = 1080 + 2 + 2, 5598 .htotal = 1080 + 2 + 2 + 2, 5599 .vdisplay = 1920, 5600 .vsync_start = 1920 + 2, 5601 .vsync_end = 1920 + 2 + 2, 5602 .vtotal = 1920 + 2 + 2 + 2, 5603 }; 5604 5605 static const struct panel_desc_dsi lg_acx467akm_7 = { 5606 .desc = { 5607 .modes = &lg_acx467akm_7_mode, 5608 .num_modes = 1, 5609 .bpc = 8, 5610 .size = { 5611 .width = 62, 5612 .height = 110, 5613 }, 5614 .connector_type = DRM_MODE_CONNECTOR_DSI, 5615 }, 5616 .flags = 0, 5617 .format = MIPI_DSI_FMT_RGB888, 5618 .lanes = 4, 5619 }; 5620 5621 static const struct drm_display_mode osd101t2045_53ts_mode = { 5622 .clock = 154500, 5623 .hdisplay = 1920, 5624 .hsync_start = 1920 + 112, 5625 .hsync_end = 1920 + 112 + 16, 5626 .htotal = 1920 + 112 + 16 + 32, 5627 .vdisplay = 1200, 5628 .vsync_start = 1200 + 16, 5629 .vsync_end = 1200 + 16 + 2, 5630 .vtotal = 1200 + 16 + 2 + 16, 5631 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5632 }; 5633 5634 static const struct panel_desc_dsi osd101t2045_53ts = { 5635 .desc = { 5636 .modes = &osd101t2045_53ts_mode, 5637 .num_modes = 1, 5638 .bpc = 8, 5639 .size = { 5640 .width = 217, 5641 .height = 136, 5642 }, 5643 .connector_type = DRM_MODE_CONNECTOR_DSI, 5644 }, 5645 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5646 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5647 MIPI_DSI_MODE_NO_EOT_PACKET, 5648 .format = MIPI_DSI_FMT_RGB888, 5649 .lanes = 4, 5650 }; 5651 5652 static const struct of_device_id dsi_of_match[] = { 5653 { 5654 .compatible = "auo,b080uan01", 5655 .data = &auo_b080uan01 5656 }, { 5657 .compatible = "boe,tv080wum-nl0", 5658 .data = &boe_tv080wum_nl0 5659 }, { 5660 .compatible = "lg,ld070wx3-sl01", 5661 .data = &lg_ld070wx3_sl01 5662 }, { 5663 .compatible = "lg,lh500wx1-sd03", 5664 .data = &lg_lh500wx1_sd03 5665 }, { 5666 .compatible = "panasonic,vvx10f004b00", 5667 .data = &panasonic_vvx10f004b00 5668 }, { 5669 .compatible = "lg,acx467akm-7", 5670 .data = &lg_acx467akm_7 5671 }, { 5672 .compatible = "osddisplays,osd101t2045-53ts", 5673 .data = &osd101t2045_53ts 5674 }, { 5675 /* sentinel */ 5676 } 5677 }; 5678 MODULE_DEVICE_TABLE(of, dsi_of_match); 5679 5680 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5681 { 5682 const struct panel_desc_dsi *desc; 5683 int err; 5684 5685 desc = of_device_get_match_data(&dsi->dev); 5686 if (!desc) 5687 return -ENODEV; 5688 5689 err = panel_simple_probe(&dsi->dev, &desc->desc); 5690 if (err < 0) 5691 return err; 5692 5693 dsi->mode_flags = desc->flags; 5694 dsi->format = desc->format; 5695 dsi->lanes = desc->lanes; 5696 5697 err = mipi_dsi_attach(dsi); 5698 if (err) { 5699 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5700 5701 drm_panel_remove(&panel->base); 5702 } 5703 5704 return err; 5705 } 5706 5707 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5708 { 5709 int err; 5710 5711 err = mipi_dsi_detach(dsi); 5712 if (err < 0) 5713 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5714 5715 panel_simple_remove(&dsi->dev); 5716 } 5717 5718 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5719 { 5720 panel_simple_shutdown(&dsi->dev); 5721 } 5722 5723 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5724 .driver = { 5725 .name = "panel-simple-dsi", 5726 .of_match_table = dsi_of_match, 5727 .pm = &panel_simple_pm_ops, 5728 }, 5729 .probe = panel_simple_dsi_probe, 5730 .remove = panel_simple_dsi_remove, 5731 .shutdown = panel_simple_dsi_shutdown, 5732 }; 5733 5734 static int __init panel_simple_init(void) 5735 { 5736 int err; 5737 5738 err = platform_driver_register(&panel_simple_platform_driver); 5739 if (err < 0) 5740 return err; 5741 5742 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5743 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5744 if (err < 0) 5745 goto err_did_platform_register; 5746 } 5747 5748 return 0; 5749 5750 err_did_platform_register: 5751 platform_driver_unregister(&panel_simple_platform_driver); 5752 5753 return err; 5754 } 5755 module_init(panel_simple_init); 5756 5757 static void __exit panel_simple_exit(void) 5758 { 5759 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5760 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5761 5762 platform_driver_unregister(&panel_simple_platform_driver); 5763 } 5764 module_exit(panel_simple_exit); 5765 5766 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5767 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5768 MODULE_LICENSE("GPL and additional rights"); 5769