1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 bool enabled; 142 143 bool prepared; 144 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 554 struct panel_simple *panel) 555 { 556 int ret, bpc; 557 558 ret = drm_of_lvds_get_data_mapping(dev->of_node); 559 if (ret < 0) { 560 if (ret == -EINVAL) 561 dev_warn(dev, "Ignore invalid data-mapping property\n"); 562 563 /* 564 * Ignore non-existing or malformatted property, fallback to 565 * default data-mapping, and return 0. 566 */ 567 return 0; 568 } 569 570 switch (ret) { 571 default: 572 WARN_ON(1); 573 fallthrough; 574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 575 fallthrough; 576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 577 bpc = 8; 578 break; 579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 580 bpc = 6; 581 } 582 583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 584 struct panel_desc *override_desc; 585 586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 587 if (!override_desc) 588 return -ENOMEM; 589 590 override_desc->bus_format = ret; 591 override_desc->bpc = bpc; 592 panel->desc = override_desc; 593 } 594 595 return 0; 596 } 597 598 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 599 { 600 struct panel_simple *panel; 601 struct display_timing dt; 602 struct device_node *ddc; 603 int connector_type; 604 u32 bus_flags; 605 int err; 606 607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 608 if (!panel) 609 return -ENOMEM; 610 611 panel->enabled = false; 612 panel->desc = desc; 613 614 panel->supply = devm_regulator_get(dev, "power"); 615 if (IS_ERR(panel->supply)) 616 return PTR_ERR(panel->supply); 617 618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 619 GPIOD_OUT_LOW); 620 if (IS_ERR(panel->enable_gpio)) 621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 622 "failed to request GPIO\n"); 623 624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 625 if (err) { 626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 627 return err; 628 } 629 630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 631 if (ddc) { 632 panel->ddc = of_find_i2c_adapter_by_node(ddc); 633 of_node_put(ddc); 634 635 if (!panel->ddc) 636 return -EPROBE_DEFER; 637 } 638 639 if (desc == &panel_dpi) { 640 /* Handle the generic panel-dpi binding */ 641 err = panel_dpi_probe(dev, panel); 642 if (err) 643 goto free_ddc; 644 desc = panel->desc; 645 } else { 646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 647 panel_simple_parse_panel_timing_node(dev, panel, &dt); 648 } 649 650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 651 /* Optional data-mapping property for overriding bus format */ 652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 653 if (err) 654 goto free_ddc; 655 } 656 657 connector_type = desc->connector_type; 658 /* Catch common mistakes for panels. */ 659 switch (connector_type) { 660 case 0: 661 dev_warn(dev, "Specify missing connector_type\n"); 662 connector_type = DRM_MODE_CONNECTOR_DPI; 663 break; 664 case DRM_MODE_CONNECTOR_LVDS: 665 WARN_ON(desc->bus_flags & 666 ~(DRM_BUS_FLAG_DE_LOW | 667 DRM_BUS_FLAG_DE_HIGH | 668 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 669 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 674 desc->bpc != 6); 675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 677 desc->bpc != 8); 678 break; 679 case DRM_MODE_CONNECTOR_eDP: 680 dev_warn(dev, "eDP panels moved to panel-edp\n"); 681 err = -EINVAL; 682 goto free_ddc; 683 case DRM_MODE_CONNECTOR_DSI: 684 if (desc->bpc != 6 && desc->bpc != 8) 685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 686 break; 687 case DRM_MODE_CONNECTOR_DPI: 688 bus_flags = DRM_BUS_FLAG_DE_LOW | 689 DRM_BUS_FLAG_DE_HIGH | 690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 692 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 693 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 696 if (desc->bus_flags & ~bus_flags) 697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 698 if (!(desc->bus_flags & bus_flags)) 699 dev_warn(dev, "Specify missing bus_flags\n"); 700 if (desc->bus_format == 0) 701 dev_warn(dev, "Specify missing bus_format\n"); 702 if (desc->bpc != 6 && desc->bpc != 8) 703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 704 break; 705 default: 706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 707 connector_type = DRM_MODE_CONNECTOR_DPI; 708 break; 709 } 710 711 dev_set_drvdata(dev, panel); 712 713 /* 714 * We use runtime PM for prepare / unprepare since those power the panel 715 * on and off and those can be very slow operations. This is important 716 * to optimize powering the panel on briefly to read the EDID before 717 * fully enabling the panel. 718 */ 719 pm_runtime_enable(dev); 720 pm_runtime_set_autosuspend_delay(dev, 1000); 721 pm_runtime_use_autosuspend(dev); 722 723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 724 725 err = drm_panel_of_backlight(&panel->base); 726 if (err) { 727 dev_err_probe(dev, err, "Could not find backlight\n"); 728 goto disable_pm_runtime; 729 } 730 731 drm_panel_add(&panel->base); 732 733 return 0; 734 735 disable_pm_runtime: 736 pm_runtime_dont_use_autosuspend(dev); 737 pm_runtime_disable(dev); 738 free_ddc: 739 if (panel->ddc) 740 put_device(&panel->ddc->dev); 741 742 return err; 743 } 744 745 static void panel_simple_remove(struct device *dev) 746 { 747 struct panel_simple *panel = dev_get_drvdata(dev); 748 749 drm_panel_remove(&panel->base); 750 drm_panel_disable(&panel->base); 751 drm_panel_unprepare(&panel->base); 752 753 pm_runtime_dont_use_autosuspend(dev); 754 pm_runtime_disable(dev); 755 if (panel->ddc) 756 put_device(&panel->ddc->dev); 757 } 758 759 static void panel_simple_shutdown(struct device *dev) 760 { 761 struct panel_simple *panel = dev_get_drvdata(dev); 762 763 drm_panel_disable(&panel->base); 764 drm_panel_unprepare(&panel->base); 765 } 766 767 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 768 .clock = 71100, 769 .hdisplay = 1280, 770 .hsync_start = 1280 + 40, 771 .hsync_end = 1280 + 40 + 80, 772 .htotal = 1280 + 40 + 80 + 40, 773 .vdisplay = 800, 774 .vsync_start = 800 + 3, 775 .vsync_end = 800 + 3 + 10, 776 .vtotal = 800 + 3 + 10 + 10, 777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 778 }; 779 780 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 781 .modes = &ire_am_1280800n3tzqw_t00h_mode, 782 .num_modes = 1, 783 .bpc = 8, 784 .size = { 785 .width = 217, 786 .height = 136, 787 }, 788 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 790 .connector_type = DRM_MODE_CONNECTOR_LVDS, 791 }; 792 793 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 794 .clock = 9000, 795 .hdisplay = 480, 796 .hsync_start = 480 + 2, 797 .hsync_end = 480 + 2 + 41, 798 .htotal = 480 + 2 + 41 + 2, 799 .vdisplay = 272, 800 .vsync_start = 272 + 2, 801 .vsync_end = 272 + 2 + 10, 802 .vtotal = 272 + 2 + 10 + 2, 803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 804 }; 805 806 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 807 .modes = &ire_am_480272h3tmqw_t01h_mode, 808 .num_modes = 1, 809 .bpc = 8, 810 .size = { 811 .width = 99, 812 .height = 58, 813 }, 814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 815 }; 816 817 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 818 .clock = 33333, 819 .hdisplay = 800, 820 .hsync_start = 800 + 0, 821 .hsync_end = 800 + 0 + 255, 822 .htotal = 800 + 0 + 255 + 0, 823 .vdisplay = 480, 824 .vsync_start = 480 + 2, 825 .vsync_end = 480 + 2 + 45, 826 .vtotal = 480 + 2 + 45 + 0, 827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 828 }; 829 830 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 831 .pixelclock = { 29930000, 33260000, 36590000 }, 832 .hactive = { 800, 800, 800 }, 833 .hfront_porch = { 1, 40, 168 }, 834 .hback_porch = { 88, 88, 88 }, 835 .hsync_len = { 1, 128, 128 }, 836 .vactive = { 480, 480, 480 }, 837 .vfront_porch = { 1, 35, 37 }, 838 .vback_porch = { 8, 8, 8 }, 839 .vsync_len = { 1, 2, 2 }, 840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 842 DISPLAY_FLAGS_SYNC_POSEDGE, 843 }; 844 845 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 846 .timings = &ire_am_800480l1tmqw_t00h_timing, 847 .num_timings = 1, 848 .bpc = 8, 849 .size = { 850 .width = 111, 851 .height = 67, 852 }, 853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 857 .connector_type = DRM_MODE_CONNECTOR_DPI, 858 }; 859 860 static const struct panel_desc ampire_am800480r3tmqwa1h = { 861 .modes = &ire_am800480r3tmqwa1h_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 152, 866 .height = 91, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 869 }; 870 871 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 872 .pixelclock = { 34500000, 39600000, 50400000 }, 873 .hactive = { 800, 800, 800 }, 874 .hfront_porch = { 12, 112, 312 }, 875 .hback_porch = { 87, 87, 48 }, 876 .hsync_len = { 1, 1, 40 }, 877 .vactive = { 600, 600, 600 }, 878 .vfront_porch = { 1, 21, 61 }, 879 .vback_porch = { 38, 38, 19 }, 880 .vsync_len = { 1, 1, 20 }, 881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 883 DISPLAY_FLAGS_SYNC_POSEDGE, 884 }; 885 886 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 887 .timings = &ire_am800600p5tmqw_tb8h_timing, 888 .num_timings = 1, 889 .bpc = 6, 890 .size = { 891 .width = 162, 892 .height = 122, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 898 .connector_type = DRM_MODE_CONNECTOR_DPI, 899 }; 900 901 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 902 .pixelclock = { 26400000, 33300000, 46800000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 16, 210, 354 }, 905 .hback_porch = { 45, 36, 6 }, 906 .hsync_len = { 1, 10, 40 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 7, 22, 147 }, 909 .vback_porch = { 22, 13, 3 }, 910 .vsync_len = { 1, 10, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 913 }; 914 915 static const struct panel_desc armadeus_st0700_adapt = { 916 .timings = &santek_st0700i5y_rbslw_f_timing, 917 .num_timings = 1, 918 .bpc = 6, 919 .size = { 920 .width = 154, 921 .height = 86, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 925 }; 926 927 static const struct drm_display_mode auo_b101aw03_mode = { 928 .clock = 51450, 929 .hdisplay = 1024, 930 .hsync_start = 1024 + 156, 931 .hsync_end = 1024 + 156 + 8, 932 .htotal = 1024 + 156 + 8 + 156, 933 .vdisplay = 600, 934 .vsync_start = 600 + 16, 935 .vsync_end = 600 + 16 + 6, 936 .vtotal = 600 + 16 + 6 + 16, 937 }; 938 939 static const struct panel_desc auo_b101aw03 = { 940 .modes = &auo_b101aw03_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 223, 945 .height = 125, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 950 }; 951 952 static const struct drm_display_mode auo_b101xtn01_mode = { 953 .clock = 72000, 954 .hdisplay = 1366, 955 .hsync_start = 1366 + 20, 956 .hsync_end = 1366 + 20 + 70, 957 .htotal = 1366 + 20 + 70, 958 .vdisplay = 768, 959 .vsync_start = 768 + 14, 960 .vsync_end = 768 + 14 + 42, 961 .vtotal = 768 + 14 + 42, 962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 963 }; 964 965 static const struct panel_desc auo_b101xtn01 = { 966 .modes = &auo_b101xtn01_mode, 967 .num_modes = 1, 968 .bpc = 6, 969 .size = { 970 .width = 223, 971 .height = 125, 972 }, 973 }; 974 975 static const struct display_timing auo_g070vvn01_timings = { 976 .pixelclock = { 33300000, 34209000, 45000000 }, 977 .hactive = { 800, 800, 800 }, 978 .hfront_porch = { 20, 40, 200 }, 979 .hback_porch = { 87, 40, 1 }, 980 .hsync_len = { 1, 48, 87 }, 981 .vactive = { 480, 480, 480 }, 982 .vfront_porch = { 5, 13, 200 }, 983 .vback_porch = { 31, 31, 29 }, 984 .vsync_len = { 1, 1, 3 }, 985 }; 986 987 static const struct panel_desc auo_g070vvn01 = { 988 .timings = &auo_g070vvn01_timings, 989 .num_timings = 1, 990 .bpc = 8, 991 .size = { 992 .width = 152, 993 .height = 91, 994 }, 995 .delay = { 996 .prepare = 200, 997 .enable = 50, 998 .disable = 50, 999 .unprepare = 1000, 1000 }, 1001 }; 1002 1003 static const struct drm_display_mode auo_g101evn010_mode = { 1004 .clock = 68930, 1005 .hdisplay = 1280, 1006 .hsync_start = 1280 + 82, 1007 .hsync_end = 1280 + 82 + 2, 1008 .htotal = 1280 + 82 + 2 + 84, 1009 .vdisplay = 800, 1010 .vsync_start = 800 + 8, 1011 .vsync_end = 800 + 8 + 2, 1012 .vtotal = 800 + 8 + 2 + 6, 1013 }; 1014 1015 static const struct panel_desc auo_g101evn010 = { 1016 .modes = &auo_g101evn010_mode, 1017 .num_modes = 1, 1018 .bpc = 6, 1019 .size = { 1020 .width = 216, 1021 .height = 135, 1022 }, 1023 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1024 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1025 }; 1026 1027 static const struct drm_display_mode auo_g104sn02_mode = { 1028 .clock = 40000, 1029 .hdisplay = 800, 1030 .hsync_start = 800 + 40, 1031 .hsync_end = 800 + 40 + 216, 1032 .htotal = 800 + 40 + 216 + 128, 1033 .vdisplay = 600, 1034 .vsync_start = 600 + 10, 1035 .vsync_end = 600 + 10 + 35, 1036 .vtotal = 600 + 10 + 35 + 2, 1037 }; 1038 1039 static const struct panel_desc auo_g104sn02 = { 1040 .modes = &auo_g104sn02_mode, 1041 .num_modes = 1, 1042 .bpc = 8, 1043 .size = { 1044 .width = 211, 1045 .height = 158, 1046 }, 1047 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1048 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1049 }; 1050 1051 static const struct display_timing auo_g121ean01_timing = { 1052 .pixelclock = { 60000000, 74400000, 90000000 }, 1053 .hactive = { 1280, 1280, 1280 }, 1054 .hfront_porch = { 20, 50, 100 }, 1055 .hback_porch = { 20, 50, 100 }, 1056 .hsync_len = { 30, 100, 200 }, 1057 .vactive = { 800, 800, 800 }, 1058 .vfront_porch = { 2, 10, 25 }, 1059 .vback_porch = { 2, 10, 25 }, 1060 .vsync_len = { 4, 18, 50 }, 1061 }; 1062 1063 static const struct panel_desc auo_g121ean01 = { 1064 .timings = &auo_g121ean01_timing, 1065 .num_timings = 1, 1066 .bpc = 8, 1067 .size = { 1068 .width = 261, 1069 .height = 163, 1070 }, 1071 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1072 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1073 }; 1074 1075 static const struct display_timing auo_g133han01_timings = { 1076 .pixelclock = { 134000000, 141200000, 149000000 }, 1077 .hactive = { 1920, 1920, 1920 }, 1078 .hfront_porch = { 39, 58, 77 }, 1079 .hback_porch = { 59, 88, 117 }, 1080 .hsync_len = { 28, 42, 56 }, 1081 .vactive = { 1080, 1080, 1080 }, 1082 .vfront_porch = { 3, 8, 11 }, 1083 .vback_porch = { 5, 14, 19 }, 1084 .vsync_len = { 4, 14, 19 }, 1085 }; 1086 1087 static const struct panel_desc auo_g133han01 = { 1088 .timings = &auo_g133han01_timings, 1089 .num_timings = 1, 1090 .bpc = 8, 1091 .size = { 1092 .width = 293, 1093 .height = 165, 1094 }, 1095 .delay = { 1096 .prepare = 200, 1097 .enable = 50, 1098 .disable = 50, 1099 .unprepare = 1000, 1100 }, 1101 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1102 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1103 }; 1104 1105 static const struct drm_display_mode auo_g156xtn01_mode = { 1106 .clock = 76000, 1107 .hdisplay = 1366, 1108 .hsync_start = 1366 + 33, 1109 .hsync_end = 1366 + 33 + 67, 1110 .htotal = 1560, 1111 .vdisplay = 768, 1112 .vsync_start = 768 + 4, 1113 .vsync_end = 768 + 4 + 4, 1114 .vtotal = 806, 1115 }; 1116 1117 static const struct panel_desc auo_g156xtn01 = { 1118 .modes = &auo_g156xtn01_mode, 1119 .num_modes = 1, 1120 .bpc = 8, 1121 .size = { 1122 .width = 344, 1123 .height = 194, 1124 }, 1125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1126 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1127 }; 1128 1129 static const struct display_timing auo_g185han01_timings = { 1130 .pixelclock = { 120000000, 144000000, 175000000 }, 1131 .hactive = { 1920, 1920, 1920 }, 1132 .hfront_porch = { 36, 120, 148 }, 1133 .hback_porch = { 24, 88, 108 }, 1134 .hsync_len = { 20, 48, 64 }, 1135 .vactive = { 1080, 1080, 1080 }, 1136 .vfront_porch = { 6, 10, 40 }, 1137 .vback_porch = { 2, 5, 20 }, 1138 .vsync_len = { 2, 5, 20 }, 1139 }; 1140 1141 static const struct panel_desc auo_g185han01 = { 1142 .timings = &auo_g185han01_timings, 1143 .num_timings = 1, 1144 .bpc = 8, 1145 .size = { 1146 .width = 409, 1147 .height = 230, 1148 }, 1149 .delay = { 1150 .prepare = 50, 1151 .enable = 200, 1152 .disable = 110, 1153 .unprepare = 1000, 1154 }, 1155 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1156 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1157 }; 1158 1159 static const struct display_timing auo_g190ean01_timings = { 1160 .pixelclock = { 90000000, 108000000, 135000000 }, 1161 .hactive = { 1280, 1280, 1280 }, 1162 .hfront_porch = { 126, 184, 1266 }, 1163 .hback_porch = { 84, 122, 844 }, 1164 .hsync_len = { 70, 102, 704 }, 1165 .vactive = { 1024, 1024, 1024 }, 1166 .vfront_porch = { 4, 26, 76 }, 1167 .vback_porch = { 2, 8, 25 }, 1168 .vsync_len = { 2, 8, 25 }, 1169 }; 1170 1171 static const struct panel_desc auo_g190ean01 = { 1172 .timings = &auo_g190ean01_timings, 1173 .num_timings = 1, 1174 .bpc = 8, 1175 .size = { 1176 .width = 376, 1177 .height = 301, 1178 }, 1179 .delay = { 1180 .prepare = 50, 1181 .enable = 200, 1182 .disable = 110, 1183 .unprepare = 1000, 1184 }, 1185 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1186 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1187 }; 1188 1189 static const struct display_timing auo_p320hvn03_timings = { 1190 .pixelclock = { 106000000, 148500000, 164000000 }, 1191 .hactive = { 1920, 1920, 1920 }, 1192 .hfront_porch = { 25, 50, 130 }, 1193 .hback_porch = { 25, 50, 130 }, 1194 .hsync_len = { 20, 40, 105 }, 1195 .vactive = { 1080, 1080, 1080 }, 1196 .vfront_porch = { 8, 17, 150 }, 1197 .vback_porch = { 8, 17, 150 }, 1198 .vsync_len = { 4, 11, 100 }, 1199 }; 1200 1201 static const struct panel_desc auo_p320hvn03 = { 1202 .timings = &auo_p320hvn03_timings, 1203 .num_timings = 1, 1204 .bpc = 8, 1205 .size = { 1206 .width = 698, 1207 .height = 393, 1208 }, 1209 .delay = { 1210 .prepare = 1, 1211 .enable = 450, 1212 .unprepare = 500, 1213 }, 1214 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1215 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1216 }; 1217 1218 static const struct drm_display_mode auo_t215hvn01_mode = { 1219 .clock = 148800, 1220 .hdisplay = 1920, 1221 .hsync_start = 1920 + 88, 1222 .hsync_end = 1920 + 88 + 44, 1223 .htotal = 1920 + 88 + 44 + 148, 1224 .vdisplay = 1080, 1225 .vsync_start = 1080 + 4, 1226 .vsync_end = 1080 + 4 + 5, 1227 .vtotal = 1080 + 4 + 5 + 36, 1228 }; 1229 1230 static const struct panel_desc auo_t215hvn01 = { 1231 .modes = &auo_t215hvn01_mode, 1232 .num_modes = 1, 1233 .bpc = 8, 1234 .size = { 1235 .width = 430, 1236 .height = 270, 1237 }, 1238 .delay = { 1239 .disable = 5, 1240 .unprepare = 1000, 1241 }, 1242 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1243 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1244 }; 1245 1246 static const struct drm_display_mode avic_tm070ddh03_mode = { 1247 .clock = 51200, 1248 .hdisplay = 1024, 1249 .hsync_start = 1024 + 160, 1250 .hsync_end = 1024 + 160 + 4, 1251 .htotal = 1024 + 160 + 4 + 156, 1252 .vdisplay = 600, 1253 .vsync_start = 600 + 17, 1254 .vsync_end = 600 + 17 + 1, 1255 .vtotal = 600 + 17 + 1 + 17, 1256 }; 1257 1258 static const struct panel_desc avic_tm070ddh03 = { 1259 .modes = &avic_tm070ddh03_mode, 1260 .num_modes = 1, 1261 .bpc = 8, 1262 .size = { 1263 .width = 154, 1264 .height = 90, 1265 }, 1266 .delay = { 1267 .prepare = 20, 1268 .enable = 200, 1269 .disable = 200, 1270 }, 1271 }; 1272 1273 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1274 .clock = 30000, 1275 .hdisplay = 800, 1276 .hsync_start = 800 + 40, 1277 .hsync_end = 800 + 40 + 48, 1278 .htotal = 800 + 40 + 48 + 40, 1279 .vdisplay = 480, 1280 .vsync_start = 480 + 13, 1281 .vsync_end = 480 + 13 + 3, 1282 .vtotal = 480 + 13 + 3 + 29, 1283 }; 1284 1285 static const struct panel_desc bananapi_s070wv20_ct16 = { 1286 .modes = &bananapi_s070wv20_ct16_mode, 1287 .num_modes = 1, 1288 .bpc = 6, 1289 .size = { 1290 .width = 154, 1291 .height = 86, 1292 }, 1293 }; 1294 1295 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1296 .pixelclock = { 69922000, 71000000, 72293000 }, 1297 .hactive = { 1280, 1280, 1280 }, 1298 .hfront_porch = { 48, 48, 48 }, 1299 .hback_porch = { 80, 80, 80 }, 1300 .hsync_len = { 32, 32, 32 }, 1301 .vactive = { 800, 800, 800 }, 1302 .vfront_porch = { 3, 3, 3 }, 1303 .vback_porch = { 14, 14, 14 }, 1304 .vsync_len = { 6, 6, 6 }, 1305 }; 1306 1307 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1308 .timings = &boe_ev121wxm_n10_1850_timing, 1309 .num_timings = 1, 1310 .bpc = 8, 1311 .size = { 1312 .width = 261, 1313 .height = 163, 1314 }, 1315 .delay = { 1316 .prepare = 9, 1317 .enable = 300, 1318 .unprepare = 300, 1319 .disable = 560, 1320 }, 1321 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1322 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1323 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1324 }; 1325 1326 static const struct drm_display_mode boe_hv070wsa_mode = { 1327 .clock = 42105, 1328 .hdisplay = 1024, 1329 .hsync_start = 1024 + 30, 1330 .hsync_end = 1024 + 30 + 30, 1331 .htotal = 1024 + 30 + 30 + 30, 1332 .vdisplay = 600, 1333 .vsync_start = 600 + 10, 1334 .vsync_end = 600 + 10 + 10, 1335 .vtotal = 600 + 10 + 10 + 10, 1336 }; 1337 1338 static const struct panel_desc boe_hv070wsa = { 1339 .modes = &boe_hv070wsa_mode, 1340 .num_modes = 1, 1341 .bpc = 8, 1342 .size = { 1343 .width = 154, 1344 .height = 90, 1345 }, 1346 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1347 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1348 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1349 }; 1350 1351 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1352 .clock = 9000, 1353 .hdisplay = 480, 1354 .hsync_start = 480 + 5, 1355 .hsync_end = 480 + 5 + 5, 1356 .htotal = 480 + 5 + 5 + 40, 1357 .vdisplay = 272, 1358 .vsync_start = 272 + 8, 1359 .vsync_end = 272 + 8 + 8, 1360 .vtotal = 272 + 8 + 8 + 8, 1361 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1362 }; 1363 1364 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1365 .modes = &cdtech_s043wq26h_ct7_mode, 1366 .num_modes = 1, 1367 .bpc = 8, 1368 .size = { 1369 .width = 95, 1370 .height = 54, 1371 }, 1372 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1373 }; 1374 1375 /* S070PWS19HP-FC21 2017/04/22 */ 1376 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1377 .clock = 51200, 1378 .hdisplay = 1024, 1379 .hsync_start = 1024 + 160, 1380 .hsync_end = 1024 + 160 + 20, 1381 .htotal = 1024 + 160 + 20 + 140, 1382 .vdisplay = 600, 1383 .vsync_start = 600 + 12, 1384 .vsync_end = 600 + 12 + 3, 1385 .vtotal = 600 + 12 + 3 + 20, 1386 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1387 }; 1388 1389 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1390 .modes = &cdtech_s070pws19hp_fc21_mode, 1391 .num_modes = 1, 1392 .bpc = 6, 1393 .size = { 1394 .width = 154, 1395 .height = 86, 1396 }, 1397 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1398 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1399 .connector_type = DRM_MODE_CONNECTOR_DPI, 1400 }; 1401 1402 /* S070SWV29HG-DC44 2017/09/21 */ 1403 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1404 .clock = 33300, 1405 .hdisplay = 800, 1406 .hsync_start = 800 + 210, 1407 .hsync_end = 800 + 210 + 2, 1408 .htotal = 800 + 210 + 2 + 44, 1409 .vdisplay = 480, 1410 .vsync_start = 480 + 22, 1411 .vsync_end = 480 + 22 + 2, 1412 .vtotal = 480 + 22 + 2 + 21, 1413 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1414 }; 1415 1416 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1417 .modes = &cdtech_s070swv29hg_dc44_mode, 1418 .num_modes = 1, 1419 .bpc = 6, 1420 .size = { 1421 .width = 154, 1422 .height = 86, 1423 }, 1424 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1425 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1426 .connector_type = DRM_MODE_CONNECTOR_DPI, 1427 }; 1428 1429 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1430 .clock = 35000, 1431 .hdisplay = 800, 1432 .hsync_start = 800 + 40, 1433 .hsync_end = 800 + 40 + 40, 1434 .htotal = 800 + 40 + 40 + 48, 1435 .vdisplay = 480, 1436 .vsync_start = 480 + 29, 1437 .vsync_end = 480 + 29 + 13, 1438 .vtotal = 480 + 29 + 13 + 3, 1439 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1440 }; 1441 1442 static const struct panel_desc cdtech_s070wv95_ct16 = { 1443 .modes = &cdtech_s070wv95_ct16_mode, 1444 .num_modes = 1, 1445 .bpc = 8, 1446 .size = { 1447 .width = 154, 1448 .height = 85, 1449 }, 1450 }; 1451 1452 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1453 .pixelclock = { 68900000, 71100000, 73400000 }, 1454 .hactive = { 1280, 1280, 1280 }, 1455 .hfront_porch = { 65, 80, 95 }, 1456 .hback_porch = { 64, 79, 94 }, 1457 .hsync_len = { 1, 1, 1 }, 1458 .vactive = { 800, 800, 800 }, 1459 .vfront_porch = { 7, 11, 14 }, 1460 .vback_porch = { 7, 11, 14 }, 1461 .vsync_len = { 1, 1, 1 }, 1462 .flags = DISPLAY_FLAGS_DE_HIGH, 1463 }; 1464 1465 static const struct panel_desc chefree_ch101olhlwh_002 = { 1466 .timings = &chefree_ch101olhlwh_002_timing, 1467 .num_timings = 1, 1468 .bpc = 8, 1469 .size = { 1470 .width = 217, 1471 .height = 135, 1472 }, 1473 .delay = { 1474 .enable = 200, 1475 .disable = 200, 1476 }, 1477 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1478 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1479 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1480 }; 1481 1482 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1483 .clock = 66770, 1484 .hdisplay = 800, 1485 .hsync_start = 800 + 49, 1486 .hsync_end = 800 + 49 + 33, 1487 .htotal = 800 + 49 + 33 + 17, 1488 .vdisplay = 1280, 1489 .vsync_start = 1280 + 1, 1490 .vsync_end = 1280 + 1 + 7, 1491 .vtotal = 1280 + 1 + 7 + 15, 1492 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1493 }; 1494 1495 static const struct panel_desc chunghwa_claa070wp03xg = { 1496 .modes = &chunghwa_claa070wp03xg_mode, 1497 .num_modes = 1, 1498 .bpc = 6, 1499 .size = { 1500 .width = 94, 1501 .height = 150, 1502 }, 1503 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1504 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1505 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1506 }; 1507 1508 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1509 .clock = 72070, 1510 .hdisplay = 1366, 1511 .hsync_start = 1366 + 58, 1512 .hsync_end = 1366 + 58 + 58, 1513 .htotal = 1366 + 58 + 58 + 58, 1514 .vdisplay = 768, 1515 .vsync_start = 768 + 4, 1516 .vsync_end = 768 + 4 + 4, 1517 .vtotal = 768 + 4 + 4 + 4, 1518 }; 1519 1520 static const struct panel_desc chunghwa_claa101wa01a = { 1521 .modes = &chunghwa_claa101wa01a_mode, 1522 .num_modes = 1, 1523 .bpc = 6, 1524 .size = { 1525 .width = 220, 1526 .height = 120, 1527 }, 1528 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1529 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1530 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1531 }; 1532 1533 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1534 .clock = 69300, 1535 .hdisplay = 1366, 1536 .hsync_start = 1366 + 48, 1537 .hsync_end = 1366 + 48 + 32, 1538 .htotal = 1366 + 48 + 32 + 20, 1539 .vdisplay = 768, 1540 .vsync_start = 768 + 16, 1541 .vsync_end = 768 + 16 + 8, 1542 .vtotal = 768 + 16 + 8 + 16, 1543 }; 1544 1545 static const struct panel_desc chunghwa_claa101wb01 = { 1546 .modes = &chunghwa_claa101wb01_mode, 1547 .num_modes = 1, 1548 .bpc = 6, 1549 .size = { 1550 .width = 223, 1551 .height = 125, 1552 }, 1553 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1554 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1555 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1556 }; 1557 1558 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1559 .pixelclock = { 5000000, 9000000, 12000000 }, 1560 .hactive = { 480, 480, 480 }, 1561 .hfront_porch = { 12, 12, 12 }, 1562 .hback_porch = { 12, 12, 12 }, 1563 .hsync_len = { 21, 21, 21 }, 1564 .vactive = { 272, 272, 272 }, 1565 .vfront_porch = { 4, 4, 4 }, 1566 .vback_porch = { 4, 4, 4 }, 1567 .vsync_len = { 8, 8, 8 }, 1568 }; 1569 1570 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1571 .timings = &dataimage_fg040346dsswbg04_timing, 1572 .num_timings = 1, 1573 .bpc = 8, 1574 .size = { 1575 .width = 95, 1576 .height = 54, 1577 }, 1578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1579 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1580 .connector_type = DRM_MODE_CONNECTOR_DPI, 1581 }; 1582 1583 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1584 .pixelclock = { 68900000, 71110000, 73400000 }, 1585 .hactive = { 1280, 1280, 1280 }, 1586 .vactive = { 800, 800, 800 }, 1587 .hback_porch = { 100, 100, 100 }, 1588 .hfront_porch = { 100, 100, 100 }, 1589 .vback_porch = { 5, 5, 5 }, 1590 .vfront_porch = { 5, 5, 5 }, 1591 .hsync_len = { 24, 24, 24 }, 1592 .vsync_len = { 3, 3, 3 }, 1593 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1594 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1595 }; 1596 1597 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1598 .timings = &dataimage_fg1001l0dsswmg01_timing, 1599 .num_timings = 1, 1600 .bpc = 8, 1601 .size = { 1602 .width = 217, 1603 .height = 136, 1604 }, 1605 }; 1606 1607 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1608 .clock = 33260, 1609 .hdisplay = 800, 1610 .hsync_start = 800 + 40, 1611 .hsync_end = 800 + 40 + 128, 1612 .htotal = 800 + 40 + 128 + 88, 1613 .vdisplay = 480, 1614 .vsync_start = 480 + 10, 1615 .vsync_end = 480 + 10 + 2, 1616 .vtotal = 480 + 10 + 2 + 33, 1617 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1618 }; 1619 1620 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1621 .modes = &dataimage_scf0700c48ggu18_mode, 1622 .num_modes = 1, 1623 .bpc = 8, 1624 .size = { 1625 .width = 152, 1626 .height = 91, 1627 }, 1628 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1629 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1630 }; 1631 1632 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1633 .pixelclock = { 45000000, 51200000, 57000000 }, 1634 .hactive = { 1024, 1024, 1024 }, 1635 .hfront_porch = { 100, 106, 113 }, 1636 .hback_porch = { 100, 106, 113 }, 1637 .hsync_len = { 100, 108, 114 }, 1638 .vactive = { 600, 600, 600 }, 1639 .vfront_porch = { 8, 11, 15 }, 1640 .vback_porch = { 8, 11, 15 }, 1641 .vsync_len = { 9, 13, 15 }, 1642 .flags = DISPLAY_FLAGS_DE_HIGH, 1643 }; 1644 1645 static const struct panel_desc dlc_dlc0700yzg_1 = { 1646 .timings = &dlc_dlc0700yzg_1_timing, 1647 .num_timings = 1, 1648 .bpc = 6, 1649 .size = { 1650 .width = 154, 1651 .height = 86, 1652 }, 1653 .delay = { 1654 .prepare = 30, 1655 .enable = 200, 1656 .disable = 200, 1657 }, 1658 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1659 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1660 }; 1661 1662 static const struct display_timing dlc_dlc1010gig_timing = { 1663 .pixelclock = { 68900000, 71100000, 73400000 }, 1664 .hactive = { 1280, 1280, 1280 }, 1665 .hfront_porch = { 43, 53, 63 }, 1666 .hback_porch = { 43, 53, 63 }, 1667 .hsync_len = { 44, 54, 64 }, 1668 .vactive = { 800, 800, 800 }, 1669 .vfront_porch = { 5, 8, 11 }, 1670 .vback_porch = { 5, 8, 11 }, 1671 .vsync_len = { 5, 7, 11 }, 1672 .flags = DISPLAY_FLAGS_DE_HIGH, 1673 }; 1674 1675 static const struct panel_desc dlc_dlc1010gig = { 1676 .timings = &dlc_dlc1010gig_timing, 1677 .num_timings = 1, 1678 .bpc = 8, 1679 .size = { 1680 .width = 216, 1681 .height = 135, 1682 }, 1683 .delay = { 1684 .prepare = 60, 1685 .enable = 150, 1686 .disable = 100, 1687 .unprepare = 60, 1688 }, 1689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1691 }; 1692 1693 static const struct drm_display_mode edt_et035012dm6_mode = { 1694 .clock = 6500, 1695 .hdisplay = 320, 1696 .hsync_start = 320 + 20, 1697 .hsync_end = 320 + 20 + 30, 1698 .htotal = 320 + 20 + 68, 1699 .vdisplay = 240, 1700 .vsync_start = 240 + 4, 1701 .vsync_end = 240 + 4 + 4, 1702 .vtotal = 240 + 4 + 4 + 14, 1703 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1704 }; 1705 1706 static const struct panel_desc edt_et035012dm6 = { 1707 .modes = &edt_et035012dm6_mode, 1708 .num_modes = 1, 1709 .bpc = 8, 1710 .size = { 1711 .width = 70, 1712 .height = 52, 1713 }, 1714 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1715 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1716 }; 1717 1718 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1719 .clock = 6520, 1720 .hdisplay = 320, 1721 .hsync_start = 320 + 20, 1722 .hsync_end = 320 + 20 + 68, 1723 .htotal = 320 + 20 + 68, 1724 .vdisplay = 240, 1725 .vsync_start = 240 + 4, 1726 .vsync_end = 240 + 4 + 18, 1727 .vtotal = 240 + 4 + 18, 1728 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1729 }; 1730 1731 static const struct panel_desc edt_etm0350g0dh6 = { 1732 .modes = &edt_etm0350g0dh6_mode, 1733 .num_modes = 1, 1734 .bpc = 6, 1735 .size = { 1736 .width = 70, 1737 .height = 53, 1738 }, 1739 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1740 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1741 .connector_type = DRM_MODE_CONNECTOR_DPI, 1742 }; 1743 1744 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1745 .clock = 10870, 1746 .hdisplay = 480, 1747 .hsync_start = 480 + 8, 1748 .hsync_end = 480 + 8 + 4, 1749 .htotal = 480 + 8 + 4 + 41, 1750 1751 /* 1752 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1753 * fb_align 1754 */ 1755 1756 .vdisplay = 288, 1757 .vsync_start = 288 + 2, 1758 .vsync_end = 288 + 2 + 4, 1759 .vtotal = 288 + 2 + 4 + 10, 1760 }; 1761 1762 static const struct panel_desc edt_etm043080dh6gp = { 1763 .modes = &edt_etm043080dh6gp_mode, 1764 .num_modes = 1, 1765 .bpc = 8, 1766 .size = { 1767 .width = 100, 1768 .height = 65, 1769 }, 1770 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1771 .connector_type = DRM_MODE_CONNECTOR_DPI, 1772 }; 1773 1774 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1775 .clock = 9000, 1776 .hdisplay = 480, 1777 .hsync_start = 480 + 2, 1778 .hsync_end = 480 + 2 + 41, 1779 .htotal = 480 + 2 + 41 + 2, 1780 .vdisplay = 272, 1781 .vsync_start = 272 + 2, 1782 .vsync_end = 272 + 2 + 10, 1783 .vtotal = 272 + 2 + 10 + 2, 1784 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1785 }; 1786 1787 static const struct panel_desc edt_etm0430g0dh6 = { 1788 .modes = &edt_etm0430g0dh6_mode, 1789 .num_modes = 1, 1790 .bpc = 6, 1791 .size = { 1792 .width = 95, 1793 .height = 54, 1794 }, 1795 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1796 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1797 .connector_type = DRM_MODE_CONNECTOR_DPI, 1798 }; 1799 1800 static const struct drm_display_mode edt_et057090dhu_mode = { 1801 .clock = 25175, 1802 .hdisplay = 640, 1803 .hsync_start = 640 + 16, 1804 .hsync_end = 640 + 16 + 30, 1805 .htotal = 640 + 16 + 30 + 114, 1806 .vdisplay = 480, 1807 .vsync_start = 480 + 10, 1808 .vsync_end = 480 + 10 + 3, 1809 .vtotal = 480 + 10 + 3 + 32, 1810 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1811 }; 1812 1813 static const struct panel_desc edt_et057090dhu = { 1814 .modes = &edt_et057090dhu_mode, 1815 .num_modes = 1, 1816 .bpc = 6, 1817 .size = { 1818 .width = 115, 1819 .height = 86, 1820 }, 1821 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1822 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1823 .connector_type = DRM_MODE_CONNECTOR_DPI, 1824 }; 1825 1826 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1827 .clock = 33260, 1828 .hdisplay = 800, 1829 .hsync_start = 800 + 40, 1830 .hsync_end = 800 + 40 + 128, 1831 .htotal = 800 + 40 + 128 + 88, 1832 .vdisplay = 480, 1833 .vsync_start = 480 + 10, 1834 .vsync_end = 480 + 10 + 2, 1835 .vtotal = 480 + 10 + 2 + 33, 1836 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1837 }; 1838 1839 static const struct panel_desc edt_etm0700g0dh6 = { 1840 .modes = &edt_etm0700g0dh6_mode, 1841 .num_modes = 1, 1842 .bpc = 6, 1843 .size = { 1844 .width = 152, 1845 .height = 91, 1846 }, 1847 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1849 .connector_type = DRM_MODE_CONNECTOR_DPI, 1850 }; 1851 1852 static const struct panel_desc edt_etm0700g0bdh6 = { 1853 .modes = &edt_etm0700g0dh6_mode, 1854 .num_modes = 1, 1855 .bpc = 6, 1856 .size = { 1857 .width = 152, 1858 .height = 91, 1859 }, 1860 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1862 .connector_type = DRM_MODE_CONNECTOR_DPI, 1863 }; 1864 1865 static const struct display_timing edt_etml0700y5dha_timing = { 1866 .pixelclock = { 40800000, 51200000, 67200000 }, 1867 .hactive = { 1024, 1024, 1024 }, 1868 .hfront_porch = { 30, 106, 125 }, 1869 .hback_porch = { 30, 106, 125 }, 1870 .hsync_len = { 30, 108, 126 }, 1871 .vactive = { 600, 600, 600 }, 1872 .vfront_porch = { 3, 12, 67}, 1873 .vback_porch = { 3, 12, 67 }, 1874 .vsync_len = { 4, 11, 66 }, 1875 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1876 DISPLAY_FLAGS_DE_HIGH, 1877 }; 1878 1879 static const struct panel_desc edt_etml0700y5dha = { 1880 .timings = &edt_etml0700y5dha_timing, 1881 .num_timings = 1, 1882 .bpc = 8, 1883 .size = { 1884 .width = 155, 1885 .height = 86, 1886 }, 1887 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1888 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1889 }; 1890 1891 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1892 .clock = 25175, 1893 .hdisplay = 640, 1894 .hsync_start = 640, 1895 .hsync_end = 640 + 16, 1896 .htotal = 640 + 16 + 30 + 114, 1897 .vdisplay = 480, 1898 .vsync_start = 480 + 10, 1899 .vsync_end = 480 + 10 + 3, 1900 .vtotal = 480 + 10 + 3 + 35, 1901 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1902 }; 1903 1904 static const struct panel_desc edt_etmv570g2dhu = { 1905 .modes = &edt_etmv570g2dhu_mode, 1906 .num_modes = 1, 1907 .bpc = 6, 1908 .size = { 1909 .width = 115, 1910 .height = 86, 1911 }, 1912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1914 .connector_type = DRM_MODE_CONNECTOR_DPI, 1915 }; 1916 1917 static const struct display_timing eink_vb3300_kca_timing = { 1918 .pixelclock = { 40000000, 40000000, 40000000 }, 1919 .hactive = { 334, 334, 334 }, 1920 .hfront_porch = { 1, 1, 1 }, 1921 .hback_porch = { 1, 1, 1 }, 1922 .hsync_len = { 1, 1, 1 }, 1923 .vactive = { 1405, 1405, 1405 }, 1924 .vfront_porch = { 1, 1, 1 }, 1925 .vback_porch = { 1, 1, 1 }, 1926 .vsync_len = { 1, 1, 1 }, 1927 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1928 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1929 }; 1930 1931 static const struct panel_desc eink_vb3300_kca = { 1932 .timings = &eink_vb3300_kca_timing, 1933 .num_timings = 1, 1934 .bpc = 6, 1935 .size = { 1936 .width = 157, 1937 .height = 209, 1938 }, 1939 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1940 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1941 .connector_type = DRM_MODE_CONNECTOR_DPI, 1942 }; 1943 1944 static const struct display_timing evervision_vgg804821_timing = { 1945 .pixelclock = { 27600000, 33300000, 50000000 }, 1946 .hactive = { 800, 800, 800 }, 1947 .hfront_porch = { 40, 66, 70 }, 1948 .hback_porch = { 40, 67, 70 }, 1949 .hsync_len = { 40, 67, 70 }, 1950 .vactive = { 480, 480, 480 }, 1951 .vfront_porch = { 6, 10, 10 }, 1952 .vback_porch = { 7, 11, 11 }, 1953 .vsync_len = { 7, 11, 11 }, 1954 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1955 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1956 DISPLAY_FLAGS_SYNC_NEGEDGE, 1957 }; 1958 1959 static const struct panel_desc evervision_vgg804821 = { 1960 .timings = &evervision_vgg804821_timing, 1961 .num_timings = 1, 1962 .bpc = 8, 1963 .size = { 1964 .width = 108, 1965 .height = 64, 1966 }, 1967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1968 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1969 }; 1970 1971 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1972 .clock = 32260, 1973 .hdisplay = 800, 1974 .hsync_start = 800 + 168, 1975 .hsync_end = 800 + 168 + 64, 1976 .htotal = 800 + 168 + 64 + 88, 1977 .vdisplay = 480, 1978 .vsync_start = 480 + 37, 1979 .vsync_end = 480 + 37 + 2, 1980 .vtotal = 480 + 37 + 2 + 8, 1981 }; 1982 1983 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1984 .modes = &foxlink_fl500wvr00_a0t_mode, 1985 .num_modes = 1, 1986 .bpc = 8, 1987 .size = { 1988 .width = 108, 1989 .height = 65, 1990 }, 1991 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1992 }; 1993 1994 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1995 { /* 60 Hz */ 1996 .clock = 6000, 1997 .hdisplay = 320, 1998 .hsync_start = 320 + 44, 1999 .hsync_end = 320 + 44 + 16, 2000 .htotal = 320 + 44 + 16 + 20, 2001 .vdisplay = 240, 2002 .vsync_start = 240 + 2, 2003 .vsync_end = 240 + 2 + 6, 2004 .vtotal = 240 + 2 + 6 + 2, 2005 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2006 }, 2007 { /* 50 Hz */ 2008 .clock = 5400, 2009 .hdisplay = 320, 2010 .hsync_start = 320 + 56, 2011 .hsync_end = 320 + 56 + 16, 2012 .htotal = 320 + 56 + 16 + 40, 2013 .vdisplay = 240, 2014 .vsync_start = 240 + 2, 2015 .vsync_end = 240 + 2 + 6, 2016 .vtotal = 240 + 2 + 6 + 2, 2017 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2018 }, 2019 }; 2020 2021 static const struct panel_desc frida_frd350h54004 = { 2022 .modes = frida_frd350h54004_modes, 2023 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2024 .bpc = 8, 2025 .size = { 2026 .width = 77, 2027 .height = 64, 2028 }, 2029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2030 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2031 .connector_type = DRM_MODE_CONNECTOR_DPI, 2032 }; 2033 2034 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2035 .clock = 67185, 2036 .hdisplay = 800, 2037 .hsync_start = 800 + 20, 2038 .hsync_end = 800 + 20 + 24, 2039 .htotal = 800 + 20 + 24 + 20, 2040 .vdisplay = 1280, 2041 .vsync_start = 1280 + 4, 2042 .vsync_end = 1280 + 4 + 8, 2043 .vtotal = 1280 + 4 + 8 + 4, 2044 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2045 }; 2046 2047 static const struct panel_desc friendlyarm_hd702e = { 2048 .modes = &friendlyarm_hd702e_mode, 2049 .num_modes = 1, 2050 .size = { 2051 .width = 94, 2052 .height = 151, 2053 }, 2054 }; 2055 2056 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2057 .clock = 9000, 2058 .hdisplay = 480, 2059 .hsync_start = 480 + 5, 2060 .hsync_end = 480 + 5 + 1, 2061 .htotal = 480 + 5 + 1 + 40, 2062 .vdisplay = 272, 2063 .vsync_start = 272 + 8, 2064 .vsync_end = 272 + 8 + 1, 2065 .vtotal = 272 + 8 + 1 + 8, 2066 }; 2067 2068 static const struct panel_desc giantplus_gpg482739qs5 = { 2069 .modes = &giantplus_gpg482739qs5_mode, 2070 .num_modes = 1, 2071 .bpc = 8, 2072 .size = { 2073 .width = 95, 2074 .height = 54, 2075 }, 2076 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2077 }; 2078 2079 static const struct display_timing giantplus_gpm940b0_timing = { 2080 .pixelclock = { 13500000, 27000000, 27500000 }, 2081 .hactive = { 320, 320, 320 }, 2082 .hfront_porch = { 14, 686, 718 }, 2083 .hback_porch = { 50, 70, 255 }, 2084 .hsync_len = { 1, 1, 1 }, 2085 .vactive = { 240, 240, 240 }, 2086 .vfront_porch = { 1, 1, 179 }, 2087 .vback_porch = { 1, 21, 31 }, 2088 .vsync_len = { 1, 1, 6 }, 2089 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2090 }; 2091 2092 static const struct panel_desc giantplus_gpm940b0 = { 2093 .timings = &giantplus_gpm940b0_timing, 2094 .num_timings = 1, 2095 .bpc = 8, 2096 .size = { 2097 .width = 60, 2098 .height = 45, 2099 }, 2100 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2101 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2102 }; 2103 2104 static const struct display_timing hannstar_hsd070pww1_timing = { 2105 .pixelclock = { 64300000, 71100000, 82000000 }, 2106 .hactive = { 1280, 1280, 1280 }, 2107 .hfront_porch = { 1, 1, 10 }, 2108 .hback_porch = { 1, 1, 10 }, 2109 /* 2110 * According to the data sheet, the minimum horizontal blanking interval 2111 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2112 * minimum working horizontal blanking interval to be 60 clocks. 2113 */ 2114 .hsync_len = { 58, 158, 661 }, 2115 .vactive = { 800, 800, 800 }, 2116 .vfront_porch = { 1, 1, 10 }, 2117 .vback_porch = { 1, 1, 10 }, 2118 .vsync_len = { 1, 21, 203 }, 2119 .flags = DISPLAY_FLAGS_DE_HIGH, 2120 }; 2121 2122 static const struct panel_desc hannstar_hsd070pww1 = { 2123 .timings = &hannstar_hsd070pww1_timing, 2124 .num_timings = 1, 2125 .bpc = 6, 2126 .size = { 2127 .width = 151, 2128 .height = 94, 2129 }, 2130 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2131 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2132 }; 2133 2134 static const struct display_timing hannstar_hsd100pxn1_timing = { 2135 .pixelclock = { 55000000, 65000000, 75000000 }, 2136 .hactive = { 1024, 1024, 1024 }, 2137 .hfront_porch = { 40, 40, 40 }, 2138 .hback_porch = { 220, 220, 220 }, 2139 .hsync_len = { 20, 60, 100 }, 2140 .vactive = { 768, 768, 768 }, 2141 .vfront_porch = { 7, 7, 7 }, 2142 .vback_porch = { 21, 21, 21 }, 2143 .vsync_len = { 10, 10, 10 }, 2144 .flags = DISPLAY_FLAGS_DE_HIGH, 2145 }; 2146 2147 static const struct panel_desc hannstar_hsd100pxn1 = { 2148 .timings = &hannstar_hsd100pxn1_timing, 2149 .num_timings = 1, 2150 .bpc = 6, 2151 .size = { 2152 .width = 203, 2153 .height = 152, 2154 }, 2155 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2156 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2157 }; 2158 2159 static const struct display_timing hannstar_hsd101pww2_timing = { 2160 .pixelclock = { 64300000, 71100000, 82000000 }, 2161 .hactive = { 1280, 1280, 1280 }, 2162 .hfront_porch = { 1, 1, 10 }, 2163 .hback_porch = { 1, 1, 10 }, 2164 .hsync_len = { 58, 158, 661 }, 2165 .vactive = { 800, 800, 800 }, 2166 .vfront_porch = { 1, 1, 10 }, 2167 .vback_porch = { 1, 1, 10 }, 2168 .vsync_len = { 1, 21, 203 }, 2169 .flags = DISPLAY_FLAGS_DE_HIGH, 2170 }; 2171 2172 static const struct panel_desc hannstar_hsd101pww2 = { 2173 .timings = &hannstar_hsd101pww2_timing, 2174 .num_timings = 1, 2175 .bpc = 8, 2176 .size = { 2177 .width = 217, 2178 .height = 136, 2179 }, 2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2181 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2182 }; 2183 2184 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2185 .clock = 33333, 2186 .hdisplay = 800, 2187 .hsync_start = 800 + 85, 2188 .hsync_end = 800 + 85 + 86, 2189 .htotal = 800 + 85 + 86 + 85, 2190 .vdisplay = 480, 2191 .vsync_start = 480 + 16, 2192 .vsync_end = 480 + 16 + 13, 2193 .vtotal = 480 + 16 + 13 + 16, 2194 }; 2195 2196 static const struct panel_desc hitachi_tx23d38vm0caa = { 2197 .modes = &hitachi_tx23d38vm0caa_mode, 2198 .num_modes = 1, 2199 .bpc = 6, 2200 .size = { 2201 .width = 195, 2202 .height = 117, 2203 }, 2204 .delay = { 2205 .enable = 160, 2206 .disable = 160, 2207 }, 2208 }; 2209 2210 static const struct drm_display_mode innolux_at043tn24_mode = { 2211 .clock = 9000, 2212 .hdisplay = 480, 2213 .hsync_start = 480 + 2, 2214 .hsync_end = 480 + 2 + 41, 2215 .htotal = 480 + 2 + 41 + 2, 2216 .vdisplay = 272, 2217 .vsync_start = 272 + 2, 2218 .vsync_end = 272 + 2 + 10, 2219 .vtotal = 272 + 2 + 10 + 2, 2220 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2221 }; 2222 2223 static const struct panel_desc innolux_at043tn24 = { 2224 .modes = &innolux_at043tn24_mode, 2225 .num_modes = 1, 2226 .bpc = 8, 2227 .size = { 2228 .width = 95, 2229 .height = 54, 2230 }, 2231 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2232 .connector_type = DRM_MODE_CONNECTOR_DPI, 2233 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2234 }; 2235 2236 static const struct drm_display_mode innolux_at070tn92_mode = { 2237 .clock = 33333, 2238 .hdisplay = 800, 2239 .hsync_start = 800 + 210, 2240 .hsync_end = 800 + 210 + 20, 2241 .htotal = 800 + 210 + 20 + 46, 2242 .vdisplay = 480, 2243 .vsync_start = 480 + 22, 2244 .vsync_end = 480 + 22 + 10, 2245 .vtotal = 480 + 22 + 23 + 10, 2246 }; 2247 2248 static const struct panel_desc innolux_at070tn92 = { 2249 .modes = &innolux_at070tn92_mode, 2250 .num_modes = 1, 2251 .size = { 2252 .width = 154, 2253 .height = 86, 2254 }, 2255 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2256 }; 2257 2258 static const struct display_timing innolux_g070ace_l01_timing = { 2259 .pixelclock = { 25200000, 35000000, 35700000 }, 2260 .hactive = { 800, 800, 800 }, 2261 .hfront_porch = { 30, 32, 87 }, 2262 .hback_porch = { 30, 32, 87 }, 2263 .hsync_len = { 1, 1, 1 }, 2264 .vactive = { 480, 480, 480 }, 2265 .vfront_porch = { 3, 3, 3 }, 2266 .vback_porch = { 13, 13, 13 }, 2267 .vsync_len = { 1, 1, 4 }, 2268 .flags = DISPLAY_FLAGS_DE_HIGH, 2269 }; 2270 2271 static const struct panel_desc innolux_g070ace_l01 = { 2272 .timings = &innolux_g070ace_l01_timing, 2273 .num_timings = 1, 2274 .bpc = 8, 2275 .size = { 2276 .width = 152, 2277 .height = 91, 2278 }, 2279 .delay = { 2280 .prepare = 10, 2281 .enable = 50, 2282 .disable = 50, 2283 .unprepare = 500, 2284 }, 2285 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2286 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2287 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2288 }; 2289 2290 static const struct display_timing innolux_g070y2_l01_timing = { 2291 .pixelclock = { 28000000, 29500000, 32000000 }, 2292 .hactive = { 800, 800, 800 }, 2293 .hfront_porch = { 61, 91, 141 }, 2294 .hback_porch = { 60, 90, 140 }, 2295 .hsync_len = { 12, 12, 12 }, 2296 .vactive = { 480, 480, 480 }, 2297 .vfront_porch = { 4, 9, 30 }, 2298 .vback_porch = { 4, 8, 28 }, 2299 .vsync_len = { 2, 2, 2 }, 2300 .flags = DISPLAY_FLAGS_DE_HIGH, 2301 }; 2302 2303 static const struct panel_desc innolux_g070y2_l01 = { 2304 .timings = &innolux_g070y2_l01_timing, 2305 .num_timings = 1, 2306 .bpc = 8, 2307 .size = { 2308 .width = 152, 2309 .height = 91, 2310 }, 2311 .delay = { 2312 .prepare = 10, 2313 .enable = 100, 2314 .disable = 100, 2315 .unprepare = 800, 2316 }, 2317 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2318 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2319 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2320 }; 2321 2322 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2323 .clock = 33333, 2324 .hdisplay = 800, 2325 .hsync_start = 800 + 210, 2326 .hsync_end = 800 + 210 + 20, 2327 .htotal = 800 + 210 + 20 + 46, 2328 .vdisplay = 480, 2329 .vsync_start = 480 + 22, 2330 .vsync_end = 480 + 22 + 10, 2331 .vtotal = 480 + 22 + 23 + 10, 2332 }; 2333 2334 static const struct panel_desc innolux_g070y2_t02 = { 2335 .modes = &innolux_g070y2_t02_mode, 2336 .num_modes = 1, 2337 .bpc = 8, 2338 .size = { 2339 .width = 152, 2340 .height = 92, 2341 }, 2342 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2343 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2344 .connector_type = DRM_MODE_CONNECTOR_DPI, 2345 }; 2346 2347 static const struct display_timing innolux_g101ice_l01_timing = { 2348 .pixelclock = { 60400000, 71100000, 74700000 }, 2349 .hactive = { 1280, 1280, 1280 }, 2350 .hfront_porch = { 41, 80, 100 }, 2351 .hback_porch = { 40, 79, 99 }, 2352 .hsync_len = { 1, 1, 1 }, 2353 .vactive = { 800, 800, 800 }, 2354 .vfront_porch = { 5, 11, 14 }, 2355 .vback_porch = { 4, 11, 14 }, 2356 .vsync_len = { 1, 1, 1 }, 2357 .flags = DISPLAY_FLAGS_DE_HIGH, 2358 }; 2359 2360 static const struct panel_desc innolux_g101ice_l01 = { 2361 .timings = &innolux_g101ice_l01_timing, 2362 .num_timings = 1, 2363 .bpc = 8, 2364 .size = { 2365 .width = 217, 2366 .height = 135, 2367 }, 2368 .delay = { 2369 .enable = 200, 2370 .disable = 200, 2371 }, 2372 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2373 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2374 }; 2375 2376 static const struct display_timing innolux_g121i1_l01_timing = { 2377 .pixelclock = { 67450000, 71000000, 74550000 }, 2378 .hactive = { 1280, 1280, 1280 }, 2379 .hfront_porch = { 40, 80, 160 }, 2380 .hback_porch = { 39, 79, 159 }, 2381 .hsync_len = { 1, 1, 1 }, 2382 .vactive = { 800, 800, 800 }, 2383 .vfront_porch = { 5, 11, 100 }, 2384 .vback_porch = { 4, 11, 99 }, 2385 .vsync_len = { 1, 1, 1 }, 2386 }; 2387 2388 static const struct panel_desc innolux_g121i1_l01 = { 2389 .timings = &innolux_g121i1_l01_timing, 2390 .num_timings = 1, 2391 .bpc = 6, 2392 .size = { 2393 .width = 261, 2394 .height = 163, 2395 }, 2396 .delay = { 2397 .enable = 200, 2398 .disable = 20, 2399 }, 2400 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2402 }; 2403 2404 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2405 .clock = 65000, 2406 .hdisplay = 1024, 2407 .hsync_start = 1024 + 0, 2408 .hsync_end = 1024 + 1, 2409 .htotal = 1024 + 0 + 1 + 320, 2410 .vdisplay = 768, 2411 .vsync_start = 768 + 38, 2412 .vsync_end = 768 + 38 + 1, 2413 .vtotal = 768 + 38 + 1 + 0, 2414 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2415 }; 2416 2417 static const struct panel_desc innolux_g121x1_l03 = { 2418 .modes = &innolux_g121x1_l03_mode, 2419 .num_modes = 1, 2420 .bpc = 6, 2421 .size = { 2422 .width = 246, 2423 .height = 185, 2424 }, 2425 .delay = { 2426 .enable = 200, 2427 .unprepare = 200, 2428 .disable = 400, 2429 }, 2430 }; 2431 2432 static const struct display_timing innolux_g156hce_l01_timings = { 2433 .pixelclock = { 120000000, 141860000, 150000000 }, 2434 .hactive = { 1920, 1920, 1920 }, 2435 .hfront_porch = { 80, 90, 100 }, 2436 .hback_porch = { 80, 90, 100 }, 2437 .hsync_len = { 20, 30, 30 }, 2438 .vactive = { 1080, 1080, 1080 }, 2439 .vfront_porch = { 3, 10, 20 }, 2440 .vback_porch = { 3, 10, 20 }, 2441 .vsync_len = { 4, 10, 10 }, 2442 }; 2443 2444 static const struct panel_desc innolux_g156hce_l01 = { 2445 .timings = &innolux_g156hce_l01_timings, 2446 .num_timings = 1, 2447 .bpc = 8, 2448 .size = { 2449 .width = 344, 2450 .height = 194, 2451 }, 2452 .delay = { 2453 .prepare = 1, /* T1+T2 */ 2454 .enable = 450, /* T5 */ 2455 .disable = 200, /* T6 */ 2456 .unprepare = 10, /* T3+T7 */ 2457 }, 2458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2459 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2460 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2461 }; 2462 2463 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2464 .clock = 69300, 2465 .hdisplay = 1366, 2466 .hsync_start = 1366 + 16, 2467 .hsync_end = 1366 + 16 + 34, 2468 .htotal = 1366 + 16 + 34 + 50, 2469 .vdisplay = 768, 2470 .vsync_start = 768 + 2, 2471 .vsync_end = 768 + 2 + 6, 2472 .vtotal = 768 + 2 + 6 + 12, 2473 }; 2474 2475 static const struct panel_desc innolux_n156bge_l21 = { 2476 .modes = &innolux_n156bge_l21_mode, 2477 .num_modes = 1, 2478 .bpc = 6, 2479 .size = { 2480 .width = 344, 2481 .height = 193, 2482 }, 2483 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2484 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2485 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2486 }; 2487 2488 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2489 .clock = 51501, 2490 .hdisplay = 1024, 2491 .hsync_start = 1024 + 128, 2492 .hsync_end = 1024 + 128 + 64, 2493 .htotal = 1024 + 128 + 64 + 128, 2494 .vdisplay = 600, 2495 .vsync_start = 600 + 16, 2496 .vsync_end = 600 + 16 + 4, 2497 .vtotal = 600 + 16 + 4 + 16, 2498 }; 2499 2500 static const struct panel_desc innolux_zj070na_01p = { 2501 .modes = &innolux_zj070na_01p_mode, 2502 .num_modes = 1, 2503 .bpc = 6, 2504 .size = { 2505 .width = 154, 2506 .height = 90, 2507 }, 2508 }; 2509 2510 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2511 .pixelclock = { 5580000, 5850000, 6200000 }, 2512 .hactive = { 320, 320, 320 }, 2513 .hfront_porch = { 30, 30, 30 }, 2514 .hback_porch = { 30, 30, 30 }, 2515 .hsync_len = { 1, 5, 17 }, 2516 .vactive = { 240, 240, 240 }, 2517 .vfront_porch = { 6, 6, 6 }, 2518 .vback_porch = { 5, 5, 5 }, 2519 .vsync_len = { 1, 2, 11 }, 2520 .flags = DISPLAY_FLAGS_DE_HIGH, 2521 }; 2522 2523 static const struct panel_desc koe_tx14d24vm1bpa = { 2524 .timings = &koe_tx14d24vm1bpa_timing, 2525 .num_timings = 1, 2526 .bpc = 6, 2527 .size = { 2528 .width = 115, 2529 .height = 86, 2530 }, 2531 }; 2532 2533 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2534 .pixelclock = { 151820000, 156720000, 159780000 }, 2535 .hactive = { 1920, 1920, 1920 }, 2536 .hfront_porch = { 105, 130, 142 }, 2537 .hback_porch = { 45, 70, 82 }, 2538 .hsync_len = { 30, 30, 30 }, 2539 .vactive = { 1200, 1200, 1200}, 2540 .vfront_porch = { 3, 5, 10 }, 2541 .vback_porch = { 2, 5, 10 }, 2542 .vsync_len = { 5, 5, 5 }, 2543 }; 2544 2545 static const struct panel_desc koe_tx26d202vm0bwa = { 2546 .timings = &koe_tx26d202vm0bwa_timing, 2547 .num_timings = 1, 2548 .bpc = 8, 2549 .size = { 2550 .width = 217, 2551 .height = 136, 2552 }, 2553 .delay = { 2554 .prepare = 1000, 2555 .enable = 1000, 2556 .unprepare = 1000, 2557 .disable = 1000, 2558 }, 2559 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2560 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2561 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2562 }; 2563 2564 static const struct display_timing koe_tx31d200vm0baa_timing = { 2565 .pixelclock = { 39600000, 43200000, 48000000 }, 2566 .hactive = { 1280, 1280, 1280 }, 2567 .hfront_porch = { 16, 36, 56 }, 2568 .hback_porch = { 16, 36, 56 }, 2569 .hsync_len = { 8, 8, 8 }, 2570 .vactive = { 480, 480, 480 }, 2571 .vfront_porch = { 6, 21, 33 }, 2572 .vback_porch = { 6, 21, 33 }, 2573 .vsync_len = { 8, 8, 8 }, 2574 .flags = DISPLAY_FLAGS_DE_HIGH, 2575 }; 2576 2577 static const struct panel_desc koe_tx31d200vm0baa = { 2578 .timings = &koe_tx31d200vm0baa_timing, 2579 .num_timings = 1, 2580 .bpc = 6, 2581 .size = { 2582 .width = 292, 2583 .height = 109, 2584 }, 2585 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2586 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2587 }; 2588 2589 static const struct display_timing kyo_tcg121xglp_timing = { 2590 .pixelclock = { 52000000, 65000000, 71000000 }, 2591 .hactive = { 1024, 1024, 1024 }, 2592 .hfront_porch = { 2, 2, 2 }, 2593 .hback_porch = { 2, 2, 2 }, 2594 .hsync_len = { 86, 124, 244 }, 2595 .vactive = { 768, 768, 768 }, 2596 .vfront_porch = { 2, 2, 2 }, 2597 .vback_porch = { 2, 2, 2 }, 2598 .vsync_len = { 6, 34, 73 }, 2599 .flags = DISPLAY_FLAGS_DE_HIGH, 2600 }; 2601 2602 static const struct panel_desc kyo_tcg121xglp = { 2603 .timings = &kyo_tcg121xglp_timing, 2604 .num_timings = 1, 2605 .bpc = 8, 2606 .size = { 2607 .width = 246, 2608 .height = 184, 2609 }, 2610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2611 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2612 }; 2613 2614 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2615 .clock = 7000, 2616 .hdisplay = 320, 2617 .hsync_start = 320 + 20, 2618 .hsync_end = 320 + 20 + 30, 2619 .htotal = 320 + 20 + 30 + 38, 2620 .vdisplay = 240, 2621 .vsync_start = 240 + 4, 2622 .vsync_end = 240 + 4 + 3, 2623 .vtotal = 240 + 4 + 3 + 15, 2624 }; 2625 2626 static const struct panel_desc lemaker_bl035_rgb_002 = { 2627 .modes = &lemaker_bl035_rgb_002_mode, 2628 .num_modes = 1, 2629 .size = { 2630 .width = 70, 2631 .height = 52, 2632 }, 2633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2634 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2635 }; 2636 2637 static const struct drm_display_mode lg_lb070wv8_mode = { 2638 .clock = 33246, 2639 .hdisplay = 800, 2640 .hsync_start = 800 + 88, 2641 .hsync_end = 800 + 88 + 80, 2642 .htotal = 800 + 88 + 80 + 88, 2643 .vdisplay = 480, 2644 .vsync_start = 480 + 10, 2645 .vsync_end = 480 + 10 + 25, 2646 .vtotal = 480 + 10 + 25 + 10, 2647 }; 2648 2649 static const struct panel_desc lg_lb070wv8 = { 2650 .modes = &lg_lb070wv8_mode, 2651 .num_modes = 1, 2652 .bpc = 8, 2653 .size = { 2654 .width = 151, 2655 .height = 91, 2656 }, 2657 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2658 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2659 }; 2660 2661 static const struct display_timing logictechno_lt161010_2nh_timing = { 2662 .pixelclock = { 26400000, 33300000, 46800000 }, 2663 .hactive = { 800, 800, 800 }, 2664 .hfront_porch = { 16, 210, 354 }, 2665 .hback_porch = { 46, 46, 46 }, 2666 .hsync_len = { 1, 20, 40 }, 2667 .vactive = { 480, 480, 480 }, 2668 .vfront_porch = { 7, 22, 147 }, 2669 .vback_porch = { 23, 23, 23 }, 2670 .vsync_len = { 1, 10, 20 }, 2671 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2672 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2673 DISPLAY_FLAGS_SYNC_POSEDGE, 2674 }; 2675 2676 static const struct panel_desc logictechno_lt161010_2nh = { 2677 .timings = &logictechno_lt161010_2nh_timing, 2678 .num_timings = 1, 2679 .bpc = 6, 2680 .size = { 2681 .width = 154, 2682 .height = 86, 2683 }, 2684 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2685 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2686 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2687 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2688 .connector_type = DRM_MODE_CONNECTOR_DPI, 2689 }; 2690 2691 static const struct display_timing logictechno_lt170410_2whc_timing = { 2692 .pixelclock = { 68900000, 71100000, 73400000 }, 2693 .hactive = { 1280, 1280, 1280 }, 2694 .hfront_porch = { 23, 60, 71 }, 2695 .hback_porch = { 23, 60, 71 }, 2696 .hsync_len = { 15, 40, 47 }, 2697 .vactive = { 800, 800, 800 }, 2698 .vfront_porch = { 5, 7, 10 }, 2699 .vback_porch = { 5, 7, 10 }, 2700 .vsync_len = { 6, 9, 12 }, 2701 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2702 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2703 DISPLAY_FLAGS_SYNC_POSEDGE, 2704 }; 2705 2706 static const struct panel_desc logictechno_lt170410_2whc = { 2707 .timings = &logictechno_lt170410_2whc_timing, 2708 .num_timings = 1, 2709 .bpc = 8, 2710 .size = { 2711 .width = 217, 2712 .height = 136, 2713 }, 2714 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2715 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2716 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2717 }; 2718 2719 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2720 .clock = 33000, 2721 .hdisplay = 800, 2722 .hsync_start = 800 + 112, 2723 .hsync_end = 800 + 112 + 3, 2724 .htotal = 800 + 112 + 3 + 85, 2725 .vdisplay = 480, 2726 .vsync_start = 480 + 38, 2727 .vsync_end = 480 + 38 + 3, 2728 .vtotal = 480 + 38 + 3 + 29, 2729 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2730 }; 2731 2732 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2733 .modes = &logictechno_lttd800480070_l2rt_mode, 2734 .num_modes = 1, 2735 .bpc = 8, 2736 .size = { 2737 .width = 154, 2738 .height = 86, 2739 }, 2740 .delay = { 2741 .prepare = 45, 2742 .enable = 100, 2743 .disable = 100, 2744 .unprepare = 45 2745 }, 2746 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2747 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2748 .connector_type = DRM_MODE_CONNECTOR_DPI, 2749 }; 2750 2751 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2752 .clock = 33000, 2753 .hdisplay = 800, 2754 .hsync_start = 800 + 154, 2755 .hsync_end = 800 + 154 + 3, 2756 .htotal = 800 + 154 + 3 + 43, 2757 .vdisplay = 480, 2758 .vsync_start = 480 + 47, 2759 .vsync_end = 480 + 47 + 3, 2760 .vtotal = 480 + 47 + 3 + 20, 2761 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2762 }; 2763 2764 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2765 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2766 .num_modes = 1, 2767 .bpc = 8, 2768 .size = { 2769 .width = 154, 2770 .height = 86, 2771 }, 2772 .delay = { 2773 .prepare = 45, 2774 .enable = 100, 2775 .disable = 100, 2776 .unprepare = 45 2777 }, 2778 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2779 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2780 .connector_type = DRM_MODE_CONNECTOR_DPI, 2781 }; 2782 2783 static const struct drm_display_mode logicpd_type_28_mode = { 2784 .clock = 9107, 2785 .hdisplay = 480, 2786 .hsync_start = 480 + 3, 2787 .hsync_end = 480 + 3 + 42, 2788 .htotal = 480 + 3 + 42 + 2, 2789 2790 .vdisplay = 272, 2791 .vsync_start = 272 + 2, 2792 .vsync_end = 272 + 2 + 11, 2793 .vtotal = 272 + 2 + 11 + 3, 2794 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2795 }; 2796 2797 static const struct panel_desc logicpd_type_28 = { 2798 .modes = &logicpd_type_28_mode, 2799 .num_modes = 1, 2800 .bpc = 8, 2801 .size = { 2802 .width = 105, 2803 .height = 67, 2804 }, 2805 .delay = { 2806 .prepare = 200, 2807 .enable = 200, 2808 .unprepare = 200, 2809 .disable = 200, 2810 }, 2811 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2812 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2813 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2814 .connector_type = DRM_MODE_CONNECTOR_DPI, 2815 }; 2816 2817 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2818 .clock = 30400, 2819 .hdisplay = 800, 2820 .hsync_start = 800 + 0, 2821 .hsync_end = 800 + 1, 2822 .htotal = 800 + 0 + 1 + 160, 2823 .vdisplay = 480, 2824 .vsync_start = 480 + 0, 2825 .vsync_end = 480 + 48 + 1, 2826 .vtotal = 480 + 48 + 1 + 0, 2827 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2828 }; 2829 2830 static const struct panel_desc mitsubishi_aa070mc01 = { 2831 .modes = &mitsubishi_aa070mc01_mode, 2832 .num_modes = 1, 2833 .bpc = 8, 2834 .size = { 2835 .width = 152, 2836 .height = 91, 2837 }, 2838 2839 .delay = { 2840 .enable = 200, 2841 .unprepare = 200, 2842 .disable = 400, 2843 }, 2844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2845 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2846 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2847 }; 2848 2849 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 2850 .clock = 56234, 2851 .hdisplay = 1024, 2852 .hsync_start = 1024 + 24, 2853 .hsync_end = 1024 + 24 + 63, 2854 .htotal = 1024 + 24 + 63 + 1, 2855 .vdisplay = 768, 2856 .vsync_start = 768 + 3, 2857 .vsync_end = 768 + 3 + 6, 2858 .vtotal = 768 + 3 + 6 + 1, 2859 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2860 }; 2861 2862 static const struct panel_desc mitsubishi_aa084xe01 = { 2863 .modes = &mitsubishi_aa084xe01_mode, 2864 .num_modes = 1, 2865 .bpc = 8, 2866 .size = { 2867 .width = 1024, 2868 .height = 768, 2869 }, 2870 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2871 .connector_type = DRM_MODE_CONNECTOR_DPI, 2872 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2873 }; 2874 2875 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2876 .pixelclock = { 29000000, 33000000, 38000000 }, 2877 .hactive = { 800, 800, 800 }, 2878 .hfront_porch = { 180, 210, 240 }, 2879 .hback_porch = { 16, 16, 16 }, 2880 .hsync_len = { 30, 30, 30 }, 2881 .vactive = { 480, 480, 480 }, 2882 .vfront_porch = { 12, 22, 32 }, 2883 .vback_porch = { 10, 10, 10 }, 2884 .vsync_len = { 13, 13, 13 }, 2885 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2886 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2887 DISPLAY_FLAGS_SYNC_POSEDGE, 2888 }; 2889 2890 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2891 .timings = &multi_inno_mi0700s4t_6_timing, 2892 .num_timings = 1, 2893 .bpc = 8, 2894 .size = { 2895 .width = 154, 2896 .height = 86, 2897 }, 2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2899 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2900 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2901 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2902 .connector_type = DRM_MODE_CONNECTOR_DPI, 2903 }; 2904 2905 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2906 .pixelclock = { 32000000, 40000000, 50000000 }, 2907 .hactive = { 800, 800, 800 }, 2908 .hfront_porch = { 16, 210, 354 }, 2909 .hback_porch = { 6, 26, 45 }, 2910 .hsync_len = { 1, 20, 40 }, 2911 .vactive = { 600, 600, 600 }, 2912 .vfront_porch = { 1, 12, 77 }, 2913 .vback_porch = { 3, 13, 22 }, 2914 .vsync_len = { 1, 10, 20 }, 2915 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2916 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2917 DISPLAY_FLAGS_SYNC_POSEDGE, 2918 }; 2919 2920 static const struct panel_desc multi_inno_mi0800ft_9 = { 2921 .timings = &multi_inno_mi0800ft_9_timing, 2922 .num_timings = 1, 2923 .bpc = 8, 2924 .size = { 2925 .width = 162, 2926 .height = 122, 2927 }, 2928 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2929 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2930 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2931 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2932 .connector_type = DRM_MODE_CONNECTOR_DPI, 2933 }; 2934 2935 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2936 .pixelclock = { 68900000, 70000000, 73400000 }, 2937 .hactive = { 1280, 1280, 1280 }, 2938 .hfront_porch = { 30, 60, 71 }, 2939 .hback_porch = { 30, 60, 71 }, 2940 .hsync_len = { 10, 10, 48 }, 2941 .vactive = { 800, 800, 800 }, 2942 .vfront_porch = { 5, 10, 10 }, 2943 .vback_porch = { 5, 10, 10 }, 2944 .vsync_len = { 5, 6, 13 }, 2945 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2946 DISPLAY_FLAGS_DE_HIGH, 2947 }; 2948 2949 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2950 .timings = &multi_inno_mi1010ait_1cp_timing, 2951 .num_timings = 1, 2952 .bpc = 8, 2953 .size = { 2954 .width = 217, 2955 .height = 136, 2956 }, 2957 .delay = { 2958 .enable = 50, 2959 .disable = 50, 2960 }, 2961 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2962 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2964 }; 2965 2966 static const struct display_timing nec_nl12880bc20_05_timing = { 2967 .pixelclock = { 67000000, 71000000, 75000000 }, 2968 .hactive = { 1280, 1280, 1280 }, 2969 .hfront_porch = { 2, 30, 30 }, 2970 .hback_porch = { 6, 100, 100 }, 2971 .hsync_len = { 2, 30, 30 }, 2972 .vactive = { 800, 800, 800 }, 2973 .vfront_porch = { 5, 5, 5 }, 2974 .vback_porch = { 11, 11, 11 }, 2975 .vsync_len = { 7, 7, 7 }, 2976 }; 2977 2978 static const struct panel_desc nec_nl12880bc20_05 = { 2979 .timings = &nec_nl12880bc20_05_timing, 2980 .num_timings = 1, 2981 .bpc = 8, 2982 .size = { 2983 .width = 261, 2984 .height = 163, 2985 }, 2986 .delay = { 2987 .enable = 50, 2988 .disable = 50, 2989 }, 2990 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2991 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2992 }; 2993 2994 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2995 .clock = 10870, 2996 .hdisplay = 480, 2997 .hsync_start = 480 + 2, 2998 .hsync_end = 480 + 2 + 41, 2999 .htotal = 480 + 2 + 41 + 2, 3000 .vdisplay = 272, 3001 .vsync_start = 272 + 2, 3002 .vsync_end = 272 + 2 + 4, 3003 .vtotal = 272 + 2 + 4 + 2, 3004 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3005 }; 3006 3007 static const struct panel_desc nec_nl4827hc19_05b = { 3008 .modes = &nec_nl4827hc19_05b_mode, 3009 .num_modes = 1, 3010 .bpc = 8, 3011 .size = { 3012 .width = 95, 3013 .height = 54, 3014 }, 3015 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3016 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3017 }; 3018 3019 static const struct drm_display_mode netron_dy_e231732_mode = { 3020 .clock = 66000, 3021 .hdisplay = 1024, 3022 .hsync_start = 1024 + 160, 3023 .hsync_end = 1024 + 160 + 70, 3024 .htotal = 1024 + 160 + 70 + 90, 3025 .vdisplay = 600, 3026 .vsync_start = 600 + 127, 3027 .vsync_end = 600 + 127 + 20, 3028 .vtotal = 600 + 127 + 20 + 3, 3029 }; 3030 3031 static const struct panel_desc netron_dy_e231732 = { 3032 .modes = &netron_dy_e231732_mode, 3033 .num_modes = 1, 3034 .size = { 3035 .width = 154, 3036 .height = 87, 3037 }, 3038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3039 }; 3040 3041 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3042 .clock = 9000, 3043 .hdisplay = 480, 3044 .hsync_start = 480 + 2, 3045 .hsync_end = 480 + 2 + 41, 3046 .htotal = 480 + 2 + 41 + 2, 3047 .vdisplay = 272, 3048 .vsync_start = 272 + 2, 3049 .vsync_end = 272 + 2 + 10, 3050 .vtotal = 272 + 2 + 10 + 2, 3051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3052 }; 3053 3054 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3055 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3056 .num_modes = 1, 3057 .bpc = 8, 3058 .size = { 3059 .width = 95, 3060 .height = 54, 3061 }, 3062 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3063 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3064 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3065 .connector_type = DRM_MODE_CONNECTOR_DPI, 3066 }; 3067 3068 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3069 .pixelclock = { 130000000, 148350000, 163000000 }, 3070 .hactive = { 1920, 1920, 1920 }, 3071 .hfront_porch = { 80, 100, 100 }, 3072 .hback_porch = { 100, 120, 120 }, 3073 .hsync_len = { 50, 60, 60 }, 3074 .vactive = { 1080, 1080, 1080 }, 3075 .vfront_porch = { 12, 30, 30 }, 3076 .vback_porch = { 4, 10, 10 }, 3077 .vsync_len = { 4, 5, 5 }, 3078 }; 3079 3080 static const struct panel_desc nlt_nl192108ac18_02d = { 3081 .timings = &nlt_nl192108ac18_02d_timing, 3082 .num_timings = 1, 3083 .bpc = 8, 3084 .size = { 3085 .width = 344, 3086 .height = 194, 3087 }, 3088 .delay = { 3089 .unprepare = 500, 3090 }, 3091 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3092 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3093 }; 3094 3095 static const struct drm_display_mode nvd_9128_mode = { 3096 .clock = 29500, 3097 .hdisplay = 800, 3098 .hsync_start = 800 + 130, 3099 .hsync_end = 800 + 130 + 98, 3100 .htotal = 800 + 0 + 130 + 98, 3101 .vdisplay = 480, 3102 .vsync_start = 480 + 10, 3103 .vsync_end = 480 + 10 + 50, 3104 .vtotal = 480 + 0 + 10 + 50, 3105 }; 3106 3107 static const struct panel_desc nvd_9128 = { 3108 .modes = &nvd_9128_mode, 3109 .num_modes = 1, 3110 .bpc = 8, 3111 .size = { 3112 .width = 156, 3113 .height = 88, 3114 }, 3115 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3116 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3117 }; 3118 3119 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3120 .pixelclock = { 30000000, 30000000, 40000000 }, 3121 .hactive = { 800, 800, 800 }, 3122 .hfront_porch = { 40, 40, 40 }, 3123 .hback_porch = { 40, 40, 40 }, 3124 .hsync_len = { 1, 48, 48 }, 3125 .vactive = { 480, 480, 480 }, 3126 .vfront_porch = { 13, 13, 13 }, 3127 .vback_porch = { 29, 29, 29 }, 3128 .vsync_len = { 3, 3, 3 }, 3129 .flags = DISPLAY_FLAGS_DE_HIGH, 3130 }; 3131 3132 static const struct panel_desc okaya_rs800480t_7x0gp = { 3133 .timings = &okaya_rs800480t_7x0gp_timing, 3134 .num_timings = 1, 3135 .bpc = 6, 3136 .size = { 3137 .width = 154, 3138 .height = 87, 3139 }, 3140 .delay = { 3141 .prepare = 41, 3142 .enable = 50, 3143 .unprepare = 41, 3144 .disable = 50, 3145 }, 3146 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3147 }; 3148 3149 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3150 .clock = 9000, 3151 .hdisplay = 480, 3152 .hsync_start = 480 + 5, 3153 .hsync_end = 480 + 5 + 30, 3154 .htotal = 480 + 5 + 30 + 10, 3155 .vdisplay = 272, 3156 .vsync_start = 272 + 8, 3157 .vsync_end = 272 + 8 + 5, 3158 .vtotal = 272 + 8 + 5 + 3, 3159 }; 3160 3161 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3162 .modes = &olimex_lcd_olinuxino_43ts_mode, 3163 .num_modes = 1, 3164 .size = { 3165 .width = 95, 3166 .height = 54, 3167 }, 3168 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3169 }; 3170 3171 /* 3172 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3173 * pixel clocks, but this is the timing that was being used in the Adafruit 3174 * installation instructions. 3175 */ 3176 static const struct drm_display_mode ontat_yx700wv03_mode = { 3177 .clock = 29500, 3178 .hdisplay = 800, 3179 .hsync_start = 824, 3180 .hsync_end = 896, 3181 .htotal = 992, 3182 .vdisplay = 480, 3183 .vsync_start = 483, 3184 .vsync_end = 493, 3185 .vtotal = 500, 3186 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3187 }; 3188 3189 /* 3190 * Specification at: 3191 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3192 */ 3193 static const struct panel_desc ontat_yx700wv03 = { 3194 .modes = &ontat_yx700wv03_mode, 3195 .num_modes = 1, 3196 .bpc = 8, 3197 .size = { 3198 .width = 154, 3199 .height = 83, 3200 }, 3201 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3202 }; 3203 3204 static const struct drm_display_mode ortustech_com37h3m_mode = { 3205 .clock = 22230, 3206 .hdisplay = 480, 3207 .hsync_start = 480 + 40, 3208 .hsync_end = 480 + 40 + 10, 3209 .htotal = 480 + 40 + 10 + 40, 3210 .vdisplay = 640, 3211 .vsync_start = 640 + 4, 3212 .vsync_end = 640 + 4 + 2, 3213 .vtotal = 640 + 4 + 2 + 4, 3214 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3215 }; 3216 3217 static const struct panel_desc ortustech_com37h3m = { 3218 .modes = &ortustech_com37h3m_mode, 3219 .num_modes = 1, 3220 .bpc = 8, 3221 .size = { 3222 .width = 56, /* 56.16mm */ 3223 .height = 75, /* 74.88mm */ 3224 }, 3225 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3226 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3227 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3228 }; 3229 3230 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3231 .clock = 25000, 3232 .hdisplay = 480, 3233 .hsync_start = 480 + 10, 3234 .hsync_end = 480 + 10 + 10, 3235 .htotal = 480 + 10 + 10 + 15, 3236 .vdisplay = 800, 3237 .vsync_start = 800 + 3, 3238 .vsync_end = 800 + 3 + 3, 3239 .vtotal = 800 + 3 + 3 + 3, 3240 }; 3241 3242 static const struct panel_desc ortustech_com43h4m85ulc = { 3243 .modes = &ortustech_com43h4m85ulc_mode, 3244 .num_modes = 1, 3245 .bpc = 6, 3246 .size = { 3247 .width = 56, 3248 .height = 93, 3249 }, 3250 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3251 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3252 .connector_type = DRM_MODE_CONNECTOR_DPI, 3253 }; 3254 3255 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3256 .clock = 33000, 3257 .hdisplay = 800, 3258 .hsync_start = 800 + 210, 3259 .hsync_end = 800 + 210 + 30, 3260 .htotal = 800 + 210 + 30 + 16, 3261 .vdisplay = 480, 3262 .vsync_start = 480 + 22, 3263 .vsync_end = 480 + 22 + 13, 3264 .vtotal = 480 + 22 + 13 + 10, 3265 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3266 }; 3267 3268 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3269 .modes = &osddisplays_osd070t1718_19ts_mode, 3270 .num_modes = 1, 3271 .bpc = 8, 3272 .size = { 3273 .width = 152, 3274 .height = 91, 3275 }, 3276 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3277 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3278 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3279 .connector_type = DRM_MODE_CONNECTOR_DPI, 3280 }; 3281 3282 static const struct drm_display_mode pda_91_00156_a0_mode = { 3283 .clock = 33300, 3284 .hdisplay = 800, 3285 .hsync_start = 800 + 1, 3286 .hsync_end = 800 + 1 + 64, 3287 .htotal = 800 + 1 + 64 + 64, 3288 .vdisplay = 480, 3289 .vsync_start = 480 + 1, 3290 .vsync_end = 480 + 1 + 23, 3291 .vtotal = 480 + 1 + 23 + 22, 3292 }; 3293 3294 static const struct panel_desc pda_91_00156_a0 = { 3295 .modes = &pda_91_00156_a0_mode, 3296 .num_modes = 1, 3297 .size = { 3298 .width = 152, 3299 .height = 91, 3300 }, 3301 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3302 }; 3303 3304 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3305 .clock = 24750, 3306 .hdisplay = 800, 3307 .hsync_start = 800 + 54, 3308 .hsync_end = 800 + 54 + 2, 3309 .htotal = 800 + 54 + 2 + 44, 3310 .vdisplay = 480, 3311 .vsync_start = 480 + 49, 3312 .vsync_end = 480 + 49 + 2, 3313 .vtotal = 480 + 49 + 2 + 22, 3314 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3315 }; 3316 3317 static const struct panel_desc powertip_ph800480t013_idf02 = { 3318 .modes = &powertip_ph800480t013_idf02_mode, 3319 .num_modes = 1, 3320 .bpc = 8, 3321 .size = { 3322 .width = 152, 3323 .height = 91, 3324 }, 3325 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3326 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3327 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3328 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3329 .connector_type = DRM_MODE_CONNECTOR_DPI, 3330 }; 3331 3332 static const struct drm_display_mode qd43003c0_40_mode = { 3333 .clock = 9000, 3334 .hdisplay = 480, 3335 .hsync_start = 480 + 8, 3336 .hsync_end = 480 + 8 + 4, 3337 .htotal = 480 + 8 + 4 + 39, 3338 .vdisplay = 272, 3339 .vsync_start = 272 + 4, 3340 .vsync_end = 272 + 4 + 10, 3341 .vtotal = 272 + 4 + 10 + 2, 3342 }; 3343 3344 static const struct panel_desc qd43003c0_40 = { 3345 .modes = &qd43003c0_40_mode, 3346 .num_modes = 1, 3347 .bpc = 8, 3348 .size = { 3349 .width = 95, 3350 .height = 53, 3351 }, 3352 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3353 }; 3354 3355 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3356 { /* 60 Hz */ 3357 .clock = 10800, 3358 .hdisplay = 480, 3359 .hsync_start = 480 + 77, 3360 .hsync_end = 480 + 77 + 41, 3361 .htotal = 480 + 77 + 41 + 2, 3362 .vdisplay = 272, 3363 .vsync_start = 272 + 16, 3364 .vsync_end = 272 + 16 + 10, 3365 .vtotal = 272 + 16 + 10 + 2, 3366 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3367 }, 3368 { /* 50 Hz */ 3369 .clock = 10800, 3370 .hdisplay = 480, 3371 .hsync_start = 480 + 17, 3372 .hsync_end = 480 + 17 + 41, 3373 .htotal = 480 + 17 + 41 + 2, 3374 .vdisplay = 272, 3375 .vsync_start = 272 + 116, 3376 .vsync_end = 272 + 116 + 10, 3377 .vtotal = 272 + 116 + 10 + 2, 3378 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3379 }, 3380 }; 3381 3382 static const struct panel_desc qishenglong_gopher2b_lcd = { 3383 .modes = qishenglong_gopher2b_lcd_modes, 3384 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3385 .bpc = 8, 3386 .size = { 3387 .width = 95, 3388 .height = 54, 3389 }, 3390 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3391 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3392 .connector_type = DRM_MODE_CONNECTOR_DPI, 3393 }; 3394 3395 static const struct display_timing rocktech_rk043fn48h_timing = { 3396 .pixelclock = { 6000000, 9000000, 12000000 }, 3397 .hactive = { 480, 480, 480 }, 3398 .hback_porch = { 8, 43, 43 }, 3399 .hfront_porch = { 2, 8, 8 }, 3400 .hsync_len = { 1, 1, 1 }, 3401 .vactive = { 272, 272, 272 }, 3402 .vback_porch = { 2, 12, 12 }, 3403 .vfront_porch = { 1, 4, 4 }, 3404 .vsync_len = { 1, 10, 10 }, 3405 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3406 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3407 }; 3408 3409 static const struct panel_desc rocktech_rk043fn48h = { 3410 .timings = &rocktech_rk043fn48h_timing, 3411 .num_timings = 1, 3412 .bpc = 8, 3413 .size = { 3414 .width = 95, 3415 .height = 54, 3416 }, 3417 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3418 .connector_type = DRM_MODE_CONNECTOR_DPI, 3419 }; 3420 3421 static const struct display_timing rocktech_rk070er9427_timing = { 3422 .pixelclock = { 26400000, 33300000, 46800000 }, 3423 .hactive = { 800, 800, 800 }, 3424 .hfront_porch = { 16, 210, 354 }, 3425 .hback_porch = { 46, 46, 46 }, 3426 .hsync_len = { 1, 1, 1 }, 3427 .vactive = { 480, 480, 480 }, 3428 .vfront_porch = { 7, 22, 147 }, 3429 .vback_porch = { 23, 23, 23 }, 3430 .vsync_len = { 1, 1, 1 }, 3431 .flags = DISPLAY_FLAGS_DE_HIGH, 3432 }; 3433 3434 static const struct panel_desc rocktech_rk070er9427 = { 3435 .timings = &rocktech_rk070er9427_timing, 3436 .num_timings = 1, 3437 .bpc = 6, 3438 .size = { 3439 .width = 154, 3440 .height = 86, 3441 }, 3442 .delay = { 3443 .prepare = 41, 3444 .enable = 50, 3445 .unprepare = 41, 3446 .disable = 50, 3447 }, 3448 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3449 }; 3450 3451 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3452 .clock = 71100, 3453 .hdisplay = 1280, 3454 .hsync_start = 1280 + 48, 3455 .hsync_end = 1280 + 48 + 32, 3456 .htotal = 1280 + 48 + 32 + 80, 3457 .vdisplay = 800, 3458 .vsync_start = 800 + 2, 3459 .vsync_end = 800 + 2 + 5, 3460 .vtotal = 800 + 2 + 5 + 16, 3461 }; 3462 3463 static const struct panel_desc rocktech_rk101ii01d_ct = { 3464 .modes = &rocktech_rk101ii01d_ct_mode, 3465 .bpc = 8, 3466 .num_modes = 1, 3467 .size = { 3468 .width = 217, 3469 .height = 136, 3470 }, 3471 .delay = { 3472 .prepare = 50, 3473 .disable = 50, 3474 }, 3475 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3477 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3478 }; 3479 3480 static const struct display_timing samsung_ltl101al01_timing = { 3481 .pixelclock = { 66663000, 66663000, 66663000 }, 3482 .hactive = { 1280, 1280, 1280 }, 3483 .hfront_porch = { 18, 18, 18 }, 3484 .hback_porch = { 36, 36, 36 }, 3485 .hsync_len = { 16, 16, 16 }, 3486 .vactive = { 800, 800, 800 }, 3487 .vfront_porch = { 4, 4, 4 }, 3488 .vback_porch = { 16, 16, 16 }, 3489 .vsync_len = { 3, 3, 3 }, 3490 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3491 }; 3492 3493 static const struct panel_desc samsung_ltl101al01 = { 3494 .timings = &samsung_ltl101al01_timing, 3495 .num_timings = 1, 3496 .bpc = 8, 3497 .size = { 3498 .width = 217, 3499 .height = 135, 3500 }, 3501 .delay = { 3502 .prepare = 40, 3503 .enable = 300, 3504 .disable = 200, 3505 .unprepare = 600, 3506 }, 3507 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3508 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3509 }; 3510 3511 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3512 .clock = 54030, 3513 .hdisplay = 1024, 3514 .hsync_start = 1024 + 24, 3515 .hsync_end = 1024 + 24 + 136, 3516 .htotal = 1024 + 24 + 136 + 160, 3517 .vdisplay = 600, 3518 .vsync_start = 600 + 3, 3519 .vsync_end = 600 + 3 + 6, 3520 .vtotal = 600 + 3 + 6 + 61, 3521 }; 3522 3523 static const struct panel_desc samsung_ltn101nt05 = { 3524 .modes = &samsung_ltn101nt05_mode, 3525 .num_modes = 1, 3526 .bpc = 6, 3527 .size = { 3528 .width = 223, 3529 .height = 125, 3530 }, 3531 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3532 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3533 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3534 }; 3535 3536 static const struct display_timing satoz_sat050at40h12r2_timing = { 3537 .pixelclock = {33300000, 33300000, 50000000}, 3538 .hactive = {800, 800, 800}, 3539 .hfront_porch = {16, 210, 354}, 3540 .hback_porch = {46, 46, 46}, 3541 .hsync_len = {1, 1, 40}, 3542 .vactive = {480, 480, 480}, 3543 .vfront_porch = {7, 22, 147}, 3544 .vback_porch = {23, 23, 23}, 3545 .vsync_len = {1, 1, 20}, 3546 }; 3547 3548 static const struct panel_desc satoz_sat050at40h12r2 = { 3549 .timings = &satoz_sat050at40h12r2_timing, 3550 .num_timings = 1, 3551 .bpc = 8, 3552 .size = { 3553 .width = 108, 3554 .height = 65, 3555 }, 3556 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3557 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3558 }; 3559 3560 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3561 .clock = 33260, 3562 .hdisplay = 800, 3563 .hsync_start = 800 + 64, 3564 .hsync_end = 800 + 64 + 128, 3565 .htotal = 800 + 64 + 128 + 64, 3566 .vdisplay = 480, 3567 .vsync_start = 480 + 8, 3568 .vsync_end = 480 + 8 + 2, 3569 .vtotal = 480 + 8 + 2 + 35, 3570 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3571 }; 3572 3573 static const struct panel_desc sharp_lq070y3dg3b = { 3574 .modes = &sharp_lq070y3dg3b_mode, 3575 .num_modes = 1, 3576 .bpc = 8, 3577 .size = { 3578 .width = 152, /* 152.4mm */ 3579 .height = 91, /* 91.4mm */ 3580 }, 3581 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3582 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3583 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3584 }; 3585 3586 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3587 .clock = 5500, 3588 .hdisplay = 240, 3589 .hsync_start = 240 + 16, 3590 .hsync_end = 240 + 16 + 7, 3591 .htotal = 240 + 16 + 7 + 5, 3592 .vdisplay = 320, 3593 .vsync_start = 320 + 9, 3594 .vsync_end = 320 + 9 + 1, 3595 .vtotal = 320 + 9 + 1 + 7, 3596 }; 3597 3598 static const struct panel_desc sharp_lq035q7db03 = { 3599 .modes = &sharp_lq035q7db03_mode, 3600 .num_modes = 1, 3601 .bpc = 6, 3602 .size = { 3603 .width = 54, 3604 .height = 72, 3605 }, 3606 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3607 }; 3608 3609 static const struct display_timing sharp_lq101k1ly04_timing = { 3610 .pixelclock = { 60000000, 65000000, 80000000 }, 3611 .hactive = { 1280, 1280, 1280 }, 3612 .hfront_porch = { 20, 20, 20 }, 3613 .hback_porch = { 20, 20, 20 }, 3614 .hsync_len = { 10, 10, 10 }, 3615 .vactive = { 800, 800, 800 }, 3616 .vfront_porch = { 4, 4, 4 }, 3617 .vback_porch = { 4, 4, 4 }, 3618 .vsync_len = { 4, 4, 4 }, 3619 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3620 }; 3621 3622 static const struct panel_desc sharp_lq101k1ly04 = { 3623 .timings = &sharp_lq101k1ly04_timing, 3624 .num_timings = 1, 3625 .bpc = 8, 3626 .size = { 3627 .width = 217, 3628 .height = 136, 3629 }, 3630 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3631 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3632 }; 3633 3634 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3635 { /* 50 Hz */ 3636 .clock = 3000, 3637 .hdisplay = 240, 3638 .hsync_start = 240 + 58, 3639 .hsync_end = 240 + 58 + 1, 3640 .htotal = 240 + 58 + 1 + 1, 3641 .vdisplay = 160, 3642 .vsync_start = 160 + 24, 3643 .vsync_end = 160 + 24 + 10, 3644 .vtotal = 160 + 24 + 10 + 6, 3645 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3646 }, 3647 { /* 60 Hz */ 3648 .clock = 3000, 3649 .hdisplay = 240, 3650 .hsync_start = 240 + 8, 3651 .hsync_end = 240 + 8 + 1, 3652 .htotal = 240 + 8 + 1 + 1, 3653 .vdisplay = 160, 3654 .vsync_start = 160 + 24, 3655 .vsync_end = 160 + 24 + 10, 3656 .vtotal = 160 + 24 + 10 + 6, 3657 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3658 }, 3659 }; 3660 3661 static const struct panel_desc sharp_ls020b1dd01d = { 3662 .modes = sharp_ls020b1dd01d_modes, 3663 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3664 .bpc = 6, 3665 .size = { 3666 .width = 42, 3667 .height = 28, 3668 }, 3669 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3670 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3671 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3672 | DRM_BUS_FLAG_SHARP_SIGNALS, 3673 }; 3674 3675 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3676 .clock = 33300, 3677 .hdisplay = 800, 3678 .hsync_start = 800 + 1, 3679 .hsync_end = 800 + 1 + 64, 3680 .htotal = 800 + 1 + 64 + 64, 3681 .vdisplay = 480, 3682 .vsync_start = 480 + 1, 3683 .vsync_end = 480 + 1 + 23, 3684 .vtotal = 480 + 1 + 23 + 22, 3685 }; 3686 3687 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3688 .modes = &shelly_sca07010_bfn_lnn_mode, 3689 .num_modes = 1, 3690 .size = { 3691 .width = 152, 3692 .height = 91, 3693 }, 3694 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3695 }; 3696 3697 static const struct drm_display_mode starry_kr070pe2t_mode = { 3698 .clock = 33000, 3699 .hdisplay = 800, 3700 .hsync_start = 800 + 209, 3701 .hsync_end = 800 + 209 + 1, 3702 .htotal = 800 + 209 + 1 + 45, 3703 .vdisplay = 480, 3704 .vsync_start = 480 + 22, 3705 .vsync_end = 480 + 22 + 1, 3706 .vtotal = 480 + 22 + 1 + 22, 3707 }; 3708 3709 static const struct panel_desc starry_kr070pe2t = { 3710 .modes = &starry_kr070pe2t_mode, 3711 .num_modes = 1, 3712 .bpc = 8, 3713 .size = { 3714 .width = 152, 3715 .height = 86, 3716 }, 3717 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3718 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3719 .connector_type = DRM_MODE_CONNECTOR_DPI, 3720 }; 3721 3722 static const struct display_timing startek_kd070wvfpa_mode = { 3723 .pixelclock = { 25200000, 27200000, 30500000 }, 3724 .hactive = { 800, 800, 800 }, 3725 .hfront_porch = { 19, 44, 115 }, 3726 .hback_porch = { 5, 16, 101 }, 3727 .hsync_len = { 1, 2, 100 }, 3728 .vactive = { 480, 480, 480 }, 3729 .vfront_porch = { 5, 43, 67 }, 3730 .vback_porch = { 5, 5, 67 }, 3731 .vsync_len = { 1, 2, 66 }, 3732 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3733 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3734 DISPLAY_FLAGS_SYNC_POSEDGE, 3735 }; 3736 3737 static const struct panel_desc startek_kd070wvfpa = { 3738 .timings = &startek_kd070wvfpa_mode, 3739 .num_timings = 1, 3740 .bpc = 8, 3741 .size = { 3742 .width = 152, 3743 .height = 91, 3744 }, 3745 .delay = { 3746 .prepare = 20, 3747 .enable = 200, 3748 .disable = 200, 3749 }, 3750 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3751 .connector_type = DRM_MODE_CONNECTOR_DPI, 3752 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3753 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3754 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3755 }; 3756 3757 static const struct display_timing tsd_tst043015cmhx_timing = { 3758 .pixelclock = { 5000000, 9000000, 12000000 }, 3759 .hactive = { 480, 480, 480 }, 3760 .hfront_porch = { 4, 5, 65 }, 3761 .hback_porch = { 36, 40, 255 }, 3762 .hsync_len = { 1, 1, 1 }, 3763 .vactive = { 272, 272, 272 }, 3764 .vfront_porch = { 2, 8, 97 }, 3765 .vback_porch = { 3, 8, 31 }, 3766 .vsync_len = { 1, 1, 1 }, 3767 3768 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3769 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3770 }; 3771 3772 static const struct panel_desc tsd_tst043015cmhx = { 3773 .timings = &tsd_tst043015cmhx_timing, 3774 .num_timings = 1, 3775 .bpc = 8, 3776 .size = { 3777 .width = 105, 3778 .height = 67, 3779 }, 3780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3781 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3782 }; 3783 3784 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3785 .clock = 30000, 3786 .hdisplay = 800, 3787 .hsync_start = 800 + 39, 3788 .hsync_end = 800 + 39 + 47, 3789 .htotal = 800 + 39 + 47 + 39, 3790 .vdisplay = 480, 3791 .vsync_start = 480 + 13, 3792 .vsync_end = 480 + 13 + 2, 3793 .vtotal = 480 + 13 + 2 + 29, 3794 }; 3795 3796 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3797 .modes = &tfc_s9700rtwv43tr_01b_mode, 3798 .num_modes = 1, 3799 .bpc = 8, 3800 .size = { 3801 .width = 155, 3802 .height = 90, 3803 }, 3804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3805 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3806 }; 3807 3808 static const struct display_timing tianma_tm070jdhg30_timing = { 3809 .pixelclock = { 62600000, 68200000, 78100000 }, 3810 .hactive = { 1280, 1280, 1280 }, 3811 .hfront_porch = { 15, 64, 159 }, 3812 .hback_porch = { 5, 5, 5 }, 3813 .hsync_len = { 1, 1, 256 }, 3814 .vactive = { 800, 800, 800 }, 3815 .vfront_porch = { 3, 40, 99 }, 3816 .vback_porch = { 2, 2, 2 }, 3817 .vsync_len = { 1, 1, 128 }, 3818 .flags = DISPLAY_FLAGS_DE_HIGH, 3819 }; 3820 3821 static const struct panel_desc tianma_tm070jdhg30 = { 3822 .timings = &tianma_tm070jdhg30_timing, 3823 .num_timings = 1, 3824 .bpc = 8, 3825 .size = { 3826 .width = 151, 3827 .height = 95, 3828 }, 3829 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3830 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3831 }; 3832 3833 static const struct panel_desc tianma_tm070jvhg33 = { 3834 .timings = &tianma_tm070jdhg30_timing, 3835 .num_timings = 1, 3836 .bpc = 8, 3837 .size = { 3838 .width = 150, 3839 .height = 94, 3840 }, 3841 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3842 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3843 }; 3844 3845 static const struct display_timing tianma_tm070rvhg71_timing = { 3846 .pixelclock = { 27700000, 29200000, 39600000 }, 3847 .hactive = { 800, 800, 800 }, 3848 .hfront_porch = { 12, 40, 212 }, 3849 .hback_porch = { 88, 88, 88 }, 3850 .hsync_len = { 1, 1, 40 }, 3851 .vactive = { 480, 480, 480 }, 3852 .vfront_porch = { 1, 13, 88 }, 3853 .vback_porch = { 32, 32, 32 }, 3854 .vsync_len = { 1, 1, 3 }, 3855 .flags = DISPLAY_FLAGS_DE_HIGH, 3856 }; 3857 3858 static const struct panel_desc tianma_tm070rvhg71 = { 3859 .timings = &tianma_tm070rvhg71_timing, 3860 .num_timings = 1, 3861 .bpc = 8, 3862 .size = { 3863 .width = 154, 3864 .height = 86, 3865 }, 3866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3868 }; 3869 3870 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3871 { 3872 .clock = 10000, 3873 .hdisplay = 320, 3874 .hsync_start = 320 + 50, 3875 .hsync_end = 320 + 50 + 6, 3876 .htotal = 320 + 50 + 6 + 38, 3877 .vdisplay = 240, 3878 .vsync_start = 240 + 3, 3879 .vsync_end = 240 + 3 + 1, 3880 .vtotal = 240 + 3 + 1 + 17, 3881 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3882 }, 3883 }; 3884 3885 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3886 .modes = ti_nspire_cx_lcd_mode, 3887 .num_modes = 1, 3888 .bpc = 8, 3889 .size = { 3890 .width = 65, 3891 .height = 49, 3892 }, 3893 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3894 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3895 }; 3896 3897 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3898 { 3899 .clock = 10000, 3900 .hdisplay = 320, 3901 .hsync_start = 320 + 6, 3902 .hsync_end = 320 + 6 + 6, 3903 .htotal = 320 + 6 + 6 + 6, 3904 .vdisplay = 240, 3905 .vsync_start = 240 + 0, 3906 .vsync_end = 240 + 0 + 1, 3907 .vtotal = 240 + 0 + 1 + 0, 3908 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3909 }, 3910 }; 3911 3912 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3913 .modes = ti_nspire_classic_lcd_mode, 3914 .num_modes = 1, 3915 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3916 .bpc = 8, 3917 .size = { 3918 .width = 71, 3919 .height = 53, 3920 }, 3921 /* This is the grayscale bus format */ 3922 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3923 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3924 }; 3925 3926 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3927 .clock = 79500, 3928 .hdisplay = 1280, 3929 .hsync_start = 1280 + 192, 3930 .hsync_end = 1280 + 192 + 128, 3931 .htotal = 1280 + 192 + 128 + 64, 3932 .vdisplay = 768, 3933 .vsync_start = 768 + 20, 3934 .vsync_end = 768 + 20 + 7, 3935 .vtotal = 768 + 20 + 7 + 3, 3936 }; 3937 3938 static const struct panel_desc toshiba_lt089ac29000 = { 3939 .modes = &toshiba_lt089ac29000_mode, 3940 .num_modes = 1, 3941 .size = { 3942 .width = 194, 3943 .height = 116, 3944 }, 3945 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3946 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3947 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3948 }; 3949 3950 static const struct drm_display_mode tpk_f07a_0102_mode = { 3951 .clock = 33260, 3952 .hdisplay = 800, 3953 .hsync_start = 800 + 40, 3954 .hsync_end = 800 + 40 + 128, 3955 .htotal = 800 + 40 + 128 + 88, 3956 .vdisplay = 480, 3957 .vsync_start = 480 + 10, 3958 .vsync_end = 480 + 10 + 2, 3959 .vtotal = 480 + 10 + 2 + 33, 3960 }; 3961 3962 static const struct panel_desc tpk_f07a_0102 = { 3963 .modes = &tpk_f07a_0102_mode, 3964 .num_modes = 1, 3965 .size = { 3966 .width = 152, 3967 .height = 91, 3968 }, 3969 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3970 }; 3971 3972 static const struct drm_display_mode tpk_f10a_0102_mode = { 3973 .clock = 45000, 3974 .hdisplay = 1024, 3975 .hsync_start = 1024 + 176, 3976 .hsync_end = 1024 + 176 + 5, 3977 .htotal = 1024 + 176 + 5 + 88, 3978 .vdisplay = 600, 3979 .vsync_start = 600 + 20, 3980 .vsync_end = 600 + 20 + 5, 3981 .vtotal = 600 + 20 + 5 + 25, 3982 }; 3983 3984 static const struct panel_desc tpk_f10a_0102 = { 3985 .modes = &tpk_f10a_0102_mode, 3986 .num_modes = 1, 3987 .size = { 3988 .width = 223, 3989 .height = 125, 3990 }, 3991 }; 3992 3993 static const struct display_timing urt_umsh_8596md_timing = { 3994 .pixelclock = { 33260000, 33260000, 33260000 }, 3995 .hactive = { 800, 800, 800 }, 3996 .hfront_porch = { 41, 41, 41 }, 3997 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3998 .hsync_len = { 71, 128, 128 }, 3999 .vactive = { 480, 480, 480 }, 4000 .vfront_porch = { 10, 10, 10 }, 4001 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4002 .vsync_len = { 2, 2, 2 }, 4003 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4004 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4005 }; 4006 4007 static const struct panel_desc urt_umsh_8596md_lvds = { 4008 .timings = &urt_umsh_8596md_timing, 4009 .num_timings = 1, 4010 .bpc = 6, 4011 .size = { 4012 .width = 152, 4013 .height = 91, 4014 }, 4015 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4016 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4017 }; 4018 4019 static const struct panel_desc urt_umsh_8596md_parallel = { 4020 .timings = &urt_umsh_8596md_timing, 4021 .num_timings = 1, 4022 .bpc = 6, 4023 .size = { 4024 .width = 152, 4025 .height = 91, 4026 }, 4027 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4028 }; 4029 4030 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4031 .clock = 60000, 4032 .hdisplay = 1024, 4033 .hsync_start = 1024 + 160, 4034 .hsync_end = 1024 + 160 + 100, 4035 .htotal = 1024 + 160 + 100 + 60, 4036 .vdisplay = 600, 4037 .vsync_start = 600 + 12, 4038 .vsync_end = 600 + 12 + 10, 4039 .vtotal = 600 + 12 + 10 + 13, 4040 }; 4041 4042 static const struct panel_desc vivax_tpc9150_panel = { 4043 .modes = &vivax_tpc9150_panel_mode, 4044 .num_modes = 1, 4045 .bpc = 6, 4046 .size = { 4047 .width = 200, 4048 .height = 115, 4049 }, 4050 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4051 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4052 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4053 }; 4054 4055 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4056 .clock = 33333, 4057 .hdisplay = 800, 4058 .hsync_start = 800 + 210, 4059 .hsync_end = 800 + 210 + 20, 4060 .htotal = 800 + 210 + 20 + 46, 4061 .vdisplay = 480, 4062 .vsync_start = 480 + 22, 4063 .vsync_end = 480 + 22 + 10, 4064 .vtotal = 480 + 22 + 10 + 23, 4065 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4066 }; 4067 4068 static const struct panel_desc vl050_8048nt_c01 = { 4069 .modes = &vl050_8048nt_c01_mode, 4070 .num_modes = 1, 4071 .bpc = 8, 4072 .size = { 4073 .width = 120, 4074 .height = 76, 4075 }, 4076 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4077 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4078 }; 4079 4080 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4081 .clock = 6410, 4082 .hdisplay = 320, 4083 .hsync_start = 320 + 20, 4084 .hsync_end = 320 + 20 + 30, 4085 .htotal = 320 + 20 + 30 + 38, 4086 .vdisplay = 240, 4087 .vsync_start = 240 + 4, 4088 .vsync_end = 240 + 4 + 3, 4089 .vtotal = 240 + 4 + 3 + 15, 4090 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4091 }; 4092 4093 static const struct panel_desc winstar_wf35ltiacd = { 4094 .modes = &winstar_wf35ltiacd_mode, 4095 .num_modes = 1, 4096 .bpc = 8, 4097 .size = { 4098 .width = 70, 4099 .height = 53, 4100 }, 4101 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4102 }; 4103 4104 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4105 .clock = 51200, 4106 .hdisplay = 1024, 4107 .hsync_start = 1024 + 100, 4108 .hsync_end = 1024 + 100 + 100, 4109 .htotal = 1024 + 100 + 100 + 120, 4110 .vdisplay = 600, 4111 .vsync_start = 600 + 10, 4112 .vsync_end = 600 + 10 + 10, 4113 .vtotal = 600 + 10 + 10 + 15, 4114 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4115 }; 4116 4117 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4118 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4119 .num_modes = 1, 4120 .bpc = 8, 4121 .size = { 4122 .width = 154, 4123 .height = 90, 4124 }, 4125 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4127 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4128 }; 4129 4130 static const struct drm_display_mode arm_rtsm_mode[] = { 4131 { 4132 .clock = 65000, 4133 .hdisplay = 1024, 4134 .hsync_start = 1024 + 24, 4135 .hsync_end = 1024 + 24 + 136, 4136 .htotal = 1024 + 24 + 136 + 160, 4137 .vdisplay = 768, 4138 .vsync_start = 768 + 3, 4139 .vsync_end = 768 + 3 + 6, 4140 .vtotal = 768 + 3 + 6 + 29, 4141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4142 }, 4143 }; 4144 4145 static const struct panel_desc arm_rtsm = { 4146 .modes = arm_rtsm_mode, 4147 .num_modes = 1, 4148 .bpc = 8, 4149 .size = { 4150 .width = 400, 4151 .height = 300, 4152 }, 4153 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4154 }; 4155 4156 static const struct of_device_id platform_of_match[] = { 4157 { 4158 .compatible = "ampire,am-1280800n3tzqw-t00h", 4159 .data = &ire_am_1280800n3tzqw_t00h, 4160 }, { 4161 .compatible = "ampire,am-480272h3tmqw-t01h", 4162 .data = &ire_am_480272h3tmqw_t01h, 4163 }, { 4164 .compatible = "ampire,am-800480l1tmqw-t00h", 4165 .data = &ire_am_800480l1tmqw_t00h, 4166 }, { 4167 .compatible = "ampire,am800480r3tmqwa1h", 4168 .data = &ire_am800480r3tmqwa1h, 4169 }, { 4170 .compatible = "ampire,am800600p5tmqw-tb8h", 4171 .data = &ire_am800600p5tmqwtb8h, 4172 }, { 4173 .compatible = "arm,rtsm-display", 4174 .data = &arm_rtsm, 4175 }, { 4176 .compatible = "armadeus,st0700-adapt", 4177 .data = &armadeus_st0700_adapt, 4178 }, { 4179 .compatible = "auo,b101aw03", 4180 .data = &auo_b101aw03, 4181 }, { 4182 .compatible = "auo,b101xtn01", 4183 .data = &auo_b101xtn01, 4184 }, { 4185 .compatible = "auo,g070vvn01", 4186 .data = &auo_g070vvn01, 4187 }, { 4188 .compatible = "auo,g101evn010", 4189 .data = &auo_g101evn010, 4190 }, { 4191 .compatible = "auo,g104sn02", 4192 .data = &auo_g104sn02, 4193 }, { 4194 .compatible = "auo,g121ean01", 4195 .data = &auo_g121ean01, 4196 }, { 4197 .compatible = "auo,g133han01", 4198 .data = &auo_g133han01, 4199 }, { 4200 .compatible = "auo,g156xtn01", 4201 .data = &auo_g156xtn01, 4202 }, { 4203 .compatible = "auo,g185han01", 4204 .data = &auo_g185han01, 4205 }, { 4206 .compatible = "auo,g190ean01", 4207 .data = &auo_g190ean01, 4208 }, { 4209 .compatible = "auo,p320hvn03", 4210 .data = &auo_p320hvn03, 4211 }, { 4212 .compatible = "auo,t215hvn01", 4213 .data = &auo_t215hvn01, 4214 }, { 4215 .compatible = "avic,tm070ddh03", 4216 .data = &avic_tm070ddh03, 4217 }, { 4218 .compatible = "bananapi,s070wv20-ct16", 4219 .data = &bananapi_s070wv20_ct16, 4220 }, { 4221 .compatible = "boe,ev121wxm-n10-1850", 4222 .data = &boe_ev121wxm_n10_1850, 4223 }, { 4224 .compatible = "boe,hv070wsa-100", 4225 .data = &boe_hv070wsa 4226 }, { 4227 .compatible = "cdtech,s043wq26h-ct7", 4228 .data = &cdtech_s043wq26h_ct7, 4229 }, { 4230 .compatible = "cdtech,s070pws19hp-fc21", 4231 .data = &cdtech_s070pws19hp_fc21, 4232 }, { 4233 .compatible = "cdtech,s070swv29hg-dc44", 4234 .data = &cdtech_s070swv29hg_dc44, 4235 }, { 4236 .compatible = "cdtech,s070wv95-ct16", 4237 .data = &cdtech_s070wv95_ct16, 4238 }, { 4239 .compatible = "chefree,ch101olhlwh-002", 4240 .data = &chefree_ch101olhlwh_002, 4241 }, { 4242 .compatible = "chunghwa,claa070wp03xg", 4243 .data = &chunghwa_claa070wp03xg, 4244 }, { 4245 .compatible = "chunghwa,claa101wa01a", 4246 .data = &chunghwa_claa101wa01a 4247 }, { 4248 .compatible = "chunghwa,claa101wb01", 4249 .data = &chunghwa_claa101wb01 4250 }, { 4251 .compatible = "dataimage,fg040346dsswbg04", 4252 .data = &dataimage_fg040346dsswbg04, 4253 }, { 4254 .compatible = "dataimage,fg1001l0dsswmg01", 4255 .data = &dataimage_fg1001l0dsswmg01, 4256 }, { 4257 .compatible = "dataimage,scf0700c48ggu18", 4258 .data = &dataimage_scf0700c48ggu18, 4259 }, { 4260 .compatible = "dlc,dlc0700yzg-1", 4261 .data = &dlc_dlc0700yzg_1, 4262 }, { 4263 .compatible = "dlc,dlc1010gig", 4264 .data = &dlc_dlc1010gig, 4265 }, { 4266 .compatible = "edt,et035012dm6", 4267 .data = &edt_et035012dm6, 4268 }, { 4269 .compatible = "edt,etm0350g0dh6", 4270 .data = &edt_etm0350g0dh6, 4271 }, { 4272 .compatible = "edt,etm043080dh6gp", 4273 .data = &edt_etm043080dh6gp, 4274 }, { 4275 .compatible = "edt,etm0430g0dh6", 4276 .data = &edt_etm0430g0dh6, 4277 }, { 4278 .compatible = "edt,et057090dhu", 4279 .data = &edt_et057090dhu, 4280 }, { 4281 .compatible = "edt,et070080dh6", 4282 .data = &edt_etm0700g0dh6, 4283 }, { 4284 .compatible = "edt,etm0700g0dh6", 4285 .data = &edt_etm0700g0dh6, 4286 }, { 4287 .compatible = "edt,etm0700g0bdh6", 4288 .data = &edt_etm0700g0bdh6, 4289 }, { 4290 .compatible = "edt,etm0700g0edh6", 4291 .data = &edt_etm0700g0bdh6, 4292 }, { 4293 .compatible = "edt,etml0700y5dha", 4294 .data = &edt_etml0700y5dha, 4295 }, { 4296 .compatible = "edt,etmv570g2dhu", 4297 .data = &edt_etmv570g2dhu, 4298 }, { 4299 .compatible = "eink,vb3300-kca", 4300 .data = &eink_vb3300_kca, 4301 }, { 4302 .compatible = "evervision,vgg804821", 4303 .data = &evervision_vgg804821, 4304 }, { 4305 .compatible = "foxlink,fl500wvr00-a0t", 4306 .data = &foxlink_fl500wvr00_a0t, 4307 }, { 4308 .compatible = "frida,frd350h54004", 4309 .data = &frida_frd350h54004, 4310 }, { 4311 .compatible = "friendlyarm,hd702e", 4312 .data = &friendlyarm_hd702e, 4313 }, { 4314 .compatible = "giantplus,gpg482739qs5", 4315 .data = &giantplus_gpg482739qs5 4316 }, { 4317 .compatible = "giantplus,gpm940b0", 4318 .data = &giantplus_gpm940b0, 4319 }, { 4320 .compatible = "hannstar,hsd070pww1", 4321 .data = &hannstar_hsd070pww1, 4322 }, { 4323 .compatible = "hannstar,hsd100pxn1", 4324 .data = &hannstar_hsd100pxn1, 4325 }, { 4326 .compatible = "hannstar,hsd101pww2", 4327 .data = &hannstar_hsd101pww2, 4328 }, { 4329 .compatible = "hit,tx23d38vm0caa", 4330 .data = &hitachi_tx23d38vm0caa 4331 }, { 4332 .compatible = "innolux,at043tn24", 4333 .data = &innolux_at043tn24, 4334 }, { 4335 .compatible = "innolux,at070tn92", 4336 .data = &innolux_at070tn92, 4337 }, { 4338 .compatible = "innolux,g070ace-l01", 4339 .data = &innolux_g070ace_l01, 4340 }, { 4341 .compatible = "innolux,g070y2-l01", 4342 .data = &innolux_g070y2_l01, 4343 }, { 4344 .compatible = "innolux,g070y2-t02", 4345 .data = &innolux_g070y2_t02, 4346 }, { 4347 .compatible = "innolux,g101ice-l01", 4348 .data = &innolux_g101ice_l01 4349 }, { 4350 .compatible = "innolux,g121i1-l01", 4351 .data = &innolux_g121i1_l01 4352 }, { 4353 .compatible = "innolux,g121x1-l03", 4354 .data = &innolux_g121x1_l03, 4355 }, { 4356 .compatible = "innolux,g156hce-l01", 4357 .data = &innolux_g156hce_l01, 4358 }, { 4359 .compatible = "innolux,n156bge-l21", 4360 .data = &innolux_n156bge_l21, 4361 }, { 4362 .compatible = "innolux,zj070na-01p", 4363 .data = &innolux_zj070na_01p, 4364 }, { 4365 .compatible = "koe,tx14d24vm1bpa", 4366 .data = &koe_tx14d24vm1bpa, 4367 }, { 4368 .compatible = "koe,tx26d202vm0bwa", 4369 .data = &koe_tx26d202vm0bwa, 4370 }, { 4371 .compatible = "koe,tx31d200vm0baa", 4372 .data = &koe_tx31d200vm0baa, 4373 }, { 4374 .compatible = "kyo,tcg121xglp", 4375 .data = &kyo_tcg121xglp, 4376 }, { 4377 .compatible = "lemaker,bl035-rgb-002", 4378 .data = &lemaker_bl035_rgb_002, 4379 }, { 4380 .compatible = "lg,lb070wv8", 4381 .data = &lg_lb070wv8, 4382 }, { 4383 .compatible = "logicpd,type28", 4384 .data = &logicpd_type_28, 4385 }, { 4386 .compatible = "logictechno,lt161010-2nhc", 4387 .data = &logictechno_lt161010_2nh, 4388 }, { 4389 .compatible = "logictechno,lt161010-2nhr", 4390 .data = &logictechno_lt161010_2nh, 4391 }, { 4392 .compatible = "logictechno,lt170410-2whc", 4393 .data = &logictechno_lt170410_2whc, 4394 }, { 4395 .compatible = "logictechno,lttd800480070-l2rt", 4396 .data = &logictechno_lttd800480070_l2rt, 4397 }, { 4398 .compatible = "logictechno,lttd800480070-l6wh-rt", 4399 .data = &logictechno_lttd800480070_l6wh_rt, 4400 }, { 4401 .compatible = "mitsubishi,aa070mc01-ca1", 4402 .data = &mitsubishi_aa070mc01, 4403 }, { 4404 .compatible = "mitsubishi,aa084xe01", 4405 .data = &mitsubishi_aa084xe01, 4406 }, { 4407 .compatible = "multi-inno,mi0700s4t-6", 4408 .data = &multi_inno_mi0700s4t_6, 4409 }, { 4410 .compatible = "multi-inno,mi0800ft-9", 4411 .data = &multi_inno_mi0800ft_9, 4412 }, { 4413 .compatible = "multi-inno,mi1010ait-1cp", 4414 .data = &multi_inno_mi1010ait_1cp, 4415 }, { 4416 .compatible = "nec,nl12880bc20-05", 4417 .data = &nec_nl12880bc20_05, 4418 }, { 4419 .compatible = "nec,nl4827hc19-05b", 4420 .data = &nec_nl4827hc19_05b, 4421 }, { 4422 .compatible = "netron-dy,e231732", 4423 .data = &netron_dy_e231732, 4424 }, { 4425 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4426 .data = &newhaven_nhd_43_480272ef_atxl, 4427 }, { 4428 .compatible = "nlt,nl192108ac18-02d", 4429 .data = &nlt_nl192108ac18_02d, 4430 }, { 4431 .compatible = "nvd,9128", 4432 .data = &nvd_9128, 4433 }, { 4434 .compatible = "okaya,rs800480t-7x0gp", 4435 .data = &okaya_rs800480t_7x0gp, 4436 }, { 4437 .compatible = "olimex,lcd-olinuxino-43-ts", 4438 .data = &olimex_lcd_olinuxino_43ts, 4439 }, { 4440 .compatible = "ontat,yx700wv03", 4441 .data = &ontat_yx700wv03, 4442 }, { 4443 .compatible = "ortustech,com37h3m05dtc", 4444 .data = &ortustech_com37h3m, 4445 }, { 4446 .compatible = "ortustech,com37h3m99dtc", 4447 .data = &ortustech_com37h3m, 4448 }, { 4449 .compatible = "ortustech,com43h4m85ulc", 4450 .data = &ortustech_com43h4m85ulc, 4451 }, { 4452 .compatible = "osddisplays,osd070t1718-19ts", 4453 .data = &osddisplays_osd070t1718_19ts, 4454 }, { 4455 .compatible = "pda,91-00156-a0", 4456 .data = &pda_91_00156_a0, 4457 }, { 4458 .compatible = "powertip,ph800480t013-idf02", 4459 .data = &powertip_ph800480t013_idf02, 4460 }, { 4461 .compatible = "qiaodian,qd43003c0-40", 4462 .data = &qd43003c0_40, 4463 }, { 4464 .compatible = "qishenglong,gopher2b-lcd", 4465 .data = &qishenglong_gopher2b_lcd, 4466 }, { 4467 .compatible = "rocktech,rk043fn48h", 4468 .data = &rocktech_rk043fn48h, 4469 }, { 4470 .compatible = "rocktech,rk070er9427", 4471 .data = &rocktech_rk070er9427, 4472 }, { 4473 .compatible = "rocktech,rk101ii01d-ct", 4474 .data = &rocktech_rk101ii01d_ct, 4475 }, { 4476 .compatible = "samsung,ltl101al01", 4477 .data = &samsung_ltl101al01, 4478 }, { 4479 .compatible = "samsung,ltn101nt05", 4480 .data = &samsung_ltn101nt05, 4481 }, { 4482 .compatible = "satoz,sat050at40h12r2", 4483 .data = &satoz_sat050at40h12r2, 4484 }, { 4485 .compatible = "sharp,lq035q7db03", 4486 .data = &sharp_lq035q7db03, 4487 }, { 4488 .compatible = "sharp,lq070y3dg3b", 4489 .data = &sharp_lq070y3dg3b, 4490 }, { 4491 .compatible = "sharp,lq101k1ly04", 4492 .data = &sharp_lq101k1ly04, 4493 }, { 4494 .compatible = "sharp,ls020b1dd01d", 4495 .data = &sharp_ls020b1dd01d, 4496 }, { 4497 .compatible = "shelly,sca07010-bfn-lnn", 4498 .data = &shelly_sca07010_bfn_lnn, 4499 }, { 4500 .compatible = "starry,kr070pe2t", 4501 .data = &starry_kr070pe2t, 4502 }, { 4503 .compatible = "startek,kd070wvfpa", 4504 .data = &startek_kd070wvfpa, 4505 }, { 4506 .compatible = "team-source-display,tst043015cmhx", 4507 .data = &tsd_tst043015cmhx, 4508 }, { 4509 .compatible = "tfc,s9700rtwv43tr-01b", 4510 .data = &tfc_s9700rtwv43tr_01b, 4511 }, { 4512 .compatible = "tianma,tm070jdhg30", 4513 .data = &tianma_tm070jdhg30, 4514 }, { 4515 .compatible = "tianma,tm070jvhg33", 4516 .data = &tianma_tm070jvhg33, 4517 }, { 4518 .compatible = "tianma,tm070rvhg71", 4519 .data = &tianma_tm070rvhg71, 4520 }, { 4521 .compatible = "ti,nspire-cx-lcd-panel", 4522 .data = &ti_nspire_cx_lcd_panel, 4523 }, { 4524 .compatible = "ti,nspire-classic-lcd-panel", 4525 .data = &ti_nspire_classic_lcd_panel, 4526 }, { 4527 .compatible = "toshiba,lt089ac29000", 4528 .data = &toshiba_lt089ac29000, 4529 }, { 4530 .compatible = "tpk,f07a-0102", 4531 .data = &tpk_f07a_0102, 4532 }, { 4533 .compatible = "tpk,f10a-0102", 4534 .data = &tpk_f10a_0102, 4535 }, { 4536 .compatible = "urt,umsh-8596md-t", 4537 .data = &urt_umsh_8596md_parallel, 4538 }, { 4539 .compatible = "urt,umsh-8596md-1t", 4540 .data = &urt_umsh_8596md_parallel, 4541 }, { 4542 .compatible = "urt,umsh-8596md-7t", 4543 .data = &urt_umsh_8596md_parallel, 4544 }, { 4545 .compatible = "urt,umsh-8596md-11t", 4546 .data = &urt_umsh_8596md_lvds, 4547 }, { 4548 .compatible = "urt,umsh-8596md-19t", 4549 .data = &urt_umsh_8596md_lvds, 4550 }, { 4551 .compatible = "urt,umsh-8596md-20t", 4552 .data = &urt_umsh_8596md_parallel, 4553 }, { 4554 .compatible = "vivax,tpc9150-panel", 4555 .data = &vivax_tpc9150_panel, 4556 }, { 4557 .compatible = "vxt,vl050-8048nt-c01", 4558 .data = &vl050_8048nt_c01, 4559 }, { 4560 .compatible = "winstar,wf35ltiacd", 4561 .data = &winstar_wf35ltiacd, 4562 }, { 4563 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4564 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4565 }, { 4566 /* Must be the last entry */ 4567 .compatible = "panel-dpi", 4568 .data = &panel_dpi, 4569 }, { 4570 /* sentinel */ 4571 } 4572 }; 4573 MODULE_DEVICE_TABLE(of, platform_of_match); 4574 4575 static int panel_simple_platform_probe(struct platform_device *pdev) 4576 { 4577 const struct panel_desc *desc; 4578 4579 desc = of_device_get_match_data(&pdev->dev); 4580 if (!desc) 4581 return -ENODEV; 4582 4583 return panel_simple_probe(&pdev->dev, desc); 4584 } 4585 4586 static void panel_simple_platform_remove(struct platform_device *pdev) 4587 { 4588 panel_simple_remove(&pdev->dev); 4589 } 4590 4591 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4592 { 4593 panel_simple_shutdown(&pdev->dev); 4594 } 4595 4596 static const struct dev_pm_ops panel_simple_pm_ops = { 4597 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4598 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4599 pm_runtime_force_resume) 4600 }; 4601 4602 static struct platform_driver panel_simple_platform_driver = { 4603 .driver = { 4604 .name = "panel-simple", 4605 .of_match_table = platform_of_match, 4606 .pm = &panel_simple_pm_ops, 4607 }, 4608 .probe = panel_simple_platform_probe, 4609 .remove_new = panel_simple_platform_remove, 4610 .shutdown = panel_simple_platform_shutdown, 4611 }; 4612 4613 struct panel_desc_dsi { 4614 struct panel_desc desc; 4615 4616 unsigned long flags; 4617 enum mipi_dsi_pixel_format format; 4618 unsigned int lanes; 4619 }; 4620 4621 static const struct drm_display_mode auo_b080uan01_mode = { 4622 .clock = 154500, 4623 .hdisplay = 1200, 4624 .hsync_start = 1200 + 62, 4625 .hsync_end = 1200 + 62 + 4, 4626 .htotal = 1200 + 62 + 4 + 62, 4627 .vdisplay = 1920, 4628 .vsync_start = 1920 + 9, 4629 .vsync_end = 1920 + 9 + 2, 4630 .vtotal = 1920 + 9 + 2 + 8, 4631 }; 4632 4633 static const struct panel_desc_dsi auo_b080uan01 = { 4634 .desc = { 4635 .modes = &auo_b080uan01_mode, 4636 .num_modes = 1, 4637 .bpc = 8, 4638 .size = { 4639 .width = 108, 4640 .height = 272, 4641 }, 4642 .connector_type = DRM_MODE_CONNECTOR_DSI, 4643 }, 4644 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4645 .format = MIPI_DSI_FMT_RGB888, 4646 .lanes = 4, 4647 }; 4648 4649 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4650 .clock = 160000, 4651 .hdisplay = 1200, 4652 .hsync_start = 1200 + 120, 4653 .hsync_end = 1200 + 120 + 20, 4654 .htotal = 1200 + 120 + 20 + 21, 4655 .vdisplay = 1920, 4656 .vsync_start = 1920 + 21, 4657 .vsync_end = 1920 + 21 + 3, 4658 .vtotal = 1920 + 21 + 3 + 18, 4659 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4660 }; 4661 4662 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4663 .desc = { 4664 .modes = &boe_tv080wum_nl0_mode, 4665 .num_modes = 1, 4666 .size = { 4667 .width = 107, 4668 .height = 172, 4669 }, 4670 .connector_type = DRM_MODE_CONNECTOR_DSI, 4671 }, 4672 .flags = MIPI_DSI_MODE_VIDEO | 4673 MIPI_DSI_MODE_VIDEO_BURST | 4674 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4675 .format = MIPI_DSI_FMT_RGB888, 4676 .lanes = 4, 4677 }; 4678 4679 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4680 .clock = 71000, 4681 .hdisplay = 800, 4682 .hsync_start = 800 + 32, 4683 .hsync_end = 800 + 32 + 1, 4684 .htotal = 800 + 32 + 1 + 57, 4685 .vdisplay = 1280, 4686 .vsync_start = 1280 + 28, 4687 .vsync_end = 1280 + 28 + 1, 4688 .vtotal = 1280 + 28 + 1 + 14, 4689 }; 4690 4691 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4692 .desc = { 4693 .modes = &lg_ld070wx3_sl01_mode, 4694 .num_modes = 1, 4695 .bpc = 8, 4696 .size = { 4697 .width = 94, 4698 .height = 151, 4699 }, 4700 .connector_type = DRM_MODE_CONNECTOR_DSI, 4701 }, 4702 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4703 .format = MIPI_DSI_FMT_RGB888, 4704 .lanes = 4, 4705 }; 4706 4707 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4708 .clock = 67000, 4709 .hdisplay = 720, 4710 .hsync_start = 720 + 12, 4711 .hsync_end = 720 + 12 + 4, 4712 .htotal = 720 + 12 + 4 + 112, 4713 .vdisplay = 1280, 4714 .vsync_start = 1280 + 8, 4715 .vsync_end = 1280 + 8 + 4, 4716 .vtotal = 1280 + 8 + 4 + 12, 4717 }; 4718 4719 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4720 .desc = { 4721 .modes = &lg_lh500wx1_sd03_mode, 4722 .num_modes = 1, 4723 .bpc = 8, 4724 .size = { 4725 .width = 62, 4726 .height = 110, 4727 }, 4728 .connector_type = DRM_MODE_CONNECTOR_DSI, 4729 }, 4730 .flags = MIPI_DSI_MODE_VIDEO, 4731 .format = MIPI_DSI_FMT_RGB888, 4732 .lanes = 4, 4733 }; 4734 4735 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4736 .clock = 157200, 4737 .hdisplay = 1920, 4738 .hsync_start = 1920 + 154, 4739 .hsync_end = 1920 + 154 + 16, 4740 .htotal = 1920 + 154 + 16 + 32, 4741 .vdisplay = 1200, 4742 .vsync_start = 1200 + 17, 4743 .vsync_end = 1200 + 17 + 2, 4744 .vtotal = 1200 + 17 + 2 + 16, 4745 }; 4746 4747 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4748 .desc = { 4749 .modes = &panasonic_vvx10f004b00_mode, 4750 .num_modes = 1, 4751 .bpc = 8, 4752 .size = { 4753 .width = 217, 4754 .height = 136, 4755 }, 4756 .connector_type = DRM_MODE_CONNECTOR_DSI, 4757 }, 4758 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4759 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4760 .format = MIPI_DSI_FMT_RGB888, 4761 .lanes = 4, 4762 }; 4763 4764 static const struct drm_display_mode lg_acx467akm_7_mode = { 4765 .clock = 150000, 4766 .hdisplay = 1080, 4767 .hsync_start = 1080 + 2, 4768 .hsync_end = 1080 + 2 + 2, 4769 .htotal = 1080 + 2 + 2 + 2, 4770 .vdisplay = 1920, 4771 .vsync_start = 1920 + 2, 4772 .vsync_end = 1920 + 2 + 2, 4773 .vtotal = 1920 + 2 + 2 + 2, 4774 }; 4775 4776 static const struct panel_desc_dsi lg_acx467akm_7 = { 4777 .desc = { 4778 .modes = &lg_acx467akm_7_mode, 4779 .num_modes = 1, 4780 .bpc = 8, 4781 .size = { 4782 .width = 62, 4783 .height = 110, 4784 }, 4785 .connector_type = DRM_MODE_CONNECTOR_DSI, 4786 }, 4787 .flags = 0, 4788 .format = MIPI_DSI_FMT_RGB888, 4789 .lanes = 4, 4790 }; 4791 4792 static const struct drm_display_mode osd101t2045_53ts_mode = { 4793 .clock = 154500, 4794 .hdisplay = 1920, 4795 .hsync_start = 1920 + 112, 4796 .hsync_end = 1920 + 112 + 16, 4797 .htotal = 1920 + 112 + 16 + 32, 4798 .vdisplay = 1200, 4799 .vsync_start = 1200 + 16, 4800 .vsync_end = 1200 + 16 + 2, 4801 .vtotal = 1200 + 16 + 2 + 16, 4802 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4803 }; 4804 4805 static const struct panel_desc_dsi osd101t2045_53ts = { 4806 .desc = { 4807 .modes = &osd101t2045_53ts_mode, 4808 .num_modes = 1, 4809 .bpc = 8, 4810 .size = { 4811 .width = 217, 4812 .height = 136, 4813 }, 4814 .connector_type = DRM_MODE_CONNECTOR_DSI, 4815 }, 4816 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4817 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4818 MIPI_DSI_MODE_NO_EOT_PACKET, 4819 .format = MIPI_DSI_FMT_RGB888, 4820 .lanes = 4, 4821 }; 4822 4823 static const struct of_device_id dsi_of_match[] = { 4824 { 4825 .compatible = "auo,b080uan01", 4826 .data = &auo_b080uan01 4827 }, { 4828 .compatible = "boe,tv080wum-nl0", 4829 .data = &boe_tv080wum_nl0 4830 }, { 4831 .compatible = "lg,ld070wx3-sl01", 4832 .data = &lg_ld070wx3_sl01 4833 }, { 4834 .compatible = "lg,lh500wx1-sd03", 4835 .data = &lg_lh500wx1_sd03 4836 }, { 4837 .compatible = "panasonic,vvx10f004b00", 4838 .data = &panasonic_vvx10f004b00 4839 }, { 4840 .compatible = "lg,acx467akm-7", 4841 .data = &lg_acx467akm_7 4842 }, { 4843 .compatible = "osddisplays,osd101t2045-53ts", 4844 .data = &osd101t2045_53ts 4845 }, { 4846 /* sentinel */ 4847 } 4848 }; 4849 MODULE_DEVICE_TABLE(of, dsi_of_match); 4850 4851 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4852 { 4853 const struct panel_desc_dsi *desc; 4854 int err; 4855 4856 desc = of_device_get_match_data(&dsi->dev); 4857 if (!desc) 4858 return -ENODEV; 4859 4860 err = panel_simple_probe(&dsi->dev, &desc->desc); 4861 if (err < 0) 4862 return err; 4863 4864 dsi->mode_flags = desc->flags; 4865 dsi->format = desc->format; 4866 dsi->lanes = desc->lanes; 4867 4868 err = mipi_dsi_attach(dsi); 4869 if (err) { 4870 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4871 4872 drm_panel_remove(&panel->base); 4873 } 4874 4875 return err; 4876 } 4877 4878 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4879 { 4880 int err; 4881 4882 err = mipi_dsi_detach(dsi); 4883 if (err < 0) 4884 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4885 4886 panel_simple_remove(&dsi->dev); 4887 } 4888 4889 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4890 { 4891 panel_simple_shutdown(&dsi->dev); 4892 } 4893 4894 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4895 .driver = { 4896 .name = "panel-simple-dsi", 4897 .of_match_table = dsi_of_match, 4898 .pm = &panel_simple_pm_ops, 4899 }, 4900 .probe = panel_simple_dsi_probe, 4901 .remove = panel_simple_dsi_remove, 4902 .shutdown = panel_simple_dsi_shutdown, 4903 }; 4904 4905 static int __init panel_simple_init(void) 4906 { 4907 int err; 4908 4909 err = platform_driver_register(&panel_simple_platform_driver); 4910 if (err < 0) 4911 return err; 4912 4913 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4914 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4915 if (err < 0) 4916 goto err_did_platform_register; 4917 } 4918 4919 return 0; 4920 4921 err_did_platform_register: 4922 platform_driver_unregister(&panel_simple_platform_driver); 4923 4924 return err; 4925 } 4926 module_init(panel_simple_init); 4927 4928 static void __exit panel_simple_exit(void) 4929 { 4930 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4931 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4932 4933 platform_driver_unregister(&panel_simple_platform_driver); 4934 } 4935 module_exit(panel_simple_exit); 4936 4937 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4938 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4939 MODULE_LICENSE("GPL and additional rights"); 4940