1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744 disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747 free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752 } 753 754 static void panel_simple_shutdown(struct device *dev) 755 { 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782 } 783 784 static void panel_simple_remove(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795 } 796 797 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808 }; 809 810 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821 }; 822 823 static const struct drm_display_mode ampire_am_1280800w8tzqw_t00h_mode = { 824 .clock = 72400, 825 .hdisplay = 1280, 826 .hsync_start = 1280 + 40, 827 .hsync_end = 1280 + 40 + 80, 828 .htotal = 1280 + 40 + 80 + 40, 829 .vdisplay = 800, 830 .vsync_start = 800 + 10, 831 .vsync_end = 800 + 10 + 18, 832 .vtotal = 800 + 10 + 18 + 10, 833 }; 834 835 static const struct panel_desc ampire_am_1280800w8tzqw_t00h = { 836 .modes = &ire_am_1280800w8tzqw_t00h_mode, 837 .num_modes = 1, 838 .bpc = 8, 839 .size = { 840 .width = 217, 841 .height = 136, 842 }, 843 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 845 .connector_type = DRM_MODE_CONNECTOR_LVDS, 846 }; 847 848 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 849 .clock = 9000, 850 .hdisplay = 480, 851 .hsync_start = 480 + 2, 852 .hsync_end = 480 + 2 + 41, 853 .htotal = 480 + 2 + 41 + 2, 854 .vdisplay = 272, 855 .vsync_start = 272 + 2, 856 .vsync_end = 272 + 2 + 10, 857 .vtotal = 272 + 2 + 10 + 2, 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 859 }; 860 861 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 862 .modes = &ire_am_480272h3tmqw_t01h_mode, 863 .num_modes = 1, 864 .bpc = 8, 865 .size = { 866 .width = 99, 867 .height = 58, 868 }, 869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 870 }; 871 872 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 873 .clock = 33333, 874 .hdisplay = 800, 875 .hsync_start = 800 + 0, 876 .hsync_end = 800 + 0 + 255, 877 .htotal = 800 + 0 + 255 + 0, 878 .vdisplay = 480, 879 .vsync_start = 480 + 2, 880 .vsync_end = 480 + 2 + 45, 881 .vtotal = 480 + 2 + 45 + 0, 882 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 883 }; 884 885 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 886 .pixelclock = { 29930000, 33260000, 36590000 }, 887 .hactive = { 800, 800, 800 }, 888 .hfront_porch = { 1, 40, 168 }, 889 .hback_porch = { 88, 88, 88 }, 890 .hsync_len = { 1, 128, 128 }, 891 .vactive = { 480, 480, 480 }, 892 .vfront_porch = { 1, 35, 37 }, 893 .vback_porch = { 8, 8, 8 }, 894 .vsync_len = { 1, 2, 2 }, 895 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 896 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 897 DISPLAY_FLAGS_SYNC_POSEDGE, 898 }; 899 900 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 901 .timings = &ire_am_800480l1tmqw_t00h_timing, 902 .num_timings = 1, 903 .bpc = 8, 904 .size = { 905 .width = 111, 906 .height = 67, 907 }, 908 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 909 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 910 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 911 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 912 .connector_type = DRM_MODE_CONNECTOR_DPI, 913 }; 914 915 static const struct panel_desc ampire_am800480r3tmqwa1h = { 916 .modes = &ire_am800480r3tmqwa1h_mode, 917 .num_modes = 1, 918 .bpc = 6, 919 .size = { 920 .width = 152, 921 .height = 91, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 924 }; 925 926 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 927 .pixelclock = { 34500000, 39600000, 50400000 }, 928 .hactive = { 800, 800, 800 }, 929 .hfront_porch = { 12, 112, 312 }, 930 .hback_porch = { 87, 87, 48 }, 931 .hsync_len = { 1, 1, 40 }, 932 .vactive = { 600, 600, 600 }, 933 .vfront_porch = { 1, 21, 61 }, 934 .vback_porch = { 38, 38, 19 }, 935 .vsync_len = { 1, 1, 20 }, 936 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 937 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 938 DISPLAY_FLAGS_SYNC_POSEDGE, 939 }; 940 941 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 942 .timings = &ire_am800600p5tmqw_tb8h_timing, 943 .num_timings = 1, 944 .bpc = 6, 945 .size = { 946 .width = 162, 947 .height = 122, 948 }, 949 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 950 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 951 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 952 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 953 .connector_type = DRM_MODE_CONNECTOR_DPI, 954 }; 955 956 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 957 .pixelclock = { 26400000, 33300000, 46800000 }, 958 .hactive = { 800, 800, 800 }, 959 .hfront_porch = { 16, 210, 354 }, 960 .hback_porch = { 45, 36, 6 }, 961 .hsync_len = { 1, 10, 40 }, 962 .vactive = { 480, 480, 480 }, 963 .vfront_porch = { 7, 22, 147 }, 964 .vback_porch = { 22, 13, 3 }, 965 .vsync_len = { 1, 10, 20 }, 966 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 967 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 968 }; 969 970 static const struct panel_desc armadeus_st0700_adapt = { 971 .timings = &santek_st0700i5y_rbslw_f_timing, 972 .num_timings = 1, 973 .bpc = 6, 974 .size = { 975 .width = 154, 976 .height = 86, 977 }, 978 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 979 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 980 }; 981 982 static const struct drm_display_mode auo_b101aw03_mode = { 983 .clock = 51450, 984 .hdisplay = 1024, 985 .hsync_start = 1024 + 156, 986 .hsync_end = 1024 + 156 + 8, 987 .htotal = 1024 + 156 + 8 + 156, 988 .vdisplay = 600, 989 .vsync_start = 600 + 16, 990 .vsync_end = 600 + 16 + 6, 991 .vtotal = 600 + 16 + 6 + 16, 992 }; 993 994 static const struct panel_desc auo_b101aw03 = { 995 .modes = &auo_b101aw03_mode, 996 .num_modes = 1, 997 .bpc = 6, 998 .size = { 999 .width = 223, 1000 .height = 125, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1005 }; 1006 1007 static const struct drm_display_mode auo_b101xtn01_mode = { 1008 .clock = 72000, 1009 .hdisplay = 1366, 1010 .hsync_start = 1366 + 20, 1011 .hsync_end = 1366 + 20 + 70, 1012 .htotal = 1366 + 20 + 70, 1013 .vdisplay = 768, 1014 .vsync_start = 768 + 14, 1015 .vsync_end = 768 + 14 + 42, 1016 .vtotal = 768 + 14 + 42, 1017 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1018 }; 1019 1020 static const struct panel_desc auo_b101xtn01 = { 1021 .modes = &auo_b101xtn01_mode, 1022 .num_modes = 1, 1023 .bpc = 6, 1024 .size = { 1025 .width = 223, 1026 .height = 125, 1027 }, 1028 }; 1029 1030 static const struct drm_display_mode auo_b116xw03_mode = { 1031 .clock = 70589, 1032 .hdisplay = 1366, 1033 .hsync_start = 1366 + 40, 1034 .hsync_end = 1366 + 40 + 40, 1035 .htotal = 1366 + 40 + 40 + 32, 1036 .vdisplay = 768, 1037 .vsync_start = 768 + 10, 1038 .vsync_end = 768 + 10 + 12, 1039 .vtotal = 768 + 10 + 12 + 6, 1040 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1041 }; 1042 1043 static const struct panel_desc auo_b116xw03 = { 1044 .modes = &auo_b116xw03_mode, 1045 .num_modes = 1, 1046 .bpc = 6, 1047 .size = { 1048 .width = 256, 1049 .height = 144, 1050 }, 1051 .delay = { 1052 .prepare = 1, 1053 .enable = 200, 1054 .disable = 200, 1055 .unprepare = 500, 1056 }, 1057 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1058 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1059 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1060 }; 1061 1062 static const struct display_timing auo_g070vvn01_timings = { 1063 .pixelclock = { 33300000, 34209000, 45000000 }, 1064 .hactive = { 800, 800, 800 }, 1065 .hfront_porch = { 20, 40, 200 }, 1066 .hback_porch = { 87, 40, 1 }, 1067 .hsync_len = { 1, 48, 87 }, 1068 .vactive = { 480, 480, 480 }, 1069 .vfront_porch = { 5, 13, 200 }, 1070 .vback_porch = { 31, 31, 29 }, 1071 .vsync_len = { 1, 1, 3 }, 1072 }; 1073 1074 static const struct panel_desc auo_g070vvn01 = { 1075 .timings = &auo_g070vvn01_timings, 1076 .num_timings = 1, 1077 .bpc = 8, 1078 .size = { 1079 .width = 152, 1080 .height = 91, 1081 }, 1082 .delay = { 1083 .prepare = 200, 1084 .enable = 50, 1085 .disable = 50, 1086 .unprepare = 1000, 1087 }, 1088 }; 1089 1090 static const struct display_timing auo_g101evn010_timing = { 1091 .pixelclock = { 64000000, 68930000, 85000000 }, 1092 .hactive = { 1280, 1280, 1280 }, 1093 .hfront_porch = { 8, 64, 256 }, 1094 .hback_porch = { 8, 64, 256 }, 1095 .hsync_len = { 40, 168, 767 }, 1096 .vactive = { 800, 800, 800 }, 1097 .vfront_porch = { 4, 8, 100 }, 1098 .vback_porch = { 4, 8, 100 }, 1099 .vsync_len = { 8, 16, 223 }, 1100 }; 1101 1102 static const struct panel_desc auo_g101evn010 = { 1103 .timings = &auo_g101evn010_timing, 1104 .num_timings = 1, 1105 .bpc = 6, 1106 .size = { 1107 .width = 216, 1108 .height = 135, 1109 }, 1110 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1111 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1112 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1113 }; 1114 1115 static const struct drm_display_mode auo_g104sn02_mode = { 1116 .clock = 40000, 1117 .hdisplay = 800, 1118 .hsync_start = 800 + 40, 1119 .hsync_end = 800 + 40 + 216, 1120 .htotal = 800 + 40 + 216 + 128, 1121 .vdisplay = 600, 1122 .vsync_start = 600 + 10, 1123 .vsync_end = 600 + 10 + 35, 1124 .vtotal = 600 + 10 + 35 + 2, 1125 }; 1126 1127 static const struct panel_desc auo_g104sn02 = { 1128 .modes = &auo_g104sn02_mode, 1129 .num_modes = 1, 1130 .bpc = 8, 1131 .size = { 1132 .width = 211, 1133 .height = 158, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1136 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1137 }; 1138 1139 static const struct drm_display_mode auo_g104stn01_mode = { 1140 .clock = 40000, 1141 .hdisplay = 800, 1142 .hsync_start = 800 + 40, 1143 .hsync_end = 800 + 40 + 88, 1144 .htotal = 800 + 40 + 88 + 128, 1145 .vdisplay = 600, 1146 .vsync_start = 600 + 1, 1147 .vsync_end = 600 + 1 + 23, 1148 .vtotal = 600 + 1 + 23 + 4, 1149 }; 1150 1151 static const struct panel_desc auo_g104stn01 = { 1152 .modes = &auo_g104stn01_mode, 1153 .num_modes = 1, 1154 .bpc = 8, 1155 .size = { 1156 .width = 211, 1157 .height = 158, 1158 }, 1159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1161 }; 1162 1163 static const struct display_timing auo_g121ean01_timing = { 1164 .pixelclock = { 60000000, 74400000, 90000000 }, 1165 .hactive = { 1280, 1280, 1280 }, 1166 .hfront_porch = { 20, 50, 100 }, 1167 .hback_porch = { 20, 50, 100 }, 1168 .hsync_len = { 30, 100, 200 }, 1169 .vactive = { 800, 800, 800 }, 1170 .vfront_porch = { 2, 10, 25 }, 1171 .vback_porch = { 2, 10, 25 }, 1172 .vsync_len = { 4, 18, 50 }, 1173 }; 1174 1175 static const struct panel_desc auo_g121ean01 = { 1176 .timings = &auo_g121ean01_timing, 1177 .num_timings = 1, 1178 .bpc = 8, 1179 .size = { 1180 .width = 261, 1181 .height = 163, 1182 }, 1183 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1184 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1185 }; 1186 1187 static const struct display_timing auo_g133han01_timings = { 1188 .pixelclock = { 134000000, 141200000, 149000000 }, 1189 .hactive = { 1920, 1920, 1920 }, 1190 .hfront_porch = { 39, 58, 77 }, 1191 .hback_porch = { 59, 88, 117 }, 1192 .hsync_len = { 28, 42, 56 }, 1193 .vactive = { 1080, 1080, 1080 }, 1194 .vfront_porch = { 3, 8, 11 }, 1195 .vback_porch = { 5, 14, 19 }, 1196 .vsync_len = { 4, 14, 19 }, 1197 }; 1198 1199 static const struct panel_desc auo_g133han01 = { 1200 .timings = &auo_g133han01_timings, 1201 .num_timings = 1, 1202 .bpc = 8, 1203 .size = { 1204 .width = 293, 1205 .height = 165, 1206 }, 1207 .delay = { 1208 .prepare = 200, 1209 .enable = 50, 1210 .disable = 50, 1211 .unprepare = 1000, 1212 }, 1213 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1214 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1215 }; 1216 1217 static const struct display_timing auo_g156han04_timings = { 1218 .pixelclock = { 137000000, 141000000, 146000000 }, 1219 .hactive = { 1920, 1920, 1920 }, 1220 .hfront_porch = { 60, 60, 60 }, 1221 .hback_porch = { 90, 92, 111 }, 1222 .hsync_len = { 32, 32, 32 }, 1223 .vactive = { 1080, 1080, 1080 }, 1224 .vfront_porch = { 12, 12, 12 }, 1225 .vback_porch = { 24, 36, 56 }, 1226 .vsync_len = { 8, 8, 8 }, 1227 }; 1228 1229 static const struct panel_desc auo_g156han04 = { 1230 .timings = &auo_g156han04_timings, 1231 .num_timings = 1, 1232 .bpc = 8, 1233 .size = { 1234 .width = 344, 1235 .height = 194, 1236 }, 1237 .delay = { 1238 .prepare = 50, /* T2 */ 1239 .enable = 200, /* T3 */ 1240 .disable = 110, /* T10 */ 1241 .unprepare = 1000, /* T13 */ 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1244 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1246 }; 1247 1248 static const struct drm_display_mode auo_g156xtn01_mode = { 1249 .clock = 76000, 1250 .hdisplay = 1366, 1251 .hsync_start = 1366 + 33, 1252 .hsync_end = 1366 + 33 + 67, 1253 .htotal = 1560, 1254 .vdisplay = 768, 1255 .vsync_start = 768 + 4, 1256 .vsync_end = 768 + 4 + 4, 1257 .vtotal = 806, 1258 }; 1259 1260 static const struct panel_desc auo_g156xtn01 = { 1261 .modes = &auo_g156xtn01_mode, 1262 .num_modes = 1, 1263 .bpc = 8, 1264 .size = { 1265 .width = 344, 1266 .height = 194, 1267 }, 1268 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1269 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1270 }; 1271 1272 static const struct display_timing auo_g185han01_timings = { 1273 .pixelclock = { 120000000, 144000000, 175000000 }, 1274 .hactive = { 1920, 1920, 1920 }, 1275 .hfront_porch = { 36, 120, 148 }, 1276 .hback_porch = { 24, 88, 108 }, 1277 .hsync_len = { 20, 48, 64 }, 1278 .vactive = { 1080, 1080, 1080 }, 1279 .vfront_porch = { 6, 10, 40 }, 1280 .vback_porch = { 2, 5, 20 }, 1281 .vsync_len = { 2, 5, 20 }, 1282 }; 1283 1284 static const struct panel_desc auo_g185han01 = { 1285 .timings = &auo_g185han01_timings, 1286 .num_timings = 1, 1287 .bpc = 8, 1288 .size = { 1289 .width = 409, 1290 .height = 230, 1291 }, 1292 .delay = { 1293 .prepare = 50, 1294 .enable = 200, 1295 .disable = 110, 1296 .unprepare = 1000, 1297 }, 1298 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1299 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1300 }; 1301 1302 static const struct display_timing auo_g190ean01_timings = { 1303 .pixelclock = { 90000000, 108000000, 135000000 }, 1304 .hactive = { 1280, 1280, 1280 }, 1305 .hfront_porch = { 126, 184, 1266 }, 1306 .hback_porch = { 84, 122, 844 }, 1307 .hsync_len = { 70, 102, 704 }, 1308 .vactive = { 1024, 1024, 1024 }, 1309 .vfront_porch = { 4, 26, 76 }, 1310 .vback_porch = { 2, 8, 25 }, 1311 .vsync_len = { 2, 8, 25 }, 1312 }; 1313 1314 static const struct panel_desc auo_g190ean01 = { 1315 .timings = &auo_g190ean01_timings, 1316 .num_timings = 1, 1317 .bpc = 8, 1318 .size = { 1319 .width = 376, 1320 .height = 301, 1321 }, 1322 .delay = { 1323 .prepare = 30, 1324 .enable = 200, 1325 .disable = 110, 1326 .unprepare = 1000, 1327 }, 1328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1329 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1330 }; 1331 1332 static const struct display_timing auo_p238han01_timings = { 1333 .pixelclock = { 107400000, 142400000, 180000000 }, 1334 .hactive = { 1920, 1920, 1920 }, 1335 .hfront_porch = { 30, 70, 650 }, 1336 .hback_porch = { 30, 70, 650 }, 1337 .hsync_len = { 20, 40, 136 }, 1338 .vactive = { 1080, 1080, 1080 }, 1339 .vfront_porch = { 5, 19, 318 }, 1340 .vback_porch = { 5, 19, 318 }, 1341 .vsync_len = { 4, 12, 120 }, 1342 }; 1343 1344 static const struct panel_desc auo_p238han01 = { 1345 .timings = &auo_p238han01_timings, 1346 .num_timings = 1, 1347 .bpc = 8, 1348 .size = { 1349 .width = 527, 1350 .height = 296, 1351 }, 1352 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1353 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1354 }; 1355 1356 static const struct display_timing auo_p320hvn03_timings = { 1357 .pixelclock = { 106000000, 148500000, 164000000 }, 1358 .hactive = { 1920, 1920, 1920 }, 1359 .hfront_porch = { 25, 50, 130 }, 1360 .hback_porch = { 25, 50, 130 }, 1361 .hsync_len = { 20, 40, 105 }, 1362 .vactive = { 1080, 1080, 1080 }, 1363 .vfront_porch = { 8, 17, 150 }, 1364 .vback_porch = { 8, 17, 150 }, 1365 .vsync_len = { 4, 11, 100 }, 1366 }; 1367 1368 static const struct panel_desc auo_p320hvn03 = { 1369 .timings = &auo_p320hvn03_timings, 1370 .num_timings = 1, 1371 .bpc = 8, 1372 .size = { 1373 .width = 698, 1374 .height = 393, 1375 }, 1376 .delay = { 1377 .prepare = 1, 1378 .enable = 450, 1379 .unprepare = 500, 1380 }, 1381 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1382 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1383 }; 1384 1385 static const struct drm_display_mode auo_t215hvn01_mode = { 1386 .clock = 148800, 1387 .hdisplay = 1920, 1388 .hsync_start = 1920 + 88, 1389 .hsync_end = 1920 + 88 + 44, 1390 .htotal = 1920 + 88 + 44 + 148, 1391 .vdisplay = 1080, 1392 .vsync_start = 1080 + 4, 1393 .vsync_end = 1080 + 4 + 5, 1394 .vtotal = 1080 + 4 + 5 + 36, 1395 }; 1396 1397 static const struct panel_desc auo_t215hvn01 = { 1398 .modes = &auo_t215hvn01_mode, 1399 .num_modes = 1, 1400 .bpc = 8, 1401 .size = { 1402 .width = 430, 1403 .height = 270, 1404 }, 1405 .delay = { 1406 .disable = 5, 1407 .unprepare = 1000, 1408 }, 1409 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1410 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1411 }; 1412 1413 static const struct drm_display_mode avic_tm070ddh03_mode = { 1414 .clock = 51200, 1415 .hdisplay = 1024, 1416 .hsync_start = 1024 + 160, 1417 .hsync_end = 1024 + 160 + 4, 1418 .htotal = 1024 + 160 + 4 + 156, 1419 .vdisplay = 600, 1420 .vsync_start = 600 + 17, 1421 .vsync_end = 600 + 17 + 1, 1422 .vtotal = 600 + 17 + 1 + 17, 1423 }; 1424 1425 static const struct panel_desc avic_tm070ddh03 = { 1426 .modes = &avic_tm070ddh03_mode, 1427 .num_modes = 1, 1428 .bpc = 8, 1429 .size = { 1430 .width = 154, 1431 .height = 90, 1432 }, 1433 .delay = { 1434 .prepare = 20, 1435 .enable = 200, 1436 .disable = 200, 1437 }, 1438 }; 1439 1440 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1441 .clock = 30000, 1442 .hdisplay = 800, 1443 .hsync_start = 800 + 40, 1444 .hsync_end = 800 + 40 + 48, 1445 .htotal = 800 + 40 + 48 + 40, 1446 .vdisplay = 480, 1447 .vsync_start = 480 + 13, 1448 .vsync_end = 480 + 13 + 3, 1449 .vtotal = 480 + 13 + 3 + 29, 1450 }; 1451 1452 static const struct panel_desc bananapi_s070wv20_ct16 = { 1453 .modes = &bananapi_s070wv20_ct16_mode, 1454 .num_modes = 1, 1455 .bpc = 6, 1456 .size = { 1457 .width = 154, 1458 .height = 86, 1459 }, 1460 }; 1461 1462 static const struct display_timing boe_av101hdt_a10_timing = { 1463 .pixelclock = { 74210000, 75330000, 76780000, }, 1464 .hactive = { 1280, 1280, 1280, }, 1465 .hfront_porch = { 10, 42, 33, }, 1466 .hback_porch = { 10, 18, 33, }, 1467 .hsync_len = { 30, 10, 30, }, 1468 .vactive = { 720, 720, 720, }, 1469 .vfront_porch = { 200, 183, 200, }, 1470 .vback_porch = { 8, 8, 8, }, 1471 .vsync_len = { 2, 19, 2, }, 1472 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1473 }; 1474 1475 static const struct panel_desc boe_av101hdt_a10 = { 1476 .timings = &boe_av101hdt_a10_timing, 1477 .num_timings = 1, 1478 .bpc = 8, 1479 .size = { 1480 .width = 224, 1481 .height = 126, 1482 }, 1483 .delay = { 1484 .enable = 50, 1485 .disable = 50, 1486 }, 1487 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1488 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1489 }; 1490 1491 static const struct display_timing boe_av123z7m_n17_timing = { 1492 .pixelclock = { 86600000, 88000000, 90800000, }, 1493 .hactive = { 1920, 1920, 1920, }, 1494 .hfront_porch = { 10, 10, 10, }, 1495 .hback_porch = { 10, 10, 10, }, 1496 .hsync_len = { 9, 12, 25, }, 1497 .vactive = { 720, 720, 720, }, 1498 .vfront_porch = { 7, 10, 13, }, 1499 .vback_porch = { 7, 10, 13, }, 1500 .vsync_len = { 7, 11, 14, }, 1501 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1502 }; 1503 1504 static const struct panel_desc boe_av123z7m_n17 = { 1505 .timings = &boe_av123z7m_n17_timing, 1506 .bpc = 8, 1507 .num_timings = 1, 1508 .size = { 1509 .width = 292, 1510 .height = 110, 1511 }, 1512 .delay = { 1513 .prepare = 50, 1514 .disable = 50, 1515 }, 1516 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1517 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1518 }; 1519 1520 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1521 .clock = 78945, 1522 .hdisplay = 1280, 1523 .hsync_start = 1280 + 0, 1524 .hsync_end = 1280 + 0 + 2, 1525 .htotal = 1280 + 62 + 0 + 2, 1526 .vdisplay = 800, 1527 .vsync_start = 800 + 8, 1528 .vsync_end = 800 + 8 + 2, 1529 .vtotal = 800 + 6 + 8 + 2, 1530 }; 1531 1532 static const struct panel_desc boe_bp082wx1_100 = { 1533 .modes = &boe_bp101wx1_100_mode, 1534 .num_modes = 1, 1535 .bpc = 8, 1536 .size = { 1537 .width = 177, 1538 .height = 110, 1539 }, 1540 .delay = { 1541 .enable = 50, 1542 .disable = 50, 1543 }, 1544 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1545 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1546 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1547 }; 1548 1549 static const struct panel_desc boe_bp101wx1_100 = { 1550 .modes = &boe_bp101wx1_100_mode, 1551 .num_modes = 1, 1552 .bpc = 8, 1553 .size = { 1554 .width = 217, 1555 .height = 136, 1556 }, 1557 .delay = { 1558 .enable = 50, 1559 .disable = 50, 1560 }, 1561 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1562 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1563 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1564 }; 1565 1566 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1567 .pixelclock = { 69922000, 71000000, 72293000 }, 1568 .hactive = { 1280, 1280, 1280 }, 1569 .hfront_porch = { 48, 48, 48 }, 1570 .hback_porch = { 80, 80, 80 }, 1571 .hsync_len = { 32, 32, 32 }, 1572 .vactive = { 800, 800, 800 }, 1573 .vfront_porch = { 3, 3, 3 }, 1574 .vback_porch = { 14, 14, 14 }, 1575 .vsync_len = { 6, 6, 6 }, 1576 }; 1577 1578 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1579 .timings = &boe_ev121wxm_n10_1850_timing, 1580 .num_timings = 1, 1581 .bpc = 8, 1582 .size = { 1583 .width = 261, 1584 .height = 163, 1585 }, 1586 .delay = { 1587 .prepare = 9, 1588 .enable = 300, 1589 .unprepare = 300, 1590 .disable = 560, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1595 }; 1596 1597 static const struct drm_display_mode boe_hv070wsa_mode = { 1598 .clock = 42105, 1599 .hdisplay = 1024, 1600 .hsync_start = 1024 + 30, 1601 .hsync_end = 1024 + 30 + 30, 1602 .htotal = 1024 + 30 + 30 + 30, 1603 .vdisplay = 600, 1604 .vsync_start = 600 + 10, 1605 .vsync_end = 600 + 10 + 10, 1606 .vtotal = 600 + 10 + 10 + 10, 1607 }; 1608 1609 static const struct panel_desc boe_hv070wsa = { 1610 .modes = &boe_hv070wsa_mode, 1611 .num_modes = 1, 1612 .bpc = 8, 1613 .size = { 1614 .width = 154, 1615 .height = 90, 1616 }, 1617 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1618 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1619 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1620 }; 1621 1622 static const struct display_timing cct_cmt430b19n00_timing = { 1623 .pixelclock = { 8000000, 9000000, 12000000 }, 1624 .hactive = { 480, 480, 480 }, 1625 .hfront_porch = { 2, 8, 75 }, 1626 .hback_porch = { 3, 43, 43 }, 1627 .hsync_len = { 2, 4, 75 }, 1628 .vactive = { 272, 272, 272 }, 1629 .vfront_porch = { 2, 8, 37 }, 1630 .vback_porch = { 2, 12, 12 }, 1631 .vsync_len = { 2, 4, 37 }, 1632 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1633 }; 1634 1635 static const struct panel_desc cct_cmt430b19n00 = { 1636 .timings = &cct_cmt430b19n00_timing, 1637 .num_timings = 1, 1638 .bpc = 8, 1639 .size = { 1640 .width = 95, 1641 .height = 53, 1642 }, 1643 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1644 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1645 .connector_type = DRM_MODE_CONNECTOR_DPI, 1646 }; 1647 1648 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1649 .clock = 9000, 1650 .hdisplay = 480, 1651 .hsync_start = 480 + 5, 1652 .hsync_end = 480 + 5 + 5, 1653 .htotal = 480 + 5 + 5 + 40, 1654 .vdisplay = 272, 1655 .vsync_start = 272 + 8, 1656 .vsync_end = 272 + 8 + 8, 1657 .vtotal = 272 + 8 + 8 + 8, 1658 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1659 }; 1660 1661 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1662 .modes = &cdtech_s043wq26h_ct7_mode, 1663 .num_modes = 1, 1664 .bpc = 8, 1665 .size = { 1666 .width = 95, 1667 .height = 54, 1668 }, 1669 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1670 }; 1671 1672 /* S070PWS19HP-FC21 2017/04/22 */ 1673 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1674 .clock = 51200, 1675 .hdisplay = 1024, 1676 .hsync_start = 1024 + 160, 1677 .hsync_end = 1024 + 160 + 20, 1678 .htotal = 1024 + 160 + 20 + 140, 1679 .vdisplay = 600, 1680 .vsync_start = 600 + 12, 1681 .vsync_end = 600 + 12 + 3, 1682 .vtotal = 600 + 12 + 3 + 20, 1683 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1684 }; 1685 1686 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1687 .modes = &cdtech_s070pws19hp_fc21_mode, 1688 .num_modes = 1, 1689 .bpc = 6, 1690 .size = { 1691 .width = 154, 1692 .height = 86, 1693 }, 1694 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1695 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1696 .connector_type = DRM_MODE_CONNECTOR_DPI, 1697 }; 1698 1699 /* S070SWV29HG-DC44 2017/09/21 */ 1700 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1701 .clock = 33300, 1702 .hdisplay = 800, 1703 .hsync_start = 800 + 210, 1704 .hsync_end = 800 + 210 + 2, 1705 .htotal = 800 + 210 + 2 + 44, 1706 .vdisplay = 480, 1707 .vsync_start = 480 + 22, 1708 .vsync_end = 480 + 22 + 2, 1709 .vtotal = 480 + 22 + 2 + 21, 1710 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1711 }; 1712 1713 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1714 .modes = &cdtech_s070swv29hg_dc44_mode, 1715 .num_modes = 1, 1716 .bpc = 6, 1717 .size = { 1718 .width = 154, 1719 .height = 86, 1720 }, 1721 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1722 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1723 .connector_type = DRM_MODE_CONNECTOR_DPI, 1724 }; 1725 1726 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1727 .clock = 35000, 1728 .hdisplay = 800, 1729 .hsync_start = 800 + 40, 1730 .hsync_end = 800 + 40 + 40, 1731 .htotal = 800 + 40 + 40 + 48, 1732 .vdisplay = 480, 1733 .vsync_start = 480 + 29, 1734 .vsync_end = 480 + 29 + 13, 1735 .vtotal = 480 + 29 + 13 + 3, 1736 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1737 }; 1738 1739 static const struct panel_desc cdtech_s070wv95_ct16 = { 1740 .modes = &cdtech_s070wv95_ct16_mode, 1741 .num_modes = 1, 1742 .bpc = 8, 1743 .size = { 1744 .width = 154, 1745 .height = 85, 1746 }, 1747 }; 1748 1749 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1750 .pixelclock = { 68900000, 71100000, 73400000 }, 1751 .hactive = { 1280, 1280, 1280 }, 1752 .hfront_porch = { 65, 80, 95 }, 1753 .hback_porch = { 64, 79, 94 }, 1754 .hsync_len = { 1, 1, 1 }, 1755 .vactive = { 800, 800, 800 }, 1756 .vfront_porch = { 7, 11, 14 }, 1757 .vback_porch = { 7, 11, 14 }, 1758 .vsync_len = { 1, 1, 1 }, 1759 .flags = DISPLAY_FLAGS_DE_HIGH, 1760 }; 1761 1762 static const struct panel_desc chefree_ch101olhlwh_002 = { 1763 .timings = &chefree_ch101olhlwh_002_timing, 1764 .num_timings = 1, 1765 .bpc = 8, 1766 .size = { 1767 .width = 217, 1768 .height = 135, 1769 }, 1770 .delay = { 1771 .enable = 200, 1772 .disable = 200, 1773 }, 1774 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1775 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1776 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1777 }; 1778 1779 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1780 .clock = 66770, 1781 .hdisplay = 800, 1782 .hsync_start = 800 + 49, 1783 .hsync_end = 800 + 49 + 33, 1784 .htotal = 800 + 49 + 33 + 17, 1785 .vdisplay = 1280, 1786 .vsync_start = 1280 + 1, 1787 .vsync_end = 1280 + 1 + 7, 1788 .vtotal = 1280 + 1 + 7 + 15, 1789 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1790 }; 1791 1792 static const struct panel_desc chunghwa_claa070wp03xg = { 1793 .modes = &chunghwa_claa070wp03xg_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 94, 1798 .height = 150, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1802 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1803 }; 1804 1805 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1806 .clock = 72070, 1807 .hdisplay = 1366, 1808 .hsync_start = 1366 + 58, 1809 .hsync_end = 1366 + 58 + 58, 1810 .htotal = 1366 + 58 + 58 + 58, 1811 .vdisplay = 768, 1812 .vsync_start = 768 + 4, 1813 .vsync_end = 768 + 4 + 4, 1814 .vtotal = 768 + 4 + 4 + 4, 1815 }; 1816 1817 static const struct panel_desc chunghwa_claa101wa01a = { 1818 .modes = &chunghwa_claa101wa01a_mode, 1819 .num_modes = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 220, 1823 .height = 120, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1828 }; 1829 1830 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1831 .clock = 69300, 1832 .hdisplay = 1366, 1833 .hsync_start = 1366 + 48, 1834 .hsync_end = 1366 + 48 + 32, 1835 .htotal = 1366 + 48 + 32 + 20, 1836 .vdisplay = 768, 1837 .vsync_start = 768 + 16, 1838 .vsync_end = 768 + 16 + 8, 1839 .vtotal = 768 + 16 + 8 + 16, 1840 }; 1841 1842 static const struct panel_desc chunghwa_claa101wb01 = { 1843 .modes = &chunghwa_claa101wb01_mode, 1844 .num_modes = 1, 1845 .bpc = 6, 1846 .size = { 1847 .width = 223, 1848 .height = 125, 1849 }, 1850 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1851 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1852 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1853 }; 1854 1855 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1856 .pixelclock = { 5000000, 9000000, 12000000 }, 1857 .hactive = { 480, 480, 480 }, 1858 .hfront_porch = { 12, 12, 12 }, 1859 .hback_porch = { 12, 12, 12 }, 1860 .hsync_len = { 21, 21, 21 }, 1861 .vactive = { 272, 272, 272 }, 1862 .vfront_porch = { 4, 4, 4 }, 1863 .vback_porch = { 4, 4, 4 }, 1864 .vsync_len = { 8, 8, 8 }, 1865 }; 1866 1867 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1868 .timings = &dataimage_fg040346dsswbg04_timing, 1869 .num_timings = 1, 1870 .bpc = 8, 1871 .size = { 1872 .width = 95, 1873 .height = 54, 1874 }, 1875 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1876 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1877 .connector_type = DRM_MODE_CONNECTOR_DPI, 1878 }; 1879 1880 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1881 .pixelclock = { 68900000, 71110000, 73400000 }, 1882 .hactive = { 1280, 1280, 1280 }, 1883 .vactive = { 800, 800, 800 }, 1884 .hback_porch = { 100, 100, 100 }, 1885 .hfront_porch = { 100, 100, 100 }, 1886 .vback_porch = { 5, 5, 5 }, 1887 .vfront_porch = { 5, 5, 5 }, 1888 .hsync_len = { 24, 24, 24 }, 1889 .vsync_len = { 3, 3, 3 }, 1890 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1891 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1892 }; 1893 1894 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1895 .timings = &dataimage_fg1001l0dsswmg01_timing, 1896 .num_timings = 1, 1897 .bpc = 8, 1898 .size = { 1899 .width = 217, 1900 .height = 136, 1901 }, 1902 }; 1903 1904 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1905 .clock = 33260, 1906 .hdisplay = 800, 1907 .hsync_start = 800 + 40, 1908 .hsync_end = 800 + 40 + 128, 1909 .htotal = 800 + 40 + 128 + 88, 1910 .vdisplay = 480, 1911 .vsync_start = 480 + 10, 1912 .vsync_end = 480 + 10 + 2, 1913 .vtotal = 480 + 10 + 2 + 33, 1914 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1915 }; 1916 1917 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1918 .modes = &dataimage_scf0700c48ggu18_mode, 1919 .num_modes = 1, 1920 .bpc = 8, 1921 .size = { 1922 .width = 152, 1923 .height = 91, 1924 }, 1925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1926 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1927 .connector_type = DRM_MODE_CONNECTOR_DPI, 1928 }; 1929 1930 static const struct display_timing displaytech_dt050btft_pts_timing = { 1931 /* The TYP pixel clock are recalculated from tV * tH * 60 Hz */ 1932 .pixelclock = { 30000000, 33264000, 50000000 }, 1933 .hactive = { 800, 800, 800 }, 1934 .hfront_porch = { 16, 210, 354 }, 1935 /* Datasheet Figure 3 indicates, that tHPW is part of tHBP */ 1936 .hback_porch = { 41, 26, 6 }, 1937 .hsync_len = { 1, 20, 40 }, 1938 .vactive = { 480, 480, 480 }, 1939 .vfront_porch = { 7, 22, 147 }, 1940 /* Datasheet Figure 2 indicates, that tVPW is part of tVBP */ 1941 .vback_porch = { 22, 13, 3 }, 1942 .vsync_len = { 1, 10, 20 }, 1943 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1944 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1945 DISPLAY_FLAGS_SYNC_POSEDGE, 1946 }; 1947 1948 static const struct panel_desc displaytech_dt050btft_pts = { 1949 .timings = &displaytech_dt050btft_pts_timing, 1950 .num_timings = 1, 1951 .bpc = 8, 1952 .size = { 1953 .width = 108, 1954 .height = 65, 1955 }, 1956 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1957 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 1958 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 1959 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 1960 .connector_type = DRM_MODE_CONNECTOR_DPI, 1961 }; 1962 1963 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1964 .pixelclock = { 45000000, 51200000, 57000000 }, 1965 .hactive = { 1024, 1024, 1024 }, 1966 .hfront_porch = { 100, 106, 113 }, 1967 .hback_porch = { 100, 106, 113 }, 1968 .hsync_len = { 100, 108, 114 }, 1969 .vactive = { 600, 600, 600 }, 1970 .vfront_porch = { 8, 11, 15 }, 1971 .vback_porch = { 8, 11, 15 }, 1972 .vsync_len = { 9, 13, 15 }, 1973 .flags = DISPLAY_FLAGS_DE_HIGH, 1974 }; 1975 1976 static const struct panel_desc dlc_dlc0700yzg_1 = { 1977 .timings = &dlc_dlc0700yzg_1_timing, 1978 .num_timings = 1, 1979 .bpc = 6, 1980 .size = { 1981 .width = 154, 1982 .height = 86, 1983 }, 1984 .delay = { 1985 .prepare = 30, 1986 .enable = 200, 1987 .disable = 200, 1988 }, 1989 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1990 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1991 }; 1992 1993 static const struct display_timing dlc_dlc1010gig_timing = { 1994 .pixelclock = { 68900000, 71100000, 73400000 }, 1995 .hactive = { 1280, 1280, 1280 }, 1996 .hfront_porch = { 43, 53, 63 }, 1997 .hback_porch = { 43, 53, 63 }, 1998 .hsync_len = { 44, 54, 64 }, 1999 .vactive = { 800, 800, 800 }, 2000 .vfront_porch = { 5, 8, 11 }, 2001 .vback_porch = { 5, 8, 11 }, 2002 .vsync_len = { 5, 7, 11 }, 2003 .flags = DISPLAY_FLAGS_DE_HIGH, 2004 }; 2005 2006 static const struct panel_desc dlc_dlc1010gig = { 2007 .timings = &dlc_dlc1010gig_timing, 2008 .num_timings = 1, 2009 .bpc = 8, 2010 .size = { 2011 .width = 216, 2012 .height = 135, 2013 }, 2014 .delay = { 2015 .prepare = 60, 2016 .enable = 150, 2017 .disable = 100, 2018 .unprepare = 60, 2019 }, 2020 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2021 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2022 }; 2023 2024 static const struct drm_display_mode edt_et035012dm6_mode = { 2025 .clock = 6500, 2026 .hdisplay = 320, 2027 .hsync_start = 320 + 20, 2028 .hsync_end = 320 + 20 + 30, 2029 .htotal = 320 + 20 + 68, 2030 .vdisplay = 240, 2031 .vsync_start = 240 + 4, 2032 .vsync_end = 240 + 4 + 4, 2033 .vtotal = 240 + 4 + 4 + 14, 2034 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2035 }; 2036 2037 static const struct panel_desc edt_et035012dm6 = { 2038 .modes = &edt_et035012dm6_mode, 2039 .num_modes = 1, 2040 .bpc = 8, 2041 .size = { 2042 .width = 70, 2043 .height = 52, 2044 }, 2045 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2046 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2047 }; 2048 2049 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 2050 .clock = 6520, 2051 .hdisplay = 320, 2052 .hsync_start = 320 + 20, 2053 .hsync_end = 320 + 20 + 68, 2054 .htotal = 320 + 20 + 68, 2055 .vdisplay = 240, 2056 .vsync_start = 240 + 4, 2057 .vsync_end = 240 + 4 + 18, 2058 .vtotal = 240 + 4 + 18, 2059 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2060 }; 2061 2062 static const struct panel_desc edt_etm0350g0dh6 = { 2063 .modes = &edt_etm0350g0dh6_mode, 2064 .num_modes = 1, 2065 .bpc = 6, 2066 .size = { 2067 .width = 70, 2068 .height = 53, 2069 }, 2070 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2071 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2072 .connector_type = DRM_MODE_CONNECTOR_DPI, 2073 }; 2074 2075 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2076 .clock = 10870, 2077 .hdisplay = 480, 2078 .hsync_start = 480 + 8, 2079 .hsync_end = 480 + 8 + 4, 2080 .htotal = 480 + 8 + 4 + 41, 2081 2082 /* 2083 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2084 * fb_align 2085 */ 2086 2087 .vdisplay = 288, 2088 .vsync_start = 288 + 2, 2089 .vsync_end = 288 + 2 + 4, 2090 .vtotal = 288 + 2 + 4 + 10, 2091 }; 2092 2093 static const struct panel_desc edt_etm043080dh6gp = { 2094 .modes = &edt_etm043080dh6gp_mode, 2095 .num_modes = 1, 2096 .bpc = 8, 2097 .size = { 2098 .width = 100, 2099 .height = 65, 2100 }, 2101 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2102 .connector_type = DRM_MODE_CONNECTOR_DPI, 2103 }; 2104 2105 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2106 .clock = 9000, 2107 .hdisplay = 480, 2108 .hsync_start = 480 + 2, 2109 .hsync_end = 480 + 2 + 41, 2110 .htotal = 480 + 2 + 41 + 2, 2111 .vdisplay = 272, 2112 .vsync_start = 272 + 2, 2113 .vsync_end = 272 + 2 + 10, 2114 .vtotal = 272 + 2 + 10 + 2, 2115 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2116 }; 2117 2118 static const struct panel_desc edt_etm0430g0dh6 = { 2119 .modes = &edt_etm0430g0dh6_mode, 2120 .num_modes = 1, 2121 .bpc = 6, 2122 .size = { 2123 .width = 95, 2124 .height = 54, 2125 }, 2126 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2127 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2128 .connector_type = DRM_MODE_CONNECTOR_DPI, 2129 }; 2130 2131 static const struct drm_display_mode edt_et057090dhu_mode = { 2132 .clock = 25175, 2133 .hdisplay = 640, 2134 .hsync_start = 640 + 16, 2135 .hsync_end = 640 + 16 + 30, 2136 .htotal = 640 + 16 + 30 + 114, 2137 .vdisplay = 480, 2138 .vsync_start = 480 + 10, 2139 .vsync_end = 480 + 10 + 3, 2140 .vtotal = 480 + 10 + 3 + 32, 2141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2142 }; 2143 2144 static const struct panel_desc edt_et057090dhu = { 2145 .modes = &edt_et057090dhu_mode, 2146 .num_modes = 1, 2147 .bpc = 6, 2148 .size = { 2149 .width = 115, 2150 .height = 86, 2151 }, 2152 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2153 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2154 .connector_type = DRM_MODE_CONNECTOR_DPI, 2155 }; 2156 2157 static const struct display_timing edt_et057023udba_timing = { 2158 .pixelclock = { 23200000, 24190000, 39640000 }, 2159 .hactive = { 640, 640, 640 }, 2160 .hfront_porch = { 20, 40, 200 }, 2161 .hback_porch = { 87, 40, 1 }, 2162 .hsync_len = { 1, 48, 87 }, 2163 .vactive = { 480, 480, 480 }, 2164 .vfront_porch = { 5, 13, 200 }, 2165 .vback_porch = { 31, 31, 29 }, 2166 .vsync_len = { 1, 1, 3 }, 2167 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2168 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2169 DISPLAY_FLAGS_SYNC_POSEDGE, 2170 }; 2171 2172 static const struct panel_desc edt_et057023udba = { 2173 .timings = &edt_et057023udba_timing, 2174 .num_timings = 1, 2175 .bpc = 8, 2176 .size = { 2177 .width = 115, 2178 .height = 86, 2179 }, 2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2181 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2182 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2183 .connector_type = DRM_MODE_CONNECTOR_DPI, 2184 }; 2185 2186 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2187 .clock = 33260, 2188 .hdisplay = 800, 2189 .hsync_start = 800 + 40, 2190 .hsync_end = 800 + 40 + 128, 2191 .htotal = 800 + 40 + 128 + 88, 2192 .vdisplay = 480, 2193 .vsync_start = 480 + 10, 2194 .vsync_end = 480 + 10 + 2, 2195 .vtotal = 480 + 10 + 2 + 33, 2196 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2197 }; 2198 2199 static const struct panel_desc edt_etm0700g0dh6 = { 2200 .modes = &edt_etm0700g0dh6_mode, 2201 .num_modes = 1, 2202 .bpc = 6, 2203 .size = { 2204 .width = 152, 2205 .height = 91, 2206 }, 2207 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2208 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2209 .connector_type = DRM_MODE_CONNECTOR_DPI, 2210 }; 2211 2212 static const struct panel_desc edt_etm0700g0bdh6 = { 2213 .modes = &edt_etm0700g0dh6_mode, 2214 .num_modes = 1, 2215 .bpc = 6, 2216 .size = { 2217 .width = 152, 2218 .height = 91, 2219 }, 2220 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2221 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2222 .connector_type = DRM_MODE_CONNECTOR_DPI, 2223 }; 2224 2225 static const struct display_timing edt_etml0700y5dha_timing = { 2226 .pixelclock = { 40800000, 51200000, 67200000 }, 2227 .hactive = { 1024, 1024, 1024 }, 2228 .hfront_porch = { 30, 106, 125 }, 2229 .hback_porch = { 30, 106, 125 }, 2230 .hsync_len = { 30, 108, 126 }, 2231 .vactive = { 600, 600, 600 }, 2232 .vfront_porch = { 3, 12, 67}, 2233 .vback_porch = { 3, 12, 67 }, 2234 .vsync_len = { 4, 11, 66 }, 2235 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2236 DISPLAY_FLAGS_DE_HIGH, 2237 }; 2238 2239 static const struct panel_desc edt_etml0700y5dha = { 2240 .timings = &edt_etml0700y5dha_timing, 2241 .num_timings = 1, 2242 .bpc = 8, 2243 .size = { 2244 .width = 155, 2245 .height = 86, 2246 }, 2247 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2248 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2249 }; 2250 2251 static const struct display_timing edt_etml1010g3dra_timing = { 2252 .pixelclock = { 66300000, 72400000, 78900000 }, 2253 .hactive = { 1280, 1280, 1280 }, 2254 .hfront_porch = { 12, 72, 132 }, 2255 .hback_porch = { 86, 86, 86 }, 2256 .hsync_len = { 2, 2, 2 }, 2257 .vactive = { 800, 800, 800 }, 2258 .vfront_porch = { 1, 15, 49 }, 2259 .vback_porch = { 21, 21, 21 }, 2260 .vsync_len = { 2, 2, 2 }, 2261 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2262 DISPLAY_FLAGS_DE_HIGH, 2263 }; 2264 2265 static const struct panel_desc edt_etml1010g3dra = { 2266 .timings = &edt_etml1010g3dra_timing, 2267 .num_timings = 1, 2268 .bpc = 8, 2269 .size = { 2270 .width = 216, 2271 .height = 135, 2272 }, 2273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2274 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2276 }; 2277 2278 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2279 .clock = 25175, 2280 .hdisplay = 640, 2281 .hsync_start = 640, 2282 .hsync_end = 640 + 16, 2283 .htotal = 640 + 16 + 30 + 114, 2284 .vdisplay = 480, 2285 .vsync_start = 480 + 10, 2286 .vsync_end = 480 + 10 + 3, 2287 .vtotal = 480 + 10 + 3 + 35, 2288 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2289 }; 2290 2291 static const struct panel_desc edt_etmv570g2dhu = { 2292 .modes = &edt_etmv570g2dhu_mode, 2293 .num_modes = 1, 2294 .bpc = 6, 2295 .size = { 2296 .width = 115, 2297 .height = 86, 2298 }, 2299 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2300 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2301 .connector_type = DRM_MODE_CONNECTOR_DPI, 2302 }; 2303 2304 static const struct display_timing eink_vb3300_kca_timing = { 2305 .pixelclock = { 40000000, 40000000, 40000000 }, 2306 .hactive = { 334, 334, 334 }, 2307 .hfront_porch = { 1, 1, 1 }, 2308 .hback_porch = { 1, 1, 1 }, 2309 .hsync_len = { 1, 1, 1 }, 2310 .vactive = { 1405, 1405, 1405 }, 2311 .vfront_porch = { 1, 1, 1 }, 2312 .vback_porch = { 1, 1, 1 }, 2313 .vsync_len = { 1, 1, 1 }, 2314 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2315 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2316 }; 2317 2318 static const struct panel_desc eink_vb3300_kca = { 2319 .timings = &eink_vb3300_kca_timing, 2320 .num_timings = 1, 2321 .bpc = 6, 2322 .size = { 2323 .width = 157, 2324 .height = 209, 2325 }, 2326 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2327 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2328 .connector_type = DRM_MODE_CONNECTOR_DPI, 2329 }; 2330 2331 static const struct display_timing evervision_vgg644804_timing = { 2332 .pixelclock = { 25175000, 25175000, 25175000 }, 2333 .hactive = { 640, 640, 640 }, 2334 .hfront_porch = { 16, 16, 16 }, 2335 .hback_porch = { 82, 114, 170 }, 2336 .hsync_len = { 5, 30, 30 }, 2337 .vactive = { 480, 480, 480 }, 2338 .vfront_porch = { 10, 10, 10 }, 2339 .vback_porch = { 30, 32, 34 }, 2340 .vsync_len = { 1, 3, 5 }, 2341 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2342 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2343 DISPLAY_FLAGS_SYNC_POSEDGE, 2344 }; 2345 2346 static const struct panel_desc evervision_vgg644804 = { 2347 .timings = &evervision_vgg644804_timing, 2348 .num_timings = 1, 2349 .bpc = 6, 2350 .size = { 2351 .width = 115, 2352 .height = 86, 2353 }, 2354 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2355 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2356 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2357 }; 2358 2359 static const struct display_timing evervision_vgg804821_timing = { 2360 .pixelclock = { 27600000, 33300000, 50000000 }, 2361 .hactive = { 800, 800, 800 }, 2362 .hfront_porch = { 40, 66, 70 }, 2363 .hback_porch = { 40, 67, 70 }, 2364 .hsync_len = { 40, 67, 70 }, 2365 .vactive = { 480, 480, 480 }, 2366 .vfront_porch = { 6, 10, 10 }, 2367 .vback_porch = { 7, 11, 11 }, 2368 .vsync_len = { 7, 11, 11 }, 2369 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2370 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2371 DISPLAY_FLAGS_SYNC_NEGEDGE, 2372 }; 2373 2374 static const struct panel_desc evervision_vgg804821 = { 2375 .timings = &evervision_vgg804821_timing, 2376 .num_timings = 1, 2377 .bpc = 8, 2378 .size = { 2379 .width = 108, 2380 .height = 64, 2381 }, 2382 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2383 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2384 }; 2385 2386 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2387 .clock = 32260, 2388 .hdisplay = 800, 2389 .hsync_start = 800 + 168, 2390 .hsync_end = 800 + 168 + 64, 2391 .htotal = 800 + 168 + 64 + 88, 2392 .vdisplay = 480, 2393 .vsync_start = 480 + 37, 2394 .vsync_end = 480 + 37 + 2, 2395 .vtotal = 480 + 37 + 2 + 8, 2396 }; 2397 2398 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2399 .modes = &foxlink_fl500wvr00_a0t_mode, 2400 .num_modes = 1, 2401 .bpc = 8, 2402 .size = { 2403 .width = 108, 2404 .height = 65, 2405 }, 2406 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2407 }; 2408 2409 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2410 { /* 60 Hz */ 2411 .clock = 6000, 2412 .hdisplay = 320, 2413 .hsync_start = 320 + 44, 2414 .hsync_end = 320 + 44 + 16, 2415 .htotal = 320 + 44 + 16 + 20, 2416 .vdisplay = 240, 2417 .vsync_start = 240 + 2, 2418 .vsync_end = 240 + 2 + 6, 2419 .vtotal = 240 + 2 + 6 + 2, 2420 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2421 }, 2422 { /* 50 Hz */ 2423 .clock = 5400, 2424 .hdisplay = 320, 2425 .hsync_start = 320 + 56, 2426 .hsync_end = 320 + 56 + 16, 2427 .htotal = 320 + 56 + 16 + 40, 2428 .vdisplay = 240, 2429 .vsync_start = 240 + 2, 2430 .vsync_end = 240 + 2 + 6, 2431 .vtotal = 240 + 2 + 6 + 2, 2432 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2433 }, 2434 }; 2435 2436 static const struct panel_desc frida_frd350h54004 = { 2437 .modes = frida_frd350h54004_modes, 2438 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2439 .bpc = 8, 2440 .size = { 2441 .width = 77, 2442 .height = 64, 2443 }, 2444 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2445 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2446 .connector_type = DRM_MODE_CONNECTOR_DPI, 2447 }; 2448 2449 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2450 .clock = 9000, 2451 .hdisplay = 480, 2452 .hsync_start = 480 + 5, 2453 .hsync_end = 480 + 5 + 1, 2454 .htotal = 480 + 5 + 1 + 40, 2455 .vdisplay = 272, 2456 .vsync_start = 272 + 8, 2457 .vsync_end = 272 + 8 + 1, 2458 .vtotal = 272 + 8 + 1 + 8, 2459 }; 2460 2461 static const struct panel_desc giantplus_gpg482739qs5 = { 2462 .modes = &giantplus_gpg482739qs5_mode, 2463 .num_modes = 1, 2464 .bpc = 8, 2465 .size = { 2466 .width = 95, 2467 .height = 54, 2468 }, 2469 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2470 }; 2471 2472 static const struct display_timing giantplus_gpm940b0_timing = { 2473 .pixelclock = { 13500000, 27000000, 27500000 }, 2474 .hactive = { 320, 320, 320 }, 2475 .hfront_porch = { 14, 686, 718 }, 2476 .hback_porch = { 50, 70, 255 }, 2477 .hsync_len = { 1, 1, 1 }, 2478 .vactive = { 240, 240, 240 }, 2479 .vfront_porch = { 1, 1, 179 }, 2480 .vback_porch = { 1, 21, 31 }, 2481 .vsync_len = { 1, 1, 6 }, 2482 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2483 }; 2484 2485 static const struct panel_desc giantplus_gpm940b0 = { 2486 .timings = &giantplus_gpm940b0_timing, 2487 .num_timings = 1, 2488 .bpc = 8, 2489 .size = { 2490 .width = 60, 2491 .height = 45, 2492 }, 2493 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2494 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2495 }; 2496 2497 static const struct display_timing hannstar_hsd070pww1_timing = { 2498 .pixelclock = { 64300000, 71100000, 82000000 }, 2499 .hactive = { 1280, 1280, 1280 }, 2500 .hfront_porch = { 1, 1, 10 }, 2501 .hback_porch = { 1, 1, 10 }, 2502 /* 2503 * According to the data sheet, the minimum horizontal blanking interval 2504 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2505 * minimum working horizontal blanking interval to be 60 clocks. 2506 */ 2507 .hsync_len = { 58, 158, 661 }, 2508 .vactive = { 800, 800, 800 }, 2509 .vfront_porch = { 1, 1, 10 }, 2510 .vback_porch = { 1, 1, 10 }, 2511 .vsync_len = { 1, 21, 203 }, 2512 .flags = DISPLAY_FLAGS_DE_HIGH, 2513 }; 2514 2515 static const struct panel_desc hannstar_hsd070pww1 = { 2516 .timings = &hannstar_hsd070pww1_timing, 2517 .num_timings = 1, 2518 .bpc = 6, 2519 .size = { 2520 .width = 151, 2521 .height = 94, 2522 }, 2523 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2524 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2525 }; 2526 2527 static const struct display_timing hannstar_hsd100pxn1_timing = { 2528 .pixelclock = { 55000000, 65000000, 75000000 }, 2529 .hactive = { 1024, 1024, 1024 }, 2530 .hfront_porch = { 40, 40, 40 }, 2531 .hback_porch = { 220, 220, 220 }, 2532 .hsync_len = { 20, 60, 100 }, 2533 .vactive = { 768, 768, 768 }, 2534 .vfront_porch = { 7, 7, 7 }, 2535 .vback_porch = { 21, 21, 21 }, 2536 .vsync_len = { 10, 10, 10 }, 2537 .flags = DISPLAY_FLAGS_DE_HIGH, 2538 }; 2539 2540 static const struct panel_desc hannstar_hsd100pxn1 = { 2541 .timings = &hannstar_hsd100pxn1_timing, 2542 .num_timings = 1, 2543 .bpc = 6, 2544 .size = { 2545 .width = 203, 2546 .height = 152, 2547 }, 2548 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2549 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2550 }; 2551 2552 static const struct display_timing hannstar_hsd101pww2_timing = { 2553 .pixelclock = { 64300000, 71100000, 82000000 }, 2554 .hactive = { 1280, 1280, 1280 }, 2555 .hfront_porch = { 1, 1, 10 }, 2556 .hback_porch = { 1, 1, 10 }, 2557 .hsync_len = { 58, 158, 661 }, 2558 .vactive = { 800, 800, 800 }, 2559 .vfront_porch = { 1, 1, 10 }, 2560 .vback_porch = { 1, 1, 10 }, 2561 .vsync_len = { 1, 21, 203 }, 2562 .flags = DISPLAY_FLAGS_DE_HIGH, 2563 }; 2564 2565 static const struct panel_desc hannstar_hsd101pww2 = { 2566 .timings = &hannstar_hsd101pww2_timing, 2567 .num_timings = 1, 2568 .bpc = 8, 2569 .size = { 2570 .width = 217, 2571 .height = 136, 2572 }, 2573 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2574 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2575 }; 2576 2577 static const struct display_timing hannstar_hsd156juw2_timing = { 2578 .pixelclock = { 66000000, 72800000, 80500000 }, 2579 .hactive = { 1920, 1920, 1920 }, 2580 .hfront_porch = { 20, 30, 30 }, 2581 .hback_porch = { 20, 30, 30 }, 2582 .hsync_len = { 50, 60, 90 }, 2583 .vactive = { 1080, 1080, 1080 }, 2584 .vfront_porch = { 1, 2, 4 }, 2585 .vback_porch = { 1, 2, 4 }, 2586 .vsync_len = { 3, 40, 80 }, 2587 .flags = DISPLAY_FLAGS_DE_HIGH, 2588 }; 2589 2590 static const struct panel_desc hannstar_hsd156juw2 = { 2591 .timings = &hannstar_hsd156juw2_timing, 2592 .num_timings = 1, 2593 .bpc = 8, 2594 .size = { 2595 .width = 344, 2596 .height = 194, 2597 }, 2598 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2599 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2600 }; 2601 2602 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2603 .clock = 33333, 2604 .hdisplay = 800, 2605 .hsync_start = 800 + 85, 2606 .hsync_end = 800 + 85 + 86, 2607 .htotal = 800 + 85 + 86 + 85, 2608 .vdisplay = 480, 2609 .vsync_start = 480 + 16, 2610 .vsync_end = 480 + 16 + 13, 2611 .vtotal = 480 + 16 + 13 + 16, 2612 }; 2613 2614 static const struct panel_desc hitachi_tx23d38vm0caa = { 2615 .modes = &hitachi_tx23d38vm0caa_mode, 2616 .num_modes = 1, 2617 .bpc = 6, 2618 .size = { 2619 .width = 195, 2620 .height = 117, 2621 }, 2622 .delay = { 2623 .enable = 160, 2624 .disable = 160, 2625 }, 2626 }; 2627 2628 static const struct drm_display_mode innolux_at043tn24_mode = { 2629 .clock = 9000, 2630 .hdisplay = 480, 2631 .hsync_start = 480 + 2, 2632 .hsync_end = 480 + 2 + 41, 2633 .htotal = 480 + 2 + 41 + 2, 2634 .vdisplay = 272, 2635 .vsync_start = 272 + 2, 2636 .vsync_end = 272 + 2 + 10, 2637 .vtotal = 272 + 2 + 10 + 2, 2638 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2639 }; 2640 2641 static const struct panel_desc innolux_at043tn24 = { 2642 .modes = &innolux_at043tn24_mode, 2643 .num_modes = 1, 2644 .bpc = 8, 2645 .size = { 2646 .width = 95, 2647 .height = 54, 2648 }, 2649 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2650 .connector_type = DRM_MODE_CONNECTOR_DPI, 2651 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2652 }; 2653 2654 static const struct drm_display_mode innolux_at070tn92_mode = { 2655 .clock = 33333, 2656 .hdisplay = 800, 2657 .hsync_start = 800 + 210, 2658 .hsync_end = 800 + 210 + 20, 2659 .htotal = 800 + 210 + 20 + 46, 2660 .vdisplay = 480, 2661 .vsync_start = 480 + 22, 2662 .vsync_end = 480 + 22 + 10, 2663 .vtotal = 480 + 22 + 23 + 10, 2664 }; 2665 2666 static const struct panel_desc innolux_at070tn92 = { 2667 .modes = &innolux_at070tn92_mode, 2668 .num_modes = 1, 2669 .size = { 2670 .width = 154, 2671 .height = 86, 2672 }, 2673 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2674 }; 2675 2676 static const struct display_timing innolux_g070ace_l01_timing = { 2677 .pixelclock = { 25200000, 35000000, 35700000 }, 2678 .hactive = { 800, 800, 800 }, 2679 .hfront_porch = { 30, 32, 87 }, 2680 .hback_porch = { 30, 32, 87 }, 2681 .hsync_len = { 1, 1, 1 }, 2682 .vactive = { 480, 480, 480 }, 2683 .vfront_porch = { 3, 3, 3 }, 2684 .vback_porch = { 13, 13, 13 }, 2685 .vsync_len = { 1, 1, 4 }, 2686 .flags = DISPLAY_FLAGS_DE_HIGH, 2687 }; 2688 2689 static const struct panel_desc innolux_g070ace_l01 = { 2690 .timings = &innolux_g070ace_l01_timing, 2691 .num_timings = 1, 2692 .bpc = 8, 2693 .size = { 2694 .width = 152, 2695 .height = 91, 2696 }, 2697 .delay = { 2698 .prepare = 10, 2699 .enable = 50, 2700 .disable = 50, 2701 .unprepare = 500, 2702 }, 2703 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2704 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2705 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2706 }; 2707 2708 static const struct display_timing innolux_g070y2_l01_timing = { 2709 .pixelclock = { 28000000, 29500000, 32000000 }, 2710 .hactive = { 800, 800, 800 }, 2711 .hfront_porch = { 61, 91, 141 }, 2712 .hback_porch = { 60, 90, 140 }, 2713 .hsync_len = { 12, 12, 12 }, 2714 .vactive = { 480, 480, 480 }, 2715 .vfront_porch = { 4, 9, 30 }, 2716 .vback_porch = { 4, 8, 28 }, 2717 .vsync_len = { 2, 2, 2 }, 2718 .flags = DISPLAY_FLAGS_DE_HIGH, 2719 }; 2720 2721 static const struct panel_desc innolux_g070y2_l01 = { 2722 .timings = &innolux_g070y2_l01_timing, 2723 .num_timings = 1, 2724 .bpc = 8, 2725 .size = { 2726 .width = 152, 2727 .height = 91, 2728 }, 2729 .delay = { 2730 .prepare = 10, 2731 .enable = 100, 2732 .disable = 100, 2733 .unprepare = 800, 2734 }, 2735 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2736 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2737 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2738 }; 2739 2740 static const struct display_timing innolux_g070ace_lh3_timing = { 2741 .pixelclock = { 25200000, 25400000, 35700000 }, 2742 .hactive = { 800, 800, 800 }, 2743 .hfront_porch = { 30, 32, 87 }, 2744 .hback_porch = { 29, 31, 86 }, 2745 .hsync_len = { 1, 1, 1 }, 2746 .vactive = { 480, 480, 480 }, 2747 .vfront_porch = { 4, 5, 65 }, 2748 .vback_porch = { 3, 4, 65 }, 2749 .vsync_len = { 1, 1, 1 }, 2750 .flags = DISPLAY_FLAGS_DE_HIGH, 2751 }; 2752 2753 static const struct panel_desc innolux_g070ace_lh3 = { 2754 .timings = &innolux_g070ace_lh3_timing, 2755 .num_timings = 1, 2756 .bpc = 8, 2757 .size = { 2758 .width = 152, 2759 .height = 91, 2760 }, 2761 .delay = { 2762 .prepare = 10, 2763 .enable = 450, 2764 .disable = 200, 2765 .unprepare = 510, 2766 }, 2767 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2768 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2769 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2770 }; 2771 2772 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2773 .clock = 33333, 2774 .hdisplay = 800, 2775 .hsync_start = 800 + 210, 2776 .hsync_end = 800 + 210 + 20, 2777 .htotal = 800 + 210 + 20 + 46, 2778 .vdisplay = 480, 2779 .vsync_start = 480 + 22, 2780 .vsync_end = 480 + 22 + 10, 2781 .vtotal = 480 + 22 + 23 + 10, 2782 }; 2783 2784 static const struct panel_desc innolux_g070y2_t02 = { 2785 .modes = &innolux_g070y2_t02_mode, 2786 .num_modes = 1, 2787 .bpc = 8, 2788 .size = { 2789 .width = 152, 2790 .height = 92, 2791 }, 2792 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2793 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2794 .connector_type = DRM_MODE_CONNECTOR_DPI, 2795 }; 2796 2797 static const struct display_timing innolux_g101ice_l01_timing = { 2798 .pixelclock = { 60400000, 71100000, 74700000 }, 2799 .hactive = { 1280, 1280, 1280 }, 2800 .hfront_porch = { 30, 60, 70 }, 2801 .hback_porch = { 30, 60, 70 }, 2802 .hsync_len = { 22, 40, 60 }, 2803 .vactive = { 800, 800, 800 }, 2804 .vfront_porch = { 3, 8, 14 }, 2805 .vback_porch = { 3, 8, 14 }, 2806 .vsync_len = { 4, 7, 12 }, 2807 .flags = DISPLAY_FLAGS_DE_HIGH, 2808 }; 2809 2810 static const struct panel_desc innolux_g101ice_l01 = { 2811 .timings = &innolux_g101ice_l01_timing, 2812 .num_timings = 1, 2813 .bpc = 8, 2814 .size = { 2815 .width = 217, 2816 .height = 135, 2817 }, 2818 .delay = { 2819 .enable = 200, 2820 .disable = 200, 2821 }, 2822 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2823 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2824 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2825 }; 2826 2827 static const struct display_timing innolux_g121i1_l01_timing = { 2828 .pixelclock = { 67450000, 71000000, 74550000 }, 2829 .hactive = { 1280, 1280, 1280 }, 2830 .hfront_porch = { 40, 80, 160 }, 2831 .hback_porch = { 39, 79, 159 }, 2832 .hsync_len = { 1, 1, 1 }, 2833 .vactive = { 800, 800, 800 }, 2834 .vfront_porch = { 5, 11, 100 }, 2835 .vback_porch = { 4, 11, 99 }, 2836 .vsync_len = { 1, 1, 1 }, 2837 }; 2838 2839 static const struct panel_desc innolux_g121i1_l01 = { 2840 .timings = &innolux_g121i1_l01_timing, 2841 .num_timings = 1, 2842 .bpc = 6, 2843 .size = { 2844 .width = 261, 2845 .height = 163, 2846 }, 2847 .delay = { 2848 .enable = 200, 2849 .disable = 20, 2850 }, 2851 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2852 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2853 }; 2854 2855 static const struct display_timing innolux_g121x1_l03_timings = { 2856 .pixelclock = { 57500000, 64900000, 74400000 }, 2857 .hactive = { 1024, 1024, 1024 }, 2858 .hfront_porch = { 90, 140, 190 }, 2859 .hback_porch = { 90, 140, 190 }, 2860 .hsync_len = { 36, 40, 60 }, 2861 .vactive = { 768, 768, 768 }, 2862 .vfront_porch = { 2, 15, 30 }, 2863 .vback_porch = { 2, 15, 30 }, 2864 .vsync_len = { 2, 8, 20 }, 2865 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2866 }; 2867 2868 static const struct panel_desc innolux_g121x1_l03 = { 2869 .timings = &innolux_g121x1_l03_timings, 2870 .num_timings = 1, 2871 .bpc = 6, 2872 .size = { 2873 .width = 246, 2874 .height = 185, 2875 }, 2876 .delay = { 2877 .enable = 200, 2878 .unprepare = 200, 2879 .disable = 400, 2880 }, 2881 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2882 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2883 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2884 }; 2885 2886 static const struct panel_desc innolux_g121xce_l01 = { 2887 .timings = &innolux_g121x1_l03_timings, 2888 .num_timings = 1, 2889 .bpc = 8, 2890 .size = { 2891 .width = 246, 2892 .height = 185, 2893 }, 2894 .delay = { 2895 .enable = 200, 2896 .unprepare = 200, 2897 .disable = 400, 2898 }, 2899 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2900 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2901 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2902 }; 2903 2904 static const struct display_timing innolux_g150xge_l05_timing = { 2905 .pixelclock = { 53350000, 65000000, 80000000 }, 2906 .hactive = { 1024, 1024, 1024 }, 2907 .hfront_porch = { 58, 160, 288 }, 2908 .hback_porch = { 58, 160, 288 }, 2909 .hsync_len = { 1, 1, 1 }, 2910 .vactive = { 768, 768, 768 }, 2911 .vfront_porch = { 6, 19, 216 }, 2912 .vback_porch = { 6, 19, 216 }, 2913 .vsync_len = { 1, 1, 1 }, 2914 .flags = DISPLAY_FLAGS_DE_HIGH, 2915 }; 2916 2917 static const struct panel_desc innolux_g150xge_l05 = { 2918 .timings = &innolux_g150xge_l05_timing, 2919 .num_timings = 1, 2920 .bpc = 8, 2921 .size = { 2922 .width = 304, 2923 .height = 228, 2924 }, 2925 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2926 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2927 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2928 }; 2929 2930 static const struct display_timing innolux_g156hce_l01_timings = { 2931 .pixelclock = { 120000000, 141860000, 150000000 }, 2932 .hactive = { 1920, 1920, 1920 }, 2933 .hfront_porch = { 80, 90, 100 }, 2934 .hback_porch = { 80, 90, 100 }, 2935 .hsync_len = { 20, 30, 30 }, 2936 .vactive = { 1080, 1080, 1080 }, 2937 .vfront_porch = { 3, 10, 20 }, 2938 .vback_porch = { 3, 10, 20 }, 2939 .vsync_len = { 4, 10, 10 }, 2940 }; 2941 2942 static const struct panel_desc innolux_g156hce_l01 = { 2943 .timings = &innolux_g156hce_l01_timings, 2944 .num_timings = 1, 2945 .bpc = 8, 2946 .size = { 2947 .width = 344, 2948 .height = 194, 2949 }, 2950 .delay = { 2951 .prepare = 1, /* T1+T2 */ 2952 .enable = 450, /* T5 */ 2953 .disable = 200, /* T6 */ 2954 .unprepare = 10, /* T3+T7 */ 2955 }, 2956 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2957 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2958 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2959 }; 2960 2961 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2962 .clock = 69300, 2963 .hdisplay = 1366, 2964 .hsync_start = 1366 + 16, 2965 .hsync_end = 1366 + 16 + 34, 2966 .htotal = 1366 + 16 + 34 + 50, 2967 .vdisplay = 768, 2968 .vsync_start = 768 + 2, 2969 .vsync_end = 768 + 2 + 6, 2970 .vtotal = 768 + 2 + 6 + 12, 2971 }; 2972 2973 static const struct panel_desc innolux_n156bge_l21 = { 2974 .modes = &innolux_n156bge_l21_mode, 2975 .num_modes = 1, 2976 .bpc = 6, 2977 .size = { 2978 .width = 344, 2979 .height = 193, 2980 }, 2981 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2982 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2983 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2984 }; 2985 2986 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2987 .clock = 51501, 2988 .hdisplay = 1024, 2989 .hsync_start = 1024 + 128, 2990 .hsync_end = 1024 + 128 + 64, 2991 .htotal = 1024 + 128 + 64 + 128, 2992 .vdisplay = 600, 2993 .vsync_start = 600 + 16, 2994 .vsync_end = 600 + 16 + 4, 2995 .vtotal = 600 + 16 + 4 + 16, 2996 }; 2997 2998 static const struct panel_desc innolux_zj070na_01p = { 2999 .modes = &innolux_zj070na_01p_mode, 3000 .num_modes = 1, 3001 .bpc = 6, 3002 .size = { 3003 .width = 154, 3004 .height = 90, 3005 }, 3006 }; 3007 3008 static const struct display_timing jutouch_jt070tm041_timing = { 3009 .pixelclock = { 40800000, 51200000, 67200000 }, 3010 .hactive = { 1024, 1024, 1024 }, 3011 .hfront_porch = { 16, 160, 216 }, 3012 .hback_porch = { 160, 160, 160 }, 3013 .hsync_len = { 1, 1, 140 }, 3014 .vactive = { 600, 600, 600 }, 3015 .vfront_porch = { 1, 12, 127 }, 3016 .vback_porch = { 23, 23, 23 }, 3017 .vsync_len = { 1, 1, 20 }, 3018 }; 3019 3020 static const struct panel_desc jutouch_jt070tm041 = { 3021 .timings = &jutouch_jt070tm041_timing, 3022 .num_timings = 1, 3023 .bpc = 8, 3024 .size = { 3025 .width = 154, 3026 .height = 86, 3027 }, 3028 .delay = { 3029 .enable = 50, 3030 .disable = 50, 3031 }, 3032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3035 }; 3036 3037 static const struct display_timing jutouch_jt101tm023_timing = { 3038 .pixelclock = { 66300000, 72400000, 78900000 }, 3039 .hactive = { 1280, 1280, 1280 }, 3040 .hfront_porch = { 12, 72, 132 }, 3041 .hback_porch = { 88, 88, 88 }, 3042 .hsync_len = { 10, 10, 48 }, 3043 .vactive = { 800, 800, 800 }, 3044 .vfront_porch = { 1, 15, 49 }, 3045 .vback_porch = { 23, 23, 23 }, 3046 .vsync_len = { 5, 6, 13 }, 3047 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3048 DISPLAY_FLAGS_DE_HIGH, 3049 }; 3050 3051 static const struct panel_desc jutouch_jt101tm023 = { 3052 .timings = &jutouch_jt101tm023_timing, 3053 .num_timings = 1, 3054 .bpc = 8, 3055 .size = { 3056 .width = 217, 3057 .height = 136, 3058 }, 3059 .delay = { 3060 .enable = 50, 3061 .disable = 50, 3062 }, 3063 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3064 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3065 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3066 }; 3067 3068 3069 static const struct display_timing koe_tx14d24vm1bpa_timing = { 3070 .pixelclock = { 5580000, 5850000, 6200000 }, 3071 .hactive = { 320, 320, 320 }, 3072 .hfront_porch = { 30, 30, 30 }, 3073 .hback_porch = { 30, 30, 30 }, 3074 .hsync_len = { 1, 5, 17 }, 3075 .vactive = { 240, 240, 240 }, 3076 .vfront_porch = { 6, 6, 6 }, 3077 .vback_porch = { 5, 5, 5 }, 3078 .vsync_len = { 1, 2, 11 }, 3079 .flags = DISPLAY_FLAGS_DE_HIGH, 3080 }; 3081 3082 static const struct panel_desc koe_tx14d24vm1bpa = { 3083 .timings = &koe_tx14d24vm1bpa_timing, 3084 .num_timings = 1, 3085 .bpc = 6, 3086 .size = { 3087 .width = 115, 3088 .height = 86, 3089 }, 3090 }; 3091 3092 static const struct display_timing koe_tx26d202vm0bwa_timing = { 3093 .pixelclock = { 151820000, 156720000, 159780000 }, 3094 .hactive = { 1920, 1920, 1920 }, 3095 .hfront_porch = { 105, 130, 142 }, 3096 .hback_porch = { 45, 70, 82 }, 3097 .hsync_len = { 30, 30, 30 }, 3098 .vactive = { 1200, 1200, 1200}, 3099 .vfront_porch = { 3, 5, 10 }, 3100 .vback_porch = { 2, 5, 10 }, 3101 .vsync_len = { 5, 5, 5 }, 3102 .flags = DISPLAY_FLAGS_DE_HIGH, 3103 }; 3104 3105 static const struct panel_desc koe_tx26d202vm0bwa = { 3106 .timings = &koe_tx26d202vm0bwa_timing, 3107 .num_timings = 1, 3108 .bpc = 8, 3109 .size = { 3110 .width = 217, 3111 .height = 136, 3112 }, 3113 .delay = { 3114 .prepare = 1000, 3115 .enable = 1000, 3116 .unprepare = 1000, 3117 .disable = 1000, 3118 }, 3119 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3120 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3121 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3122 }; 3123 3124 static const struct display_timing koe_tx31d200vm0baa_timing = { 3125 .pixelclock = { 39600000, 43200000, 48000000 }, 3126 .hactive = { 1280, 1280, 1280 }, 3127 .hfront_porch = { 16, 36, 56 }, 3128 .hback_porch = { 16, 36, 56 }, 3129 .hsync_len = { 8, 8, 8 }, 3130 .vactive = { 480, 480, 480 }, 3131 .vfront_porch = { 6, 21, 33 }, 3132 .vback_porch = { 6, 21, 33 }, 3133 .vsync_len = { 8, 8, 8 }, 3134 .flags = DISPLAY_FLAGS_DE_HIGH, 3135 }; 3136 3137 static const struct panel_desc koe_tx31d200vm0baa = { 3138 .timings = &koe_tx31d200vm0baa_timing, 3139 .num_timings = 1, 3140 .bpc = 6, 3141 .size = { 3142 .width = 292, 3143 .height = 109, 3144 }, 3145 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3146 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3147 }; 3148 3149 static const struct display_timing kyo_tcg121xglp_timing = { 3150 .pixelclock = { 52000000, 65000000, 71000000 }, 3151 .hactive = { 1024, 1024, 1024 }, 3152 .hfront_porch = { 2, 2, 2 }, 3153 .hback_porch = { 2, 2, 2 }, 3154 .hsync_len = { 86, 124, 244 }, 3155 .vactive = { 768, 768, 768 }, 3156 .vfront_porch = { 2, 2, 2 }, 3157 .vback_porch = { 2, 2, 2 }, 3158 .vsync_len = { 6, 34, 73 }, 3159 .flags = DISPLAY_FLAGS_DE_HIGH, 3160 }; 3161 3162 static const struct panel_desc kyo_tcg121xglp = { 3163 .timings = &kyo_tcg121xglp_timing, 3164 .num_timings = 1, 3165 .bpc = 8, 3166 .size = { 3167 .width = 246, 3168 .height = 184, 3169 }, 3170 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3171 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3172 }; 3173 3174 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3175 .clock = 7000, 3176 .hdisplay = 320, 3177 .hsync_start = 320 + 20, 3178 .hsync_end = 320 + 20 + 30, 3179 .htotal = 320 + 20 + 30 + 38, 3180 .vdisplay = 240, 3181 .vsync_start = 240 + 4, 3182 .vsync_end = 240 + 4 + 3, 3183 .vtotal = 240 + 4 + 3 + 15, 3184 }; 3185 3186 static const struct panel_desc lemaker_bl035_rgb_002 = { 3187 .modes = &lemaker_bl035_rgb_002_mode, 3188 .num_modes = 1, 3189 .size = { 3190 .width = 70, 3191 .height = 52, 3192 }, 3193 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3194 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3195 }; 3196 3197 static const struct display_timing lg_lb070wv8_timing = { 3198 .pixelclock = { 31950000, 33260000, 34600000 }, 3199 .hactive = { 800, 800, 800 }, 3200 .hfront_porch = { 88, 88, 88 }, 3201 .hback_porch = { 88, 88, 88 }, 3202 .hsync_len = { 80, 80, 80 }, 3203 .vactive = { 480, 480, 480 }, 3204 .vfront_porch = { 10, 10, 10 }, 3205 .vback_porch = { 10, 10, 10 }, 3206 .vsync_len = { 25, 25, 25 }, 3207 }; 3208 3209 static const struct panel_desc lg_lb070wv8 = { 3210 .timings = &lg_lb070wv8_timing, 3211 .num_timings = 1, 3212 .bpc = 8, 3213 .size = { 3214 .width = 151, 3215 .height = 91, 3216 }, 3217 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3218 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3219 }; 3220 3221 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3222 .clock = 155127, 3223 .hdisplay = 1920, 3224 .hsync_start = 1920 + 128, 3225 .hsync_end = 1920 + 128 + 20, 3226 .htotal = 1920 + 128 + 20 + 12, 3227 .vdisplay = 1200, 3228 .vsync_start = 1200 + 19, 3229 .vsync_end = 1200 + 19 + 4, 3230 .vtotal = 1200 + 19 + 4 + 20, 3231 }; 3232 3233 static const struct panel_desc lincolntech_lcd185_101ct = { 3234 .modes = &lincolntech_lcd185_101ct_mode, 3235 .bpc = 8, 3236 .num_modes = 1, 3237 .size = { 3238 .width = 217, 3239 .height = 136, 3240 }, 3241 .delay = { 3242 .prepare = 50, 3243 .disable = 50, 3244 }, 3245 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3248 }; 3249 3250 static const struct display_timing logictechno_lt161010_2nh_timing = { 3251 .pixelclock = { 26400000, 33300000, 46800000 }, 3252 .hactive = { 800, 800, 800 }, 3253 .hfront_porch = { 16, 210, 354 }, 3254 .hback_porch = { 46, 46, 46 }, 3255 .hsync_len = { 1, 20, 40 }, 3256 .vactive = { 480, 480, 480 }, 3257 .vfront_porch = { 7, 22, 147 }, 3258 .vback_porch = { 23, 23, 23 }, 3259 .vsync_len = { 1, 10, 20 }, 3260 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3261 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3262 DISPLAY_FLAGS_SYNC_POSEDGE, 3263 }; 3264 3265 static const struct panel_desc logictechno_lt161010_2nh = { 3266 .timings = &logictechno_lt161010_2nh_timing, 3267 .num_timings = 1, 3268 .bpc = 6, 3269 .size = { 3270 .width = 154, 3271 .height = 86, 3272 }, 3273 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3274 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3275 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3276 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3277 .connector_type = DRM_MODE_CONNECTOR_DPI, 3278 }; 3279 3280 static const struct display_timing logictechno_lt170410_2whc_timing = { 3281 .pixelclock = { 68900000, 71100000, 73400000 }, 3282 .hactive = { 1280, 1280, 1280 }, 3283 .hfront_porch = { 23, 60, 71 }, 3284 .hback_porch = { 23, 60, 71 }, 3285 .hsync_len = { 15, 40, 47 }, 3286 .vactive = { 800, 800, 800 }, 3287 .vfront_porch = { 5, 7, 10 }, 3288 .vback_porch = { 5, 7, 10 }, 3289 .vsync_len = { 6, 9, 12 }, 3290 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3291 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3292 DISPLAY_FLAGS_SYNC_POSEDGE, 3293 }; 3294 3295 static const struct panel_desc logictechno_lt170410_2whc = { 3296 .timings = &logictechno_lt170410_2whc_timing, 3297 .num_timings = 1, 3298 .bpc = 8, 3299 .size = { 3300 .width = 217, 3301 .height = 136, 3302 }, 3303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3304 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3305 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3306 }; 3307 3308 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3309 .clock = 33000, 3310 .hdisplay = 800, 3311 .hsync_start = 800 + 112, 3312 .hsync_end = 800 + 112 + 3, 3313 .htotal = 800 + 112 + 3 + 85, 3314 .vdisplay = 480, 3315 .vsync_start = 480 + 38, 3316 .vsync_end = 480 + 38 + 3, 3317 .vtotal = 480 + 38 + 3 + 29, 3318 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3319 }; 3320 3321 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3322 .modes = &logictechno_lttd800480070_l2rt_mode, 3323 .num_modes = 1, 3324 .bpc = 8, 3325 .size = { 3326 .width = 154, 3327 .height = 86, 3328 }, 3329 .delay = { 3330 .prepare = 45, 3331 .enable = 100, 3332 .disable = 100, 3333 .unprepare = 45 3334 }, 3335 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3336 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3337 .connector_type = DRM_MODE_CONNECTOR_DPI, 3338 }; 3339 3340 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3341 .clock = 33000, 3342 .hdisplay = 800, 3343 .hsync_start = 800 + 154, 3344 .hsync_end = 800 + 154 + 3, 3345 .htotal = 800 + 154 + 3 + 43, 3346 .vdisplay = 480, 3347 .vsync_start = 480 + 47, 3348 .vsync_end = 480 + 47 + 3, 3349 .vtotal = 480 + 47 + 3 + 20, 3350 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3351 }; 3352 3353 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3354 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3355 .num_modes = 1, 3356 .bpc = 8, 3357 .size = { 3358 .width = 154, 3359 .height = 86, 3360 }, 3361 .delay = { 3362 .prepare = 45, 3363 .enable = 100, 3364 .disable = 100, 3365 .unprepare = 45 3366 }, 3367 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3368 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3369 .connector_type = DRM_MODE_CONNECTOR_DPI, 3370 }; 3371 3372 static const struct drm_display_mode logicpd_type_28_mode = { 3373 .clock = 9107, 3374 .hdisplay = 480, 3375 .hsync_start = 480 + 3, 3376 .hsync_end = 480 + 3 + 42, 3377 .htotal = 480 + 3 + 42 + 2, 3378 3379 .vdisplay = 272, 3380 .vsync_start = 272 + 2, 3381 .vsync_end = 272 + 2 + 11, 3382 .vtotal = 272 + 2 + 11 + 3, 3383 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3384 }; 3385 3386 static const struct panel_desc logicpd_type_28 = { 3387 .modes = &logicpd_type_28_mode, 3388 .num_modes = 1, 3389 .bpc = 8, 3390 .size = { 3391 .width = 105, 3392 .height = 67, 3393 }, 3394 .delay = { 3395 .prepare = 200, 3396 .enable = 200, 3397 .unprepare = 200, 3398 .disable = 200, 3399 }, 3400 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3401 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3402 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3403 .connector_type = DRM_MODE_CONNECTOR_DPI, 3404 }; 3405 3406 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3407 .clock = 150275, 3408 .hdisplay = 1920, 3409 .hsync_start = 1920 + 32, 3410 .hsync_end = 1920 + 32 + 52, 3411 .htotal = 1920 + 32 + 52 + 24, 3412 .vdisplay = 1200, 3413 .vsync_start = 1200 + 24, 3414 .vsync_end = 1200 + 24 + 8, 3415 .vtotal = 1200 + 24 + 8 + 3, 3416 }; 3417 3418 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3419 .modes = µtips_mf_101hiebcaf0_c_mode, 3420 .bpc = 8, 3421 .num_modes = 1, 3422 .size = { 3423 .width = 217, 3424 .height = 136, 3425 }, 3426 .delay = { 3427 .prepare = 50, 3428 .disable = 50, 3429 }, 3430 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3433 }; 3434 3435 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3436 .clock = 93301, 3437 .hdisplay = 1920, 3438 .hsync_start = 1920 + 72, 3439 .hsync_end = 1920 + 72 + 72, 3440 .htotal = 1920 + 72 + 72 + 72, 3441 .vdisplay = 720, 3442 .vsync_start = 720 + 3, 3443 .vsync_end = 720 + 3 + 3, 3444 .vtotal = 720 + 3 + 3 + 2, 3445 }; 3446 3447 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3448 .modes = µtips_mf_103hieb0ga0_mode, 3449 .bpc = 8, 3450 .num_modes = 1, 3451 .size = { 3452 .width = 244, 3453 .height = 92, 3454 }, 3455 .delay = { 3456 .prepare = 50, 3457 .disable = 50, 3458 }, 3459 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3460 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3461 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3462 }; 3463 3464 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3465 .clock = 30400, 3466 .hdisplay = 800, 3467 .hsync_start = 800 + 0, 3468 .hsync_end = 800 + 1, 3469 .htotal = 800 + 0 + 1 + 160, 3470 .vdisplay = 480, 3471 .vsync_start = 480 + 0, 3472 .vsync_end = 480 + 48 + 1, 3473 .vtotal = 480 + 48 + 1 + 0, 3474 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3475 }; 3476 3477 static const struct panel_desc mitsubishi_aa070mc01 = { 3478 .modes = &mitsubishi_aa070mc01_mode, 3479 .num_modes = 1, 3480 .bpc = 8, 3481 .size = { 3482 .width = 152, 3483 .height = 91, 3484 }, 3485 3486 .delay = { 3487 .enable = 200, 3488 .unprepare = 200, 3489 .disable = 400, 3490 }, 3491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3493 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3494 }; 3495 3496 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3497 .clock = 56234, 3498 .hdisplay = 1024, 3499 .hsync_start = 1024 + 24, 3500 .hsync_end = 1024 + 24 + 63, 3501 .htotal = 1024 + 24 + 63 + 1, 3502 .vdisplay = 768, 3503 .vsync_start = 768 + 3, 3504 .vsync_end = 768 + 3 + 6, 3505 .vtotal = 768 + 3 + 6 + 1, 3506 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3507 }; 3508 3509 static const struct panel_desc mitsubishi_aa084xe01 = { 3510 .modes = &mitsubishi_aa084xe01_mode, 3511 .num_modes = 1, 3512 .bpc = 8, 3513 .size = { 3514 .width = 1024, 3515 .height = 768, 3516 }, 3517 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3518 .connector_type = DRM_MODE_CONNECTOR_DPI, 3519 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3520 }; 3521 3522 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3523 .pixelclock = { 26400000, 33000000, 46800000 }, 3524 .hactive = { 800, 800, 800 }, 3525 .hfront_porch = { 16, 204, 354 }, 3526 .hback_porch = { 46, 46, 46 }, 3527 .hsync_len = { 1, 6, 40 }, 3528 .vactive = { 480, 480, 480 }, 3529 .vfront_porch = { 7, 22, 147 }, 3530 .vback_porch = { 23, 23, 23 }, 3531 .vsync_len = { 1, 3, 20 }, 3532 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3533 DISPLAY_FLAGS_DE_HIGH, 3534 }; 3535 3536 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3537 .timings = &multi_inno_mi0700a2t_30_timing, 3538 .num_timings = 1, 3539 .bpc = 6, 3540 .size = { 3541 .width = 153, 3542 .height = 92, 3543 }, 3544 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3545 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3546 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3547 }; 3548 3549 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3550 .pixelclock = { 29000000, 33000000, 38000000 }, 3551 .hactive = { 800, 800, 800 }, 3552 .hfront_porch = { 180, 210, 240 }, 3553 .hback_porch = { 16, 16, 16 }, 3554 .hsync_len = { 30, 30, 30 }, 3555 .vactive = { 480, 480, 480 }, 3556 .vfront_porch = { 12, 22, 32 }, 3557 .vback_porch = { 10, 10, 10 }, 3558 .vsync_len = { 13, 13, 13 }, 3559 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3560 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3561 DISPLAY_FLAGS_SYNC_POSEDGE, 3562 }; 3563 3564 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3565 .timings = &multi_inno_mi0700s4t_6_timing, 3566 .num_timings = 1, 3567 .bpc = 8, 3568 .size = { 3569 .width = 154, 3570 .height = 86, 3571 }, 3572 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3573 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3574 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3575 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3576 .connector_type = DRM_MODE_CONNECTOR_DPI, 3577 }; 3578 3579 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3580 .pixelclock = { 32000000, 40000000, 50000000 }, 3581 .hactive = { 800, 800, 800 }, 3582 .hfront_porch = { 16, 210, 354 }, 3583 .hback_porch = { 6, 26, 45 }, 3584 .hsync_len = { 1, 20, 40 }, 3585 .vactive = { 600, 600, 600 }, 3586 .vfront_porch = { 1, 12, 77 }, 3587 .vback_porch = { 3, 13, 22 }, 3588 .vsync_len = { 1, 10, 20 }, 3589 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3590 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3591 DISPLAY_FLAGS_SYNC_POSEDGE, 3592 }; 3593 3594 static const struct panel_desc multi_inno_mi0800ft_9 = { 3595 .timings = &multi_inno_mi0800ft_9_timing, 3596 .num_timings = 1, 3597 .bpc = 8, 3598 .size = { 3599 .width = 162, 3600 .height = 122, 3601 }, 3602 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3603 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3604 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3605 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3606 .connector_type = DRM_MODE_CONNECTOR_DPI, 3607 }; 3608 3609 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3610 .pixelclock = { 68900000, 70000000, 73400000 }, 3611 .hactive = { 1280, 1280, 1280 }, 3612 .hfront_porch = { 30, 60, 71 }, 3613 .hback_porch = { 30, 60, 71 }, 3614 .hsync_len = { 10, 10, 48 }, 3615 .vactive = { 800, 800, 800 }, 3616 .vfront_porch = { 5, 10, 10 }, 3617 .vback_porch = { 5, 10, 10 }, 3618 .vsync_len = { 5, 6, 13 }, 3619 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3620 DISPLAY_FLAGS_DE_HIGH, 3621 }; 3622 3623 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3624 .timings = &multi_inno_mi1010ait_1cp_timing, 3625 .num_timings = 1, 3626 .bpc = 8, 3627 .size = { 3628 .width = 217, 3629 .height = 136, 3630 }, 3631 .delay = { 3632 .enable = 50, 3633 .disable = 50, 3634 }, 3635 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3636 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3637 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3638 }; 3639 3640 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3641 .pixelclock = { 40800000, 51200000, 67200000 }, 3642 .hactive = { 1024, 1024, 1024 }, 3643 .hfront_porch = { 30, 110, 130 }, 3644 .hback_porch = { 30, 110, 130 }, 3645 .hsync_len = { 30, 100, 116 }, 3646 .vactive = { 600, 600, 600 }, 3647 .vfront_porch = { 4, 13, 80 }, 3648 .vback_porch = { 4, 13, 80 }, 3649 .vsync_len = { 2, 9, 40 }, 3650 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3651 DISPLAY_FLAGS_DE_HIGH, 3652 }; 3653 3654 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3655 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3656 .num_timings = 1, 3657 .bpc = 6, 3658 .size = { 3659 .width = 260, 3660 .height = 162, 3661 }, 3662 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3663 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3664 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3665 }; 3666 3667 static const struct display_timing nec_nl12880bc20_05_timing = { 3668 .pixelclock = { 67000000, 71000000, 75000000 }, 3669 .hactive = { 1280, 1280, 1280 }, 3670 .hfront_porch = { 2, 30, 30 }, 3671 .hback_porch = { 6, 100, 100 }, 3672 .hsync_len = { 2, 30, 30 }, 3673 .vactive = { 800, 800, 800 }, 3674 .vfront_porch = { 5, 5, 5 }, 3675 .vback_porch = { 11, 11, 11 }, 3676 .vsync_len = { 7, 7, 7 }, 3677 }; 3678 3679 static const struct panel_desc nec_nl12880bc20_05 = { 3680 .timings = &nec_nl12880bc20_05_timing, 3681 .num_timings = 1, 3682 .bpc = 8, 3683 .size = { 3684 .width = 261, 3685 .height = 163, 3686 }, 3687 .delay = { 3688 .enable = 50, 3689 .disable = 50, 3690 }, 3691 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3692 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3693 }; 3694 3695 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3696 .clock = 10870, 3697 .hdisplay = 480, 3698 .hsync_start = 480 + 2, 3699 .hsync_end = 480 + 2 + 41, 3700 .htotal = 480 + 2 + 41 + 2, 3701 .vdisplay = 272, 3702 .vsync_start = 272 + 2, 3703 .vsync_end = 272 + 2 + 4, 3704 .vtotal = 272 + 2 + 4 + 2, 3705 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3706 }; 3707 3708 static const struct panel_desc nec_nl4827hc19_05b = { 3709 .modes = &nec_nl4827hc19_05b_mode, 3710 .num_modes = 1, 3711 .bpc = 8, 3712 .size = { 3713 .width = 95, 3714 .height = 54, 3715 }, 3716 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3717 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3718 }; 3719 3720 static const struct drm_display_mode nec_nl6448bc33_70c_mode = { 3721 .clock = 25175, 3722 .hdisplay = 640, 3723 .hsync_start = 640 + 16, 3724 .hsync_end = 640 + 16 + 48, 3725 .htotal = 640 + 16 + 48 + 96, 3726 .vdisplay = 480, 3727 .vsync_start = 480 + 2, 3728 .vsync_end = 480 + 2 + 31, 3729 .vtotal = 480 + 2 + 31 + 31, 3730 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 3731 }; 3732 3733 static const struct panel_desc nec_nl6448bc33_70c = { 3734 .modes = &nec_nl6448bc33_70c_mode, 3735 .num_modes = 1, 3736 .bpc = 6, 3737 .size = { 3738 .width = 211, 3739 .height = 158, 3740 }, 3741 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3742 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3743 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3744 }; 3745 3746 static const struct drm_display_mode netron_dy_e231732_mode = { 3747 .clock = 66000, 3748 .hdisplay = 1024, 3749 .hsync_start = 1024 + 160, 3750 .hsync_end = 1024 + 160 + 70, 3751 .htotal = 1024 + 160 + 70 + 90, 3752 .vdisplay = 600, 3753 .vsync_start = 600 + 127, 3754 .vsync_end = 600 + 127 + 20, 3755 .vtotal = 600 + 127 + 20 + 3, 3756 }; 3757 3758 static const struct panel_desc netron_dy_e231732 = { 3759 .modes = &netron_dy_e231732_mode, 3760 .num_modes = 1, 3761 .size = { 3762 .width = 154, 3763 .height = 87, 3764 }, 3765 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3766 }; 3767 3768 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3769 .clock = 9000, 3770 .hdisplay = 480, 3771 .hsync_start = 480 + 2, 3772 .hsync_end = 480 + 2 + 41, 3773 .htotal = 480 + 2 + 41 + 2, 3774 .vdisplay = 272, 3775 .vsync_start = 272 + 2, 3776 .vsync_end = 272 + 2 + 10, 3777 .vtotal = 272 + 2 + 10 + 2, 3778 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3779 }; 3780 3781 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3782 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3783 .num_modes = 1, 3784 .bpc = 8, 3785 .size = { 3786 .width = 95, 3787 .height = 54, 3788 }, 3789 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3790 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3791 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3792 .connector_type = DRM_MODE_CONNECTOR_DPI, 3793 }; 3794 3795 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3796 .clock = 75400, 3797 .hdisplay = 1366, 3798 .hsync_start = 1366 + 14, 3799 .hsync_end = 1366 + 14 + 56, 3800 .htotal = 1366 + 14 + 56 + 64, 3801 .vdisplay = 768, 3802 .vsync_start = 768 + 1, 3803 .vsync_end = 768 + 1 + 3, 3804 .vtotal = 768 + 1 + 3 + 22, 3805 }; 3806 3807 static const struct panel_desc nlt_nl13676bc25_03f = { 3808 .modes = &nlt_nl13676bc25_03f_mode, 3809 .num_modes = 1, 3810 .bpc = 8, 3811 .size = { 3812 .width = 363, 3813 .height = 215, 3814 }, 3815 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3816 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3817 }; 3818 3819 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3820 .pixelclock = { 130000000, 148350000, 163000000 }, 3821 .hactive = { 1920, 1920, 1920 }, 3822 .hfront_porch = { 80, 100, 100 }, 3823 .hback_porch = { 100, 120, 120 }, 3824 .hsync_len = { 50, 60, 60 }, 3825 .vactive = { 1080, 1080, 1080 }, 3826 .vfront_porch = { 12, 30, 30 }, 3827 .vback_porch = { 4, 10, 10 }, 3828 .vsync_len = { 4, 5, 5 }, 3829 }; 3830 3831 static const struct panel_desc nlt_nl192108ac18_02d = { 3832 .timings = &nlt_nl192108ac18_02d_timing, 3833 .num_timings = 1, 3834 .bpc = 8, 3835 .size = { 3836 .width = 344, 3837 .height = 194, 3838 }, 3839 .delay = { 3840 .unprepare = 500, 3841 }, 3842 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3843 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3844 }; 3845 3846 static const struct drm_display_mode nvd_9128_mode = { 3847 .clock = 29500, 3848 .hdisplay = 800, 3849 .hsync_start = 800 + 130, 3850 .hsync_end = 800 + 130 + 98, 3851 .htotal = 800 + 0 + 130 + 98, 3852 .vdisplay = 480, 3853 .vsync_start = 480 + 10, 3854 .vsync_end = 480 + 10 + 50, 3855 .vtotal = 480 + 0 + 10 + 50, 3856 }; 3857 3858 static const struct panel_desc nvd_9128 = { 3859 .modes = &nvd_9128_mode, 3860 .num_modes = 1, 3861 .bpc = 8, 3862 .size = { 3863 .width = 156, 3864 .height = 88, 3865 }, 3866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3868 }; 3869 3870 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3871 .pixelclock = { 30000000, 30000000, 40000000 }, 3872 .hactive = { 800, 800, 800 }, 3873 .hfront_porch = { 40, 40, 40 }, 3874 .hback_porch = { 40, 40, 40 }, 3875 .hsync_len = { 1, 48, 48 }, 3876 .vactive = { 480, 480, 480 }, 3877 .vfront_porch = { 13, 13, 13 }, 3878 .vback_porch = { 29, 29, 29 }, 3879 .vsync_len = { 3, 3, 3 }, 3880 .flags = DISPLAY_FLAGS_DE_HIGH, 3881 }; 3882 3883 static const struct panel_desc okaya_rs800480t_7x0gp = { 3884 .timings = &okaya_rs800480t_7x0gp_timing, 3885 .num_timings = 1, 3886 .bpc = 6, 3887 .size = { 3888 .width = 154, 3889 .height = 87, 3890 }, 3891 .delay = { 3892 .prepare = 41, 3893 .enable = 50, 3894 .unprepare = 41, 3895 .disable = 50, 3896 }, 3897 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3898 }; 3899 3900 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3901 .clock = 9000, 3902 .hdisplay = 480, 3903 .hsync_start = 480 + 5, 3904 .hsync_end = 480 + 5 + 30, 3905 .htotal = 480 + 5 + 30 + 10, 3906 .vdisplay = 272, 3907 .vsync_start = 272 + 8, 3908 .vsync_end = 272 + 8 + 5, 3909 .vtotal = 272 + 8 + 5 + 3, 3910 }; 3911 3912 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3913 .modes = &olimex_lcd_olinuxino_43ts_mode, 3914 .num_modes = 1, 3915 .size = { 3916 .width = 95, 3917 .height = 54, 3918 }, 3919 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3920 }; 3921 3922 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3923 .clock = 33300, 3924 .hdisplay = 800, 3925 .hsync_start = 800 + 210, 3926 .hsync_end = 800 + 210 + 20, 3927 .htotal = 800 + 210 + 20 + 26, 3928 .vdisplay = 480, 3929 .vsync_start = 480 + 22, 3930 .vsync_end = 480 + 22 + 10, 3931 .vtotal = 480 + 22 + 10 + 13, 3932 }; 3933 3934 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3935 .modes = &olimex_lcd_olinuxino_5cts_mode, 3936 .num_modes = 1, 3937 .size = { 3938 .width = 154, 3939 .height = 86, 3940 }, 3941 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3942 }; 3943 3944 3945 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3946 .pixelclock = { 30000000, 30000000, 50000000 }, 3947 .hactive = { 800, 800, 800 }, 3948 .hfront_porch = { 1, 40, 255 }, 3949 .hback_porch = { 1, 40, 87 }, 3950 .hsync_len = { 1, 48, 87 }, 3951 .vactive = { 480, 480, 480 }, 3952 .vfront_porch = { 1, 13, 255 }, 3953 .vback_porch = { 1, 29, 29 }, 3954 .vsync_len = { 3, 3, 31 }, 3955 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3956 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3957 }; 3958 3959 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3960 .timings = &ontat_kd50g21_40nt_a1_timing, 3961 .num_timings = 1, 3962 .bpc = 8, 3963 .size = { 3964 .width = 108, 3965 .height = 65, 3966 }, 3967 .delay = { 3968 .prepare = 147, /* 5 VSDs */ 3969 .enable = 147, /* 5 VSDs */ 3970 .disable = 88, /* 3 VSDs */ 3971 .unprepare = 117, /* 4 VSDs */ 3972 }, 3973 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3974 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3975 .connector_type = DRM_MODE_CONNECTOR_DPI, 3976 }; 3977 3978 /* 3979 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3980 * pixel clocks, but this is the timing that was being used in the Adafruit 3981 * installation instructions. 3982 */ 3983 static const struct drm_display_mode ontat_yx700wv03_mode = { 3984 .clock = 29500, 3985 .hdisplay = 800, 3986 .hsync_start = 824, 3987 .hsync_end = 896, 3988 .htotal = 992, 3989 .vdisplay = 480, 3990 .vsync_start = 483, 3991 .vsync_end = 493, 3992 .vtotal = 500, 3993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3994 }; 3995 3996 /* 3997 * Specification at: 3998 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3999 */ 4000 static const struct panel_desc ontat_yx700wv03 = { 4001 .modes = &ontat_yx700wv03_mode, 4002 .num_modes = 1, 4003 .bpc = 8, 4004 .size = { 4005 .width = 154, 4006 .height = 83, 4007 }, 4008 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4009 }; 4010 4011 static const struct drm_display_mode ortustech_com37h3m_mode = { 4012 .clock = 22230, 4013 .hdisplay = 480, 4014 .hsync_start = 480 + 40, 4015 .hsync_end = 480 + 40 + 10, 4016 .htotal = 480 + 40 + 10 + 40, 4017 .vdisplay = 640, 4018 .vsync_start = 640 + 4, 4019 .vsync_end = 640 + 4 + 2, 4020 .vtotal = 640 + 4 + 2 + 4, 4021 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4022 }; 4023 4024 static const struct panel_desc ortustech_com37h3m = { 4025 .modes = &ortustech_com37h3m_mode, 4026 .num_modes = 1, 4027 .bpc = 8, 4028 .size = { 4029 .width = 56, /* 56.16mm */ 4030 .height = 75, /* 74.88mm */ 4031 }, 4032 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4033 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4034 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4035 }; 4036 4037 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 4038 .clock = 25000, 4039 .hdisplay = 480, 4040 .hsync_start = 480 + 10, 4041 .hsync_end = 480 + 10 + 10, 4042 .htotal = 480 + 10 + 10 + 15, 4043 .vdisplay = 800, 4044 .vsync_start = 800 + 3, 4045 .vsync_end = 800 + 3 + 3, 4046 .vtotal = 800 + 3 + 3 + 3, 4047 }; 4048 4049 static const struct panel_desc ortustech_com43h4m85ulc = { 4050 .modes = &ortustech_com43h4m85ulc_mode, 4051 .num_modes = 1, 4052 .bpc = 6, 4053 .size = { 4054 .width = 56, 4055 .height = 93, 4056 }, 4057 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4058 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4059 .connector_type = DRM_MODE_CONNECTOR_DPI, 4060 }; 4061 4062 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 4063 .clock = 33000, 4064 .hdisplay = 800, 4065 .hsync_start = 800 + 210, 4066 .hsync_end = 800 + 210 + 30, 4067 .htotal = 800 + 210 + 30 + 16, 4068 .vdisplay = 480, 4069 .vsync_start = 480 + 22, 4070 .vsync_end = 480 + 22 + 13, 4071 .vtotal = 480 + 22 + 13 + 10, 4072 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4073 }; 4074 4075 static const struct panel_desc osddisplays_osd070t1718_19ts = { 4076 .modes = &osddisplays_osd070t1718_19ts_mode, 4077 .num_modes = 1, 4078 .bpc = 8, 4079 .size = { 4080 .width = 152, 4081 .height = 91, 4082 }, 4083 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4084 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 4085 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4086 .connector_type = DRM_MODE_CONNECTOR_DPI, 4087 }; 4088 4089 static const struct drm_display_mode pda_91_00156_a0_mode = { 4090 .clock = 33300, 4091 .hdisplay = 800, 4092 .hsync_start = 800 + 1, 4093 .hsync_end = 800 + 1 + 64, 4094 .htotal = 800 + 1 + 64 + 64, 4095 .vdisplay = 480, 4096 .vsync_start = 480 + 1, 4097 .vsync_end = 480 + 1 + 23, 4098 .vtotal = 480 + 1 + 23 + 22, 4099 }; 4100 4101 static const struct panel_desc pda_91_00156_a0 = { 4102 .modes = &pda_91_00156_a0_mode, 4103 .num_modes = 1, 4104 .size = { 4105 .width = 152, 4106 .height = 91, 4107 }, 4108 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4109 }; 4110 4111 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 4112 .clock = 71150, 4113 .hdisplay = 1280, 4114 .hsync_start = 1280 + 48, 4115 .hsync_end = 1280 + 48 + 32, 4116 .htotal = 1280 + 48 + 32 + 80, 4117 .vdisplay = 800, 4118 .vsync_start = 800 + 9, 4119 .vsync_end = 800 + 9 + 8, 4120 .vtotal = 800 + 9 + 8 + 6, 4121 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4122 }; 4123 4124 static const struct panel_desc powertip_ph128800t004_zza01 = { 4125 .modes = &powertip_ph128800t004_zza01_mode, 4126 .num_modes = 1, 4127 .bpc = 8, 4128 .size = { 4129 .width = 216, 4130 .height = 135, 4131 }, 4132 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4133 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4135 }; 4136 4137 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 4138 .clock = 66500, 4139 .hdisplay = 1280, 4140 .hsync_start = 1280 + 12, 4141 .hsync_end = 1280 + 12 + 20, 4142 .htotal = 1280 + 12 + 20 + 56, 4143 .vdisplay = 800, 4144 .vsync_start = 800 + 1, 4145 .vsync_end = 800 + 1 + 3, 4146 .vtotal = 800 + 1 + 3 + 20, 4147 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4148 }; 4149 4150 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4151 .modes = &powertip_ph128800t006_zhc01_mode, 4152 .num_modes = 1, 4153 .bpc = 8, 4154 .size = { 4155 .width = 216, 4156 .height = 135, 4157 }, 4158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4159 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4161 }; 4162 4163 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4164 .clock = 24750, 4165 .hdisplay = 800, 4166 .hsync_start = 800 + 54, 4167 .hsync_end = 800 + 54 + 2, 4168 .htotal = 800 + 54 + 2 + 44, 4169 .vdisplay = 480, 4170 .vsync_start = 480 + 49, 4171 .vsync_end = 480 + 49 + 2, 4172 .vtotal = 480 + 49 + 2 + 22, 4173 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4174 }; 4175 4176 static const struct panel_desc powertip_ph800480t013_idf02 = { 4177 .modes = &powertip_ph800480t013_idf02_mode, 4178 .num_modes = 1, 4179 .bpc = 8, 4180 .size = { 4181 .width = 152, 4182 .height = 91, 4183 }, 4184 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4185 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4186 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4187 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4188 .connector_type = DRM_MODE_CONNECTOR_DPI, 4189 }; 4190 4191 static const struct drm_display_mode powertip_ph800480t032_zhc19_mode = { 4192 .clock = 27200, 4193 .hdisplay = 800, 4194 .hsync_start = 800 + 52, 4195 .hsync_end = 800 + 52 + 2, 4196 .htotal = 800 + 52 + 2 + 44, 4197 .vdisplay = 480, 4198 .vsync_start = 480 + 7, 4199 .vsync_end = 480 + 7 + 2, 4200 .vtotal = 480 + 7 + 2 + 2, 4201 }; 4202 4203 static const struct panel_desc powertip_ph800480t032_zhc19 = { 4204 .modes = &powertip_ph800480t032_zhc19_mode, 4205 .num_modes = 1, 4206 .bpc = 8, 4207 .size = { 4208 .width = 152, 4209 .height = 91, 4210 }, 4211 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4212 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4213 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4214 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4215 .connector_type = DRM_MODE_CONNECTOR_DPI, 4216 }; 4217 4218 static const struct drm_display_mode primeview_pm070wl4_mode = { 4219 .clock = 32000, 4220 .hdisplay = 800, 4221 .hsync_start = 800 + 42, 4222 .hsync_end = 800 + 42 + 128, 4223 .htotal = 800 + 42 + 128 + 86, 4224 .vdisplay = 480, 4225 .vsync_start = 480 + 10, 4226 .vsync_end = 480 + 10 + 2, 4227 .vtotal = 480 + 10 + 2 + 33, 4228 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4229 }; 4230 4231 static const struct panel_desc primeview_pm070wl4 = { 4232 .modes = &primeview_pm070wl4_mode, 4233 .num_modes = 1, 4234 .bpc = 6, 4235 .size = { 4236 .width = 152, 4237 .height = 91, 4238 }, 4239 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4240 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4241 .connector_type = DRM_MODE_CONNECTOR_DPI, 4242 }; 4243 4244 static const struct drm_display_mode qd43003c0_40_mode = { 4245 .clock = 9000, 4246 .hdisplay = 480, 4247 .hsync_start = 480 + 8, 4248 .hsync_end = 480 + 8 + 4, 4249 .htotal = 480 + 8 + 4 + 39, 4250 .vdisplay = 272, 4251 .vsync_start = 272 + 4, 4252 .vsync_end = 272 + 4 + 10, 4253 .vtotal = 272 + 4 + 10 + 2, 4254 }; 4255 4256 static const struct panel_desc qd43003c0_40 = { 4257 .modes = &qd43003c0_40_mode, 4258 .num_modes = 1, 4259 .bpc = 8, 4260 .size = { 4261 .width = 95, 4262 .height = 53, 4263 }, 4264 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4265 }; 4266 4267 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4268 { /* 60 Hz */ 4269 .clock = 10800, 4270 .hdisplay = 480, 4271 .hsync_start = 480 + 77, 4272 .hsync_end = 480 + 77 + 41, 4273 .htotal = 480 + 77 + 41 + 2, 4274 .vdisplay = 272, 4275 .vsync_start = 272 + 16, 4276 .vsync_end = 272 + 16 + 10, 4277 .vtotal = 272 + 16 + 10 + 2, 4278 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4279 }, 4280 { /* 50 Hz */ 4281 .clock = 10800, 4282 .hdisplay = 480, 4283 .hsync_start = 480 + 17, 4284 .hsync_end = 480 + 17 + 41, 4285 .htotal = 480 + 17 + 41 + 2, 4286 .vdisplay = 272, 4287 .vsync_start = 272 + 116, 4288 .vsync_end = 272 + 116 + 10, 4289 .vtotal = 272 + 116 + 10 + 2, 4290 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4291 }, 4292 }; 4293 4294 static const struct panel_desc qishenglong_gopher2b_lcd = { 4295 .modes = qishenglong_gopher2b_lcd_modes, 4296 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4297 .bpc = 8, 4298 .size = { 4299 .width = 95, 4300 .height = 54, 4301 }, 4302 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4303 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4304 .connector_type = DRM_MODE_CONNECTOR_DPI, 4305 }; 4306 4307 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4308 .pixelclock = { 23000000, 25000000, 27000000 }, 4309 .hactive = { 800, 800, 800 }, 4310 .hback_porch = { 4, 8, 48 }, 4311 .hfront_porch = { 4, 8, 48 }, 4312 .hsync_len = { 2, 4, 8 }, 4313 .vactive = { 480, 480, 480 }, 4314 .vback_porch = { 4, 8, 12 }, 4315 .vfront_porch = { 4, 8, 12 }, 4316 .vsync_len = { 2, 4, 8 }, 4317 }; 4318 4319 static const struct panel_desc raystar_rff500f_awh_dnn = { 4320 .timings = &raystar_rff500f_awh_dnn_timing, 4321 .num_timings = 1, 4322 .bpc = 8, 4323 .size = { 4324 .width = 108, 4325 .height = 65, 4326 }, 4327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4329 }; 4330 4331 static const struct display_timing rocktech_rk043fn48h_timing = { 4332 .pixelclock = { 6000000, 9000000, 12000000 }, 4333 .hactive = { 480, 480, 480 }, 4334 .hback_porch = { 8, 43, 43 }, 4335 .hfront_porch = { 2, 8, 10 }, 4336 .hsync_len = { 1, 1, 1 }, 4337 .vactive = { 272, 272, 272 }, 4338 .vback_porch = { 2, 12, 26 }, 4339 .vfront_porch = { 1, 4, 4 }, 4340 .vsync_len = { 1, 10, 10 }, 4341 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4342 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4343 DISPLAY_FLAGS_SYNC_POSEDGE, 4344 }; 4345 4346 static const struct panel_desc rocktech_rk043fn48h = { 4347 .timings = &rocktech_rk043fn48h_timing, 4348 .num_timings = 1, 4349 .bpc = 8, 4350 .size = { 4351 .width = 95, 4352 .height = 54, 4353 }, 4354 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4355 .connector_type = DRM_MODE_CONNECTOR_DPI, 4356 }; 4357 4358 static const struct display_timing rocktech_rk070er9427_timing = { 4359 .pixelclock = { 26400000, 33300000, 46800000 }, 4360 .hactive = { 800, 800, 800 }, 4361 .hfront_porch = { 16, 210, 354 }, 4362 .hback_porch = { 46, 46, 46 }, 4363 .hsync_len = { 1, 1, 1 }, 4364 .vactive = { 480, 480, 480 }, 4365 .vfront_porch = { 7, 22, 147 }, 4366 .vback_porch = { 23, 23, 23 }, 4367 .vsync_len = { 1, 1, 1 }, 4368 .flags = DISPLAY_FLAGS_DE_HIGH, 4369 }; 4370 4371 static const struct panel_desc rocktech_rk070er9427 = { 4372 .timings = &rocktech_rk070er9427_timing, 4373 .num_timings = 1, 4374 .bpc = 6, 4375 .size = { 4376 .width = 154, 4377 .height = 86, 4378 }, 4379 .delay = { 4380 .prepare = 41, 4381 .enable = 50, 4382 .unprepare = 41, 4383 .disable = 50, 4384 }, 4385 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4386 }; 4387 4388 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4389 .clock = 71100, 4390 .hdisplay = 1280, 4391 .hsync_start = 1280 + 48, 4392 .hsync_end = 1280 + 48 + 32, 4393 .htotal = 1280 + 48 + 32 + 80, 4394 .vdisplay = 800, 4395 .vsync_start = 800 + 2, 4396 .vsync_end = 800 + 2 + 5, 4397 .vtotal = 800 + 2 + 5 + 16, 4398 }; 4399 4400 static const struct panel_desc rocktech_rk101ii01d_ct = { 4401 .modes = &rocktech_rk101ii01d_ct_mode, 4402 .bpc = 8, 4403 .num_modes = 1, 4404 .size = { 4405 .width = 217, 4406 .height = 136, 4407 }, 4408 .delay = { 4409 .prepare = 50, 4410 .disable = 50, 4411 }, 4412 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4413 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4414 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4415 }; 4416 4417 static const struct display_timing samsung_ltl101al01_timing = { 4418 .pixelclock = { 66663000, 66663000, 66663000 }, 4419 .hactive = { 1280, 1280, 1280 }, 4420 .hfront_porch = { 18, 18, 18 }, 4421 .hback_porch = { 36, 36, 36 }, 4422 .hsync_len = { 16, 16, 16 }, 4423 .vactive = { 800, 800, 800 }, 4424 .vfront_porch = { 4, 4, 4 }, 4425 .vback_porch = { 16, 16, 16 }, 4426 .vsync_len = { 3, 3, 3 }, 4427 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4428 }; 4429 4430 static const struct panel_desc samsung_ltl101al01 = { 4431 .timings = &samsung_ltl101al01_timing, 4432 .num_timings = 1, 4433 .bpc = 8, 4434 .size = { 4435 .width = 217, 4436 .height = 135, 4437 }, 4438 .delay = { 4439 .prepare = 40, 4440 .enable = 300, 4441 .disable = 200, 4442 .unprepare = 600, 4443 }, 4444 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4445 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4446 }; 4447 4448 static const struct display_timing samsung_ltl106al01_timing = { 4449 .pixelclock = { 71980000, 71980000, 71980000 }, 4450 .hactive = { 1366, 1366, 1366 }, 4451 .hfront_porch = { 56, 56, 56 }, 4452 .hback_porch = { 106, 106, 106 }, 4453 .hsync_len = { 14, 14, 14 }, 4454 .vactive = { 768, 768, 768 }, 4455 .vfront_porch = { 3, 3, 3 }, 4456 .vback_porch = { 6, 6, 6 }, 4457 .vsync_len = { 1, 1, 1 }, 4458 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4459 }; 4460 4461 static const struct panel_desc samsung_ltl106al01 = { 4462 .timings = &samsung_ltl106al01_timing, 4463 .num_timings = 1, 4464 .bpc = 8, 4465 .size = { 4466 .width = 235, 4467 .height = 132, 4468 }, 4469 .delay = { 4470 .prepare = 5, 4471 .enable = 10, 4472 .disable = 10, 4473 .unprepare = 5, 4474 }, 4475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4476 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4477 }; 4478 4479 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4480 .clock = 54030, 4481 .hdisplay = 1024, 4482 .hsync_start = 1024 + 24, 4483 .hsync_end = 1024 + 24 + 136, 4484 .htotal = 1024 + 24 + 136 + 160, 4485 .vdisplay = 600, 4486 .vsync_start = 600 + 3, 4487 .vsync_end = 600 + 3 + 6, 4488 .vtotal = 600 + 3 + 6 + 61, 4489 }; 4490 4491 static const struct panel_desc samsung_ltn101nt05 = { 4492 .modes = &samsung_ltn101nt05_mode, 4493 .num_modes = 1, 4494 .bpc = 6, 4495 .size = { 4496 .width = 223, 4497 .height = 125, 4498 }, 4499 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4500 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4501 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4502 }; 4503 4504 static const struct display_timing satoz_sat050at40h12r2_timing = { 4505 .pixelclock = {33300000, 33300000, 50000000}, 4506 .hactive = {800, 800, 800}, 4507 .hfront_porch = {16, 210, 354}, 4508 .hback_porch = {46, 46, 46}, 4509 .hsync_len = {1, 1, 40}, 4510 .vactive = {480, 480, 480}, 4511 .vfront_porch = {7, 22, 147}, 4512 .vback_porch = {23, 23, 23}, 4513 .vsync_len = {1, 1, 20}, 4514 }; 4515 4516 static const struct panel_desc satoz_sat050at40h12r2 = { 4517 .timings = &satoz_sat050at40h12r2_timing, 4518 .num_timings = 1, 4519 .bpc = 8, 4520 .size = { 4521 .width = 108, 4522 .height = 65, 4523 }, 4524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4525 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4526 }; 4527 4528 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4529 .clock = 33260, 4530 .hdisplay = 800, 4531 .hsync_start = 800 + 64, 4532 .hsync_end = 800 + 64 + 128, 4533 .htotal = 800 + 64 + 128 + 64, 4534 .vdisplay = 480, 4535 .vsync_start = 480 + 8, 4536 .vsync_end = 480 + 8 + 2, 4537 .vtotal = 480 + 8 + 2 + 35, 4538 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4539 }; 4540 4541 static const struct panel_desc sharp_lq070y3dg3b = { 4542 .modes = &sharp_lq070y3dg3b_mode, 4543 .num_modes = 1, 4544 .bpc = 8, 4545 .size = { 4546 .width = 152, /* 152.4mm */ 4547 .height = 91, /* 91.4mm */ 4548 }, 4549 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4550 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4551 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4552 }; 4553 4554 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4555 .clock = 5500, 4556 .hdisplay = 240, 4557 .hsync_start = 240 + 16, 4558 .hsync_end = 240 + 16 + 7, 4559 .htotal = 240 + 16 + 7 + 5, 4560 .vdisplay = 320, 4561 .vsync_start = 320 + 9, 4562 .vsync_end = 320 + 9 + 1, 4563 .vtotal = 320 + 9 + 1 + 7, 4564 }; 4565 4566 static const struct panel_desc sharp_lq035q7db03 = { 4567 .modes = &sharp_lq035q7db03_mode, 4568 .num_modes = 1, 4569 .bpc = 6, 4570 .size = { 4571 .width = 54, 4572 .height = 72, 4573 }, 4574 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4575 }; 4576 4577 static const struct display_timing sharp_lq101k1ly04_timing = { 4578 .pixelclock = { 60000000, 65000000, 80000000 }, 4579 .hactive = { 1280, 1280, 1280 }, 4580 .hfront_porch = { 20, 20, 20 }, 4581 .hback_porch = { 20, 20, 20 }, 4582 .hsync_len = { 10, 10, 10 }, 4583 .vactive = { 800, 800, 800 }, 4584 .vfront_porch = { 4, 4, 4 }, 4585 .vback_porch = { 4, 4, 4 }, 4586 .vsync_len = { 4, 4, 4 }, 4587 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4588 }; 4589 4590 static const struct panel_desc sharp_lq101k1ly04 = { 4591 .timings = &sharp_lq101k1ly04_timing, 4592 .num_timings = 1, 4593 .bpc = 8, 4594 .size = { 4595 .width = 217, 4596 .height = 136, 4597 }, 4598 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4599 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4600 }; 4601 4602 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4603 { /* 50 Hz */ 4604 .clock = 3000, 4605 .hdisplay = 240, 4606 .hsync_start = 240 + 58, 4607 .hsync_end = 240 + 58 + 1, 4608 .htotal = 240 + 58 + 1 + 1, 4609 .vdisplay = 160, 4610 .vsync_start = 160 + 24, 4611 .vsync_end = 160 + 24 + 10, 4612 .vtotal = 160 + 24 + 10 + 6, 4613 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4614 }, 4615 { /* 60 Hz */ 4616 .clock = 3000, 4617 .hdisplay = 240, 4618 .hsync_start = 240 + 8, 4619 .hsync_end = 240 + 8 + 1, 4620 .htotal = 240 + 8 + 1 + 1, 4621 .vdisplay = 160, 4622 .vsync_start = 160 + 24, 4623 .vsync_end = 160 + 24 + 10, 4624 .vtotal = 160 + 24 + 10 + 6, 4625 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4626 }, 4627 }; 4628 4629 static const struct panel_desc sharp_ls020b1dd01d = { 4630 .modes = sharp_ls020b1dd01d_modes, 4631 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4632 .bpc = 6, 4633 .size = { 4634 .width = 42, 4635 .height = 28, 4636 }, 4637 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4638 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4639 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4640 | DRM_BUS_FLAG_SHARP_SIGNALS, 4641 }; 4642 4643 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4644 .clock = 33300, 4645 .hdisplay = 800, 4646 .hsync_start = 800 + 1, 4647 .hsync_end = 800 + 1 + 64, 4648 .htotal = 800 + 1 + 64 + 64, 4649 .vdisplay = 480, 4650 .vsync_start = 480 + 1, 4651 .vsync_end = 480 + 1 + 23, 4652 .vtotal = 480 + 1 + 23 + 22, 4653 }; 4654 4655 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4656 .modes = &shelly_sca07010_bfn_lnn_mode, 4657 .num_modes = 1, 4658 .size = { 4659 .width = 152, 4660 .height = 91, 4661 }, 4662 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4663 }; 4664 4665 static const struct drm_display_mode starry_kr070pe2t_mode = { 4666 .clock = 33000, 4667 .hdisplay = 800, 4668 .hsync_start = 800 + 209, 4669 .hsync_end = 800 + 209 + 1, 4670 .htotal = 800 + 209 + 1 + 45, 4671 .vdisplay = 480, 4672 .vsync_start = 480 + 22, 4673 .vsync_end = 480 + 22 + 1, 4674 .vtotal = 480 + 22 + 1 + 22, 4675 }; 4676 4677 static const struct panel_desc starry_kr070pe2t = { 4678 .modes = &starry_kr070pe2t_mode, 4679 .num_modes = 1, 4680 .bpc = 8, 4681 .size = { 4682 .width = 152, 4683 .height = 86, 4684 }, 4685 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4686 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4687 .connector_type = DRM_MODE_CONNECTOR_DPI, 4688 }; 4689 4690 static const struct display_timing startek_kd070hdfld092_timing = { 4691 .pixelclock = { 40800000, 51200000, 67200000 }, 4692 .hactive = { 1024, 1024, 1024 }, 4693 .hfront_porch = { 40, 160, 216 }, 4694 .hback_porch = { 30, 140, 140 }, 4695 .hsync_len = { 20, 20, 20 }, 4696 .vactive = { 600, 600, 600 }, 4697 .vfront_porch = { 2, 12, 177 }, 4698 .vback_porch = { 5, 20, 20 }, 4699 .vsync_len = { 3, 3, 3 }, 4700 .flags = DISPLAY_FLAGS_DE_HIGH, 4701 }; 4702 4703 static const struct panel_desc startek_kd070hdfld092 = { 4704 .timings = &startek_kd070hdfld092_timing, 4705 .num_timings = 1, 4706 .bpc = 8, 4707 .size = { 4708 .width = 154, 4709 .height = 86, 4710 }, 4711 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4712 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4713 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4714 }; 4715 4716 static const struct display_timing startek_kd070wvfpa_mode = { 4717 .pixelclock = { 25200000, 27200000, 30500000 }, 4718 .hactive = { 800, 800, 800 }, 4719 .hfront_porch = { 19, 44, 115 }, 4720 .hback_porch = { 5, 16, 101 }, 4721 .hsync_len = { 1, 2, 100 }, 4722 .vactive = { 480, 480, 480 }, 4723 .vfront_porch = { 5, 43, 67 }, 4724 .vback_porch = { 5, 5, 67 }, 4725 .vsync_len = { 1, 2, 66 }, 4726 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4727 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4728 DISPLAY_FLAGS_SYNC_POSEDGE, 4729 }; 4730 4731 static const struct panel_desc startek_kd070wvfpa = { 4732 .timings = &startek_kd070wvfpa_mode, 4733 .num_timings = 1, 4734 .bpc = 8, 4735 .size = { 4736 .width = 152, 4737 .height = 91, 4738 }, 4739 .delay = { 4740 .prepare = 20, 4741 .enable = 200, 4742 .disable = 200, 4743 }, 4744 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4745 .connector_type = DRM_MODE_CONNECTOR_DPI, 4746 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4747 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4748 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4749 }; 4750 4751 static const struct display_timing tsd_tst043015cmhx_timing = { 4752 .pixelclock = { 5000000, 9000000, 12000000 }, 4753 .hactive = { 480, 480, 480 }, 4754 .hfront_porch = { 4, 5, 65 }, 4755 .hback_porch = { 36, 40, 255 }, 4756 .hsync_len = { 1, 1, 1 }, 4757 .vactive = { 272, 272, 272 }, 4758 .vfront_porch = { 2, 8, 97 }, 4759 .vback_porch = { 3, 8, 31 }, 4760 .vsync_len = { 1, 1, 1 }, 4761 4762 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4763 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4764 }; 4765 4766 static const struct panel_desc tsd_tst043015cmhx = { 4767 .timings = &tsd_tst043015cmhx_timing, 4768 .num_timings = 1, 4769 .bpc = 8, 4770 .size = { 4771 .width = 105, 4772 .height = 67, 4773 }, 4774 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4776 }; 4777 4778 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4779 .clock = 30000, 4780 .hdisplay = 800, 4781 .hsync_start = 800 + 39, 4782 .hsync_end = 800 + 39 + 47, 4783 .htotal = 800 + 39 + 47 + 39, 4784 .vdisplay = 480, 4785 .vsync_start = 480 + 13, 4786 .vsync_end = 480 + 13 + 2, 4787 .vtotal = 480 + 13 + 2 + 29, 4788 }; 4789 4790 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4791 .modes = &tfc_s9700rtwv43tr_01b_mode, 4792 .num_modes = 1, 4793 .bpc = 8, 4794 .size = { 4795 .width = 155, 4796 .height = 90, 4797 }, 4798 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4799 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4800 }; 4801 4802 static const struct display_timing tianma_tm070jdhg30_timing = { 4803 .pixelclock = { 62600000, 68200000, 78100000 }, 4804 .hactive = { 1280, 1280, 1280 }, 4805 .hfront_porch = { 15, 64, 159 }, 4806 .hback_porch = { 5, 5, 5 }, 4807 .hsync_len = { 1, 1, 256 }, 4808 .vactive = { 800, 800, 800 }, 4809 .vfront_porch = { 3, 40, 99 }, 4810 .vback_porch = { 2, 2, 2 }, 4811 .vsync_len = { 1, 1, 128 }, 4812 .flags = DISPLAY_FLAGS_DE_HIGH, 4813 }; 4814 4815 static const struct panel_desc tianma_tm070jdhg30 = { 4816 .timings = &tianma_tm070jdhg30_timing, 4817 .num_timings = 1, 4818 .bpc = 8, 4819 .size = { 4820 .width = 151, 4821 .height = 95, 4822 }, 4823 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4824 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4825 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4826 }; 4827 4828 static const struct panel_desc tianma_tm070jvhg33 = { 4829 .timings = &tianma_tm070jdhg30_timing, 4830 .num_timings = 1, 4831 .bpc = 8, 4832 .size = { 4833 .width = 150, 4834 .height = 94, 4835 }, 4836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4837 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4838 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4839 }; 4840 4841 /* 4842 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4843 * front porch, not including sync pulse width. This is for both H and 4844 * V. To make the total blanking and period correct, subtract the pulse 4845 * width from the front porch. 4846 * 4847 * This works well for the Min and Typ values, but for Max values the sync 4848 * pulse width is higher than back porch + front porch, so work around that 4849 * by reducing the Max sync length value to 1 and then treating the Max 4850 * porches as in the Min and Typ cases. 4851 * 4852 * Exact datasheet values are added as a comment where they differ from the 4853 * ones implemented for the above reason. 4854 * 4855 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4856 * and total blanking time, however the resulting values are the same as 4857 * the TM070JDHG34-00. 4858 */ 4859 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4860 .pixelclock = { 68400000, 71900000, 78100000 }, 4861 .hactive = { 1280, 1280, 1280 }, 4862 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4863 .hback_porch = { 5, 5, 5 }, 4864 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4865 .vactive = { 800, 800, 800 }, 4866 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4867 .vback_porch = { 2, 2, 2 }, 4868 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4869 .flags = DISPLAY_FLAGS_DE_HIGH, 4870 }; 4871 4872 static const struct panel_desc tianma_tm070jdhg34_00 = { 4873 .timings = &tianma_tm070jdhg34_00_timing, 4874 .num_timings = 1, 4875 .bpc = 8, 4876 .size = { 4877 .width = 150, /* 149.76 */ 4878 .height = 94, /* 93.60 */ 4879 }, 4880 .delay = { 4881 .prepare = 15, /* Tp1 */ 4882 .enable = 150, /* Tp2 */ 4883 .disable = 150, /* Tp4 */ 4884 .unprepare = 120, /* Tp3 */ 4885 }, 4886 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4887 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4888 }; 4889 4890 static const struct panel_desc tianma_p0700wxf1mbaa = { 4891 .timings = &tianma_tm070jdhg34_00_timing, 4892 .num_timings = 1, 4893 .bpc = 8, 4894 .size = { 4895 .width = 150, /* 149.76 */ 4896 .height = 94, /* 93.60 */ 4897 }, 4898 .delay = { 4899 .prepare = 18, /* Tr + Tp1 */ 4900 .enable = 152, /* Tp2 + Tp5 */ 4901 .disable = 152, /* Tp6 + Tp4 */ 4902 .unprepare = 120, /* Tp3 */ 4903 }, 4904 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4905 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4906 }; 4907 4908 static const struct display_timing tianma_tm070rvhg71_timing = { 4909 .pixelclock = { 27700000, 29200000, 39600000 }, 4910 .hactive = { 800, 800, 800 }, 4911 .hfront_porch = { 12, 40, 212 }, 4912 .hback_porch = { 88, 88, 88 }, 4913 .hsync_len = { 1, 1, 40 }, 4914 .vactive = { 480, 480, 480 }, 4915 .vfront_porch = { 1, 13, 88 }, 4916 .vback_porch = { 32, 32, 32 }, 4917 .vsync_len = { 1, 1, 3 }, 4918 .flags = DISPLAY_FLAGS_DE_HIGH, 4919 }; 4920 4921 static const struct panel_desc tianma_tm070rvhg71 = { 4922 .timings = &tianma_tm070rvhg71_timing, 4923 .num_timings = 1, 4924 .bpc = 8, 4925 .size = { 4926 .width = 154, 4927 .height = 86, 4928 }, 4929 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4930 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4931 }; 4932 4933 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4934 { 4935 .clock = 10000, 4936 .hdisplay = 320, 4937 .hsync_start = 320 + 50, 4938 .hsync_end = 320 + 50 + 6, 4939 .htotal = 320 + 50 + 6 + 38, 4940 .vdisplay = 240, 4941 .vsync_start = 240 + 3, 4942 .vsync_end = 240 + 3 + 1, 4943 .vtotal = 240 + 3 + 1 + 17, 4944 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4945 }, 4946 }; 4947 4948 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4949 .modes = ti_nspire_cx_lcd_mode, 4950 .num_modes = 1, 4951 .bpc = 8, 4952 .size = { 4953 .width = 65, 4954 .height = 49, 4955 }, 4956 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4957 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4958 }; 4959 4960 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4961 { 4962 .clock = 10000, 4963 .hdisplay = 320, 4964 .hsync_start = 320 + 6, 4965 .hsync_end = 320 + 6 + 6, 4966 .htotal = 320 + 6 + 6 + 6, 4967 .vdisplay = 240, 4968 .vsync_start = 240 + 0, 4969 .vsync_end = 240 + 0 + 1, 4970 .vtotal = 240 + 0 + 1 + 0, 4971 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4972 }, 4973 }; 4974 4975 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4976 .modes = ti_nspire_classic_lcd_mode, 4977 .num_modes = 1, 4978 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4979 .bpc = 8, 4980 .size = { 4981 .width = 71, 4982 .height = 53, 4983 }, 4984 /* This is the grayscale bus format */ 4985 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4986 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4987 }; 4988 4989 static const struct display_timing topland_tian_g07017_01_timing = { 4990 .pixelclock = { 44900000, 51200000, 63000000 }, 4991 .hactive = { 1024, 1024, 1024 }, 4992 .hfront_porch = { 16, 160, 216 }, 4993 .hback_porch = { 160, 160, 160 }, 4994 .hsync_len = { 1, 1, 140 }, 4995 .vactive = { 600, 600, 600 }, 4996 .vfront_porch = { 1, 12, 127 }, 4997 .vback_porch = { 23, 23, 23 }, 4998 .vsync_len = { 1, 1, 20 }, 4999 }; 5000 5001 static const struct panel_desc topland_tian_g07017_01 = { 5002 .timings = &topland_tian_g07017_01_timing, 5003 .num_timings = 1, 5004 .bpc = 8, 5005 .size = { 5006 .width = 154, 5007 .height = 86, 5008 }, 5009 .delay = { 5010 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 5011 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 5012 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 5013 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 5014 }, 5015 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5016 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5017 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5018 }; 5019 5020 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 5021 .clock = 79500, 5022 .hdisplay = 1280, 5023 .hsync_start = 1280 + 192, 5024 .hsync_end = 1280 + 192 + 128, 5025 .htotal = 1280 + 192 + 128 + 64, 5026 .vdisplay = 768, 5027 .vsync_start = 768 + 20, 5028 .vsync_end = 768 + 20 + 7, 5029 .vtotal = 768 + 20 + 7 + 3, 5030 }; 5031 5032 static const struct panel_desc toshiba_lt089ac29000 = { 5033 .modes = &toshiba_lt089ac29000_mode, 5034 .num_modes = 1, 5035 .size = { 5036 .width = 194, 5037 .height = 116, 5038 }, 5039 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5040 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5041 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5042 }; 5043 5044 static const struct drm_display_mode tpk_f07a_0102_mode = { 5045 .clock = 33260, 5046 .hdisplay = 800, 5047 .hsync_start = 800 + 40, 5048 .hsync_end = 800 + 40 + 128, 5049 .htotal = 800 + 40 + 128 + 88, 5050 .vdisplay = 480, 5051 .vsync_start = 480 + 10, 5052 .vsync_end = 480 + 10 + 2, 5053 .vtotal = 480 + 10 + 2 + 33, 5054 }; 5055 5056 static const struct panel_desc tpk_f07a_0102 = { 5057 .modes = &tpk_f07a_0102_mode, 5058 .num_modes = 1, 5059 .size = { 5060 .width = 152, 5061 .height = 91, 5062 }, 5063 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 5064 }; 5065 5066 static const struct drm_display_mode tpk_f10a_0102_mode = { 5067 .clock = 45000, 5068 .hdisplay = 1024, 5069 .hsync_start = 1024 + 176, 5070 .hsync_end = 1024 + 176 + 5, 5071 .htotal = 1024 + 176 + 5 + 88, 5072 .vdisplay = 600, 5073 .vsync_start = 600 + 20, 5074 .vsync_end = 600 + 20 + 5, 5075 .vtotal = 600 + 20 + 5 + 25, 5076 }; 5077 5078 static const struct panel_desc tpk_f10a_0102 = { 5079 .modes = &tpk_f10a_0102_mode, 5080 .num_modes = 1, 5081 .size = { 5082 .width = 223, 5083 .height = 125, 5084 }, 5085 }; 5086 5087 static const struct display_timing urt_umsh_8596md_timing = { 5088 .pixelclock = { 33260000, 33260000, 33260000 }, 5089 .hactive = { 800, 800, 800 }, 5090 .hfront_porch = { 41, 41, 41 }, 5091 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 5092 .hsync_len = { 71, 128, 128 }, 5093 .vactive = { 480, 480, 480 }, 5094 .vfront_porch = { 10, 10, 10 }, 5095 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 5096 .vsync_len = { 2, 2, 2 }, 5097 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 5098 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 5099 }; 5100 5101 static const struct panel_desc urt_umsh_8596md_lvds = { 5102 .timings = &urt_umsh_8596md_timing, 5103 .num_timings = 1, 5104 .bpc = 6, 5105 .size = { 5106 .width = 152, 5107 .height = 91, 5108 }, 5109 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5111 }; 5112 5113 static const struct panel_desc urt_umsh_8596md_parallel = { 5114 .timings = &urt_umsh_8596md_timing, 5115 .num_timings = 1, 5116 .bpc = 6, 5117 .size = { 5118 .width = 152, 5119 .height = 91, 5120 }, 5121 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 5122 }; 5123 5124 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 5125 .clock = 60000, 5126 .hdisplay = 1024, 5127 .hsync_start = 1024 + 160, 5128 .hsync_end = 1024 + 160 + 100, 5129 .htotal = 1024 + 160 + 100 + 60, 5130 .vdisplay = 600, 5131 .vsync_start = 600 + 12, 5132 .vsync_end = 600 + 12 + 10, 5133 .vtotal = 600 + 12 + 10 + 13, 5134 }; 5135 5136 static const struct panel_desc vivax_tpc9150_panel = { 5137 .modes = &vivax_tpc9150_panel_mode, 5138 .num_modes = 1, 5139 .bpc = 6, 5140 .size = { 5141 .width = 200, 5142 .height = 115, 5143 }, 5144 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5145 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5146 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5147 }; 5148 5149 static const struct drm_display_mode vl050_8048nt_c01_mode = { 5150 .clock = 33333, 5151 .hdisplay = 800, 5152 .hsync_start = 800 + 210, 5153 .hsync_end = 800 + 210 + 20, 5154 .htotal = 800 + 210 + 20 + 46, 5155 .vdisplay = 480, 5156 .vsync_start = 480 + 22, 5157 .vsync_end = 480 + 22 + 10, 5158 .vtotal = 480 + 22 + 10 + 23, 5159 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5160 }; 5161 5162 static const struct panel_desc vl050_8048nt_c01 = { 5163 .modes = &vl050_8048nt_c01_mode, 5164 .num_modes = 1, 5165 .bpc = 8, 5166 .size = { 5167 .width = 120, 5168 .height = 76, 5169 }, 5170 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5171 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5172 }; 5173 5174 static const struct drm_display_mode waveshare_28_lcd_mode = { 5175 .clock = 50000, 5176 .hdisplay = 480, 5177 .hsync_start = 480 + 150, 5178 .hsync_end = 480 + 150 + 50, 5179 .htotal = 480 + 150 + 50 + 150, 5180 .vdisplay = 640, 5181 .vsync_start = 640 + 150, 5182 .vsync_end = 640 + 150 + 50, 5183 .vtotal = 640 + 150 + 50 + 150, 5184 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5185 }; 5186 5187 static const struct panel_desc waveshare_28_lcd_panel = { 5188 .modes = &waveshare_28_lcd_mode, 5189 .num_modes = 1, 5190 .bpc = 8, 5191 .size = { 5192 .width = 44, 5193 .height = 58, 5194 }, 5195 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5196 .connector_type = DRM_MODE_CONNECTOR_DPI, 5197 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5198 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5199 }; 5200 5201 static const struct drm_display_mode waveshare_34_lcd_c_mode = { 5202 .clock = 50000, 5203 .hdisplay = 800, 5204 .hsync_start = 800 + 32, 5205 .hsync_end = 800 + 32 + 6, 5206 .htotal = 800 + 32 + 6 + 120, 5207 .vdisplay = 800, 5208 .vsync_start = 800 + 8, 5209 .vsync_end = 800 + 8 + 4, 5210 .vtotal = 800 + 8 + 4 + 16, 5211 }; 5212 5213 static const struct panel_desc waveshare_34_lcd_c_panel = { 5214 .modes = &waveshare_34_lcd_c_mode, 5215 .num_modes = 1, 5216 .bpc = 8, 5217 .size = { 5218 .width = 88, 5219 .height = 88, 5220 }, 5221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5223 }; 5224 5225 static const struct drm_display_mode waveshare_40_lcd_mode = { 5226 .clock = 50000, 5227 .hdisplay = 480, 5228 .hsync_start = 480 + 150, 5229 .hsync_end = 480 + 150 + 100, 5230 .htotal = 480 + 150 + 100 + 150, 5231 .vdisplay = 800, 5232 .vsync_start = 800 + 20, 5233 .vsync_end = 800 + 20 + 100, 5234 .vtotal = 800 + 20 + 100 + 20, 5235 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5236 }; 5237 5238 static const struct panel_desc waveshare_40_lcd_panel = { 5239 .modes = &waveshare_40_lcd_mode, 5240 .num_modes = 1, 5241 .bpc = 8, 5242 .size = { 5243 .width = 52, 5244 .height = 87, 5245 }, 5246 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5247 .connector_type = DRM_MODE_CONNECTOR_DPI, 5248 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5249 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5250 }; 5251 5252 static const struct drm_display_mode waveshare_40_lcd_c_mode = { 5253 .clock = 50000, 5254 .hdisplay = 720, 5255 .hsync_start = 720 + 32, 5256 .hsync_end = 720 + 32 + 200, 5257 .htotal = 720 + 32 + 200 + 120, 5258 .vdisplay = 720, 5259 .vsync_start = 720 + 8, 5260 .vsync_end = 720 + 8 + 4, 5261 .vtotal = 720 + 8 + 4 + 16, 5262 }; 5263 5264 static const struct panel_desc waveshare_40_lcd_c_panel = { 5265 .modes = &waveshare_40_lcd_c_mode, 5266 .num_modes = 1, 5267 .bpc = 8, 5268 .size = { 5269 .width = 102, 5270 .height = 102, 5271 }, 5272 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5273 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5274 }; 5275 5276 static const struct drm_display_mode waveshare_50_lcd_c_mode = { 5277 .clock = 50000, 5278 .hdisplay = 1024, 5279 .hsync_start = 1024 + 100, 5280 .hsync_end = 1024 + 100 + 100, 5281 .htotal = 1024 + 100 + 100 + 100, 5282 .vdisplay = 600, 5283 .vsync_start = 600 + 10, 5284 .vsync_end = 600 + 10 + 10, 5285 .vtotal = 600 + 10 + 10 + 10, 5286 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5287 }; 5288 5289 static const struct panel_desc waveshare_50_lcd_c_panel = { 5290 .modes = &waveshare_50_lcd_c_mode, 5291 .num_modes = 1, 5292 .bpc = 8, 5293 .size = { 5294 .width = 109, 5295 .height = 66, 5296 }, 5297 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5298 .connector_type = DRM_MODE_CONNECTOR_DPI, 5299 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5300 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5301 }; 5302 5303 static const struct drm_display_mode waveshare_50_lcd_d_mode = { 5304 .clock = 83333, 5305 .hdisplay = 720, 5306 .hsync_start = 720 + 100, 5307 .hsync_end = 720 + 100 + 80, 5308 .htotal = 720 + 100 + 80 + 100, 5309 .vdisplay = 1280, 5310 .vsync_start = 1280 + 20, 5311 .vsync_end = 1280 + 20 + 20, 5312 .vtotal = 1280 + 20 + 20 + 20, 5313 }; 5314 5315 static const struct panel_desc waveshare_50_lcd_d_panel = { 5316 .modes = &waveshare_50_lcd_d_mode, 5317 .num_modes = 1, 5318 .bpc = 8, 5319 .size = { 5320 .width = 62, 5321 .height = 110, 5322 }, 5323 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5324 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5325 }; 5326 5327 static const struct drm_display_mode waveshare_625_lcd_mode = { 5328 .clock = 83333, 5329 .hdisplay = 720, 5330 .hsync_start = 720 + 50, 5331 .hsync_end = 720 + 50 + 50, 5332 .htotal = 720 + 50 + 50 + 50, 5333 .vdisplay = 1560, 5334 .vsync_start = 1560 + 20, 5335 .vsync_end = 1560 + 20 + 20, 5336 .vtotal = 1560 + 20 + 20 + 20, 5337 }; 5338 5339 static const struct panel_desc waveshare_625_lcd_panel = { 5340 .modes = &waveshare_625_lcd_mode, 5341 .num_modes = 1, 5342 .bpc = 8, 5343 .size = { 5344 .width = 66, 5345 .height = 144, 5346 }, 5347 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5348 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5349 }; 5350 5351 static const struct panel_desc waveshare_70_lcd_c_panel = { 5352 .modes = &waveshare_50_lcd_c_mode, 5353 .num_modes = 1, 5354 .bpc = 8, 5355 .size = { 5356 .width = 155, 5357 .height = 87, 5358 }, 5359 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5360 .connector_type = DRM_MODE_CONNECTOR_DPI, 5361 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5362 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5363 }; 5364 5365 static const struct drm_display_mode waveshare_80_lcd_c_mode; 5366 static const struct panel_desc waveshare_70_lcd_e_panel = { 5367 .modes = &waveshare_80_lcd_c_mode, 5368 .num_modes = 1, 5369 .bpc = 8, 5370 .size = { 5371 .width = 152, 5372 .height = 95, 5373 }, 5374 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5375 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5376 }; 5377 5378 static const struct drm_display_mode waveshare_70_lcd_h_mode = { 5379 .clock = 83333, 5380 .hdisplay = 1280, 5381 .hsync_start = 1280 + 64, 5382 .hsync_end = 1280 + 64 + 64, 5383 .htotal = 1280 + 64 + 64 + 64, 5384 .vdisplay = 720, 5385 .vsync_start = 720 + 64, 5386 .vsync_end = 720 + 64 + 64, 5387 .vtotal = 720 + 64 + 64 + 64, 5388 }; 5389 5390 static const struct panel_desc waveshare_70_lcd_h_panel = { 5391 .modes = &waveshare_70_lcd_h_mode, 5392 .num_modes = 1, 5393 .bpc = 8, 5394 .size = { 5395 .width = 155, 5396 .height = 88, 5397 }, 5398 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5399 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5400 }; 5401 5402 static const struct drm_display_mode waveshare_79_lcd_mode = { 5403 .clock = 50000, 5404 .hdisplay = 400, 5405 .hsync_start = 400 + 40, 5406 .hsync_end = 400 + 40 + 30, 5407 .htotal = 400 + 40 + 30 + 40, 5408 .vdisplay = 1280, 5409 .vsync_start = 1280 + 20, 5410 .vsync_end = 1280 + 20 + 10, 5411 .vtotal = 1280 + 20 + 10 + 20, 5412 }; 5413 5414 static const struct panel_desc waveshare_79_lcd_panel = { 5415 .modes = &waveshare_79_lcd_mode, 5416 .num_modes = 1, 5417 .bpc = 8, 5418 .size = { 5419 .width = 60, 5420 .height = 191, 5421 }, 5422 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5423 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5424 }; 5425 5426 static const struct drm_display_mode waveshare_80_lcd_c_mode = { 5427 .clock = 83333, 5428 .hdisplay = 1280, 5429 .hsync_start = 1280 + 156, 5430 .hsync_end = 1280 + 156 + 20, 5431 .htotal = 1280 + 156 + 20 + 40, 5432 .vdisplay = 800, 5433 .vsync_start = 800 + 40, 5434 .vsync_end = 800 + 40 + 48, 5435 .vtotal = 800 + 40 + 48 + 40, 5436 }; 5437 5438 static const struct panel_desc waveshare_80_lcd_c_panel = { 5439 .modes = &waveshare_80_lcd_c_mode, 5440 .num_modes = 1, 5441 .bpc = 8, 5442 .size = { 5443 .width = 173, 5444 .height = 108, 5445 }, 5446 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5447 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5448 }; 5449 5450 static const struct drm_display_mode waveshare_88_lcd_mode = { 5451 .clock = 83333, 5452 .hdisplay = 480, 5453 .hsync_start = 480 + 50, 5454 .hsync_end = 480 + 50 + 50, 5455 .htotal = 480 + 50 + 50 + 50, 5456 .vdisplay = 1920, 5457 .vsync_start = 1920 + 20, 5458 .vsync_end = 1920 + 20 + 20, 5459 .vtotal = 1920 + 20 + 20 + 20, 5460 }; 5461 5462 static const struct panel_desc waveshare_88_lcd_panel = { 5463 .modes = &waveshare_88_lcd_mode, 5464 .num_modes = 1, 5465 .bpc = 8, 5466 .size = { 5467 .width = 56, 5468 .height = 220, 5469 }, 5470 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5471 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5472 }; 5473 5474 static const struct panel_desc waveshare_101_lcd_c_panel = { 5475 .modes = &waveshare_80_lcd_c_mode, 5476 .num_modes = 1, 5477 .bpc = 8, 5478 .size = { 5479 .width = 217, 5480 .height = 136, 5481 }, 5482 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5483 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5484 }; 5485 5486 static const struct drm_display_mode waveshare_119_lcd_mode = { 5487 .clock = 50000, 5488 .hdisplay = 320, 5489 .hsync_start = 320 + 60, 5490 .hsync_end = 320 + 60 + 60, 5491 .htotal = 320 + 60 + 60 + 60, 5492 .vdisplay = 1480, 5493 .vsync_start = 1480 + 60, 5494 .vsync_end = 1480 + 60 + 60, 5495 .vtotal = 1480 + 60 + 60 + 60, 5496 }; 5497 5498 static const struct panel_desc waveshare_119_lcd_panel = { 5499 .modes = &waveshare_119_lcd_mode, 5500 .num_modes = 1, 5501 .bpc = 8, 5502 .size = { 5503 .width = 58, 5504 .height = 268, 5505 }, 5506 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5507 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5508 }; 5509 5510 static const struct drm_display_mode waveshare_133inch_mode = { 5511 .clock = 148500, 5512 .hdisplay = 1920, 5513 .hsync_start = 1920 + 88, 5514 .hsync_end = 1920 + 88 + 44, 5515 .htotal = 1920 + 88 + 44 + 148, 5516 .vdisplay = 1080, 5517 .vsync_start = 1080 + 4, 5518 .vsync_end = 1080 + 4 + 5, 5519 .vtotal = 1080 + 4 + 5 + 36, 5520 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5521 }; 5522 5523 static const struct panel_desc waveshare_133inch = { 5524 .modes = &waveshare_133inch_mode, 5525 .num_modes = 1, 5526 .bpc = 8, 5527 .size = { 5528 .width = 293, 5529 .height = 163, 5530 }, 5531 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5532 .connector_type = DRM_MODE_CONNECTOR_DPI, 5533 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5534 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5535 }; 5536 5537 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 5538 .clock = 6410, 5539 .hdisplay = 320, 5540 .hsync_start = 320 + 20, 5541 .hsync_end = 320 + 20 + 30, 5542 .htotal = 320 + 20 + 30 + 38, 5543 .vdisplay = 240, 5544 .vsync_start = 240 + 4, 5545 .vsync_end = 240 + 4 + 3, 5546 .vtotal = 240 + 4 + 3 + 15, 5547 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5548 }; 5549 5550 static const struct panel_desc winstar_wf35ltiacd = { 5551 .modes = &winstar_wf35ltiacd_mode, 5552 .num_modes = 1, 5553 .bpc = 8, 5554 .size = { 5555 .width = 70, 5556 .height = 53, 5557 }, 5558 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5559 }; 5560 5561 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5562 .clock = 51200, 5563 .hdisplay = 1024, 5564 .hsync_start = 1024 + 100, 5565 .hsync_end = 1024 + 100 + 100, 5566 .htotal = 1024 + 100 + 100 + 120, 5567 .vdisplay = 600, 5568 .vsync_start = 600 + 10, 5569 .vsync_end = 600 + 10 + 10, 5570 .vtotal = 600 + 10 + 10 + 15, 5571 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5572 }; 5573 5574 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5575 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5576 .num_modes = 1, 5577 .bpc = 8, 5578 .size = { 5579 .width = 154, 5580 .height = 90, 5581 }, 5582 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5583 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5584 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5585 }; 5586 5587 static const struct drm_display_mode mchp_ac69t88a_mode = { 5588 .clock = 25000, 5589 .hdisplay = 800, 5590 .hsync_start = 800 + 88, 5591 .hsync_end = 800 + 88 + 5, 5592 .htotal = 800 + 88 + 5 + 40, 5593 .vdisplay = 480, 5594 .vsync_start = 480 + 23, 5595 .vsync_end = 480 + 23 + 5, 5596 .vtotal = 480 + 23 + 5 + 1, 5597 }; 5598 5599 static const struct panel_desc mchp_ac69t88a = { 5600 .modes = &mchp_ac69t88a_mode, 5601 .num_modes = 1, 5602 .bpc = 8, 5603 .size = { 5604 .width = 108, 5605 .height = 65, 5606 }, 5607 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5608 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5609 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5610 }; 5611 5612 static const struct drm_display_mode arm_rtsm_mode[] = { 5613 { 5614 .clock = 65000, 5615 .hdisplay = 1024, 5616 .hsync_start = 1024 + 24, 5617 .hsync_end = 1024 + 24 + 136, 5618 .htotal = 1024 + 24 + 136 + 160, 5619 .vdisplay = 768, 5620 .vsync_start = 768 + 3, 5621 .vsync_end = 768 + 3 + 6, 5622 .vtotal = 768 + 3 + 6 + 29, 5623 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5624 }, 5625 }; 5626 5627 static const struct panel_desc arm_rtsm = { 5628 .modes = arm_rtsm_mode, 5629 .num_modes = 1, 5630 .bpc = 8, 5631 .size = { 5632 .width = 400, 5633 .height = 300, 5634 }, 5635 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5636 }; 5637 5638 static const struct of_device_id platform_of_match[] = { 5639 { 5640 .compatible = "ampire,am-1280800n3tzqw-t00h", 5641 .data = &ire_am_1280800n3tzqw_t00h, 5642 }, { 5643 .compatible = "ampire,am-1280800w8tzqw-t00h", 5644 .data = &ire_am_1280800w8tzqw_t00h, 5645 }, { 5646 .compatible = "ampire,am-480272h3tmqw-t01h", 5647 .data = &ire_am_480272h3tmqw_t01h, 5648 }, { 5649 .compatible = "ampire,am-800480l1tmqw-t00h", 5650 .data = &ire_am_800480l1tmqw_t00h, 5651 }, { 5652 .compatible = "ampire,am800480r3tmqwa1h", 5653 .data = &ire_am800480r3tmqwa1h, 5654 }, { 5655 .compatible = "ampire,am800600p5tmqw-tb8h", 5656 .data = &ire_am800600p5tmqwtb8h, 5657 }, { 5658 .compatible = "arm,rtsm-display", 5659 .data = &arm_rtsm, 5660 }, { 5661 .compatible = "armadeus,st0700-adapt", 5662 .data = &armadeus_st0700_adapt, 5663 }, { 5664 .compatible = "auo,b101aw03", 5665 .data = &auo_b101aw03, 5666 }, { 5667 .compatible = "auo,b101xtn01", 5668 .data = &auo_b101xtn01, 5669 }, { 5670 .compatible = "auo,b116xw03", 5671 .data = &auo_b116xw03, 5672 }, { 5673 .compatible = "auo,g070vvn01", 5674 .data = &auo_g070vvn01, 5675 }, { 5676 .compatible = "auo,g101evn010", 5677 .data = &auo_g101evn010, 5678 }, { 5679 .compatible = "auo,g104sn02", 5680 .data = &auo_g104sn02, 5681 }, { 5682 .compatible = "auo,g104stn01", 5683 .data = &auo_g104stn01, 5684 }, { 5685 .compatible = "auo,g121ean01", 5686 .data = &auo_g121ean01, 5687 }, { 5688 .compatible = "auo,g133han01", 5689 .data = &auo_g133han01, 5690 }, { 5691 .compatible = "auo,g156han04", 5692 .data = &auo_g156han04, 5693 }, { 5694 .compatible = "auo,g156xtn01", 5695 .data = &auo_g156xtn01, 5696 }, { 5697 .compatible = "auo,g185han01", 5698 .data = &auo_g185han01, 5699 }, { 5700 .compatible = "auo,g190ean01", 5701 .data = &auo_g190ean01, 5702 }, { 5703 .compatible = "auo,p238han01", 5704 .data = &auo_p238han01, 5705 }, { 5706 .compatible = "auo,p320hvn03", 5707 .data = &auo_p320hvn03, 5708 }, { 5709 .compatible = "auo,t215hvn01", 5710 .data = &auo_t215hvn01, 5711 }, { 5712 .compatible = "avic,tm070ddh03", 5713 .data = &avic_tm070ddh03, 5714 }, { 5715 .compatible = "bananapi,s070wv20-ct16", 5716 .data = &bananapi_s070wv20_ct16, 5717 }, { 5718 .compatible = "boe,av101hdt-a10", 5719 .data = &boe_av101hdt_a10, 5720 }, { 5721 .compatible = "boe,av123z7m-n17", 5722 .data = &boe_av123z7m_n17, 5723 }, { 5724 .compatible = "boe,bp082wx1-100", 5725 .data = &boe_bp082wx1_100, 5726 }, { 5727 .compatible = "boe,bp101wx1-100", 5728 .data = &boe_bp101wx1_100, 5729 }, { 5730 .compatible = "boe,ev121wxm-n10-1850", 5731 .data = &boe_ev121wxm_n10_1850, 5732 }, { 5733 .compatible = "boe,hv070wsa-100", 5734 .data = &boe_hv070wsa 5735 }, { 5736 .compatible = "cct,cmt430b19n00", 5737 .data = &cct_cmt430b19n00, 5738 }, { 5739 .compatible = "cdtech,s043wq26h-ct7", 5740 .data = &cdtech_s043wq26h_ct7, 5741 }, { 5742 .compatible = "cdtech,s070pws19hp-fc21", 5743 .data = &cdtech_s070pws19hp_fc21, 5744 }, { 5745 .compatible = "cdtech,s070swv29hg-dc44", 5746 .data = &cdtech_s070swv29hg_dc44, 5747 }, { 5748 .compatible = "cdtech,s070wv95-ct16", 5749 .data = &cdtech_s070wv95_ct16, 5750 }, { 5751 .compatible = "chefree,ch101olhlwh-002", 5752 .data = &chefree_ch101olhlwh_002, 5753 }, { 5754 .compatible = "chunghwa,claa070wp03xg", 5755 .data = &chunghwa_claa070wp03xg, 5756 }, { 5757 .compatible = "chunghwa,claa101wa01a", 5758 .data = &chunghwa_claa101wa01a 5759 }, { 5760 .compatible = "chunghwa,claa101wb01", 5761 .data = &chunghwa_claa101wb01 5762 }, { 5763 .compatible = "dataimage,fg040346dsswbg04", 5764 .data = &dataimage_fg040346dsswbg04, 5765 }, { 5766 .compatible = "dataimage,fg1001l0dsswmg01", 5767 .data = &dataimage_fg1001l0dsswmg01, 5768 }, { 5769 .compatible = "dataimage,scf0700c48ggu18", 5770 .data = &dataimage_scf0700c48ggu18, 5771 }, { 5772 .compatible = "displaytech,dt050btft-pts", 5773 .data = &displaytech_dt050btft_pts, 5774 }, { 5775 .compatible = "dlc,dlc0700yzg-1", 5776 .data = &dlc_dlc0700yzg_1, 5777 }, { 5778 .compatible = "dlc,dlc1010gig", 5779 .data = &dlc_dlc1010gig, 5780 }, { 5781 .compatible = "edt,et035012dm6", 5782 .data = &edt_et035012dm6, 5783 }, { 5784 .compatible = "edt,etm0350g0dh6", 5785 .data = &edt_etm0350g0dh6, 5786 }, { 5787 .compatible = "edt,etm043080dh6gp", 5788 .data = &edt_etm043080dh6gp, 5789 }, { 5790 .compatible = "edt,etm0430g0dh6", 5791 .data = &edt_etm0430g0dh6, 5792 }, { 5793 .compatible = "edt,et057023udba", 5794 .data = &edt_et057023udba, 5795 }, { 5796 .compatible = "edt,et057090dhu", 5797 .data = &edt_et057090dhu, 5798 }, { 5799 .compatible = "edt,et070080dh6", 5800 .data = &edt_etm0700g0dh6, 5801 }, { 5802 .compatible = "edt,etm0700g0dh6", 5803 .data = &edt_etm0700g0dh6, 5804 }, { 5805 .compatible = "edt,etm0700g0bdh6", 5806 .data = &edt_etm0700g0bdh6, 5807 }, { 5808 .compatible = "edt,etm0700g0edh6", 5809 .data = &edt_etm0700g0bdh6, 5810 }, { 5811 .compatible = "edt,etml0700y5dha", 5812 .data = &edt_etml0700y5dha, 5813 }, { 5814 .compatible = "edt,etml1010g3dra", 5815 .data = &edt_etml1010g3dra, 5816 }, { 5817 .compatible = "edt,etmv570g2dhu", 5818 .data = &edt_etmv570g2dhu, 5819 }, { 5820 .compatible = "eink,vb3300-kca", 5821 .data = &eink_vb3300_kca, 5822 }, { 5823 .compatible = "evervision,vgg644804", 5824 .data = &evervision_vgg644804, 5825 }, { 5826 .compatible = "evervision,vgg804821", 5827 .data = &evervision_vgg804821, 5828 }, { 5829 .compatible = "foxlink,fl500wvr00-a0t", 5830 .data = &foxlink_fl500wvr00_a0t, 5831 }, { 5832 .compatible = "frida,frd350h54004", 5833 .data = &frida_frd350h54004, 5834 }, { 5835 .compatible = "giantplus,gpg482739qs5", 5836 .data = &giantplus_gpg482739qs5 5837 }, { 5838 .compatible = "giantplus,gpm940b0", 5839 .data = &giantplus_gpm940b0, 5840 }, { 5841 .compatible = "hannstar,hsd070pww1", 5842 .data = &hannstar_hsd070pww1, 5843 }, { 5844 .compatible = "hannstar,hsd100pxn1", 5845 .data = &hannstar_hsd100pxn1, 5846 }, { 5847 .compatible = "hannstar,hsd101pww2", 5848 .data = &hannstar_hsd101pww2, 5849 }, { 5850 .compatible = "hannstar,hsd156juw2", 5851 .data = &hannstar_hsd156juw2, 5852 }, { 5853 .compatible = "hit,tx23d38vm0caa", 5854 .data = &hitachi_tx23d38vm0caa 5855 }, { 5856 .compatible = "innolux,at043tn24", 5857 .data = &innolux_at043tn24, 5858 }, { 5859 .compatible = "innolux,at070tn92", 5860 .data = &innolux_at070tn92, 5861 }, { 5862 .compatible = "innolux,g070ace-l01", 5863 .data = &innolux_g070ace_l01, 5864 }, { 5865 .compatible = "innolux,g070ace-lh3", 5866 .data = &innolux_g070ace_lh3, 5867 }, { 5868 .compatible = "innolux,g070y2-l01", 5869 .data = &innolux_g070y2_l01, 5870 }, { 5871 .compatible = "innolux,g070y2-t02", 5872 .data = &innolux_g070y2_t02, 5873 }, { 5874 .compatible = "innolux,g101ice-l01", 5875 .data = &innolux_g101ice_l01 5876 }, { 5877 .compatible = "innolux,g121i1-l01", 5878 .data = &innolux_g121i1_l01 5879 }, { 5880 .compatible = "innolux,g121x1-l03", 5881 .data = &innolux_g121x1_l03, 5882 }, { 5883 .compatible = "innolux,g121xce-l01", 5884 .data = &innolux_g121xce_l01, 5885 }, { 5886 .compatible = "innolux,g150xge-l05", 5887 .data = &innolux_g150xge_l05, 5888 }, { 5889 .compatible = "innolux,g156hce-l01", 5890 .data = &innolux_g156hce_l01, 5891 }, { 5892 .compatible = "innolux,n156bge-l21", 5893 .data = &innolux_n156bge_l21, 5894 }, { 5895 .compatible = "innolux,zj070na-01p", 5896 .data = &innolux_zj070na_01p, 5897 }, { 5898 .compatible = "jutouch,jt070tm041", 5899 .data = &jutouch_jt070tm041, 5900 }, { 5901 .compatible = "jutouch,jt101tm023", 5902 .data = &jutouch_jt101tm023, 5903 }, { 5904 .compatible = "koe,tx14d24vm1bpa", 5905 .data = &koe_tx14d24vm1bpa, 5906 }, { 5907 .compatible = "koe,tx26d202vm0bwa", 5908 .data = &koe_tx26d202vm0bwa, 5909 }, { 5910 .compatible = "koe,tx31d200vm0baa", 5911 .data = &koe_tx31d200vm0baa, 5912 }, { 5913 .compatible = "kyo,tcg121xglp", 5914 .data = &kyo_tcg121xglp, 5915 }, { 5916 .compatible = "lemaker,bl035-rgb-002", 5917 .data = &lemaker_bl035_rgb_002, 5918 }, { 5919 .compatible = "lg,lb070wv8", 5920 .data = &lg_lb070wv8, 5921 }, { 5922 .compatible = "lincolntech,lcd185-101ct", 5923 .data = &lincolntech_lcd185_101ct, 5924 }, { 5925 .compatible = "logicpd,type28", 5926 .data = &logicpd_type_28, 5927 }, { 5928 .compatible = "logictechno,lt161010-2nhc", 5929 .data = &logictechno_lt161010_2nh, 5930 }, { 5931 .compatible = "logictechno,lt161010-2nhr", 5932 .data = &logictechno_lt161010_2nh, 5933 }, { 5934 .compatible = "logictechno,lt170410-2whc", 5935 .data = &logictechno_lt170410_2whc, 5936 }, { 5937 .compatible = "logictechno,lttd800480070-l2rt", 5938 .data = &logictechno_lttd800480070_l2rt, 5939 }, { 5940 .compatible = "logictechno,lttd800480070-l6wh-rt", 5941 .data = &logictechno_lttd800480070_l6wh_rt, 5942 }, { 5943 .compatible = "microtips,mf-101hiebcaf0", 5944 .data = µtips_mf_101hiebcaf0_c, 5945 }, { 5946 .compatible = "microtips,mf-103hieb0ga0", 5947 .data = µtips_mf_103hieb0ga0, 5948 }, { 5949 .compatible = "mitsubishi,aa070mc01-ca1", 5950 .data = &mitsubishi_aa070mc01, 5951 }, { 5952 .compatible = "mitsubishi,aa084xe01", 5953 .data = &mitsubishi_aa084xe01, 5954 }, { 5955 .compatible = "multi-inno,mi0700a2t-30", 5956 .data = &multi_inno_mi0700a2t_30, 5957 }, { 5958 .compatible = "multi-inno,mi0700s4t-6", 5959 .data = &multi_inno_mi0700s4t_6, 5960 }, { 5961 .compatible = "multi-inno,mi0800ft-9", 5962 .data = &multi_inno_mi0800ft_9, 5963 }, { 5964 .compatible = "multi-inno,mi1010ait-1cp", 5965 .data = &multi_inno_mi1010ait_1cp, 5966 }, { 5967 .compatible = "multi-inno,mi1010z1t-1cp11", 5968 .data = &multi_inno_mi1010z1t_1cp11, 5969 }, { 5970 .compatible = "nec,nl12880bc20-05", 5971 .data = &nec_nl12880bc20_05, 5972 }, { 5973 .compatible = "nec,nl4827hc19-05b", 5974 .data = &nec_nl4827hc19_05b, 5975 }, { 5976 .compatible = "nec,nl6448bc33-70c", 5977 .data = &nec_nl6448bc33_70c, 5978 }, { 5979 .compatible = "netron-dy,e231732", 5980 .data = &netron_dy_e231732, 5981 }, { 5982 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5983 .data = &newhaven_nhd_43_480272ef_atxl, 5984 }, { 5985 .compatible = "nlt,nl13676bc25-03f", 5986 .data = &nlt_nl13676bc25_03f, 5987 }, { 5988 .compatible = "nlt,nl192108ac18-02d", 5989 .data = &nlt_nl192108ac18_02d, 5990 }, { 5991 .compatible = "nvd,9128", 5992 .data = &nvd_9128, 5993 }, { 5994 .compatible = "okaya,rs800480t-7x0gp", 5995 .data = &okaya_rs800480t_7x0gp, 5996 }, { 5997 .compatible = "olimex,lcd-olinuxino-43-ts", 5998 .data = &olimex_lcd_olinuxino_43ts, 5999 }, { 6000 .compatible = "olimex,lcd-olinuxino-5-cts", 6001 .data = &olimex_lcd_olinuxino_5cts, 6002 }, { 6003 .compatible = "ontat,kd50g21-40nt-a1", 6004 .data = &ontat_kd50g21_40nt_a1, 6005 }, { 6006 .compatible = "ontat,yx700wv03", 6007 .data = &ontat_yx700wv03, 6008 }, { 6009 .compatible = "ortustech,com37h3m05dtc", 6010 .data = &ortustech_com37h3m, 6011 }, { 6012 .compatible = "ortustech,com37h3m99dtc", 6013 .data = &ortustech_com37h3m, 6014 }, { 6015 .compatible = "ortustech,com43h4m85ulc", 6016 .data = &ortustech_com43h4m85ulc, 6017 }, { 6018 .compatible = "osddisplays,osd070t1718-19ts", 6019 .data = &osddisplays_osd070t1718_19ts, 6020 }, { 6021 .compatible = "pda,91-00156-a0", 6022 .data = &pda_91_00156_a0, 6023 }, { 6024 .compatible = "powertip,ph128800t004-zza01", 6025 .data = &powertip_ph128800t004_zza01, 6026 }, { 6027 .compatible = "powertip,ph128800t006-zhc01", 6028 .data = &powertip_ph128800t006_zhc01, 6029 }, { 6030 .compatible = "powertip,ph800480t013-idf02", 6031 .data = &powertip_ph800480t013_idf02, 6032 }, { 6033 .compatible = "powertip,ph800480t032-zhc19", 6034 .data = &powertip_ph800480t032_zhc19, 6035 }, { 6036 .compatible = "primeview,pm070wl4", 6037 .data = &primeview_pm070wl4, 6038 }, { 6039 .compatible = "qiaodian,qd43003c0-40", 6040 .data = &qd43003c0_40, 6041 }, { 6042 .compatible = "qishenglong,gopher2b-lcd", 6043 .data = &qishenglong_gopher2b_lcd, 6044 }, { 6045 .compatible = "raystar,rff500f-awh-dnn", 6046 .data = &raystar_rff500f_awh_dnn, 6047 }, { 6048 .compatible = "rocktech,rk043fn48h", 6049 .data = &rocktech_rk043fn48h, 6050 }, { 6051 .compatible = "rocktech,rk070er9427", 6052 .data = &rocktech_rk070er9427, 6053 }, { 6054 .compatible = "rocktech,rk101ii01d-ct", 6055 .data = &rocktech_rk101ii01d_ct, 6056 }, { 6057 .compatible = "samsung,ltl101al01", 6058 .data = &samsung_ltl101al01, 6059 }, { 6060 .compatible = "samsung,ltl106al01", 6061 .data = &samsung_ltl106al01, 6062 }, { 6063 .compatible = "samsung,ltn101nt05", 6064 .data = &samsung_ltn101nt05, 6065 }, { 6066 .compatible = "satoz,sat050at40h12r2", 6067 .data = &satoz_sat050at40h12r2, 6068 }, { 6069 .compatible = "sharp,lq035q7db03", 6070 .data = &sharp_lq035q7db03, 6071 }, { 6072 .compatible = "sharp,lq070y3dg3b", 6073 .data = &sharp_lq070y3dg3b, 6074 }, { 6075 .compatible = "sharp,lq101k1ly04", 6076 .data = &sharp_lq101k1ly04, 6077 }, { 6078 .compatible = "sharp,ls020b1dd01d", 6079 .data = &sharp_ls020b1dd01d, 6080 }, { 6081 .compatible = "shelly,sca07010-bfn-lnn", 6082 .data = &shelly_sca07010_bfn_lnn, 6083 }, { 6084 .compatible = "starry,kr070pe2t", 6085 .data = &starry_kr070pe2t, 6086 }, { 6087 .compatible = "startek,kd070hdfld092", 6088 .data = &startek_kd070hdfld092, 6089 }, { 6090 .compatible = "startek,kd070wvfpa", 6091 .data = &startek_kd070wvfpa, 6092 }, { 6093 .compatible = "team-source-display,tst043015cmhx", 6094 .data = &tsd_tst043015cmhx, 6095 }, { 6096 .compatible = "tfc,s9700rtwv43tr-01b", 6097 .data = &tfc_s9700rtwv43tr_01b, 6098 }, { 6099 .compatible = "tianma,p0700wxf1mbaa", 6100 .data = &tianma_p0700wxf1mbaa, 6101 }, { 6102 .compatible = "tianma,tm050rdh03", 6103 .data = &ontat_kd50g21_40nt_a1, 6104 }, { 6105 .compatible = "tianma,tm070jdhg30", 6106 .data = &tianma_tm070jdhg30, 6107 }, { 6108 .compatible = "tianma,tm070jdhg34-00", 6109 .data = &tianma_tm070jdhg34_00, 6110 }, { 6111 .compatible = "tianma,tm070jvhg33", 6112 .data = &tianma_tm070jvhg33, 6113 }, { 6114 .compatible = "tianma,tm070rvhg71", 6115 .data = &tianma_tm070rvhg71, 6116 }, { 6117 .compatible = "ti,nspire-cx-lcd-panel", 6118 .data = &ti_nspire_cx_lcd_panel, 6119 }, { 6120 .compatible = "ti,nspire-classic-lcd-panel", 6121 .data = &ti_nspire_classic_lcd_panel, 6122 }, { 6123 .compatible = "toshiba,lt089ac29000", 6124 .data = &toshiba_lt089ac29000, 6125 }, { 6126 .compatible = "topland,tian-g07017-01", 6127 .data = &topland_tian_g07017_01, 6128 }, { 6129 .compatible = "tpk,f07a-0102", 6130 .data = &tpk_f07a_0102, 6131 }, { 6132 .compatible = "tpk,f10a-0102", 6133 .data = &tpk_f10a_0102, 6134 }, { 6135 .compatible = "urt,umsh-8596md-t", 6136 .data = &urt_umsh_8596md_parallel, 6137 }, { 6138 .compatible = "urt,umsh-8596md-1t", 6139 .data = &urt_umsh_8596md_parallel, 6140 }, { 6141 .compatible = "urt,umsh-8596md-7t", 6142 .data = &urt_umsh_8596md_parallel, 6143 }, { 6144 .compatible = "urt,umsh-8596md-11t", 6145 .data = &urt_umsh_8596md_lvds, 6146 }, { 6147 .compatible = "urt,umsh-8596md-19t", 6148 .data = &urt_umsh_8596md_lvds, 6149 }, { 6150 .compatible = "urt,umsh-8596md-20t", 6151 .data = &urt_umsh_8596md_parallel, 6152 }, { 6153 .compatible = "vivax,tpc9150-panel", 6154 .data = &vivax_tpc9150_panel, 6155 }, { 6156 .compatible = "vxt,vl050-8048nt-c01", 6157 .data = &vl050_8048nt_c01, 6158 }, { 6159 .compatible = "waveshare,2.8inch-panel", 6160 .data = &waveshare_28_lcd_panel 6161 }, { 6162 .compatible = "waveshare,3.4inch-c-panel", 6163 .data = &waveshare_34_lcd_c_panel 6164 }, { 6165 .compatible = "waveshare,4.0inch-panel", 6166 .data = &waveshare_40_lcd_panel 6167 }, { 6168 .compatible = "waveshare,4.0inch-c-panel", 6169 .data = &waveshare_40_lcd_c_panel 6170 }, { 6171 .compatible = "waveshare,5.0inch-c-panel", 6172 .data = &waveshare_50_lcd_c_panel 6173 }, { 6174 .compatible = "waveshare,5.0inch-d-panel", 6175 .data = &waveshare_50_lcd_d_panel 6176 }, { 6177 .compatible = "waveshare,6.25inch-panel", 6178 .data = &waveshare_625_lcd_panel 6179 }, { 6180 .compatible = "waveshare,7.0inch-c-panel", 6181 .data = &waveshare_70_lcd_c_panel 6182 }, { 6183 .compatible = "waveshare,7.0inch-e-panel", 6184 .data = &waveshare_70_lcd_e_panel 6185 }, { 6186 .compatible = "waveshare,7.0inch-h-panel", 6187 .data = &waveshare_70_lcd_h_panel 6188 }, { 6189 .compatible = "waveshare,7.9inch-panel", 6190 .data = &waveshare_79_lcd_panel 6191 }, { 6192 .compatible = "waveshare,8.0inch-c-panel", 6193 .data = &waveshare_80_lcd_c_panel 6194 }, { 6195 .compatible = "waveshare,8.8inch-panel", 6196 .data = &waveshare_88_lcd_panel 6197 }, { 6198 .compatible = "waveshare,10.1inch-c-panel", 6199 .data = &waveshare_101_lcd_c_panel 6200 }, { 6201 .compatible = "waveshare,11.9inch-panel", 6202 .data = &waveshare_119_lcd_panel 6203 }, { 6204 .compatible = "waveshare,13.3inch-panel", 6205 .data = &waveshare_133inch, 6206 }, { 6207 .compatible = "winstar,wf35ltiacd", 6208 .data = &winstar_wf35ltiacd, 6209 }, { 6210 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 6211 .data = &yes_optoelectronics_ytc700tlag_05_201c, 6212 }, { 6213 .compatible = "microchip,ac69t88a", 6214 .data = &mchp_ac69t88a, 6215 }, { 6216 /* Must be the last entry */ 6217 .compatible = "panel-dpi", 6218 6219 /* 6220 * Explicitly NULL, the panel_desc structure will be 6221 * allocated by panel_dpi_probe(). 6222 */ 6223 .data = NULL, 6224 }, { 6225 /* sentinel */ 6226 } 6227 }; 6228 MODULE_DEVICE_TABLE(of, platform_of_match); 6229 6230 static int panel_simple_platform_probe(struct platform_device *pdev) 6231 { 6232 struct panel_simple *panel; 6233 6234 panel = panel_simple_probe(&pdev->dev); 6235 if (IS_ERR(panel)) 6236 return PTR_ERR(panel); 6237 6238 return 0; 6239 } 6240 6241 static void panel_simple_platform_remove(struct platform_device *pdev) 6242 { 6243 panel_simple_remove(&pdev->dev); 6244 } 6245 6246 static void panel_simple_platform_shutdown(struct platform_device *pdev) 6247 { 6248 panel_simple_shutdown(&pdev->dev); 6249 } 6250 6251 static const struct dev_pm_ops panel_simple_pm_ops = { 6252 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 6253 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 6254 pm_runtime_force_resume) 6255 }; 6256 6257 static struct platform_driver panel_simple_platform_driver = { 6258 .driver = { 6259 .name = "panel-simple", 6260 .of_match_table = platform_of_match, 6261 .pm = &panel_simple_pm_ops, 6262 }, 6263 .probe = panel_simple_platform_probe, 6264 .remove = panel_simple_platform_remove, 6265 .shutdown = panel_simple_platform_shutdown, 6266 }; 6267 6268 static const struct drm_display_mode auo_b080uan01_mode = { 6269 .clock = 154500, 6270 .hdisplay = 1200, 6271 .hsync_start = 1200 + 62, 6272 .hsync_end = 1200 + 62 + 4, 6273 .htotal = 1200 + 62 + 4 + 62, 6274 .vdisplay = 1920, 6275 .vsync_start = 1920 + 9, 6276 .vsync_end = 1920 + 9 + 2, 6277 .vtotal = 1920 + 9 + 2 + 8, 6278 }; 6279 6280 static const struct panel_desc_dsi auo_b080uan01 = { 6281 .desc = { 6282 .modes = &auo_b080uan01_mode, 6283 .num_modes = 1, 6284 .bpc = 8, 6285 .size = { 6286 .width = 108, 6287 .height = 272, 6288 }, 6289 .connector_type = DRM_MODE_CONNECTOR_DSI, 6290 }, 6291 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 6292 .format = MIPI_DSI_FMT_RGB888, 6293 .lanes = 4, 6294 }; 6295 6296 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 6297 .clock = 160000, 6298 .hdisplay = 1200, 6299 .hsync_start = 1200 + 120, 6300 .hsync_end = 1200 + 120 + 20, 6301 .htotal = 1200 + 120 + 20 + 21, 6302 .vdisplay = 1920, 6303 .vsync_start = 1920 + 21, 6304 .vsync_end = 1920 + 21 + 3, 6305 .vtotal = 1920 + 21 + 3 + 18, 6306 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 6307 }; 6308 6309 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 6310 .desc = { 6311 .modes = &boe_tv080wum_nl0_mode, 6312 .num_modes = 1, 6313 .size = { 6314 .width = 107, 6315 .height = 172, 6316 }, 6317 .connector_type = DRM_MODE_CONNECTOR_DSI, 6318 }, 6319 .flags = MIPI_DSI_MODE_VIDEO | 6320 MIPI_DSI_MODE_VIDEO_BURST | 6321 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6322 .format = MIPI_DSI_FMT_RGB888, 6323 .lanes = 4, 6324 }; 6325 6326 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 6327 .clock = 67000, 6328 .hdisplay = 720, 6329 .hsync_start = 720 + 12, 6330 .hsync_end = 720 + 12 + 4, 6331 .htotal = 720 + 12 + 4 + 112, 6332 .vdisplay = 1280, 6333 .vsync_start = 1280 + 8, 6334 .vsync_end = 1280 + 8 + 4, 6335 .vtotal = 1280 + 8 + 4 + 12, 6336 }; 6337 6338 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 6339 .desc = { 6340 .modes = &lg_lh500wx1_sd03_mode, 6341 .num_modes = 1, 6342 .bpc = 8, 6343 .size = { 6344 .width = 62, 6345 .height = 110, 6346 }, 6347 .connector_type = DRM_MODE_CONNECTOR_DSI, 6348 }, 6349 .flags = MIPI_DSI_MODE_VIDEO, 6350 .format = MIPI_DSI_FMT_RGB888, 6351 .lanes = 4, 6352 }; 6353 6354 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 6355 .clock = 157200, 6356 .hdisplay = 1920, 6357 .hsync_start = 1920 + 154, 6358 .hsync_end = 1920 + 154 + 16, 6359 .htotal = 1920 + 154 + 16 + 32, 6360 .vdisplay = 1200, 6361 .vsync_start = 1200 + 17, 6362 .vsync_end = 1200 + 17 + 2, 6363 .vtotal = 1200 + 17 + 2 + 16, 6364 }; 6365 6366 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 6367 .desc = { 6368 .modes = &panasonic_vvx10f004b00_mode, 6369 .num_modes = 1, 6370 .bpc = 8, 6371 .size = { 6372 .width = 217, 6373 .height = 136, 6374 }, 6375 .connector_type = DRM_MODE_CONNECTOR_DSI, 6376 }, 6377 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6378 MIPI_DSI_CLOCK_NON_CONTINUOUS, 6379 .format = MIPI_DSI_FMT_RGB888, 6380 .lanes = 4, 6381 }; 6382 6383 static const struct drm_display_mode lg_acx467akm_7_mode = { 6384 .clock = 150000, 6385 .hdisplay = 1080, 6386 .hsync_start = 1080 + 2, 6387 .hsync_end = 1080 + 2 + 2, 6388 .htotal = 1080 + 2 + 2 + 2, 6389 .vdisplay = 1920, 6390 .vsync_start = 1920 + 2, 6391 .vsync_end = 1920 + 2 + 2, 6392 .vtotal = 1920 + 2 + 2 + 2, 6393 }; 6394 6395 static const struct panel_desc_dsi lg_acx467akm_7 = { 6396 .desc = { 6397 .modes = &lg_acx467akm_7_mode, 6398 .num_modes = 1, 6399 .bpc = 8, 6400 .size = { 6401 .width = 62, 6402 .height = 110, 6403 }, 6404 .connector_type = DRM_MODE_CONNECTOR_DSI, 6405 }, 6406 .flags = 0, 6407 .format = MIPI_DSI_FMT_RGB888, 6408 .lanes = 4, 6409 }; 6410 6411 static const struct drm_display_mode osd101t2045_53ts_mode = { 6412 .clock = 154500, 6413 .hdisplay = 1920, 6414 .hsync_start = 1920 + 112, 6415 .hsync_end = 1920 + 112 + 16, 6416 .htotal = 1920 + 112 + 16 + 32, 6417 .vdisplay = 1200, 6418 .vsync_start = 1200 + 16, 6419 .vsync_end = 1200 + 16 + 2, 6420 .vtotal = 1200 + 16 + 2 + 16, 6421 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 6422 }; 6423 6424 static const struct panel_desc_dsi osd101t2045_53ts = { 6425 .desc = { 6426 .modes = &osd101t2045_53ts_mode, 6427 .num_modes = 1, 6428 .bpc = 8, 6429 .size = { 6430 .width = 217, 6431 .height = 136, 6432 }, 6433 .connector_type = DRM_MODE_CONNECTOR_DSI, 6434 }, 6435 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 6436 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6437 MIPI_DSI_MODE_NO_EOT_PACKET, 6438 .format = MIPI_DSI_FMT_RGB888, 6439 .lanes = 4, 6440 }; 6441 6442 static const struct drm_display_mode tsd_tst070wsbe_196c_mode = { 6443 .clock = 52477, 6444 .hdisplay = 1024, 6445 .hsync_start = 1024 + 160, 6446 .hsync_end = 1024 + 160 + 12, 6447 .htotal = 1024 + 160 + 160 + 12, 6448 .vdisplay = 600, 6449 .vsync_start = 600 + 12, 6450 .vsync_end = 600 + 12 + 10, 6451 .vtotal = 600 + 12 + 10 + 23, 6452 }; 6453 6454 static const struct panel_desc_dsi tsd_tst070wsbe_196c = { 6455 .desc = { 6456 .modes = &tsd_tst070wsbe_196c_mode, 6457 .num_modes = 1, 6458 .bpc = 8, 6459 .size = { 6460 .width = 190, 6461 .height = 121, 6462 }, 6463 .delay = { 6464 .prepare = 20, 6465 }, 6466 .connector_type = DRM_MODE_CONNECTOR_DSI, 6467 }, 6468 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | 6469 MIPI_DSI_MODE_VIDEO_BURST | 6470 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6471 .format = MIPI_DSI_FMT_RGB888, 6472 .lanes = 4, 6473 }; 6474 6475 static const struct of_device_id dsi_of_match[] = { 6476 { 6477 .compatible = "auo,b080uan01", 6478 .data = &auo_b080uan01 6479 }, { 6480 .compatible = "boe,tv080wum-nl0", 6481 .data = &boe_tv080wum_nl0 6482 }, { 6483 .compatible = "lg,lh500wx1-sd03", 6484 .data = &lg_lh500wx1_sd03 6485 }, { 6486 .compatible = "panasonic,vvx10f004b00", 6487 .data = &panasonic_vvx10f004b00 6488 }, { 6489 .compatible = "lg,acx467akm-7", 6490 .data = &lg_acx467akm_7 6491 }, { 6492 .compatible = "osddisplays,osd101t2045-53ts", 6493 .data = &osd101t2045_53ts 6494 }, { 6495 .compatible = "team-source-display,tst070wsbe-196c", 6496 .data = &tsd_tst070wsbe_196c 6497 }, { 6498 /* sentinel */ 6499 } 6500 }; 6501 MODULE_DEVICE_TABLE(of, dsi_of_match); 6502 6503 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 6504 { 6505 const struct panel_desc_dsi *desc; 6506 struct panel_simple *panel; 6507 int err; 6508 6509 panel = panel_simple_probe(&dsi->dev); 6510 if (IS_ERR(panel)) 6511 return PTR_ERR(panel); 6512 6513 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 6514 dsi->mode_flags = desc->flags; 6515 dsi->format = desc->format; 6516 dsi->lanes = desc->lanes; 6517 6518 err = mipi_dsi_attach(dsi); 6519 if (err) { 6520 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 6521 6522 drm_panel_remove(&panel->base); 6523 } 6524 6525 return err; 6526 } 6527 6528 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 6529 { 6530 int err; 6531 6532 err = mipi_dsi_detach(dsi); 6533 if (err < 0) 6534 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 6535 6536 panel_simple_remove(&dsi->dev); 6537 } 6538 6539 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 6540 { 6541 panel_simple_shutdown(&dsi->dev); 6542 } 6543 6544 static struct mipi_dsi_driver panel_simple_dsi_driver = { 6545 .driver = { 6546 .name = "panel-simple-dsi", 6547 .of_match_table = dsi_of_match, 6548 .pm = &panel_simple_pm_ops, 6549 }, 6550 .probe = panel_simple_dsi_probe, 6551 .remove = panel_simple_dsi_remove, 6552 .shutdown = panel_simple_dsi_shutdown, 6553 }; 6554 6555 static int __init panel_simple_init(void) 6556 { 6557 int err; 6558 6559 err = platform_driver_register(&panel_simple_platform_driver); 6560 if (err < 0) 6561 return err; 6562 6563 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 6564 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 6565 if (err < 0) 6566 goto err_did_platform_register; 6567 } 6568 6569 return 0; 6570 6571 err_did_platform_register: 6572 platform_driver_unregister(&panel_simple_platform_driver); 6573 6574 return err; 6575 } 6576 module_init(panel_simple_init); 6577 6578 static void __exit panel_simple_exit(void) 6579 { 6580 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6581 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 6582 6583 platform_driver_unregister(&panel_simple_platform_driver); 6584 } 6585 module_exit(panel_simple_exit); 6586 6587 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 6588 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 6589 MODULE_LICENSE("GPL and additional rights"); 6590