1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 627 &panel_simple_funcs, desc->connector_type); 628 if (IS_ERR(panel)) 629 return ERR_CAST(panel); 630 631 panel->desc = desc; 632 633 panel->supply = devm_regulator_get(dev, "power"); 634 if (IS_ERR(panel->supply)) 635 return ERR_CAST(panel->supply); 636 637 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 638 GPIOD_OUT_LOW); 639 if (IS_ERR(panel->enable_gpio)) 640 return dev_err_cast_probe(dev, panel->enable_gpio, 641 "failed to request GPIO\n"); 642 643 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 644 if (err) { 645 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 646 return ERR_PTR(err); 647 } 648 649 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 650 if (ddc) { 651 panel->ddc = of_find_i2c_adapter_by_node(ddc); 652 of_node_put(ddc); 653 654 if (!panel->ddc) 655 return ERR_PTR(-EPROBE_DEFER); 656 } 657 658 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 659 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 660 panel_simple_parse_panel_timing_node(dev, panel, &dt); 661 662 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 663 /* Optional data-mapping property for overriding bus format */ 664 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 665 if (err) 666 goto free_ddc; 667 } 668 669 connector_type = desc->connector_type; 670 /* Catch common mistakes for panels. */ 671 switch (connector_type) { 672 case 0: 673 dev_warn(dev, "Specify missing connector_type\n"); 674 connector_type = DRM_MODE_CONNECTOR_DPI; 675 break; 676 case DRM_MODE_CONNECTOR_LVDS: 677 WARN_ON(desc->bus_flags & 678 ~(DRM_BUS_FLAG_DE_LOW | 679 DRM_BUS_FLAG_DE_HIGH | 680 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 681 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 682 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 683 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 684 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 685 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 686 desc->bpc != 6); 687 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 688 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 689 desc->bpc != 8); 690 break; 691 case DRM_MODE_CONNECTOR_eDP: 692 dev_warn(dev, "eDP panels moved to panel-edp\n"); 693 err = -EINVAL; 694 goto free_ddc; 695 case DRM_MODE_CONNECTOR_DSI: 696 if (desc->bpc != 6 && desc->bpc != 8) 697 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 698 break; 699 case DRM_MODE_CONNECTOR_DPI: 700 bus_flags = DRM_BUS_FLAG_DE_LOW | 701 DRM_BUS_FLAG_DE_HIGH | 702 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 703 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 704 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 705 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 706 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 707 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 708 if (desc->bus_flags & ~bus_flags) 709 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 710 if (!(desc->bus_flags & bus_flags)) 711 dev_warn(dev, "Specify missing bus_flags\n"); 712 if (desc->bus_format == 0) 713 dev_warn(dev, "Specify missing bus_format\n"); 714 if (desc->bpc != 6 && desc->bpc != 8) 715 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 716 break; 717 default: 718 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 719 connector_type = DRM_MODE_CONNECTOR_DPI; 720 break; 721 } 722 723 dev_set_drvdata(dev, panel); 724 725 /* 726 * We use runtime PM for prepare / unprepare since those power the panel 727 * on and off and those can be very slow operations. This is important 728 * to optimize powering the panel on briefly to read the EDID before 729 * fully enabling the panel. 730 */ 731 pm_runtime_enable(dev); 732 pm_runtime_set_autosuspend_delay(dev, 1000); 733 pm_runtime_use_autosuspend(dev); 734 735 err = drm_panel_of_backlight(&panel->base); 736 if (err) { 737 dev_err_probe(dev, err, "Could not find backlight\n"); 738 goto disable_pm_runtime; 739 } 740 741 drm_panel_add(&panel->base); 742 743 return panel; 744 745 disable_pm_runtime: 746 pm_runtime_dont_use_autosuspend(dev); 747 pm_runtime_disable(dev); 748 free_ddc: 749 if (panel->ddc) 750 put_device(&panel->ddc->dev); 751 752 return ERR_PTR(err); 753 } 754 755 static void panel_simple_shutdown(struct device *dev) 756 { 757 struct panel_simple *panel = dev_get_drvdata(dev); 758 759 /* 760 * NOTE: the following two calls don't really belong here. It is the 761 * responsibility of a correctly written DRM modeset driver to call 762 * drm_atomic_helper_shutdown() at shutdown time and that should 763 * cause the panel to be disabled / unprepared if needed. For now, 764 * however, we'll keep these calls due to the sheer number of 765 * different DRM modeset drivers used with panel-simple. Once we've 766 * confirmed that all DRM modeset drivers using this panel properly 767 * call drm_atomic_helper_shutdown() we can simply delete the two 768 * calls below. 769 * 770 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 771 * PANEL DRIVERS. 772 * 773 * FIXME: If we're still haven't figured out if all DRM modeset 774 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 775 * managed to make sure that DRM modeset drivers get their shutdown() 776 * callback before the panel's shutdown() callback (perhaps using 777 * device link), we could add a WARN_ON here to help move forward. 778 */ 779 if (panel->base.enabled) 780 drm_panel_disable(&panel->base); 781 if (panel->base.prepared) 782 drm_panel_unprepare(&panel->base); 783 } 784 785 static void panel_simple_remove(struct device *dev) 786 { 787 struct panel_simple *panel = dev_get_drvdata(dev); 788 789 drm_panel_remove(&panel->base); 790 panel_simple_shutdown(dev); 791 792 pm_runtime_dont_use_autosuspend(dev); 793 pm_runtime_disable(dev); 794 if (panel->ddc) 795 put_device(&panel->ddc->dev); 796 } 797 798 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 799 .clock = 71100, 800 .hdisplay = 1280, 801 .hsync_start = 1280 + 40, 802 .hsync_end = 1280 + 40 + 80, 803 .htotal = 1280 + 40 + 80 + 40, 804 .vdisplay = 800, 805 .vsync_start = 800 + 3, 806 .vsync_end = 800 + 3 + 10, 807 .vtotal = 800 + 3 + 10 + 10, 808 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 809 }; 810 811 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 812 .modes = &ire_am_1280800n3tzqw_t00h_mode, 813 .num_modes = 1, 814 .bpc = 8, 815 .size = { 816 .width = 217, 817 .height = 136, 818 }, 819 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 820 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 821 .connector_type = DRM_MODE_CONNECTOR_LVDS, 822 }; 823 824 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 825 .clock = 9000, 826 .hdisplay = 480, 827 .hsync_start = 480 + 2, 828 .hsync_end = 480 + 2 + 41, 829 .htotal = 480 + 2 + 41 + 2, 830 .vdisplay = 272, 831 .vsync_start = 272 + 2, 832 .vsync_end = 272 + 2 + 10, 833 .vtotal = 272 + 2 + 10 + 2, 834 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 835 }; 836 837 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 838 .modes = &ire_am_480272h3tmqw_t01h_mode, 839 .num_modes = 1, 840 .bpc = 8, 841 .size = { 842 .width = 99, 843 .height = 58, 844 }, 845 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 846 }; 847 848 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 849 .clock = 33333, 850 .hdisplay = 800, 851 .hsync_start = 800 + 0, 852 .hsync_end = 800 + 0 + 255, 853 .htotal = 800 + 0 + 255 + 0, 854 .vdisplay = 480, 855 .vsync_start = 480 + 2, 856 .vsync_end = 480 + 2 + 45, 857 .vtotal = 480 + 2 + 45 + 0, 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 859 }; 860 861 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 862 .pixelclock = { 29930000, 33260000, 36590000 }, 863 .hactive = { 800, 800, 800 }, 864 .hfront_porch = { 1, 40, 168 }, 865 .hback_porch = { 88, 88, 88 }, 866 .hsync_len = { 1, 128, 128 }, 867 .vactive = { 480, 480, 480 }, 868 .vfront_porch = { 1, 35, 37 }, 869 .vback_porch = { 8, 8, 8 }, 870 .vsync_len = { 1, 2, 2 }, 871 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 872 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 873 DISPLAY_FLAGS_SYNC_POSEDGE, 874 }; 875 876 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 877 .timings = &ire_am_800480l1tmqw_t00h_timing, 878 .num_timings = 1, 879 .bpc = 8, 880 .size = { 881 .width = 111, 882 .height = 67, 883 }, 884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 885 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 886 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 887 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 888 .connector_type = DRM_MODE_CONNECTOR_DPI, 889 }; 890 891 static const struct panel_desc ampire_am800480r3tmqwa1h = { 892 .modes = &ire_am800480r3tmqwa1h_mode, 893 .num_modes = 1, 894 .bpc = 6, 895 .size = { 896 .width = 152, 897 .height = 91, 898 }, 899 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 900 }; 901 902 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 903 .pixelclock = { 34500000, 39600000, 50400000 }, 904 .hactive = { 800, 800, 800 }, 905 .hfront_porch = { 12, 112, 312 }, 906 .hback_porch = { 87, 87, 48 }, 907 .hsync_len = { 1, 1, 40 }, 908 .vactive = { 600, 600, 600 }, 909 .vfront_porch = { 1, 21, 61 }, 910 .vback_porch = { 38, 38, 19 }, 911 .vsync_len = { 1, 1, 20 }, 912 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 913 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 914 DISPLAY_FLAGS_SYNC_POSEDGE, 915 }; 916 917 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 918 .timings = &ire_am800600p5tmqw_tb8h_timing, 919 .num_timings = 1, 920 .bpc = 6, 921 .size = { 922 .width = 162, 923 .height = 122, 924 }, 925 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 926 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 927 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 928 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 929 .connector_type = DRM_MODE_CONNECTOR_DPI, 930 }; 931 932 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 933 .pixelclock = { 26400000, 33300000, 46800000 }, 934 .hactive = { 800, 800, 800 }, 935 .hfront_porch = { 16, 210, 354 }, 936 .hback_porch = { 45, 36, 6 }, 937 .hsync_len = { 1, 10, 40 }, 938 .vactive = { 480, 480, 480 }, 939 .vfront_porch = { 7, 22, 147 }, 940 .vback_porch = { 22, 13, 3 }, 941 .vsync_len = { 1, 10, 20 }, 942 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 943 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 944 }; 945 946 static const struct panel_desc armadeus_st0700_adapt = { 947 .timings = &santek_st0700i5y_rbslw_f_timing, 948 .num_timings = 1, 949 .bpc = 6, 950 .size = { 951 .width = 154, 952 .height = 86, 953 }, 954 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 955 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 956 }; 957 958 static const struct drm_display_mode auo_b101aw03_mode = { 959 .clock = 51450, 960 .hdisplay = 1024, 961 .hsync_start = 1024 + 156, 962 .hsync_end = 1024 + 156 + 8, 963 .htotal = 1024 + 156 + 8 + 156, 964 .vdisplay = 600, 965 .vsync_start = 600 + 16, 966 .vsync_end = 600 + 16 + 6, 967 .vtotal = 600 + 16 + 6 + 16, 968 }; 969 970 static const struct panel_desc auo_b101aw03 = { 971 .modes = &auo_b101aw03_mode, 972 .num_modes = 1, 973 .bpc = 6, 974 .size = { 975 .width = 223, 976 .height = 125, 977 }, 978 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 979 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 980 .connector_type = DRM_MODE_CONNECTOR_LVDS, 981 }; 982 983 static const struct drm_display_mode auo_b101xtn01_mode = { 984 .clock = 72000, 985 .hdisplay = 1366, 986 .hsync_start = 1366 + 20, 987 .hsync_end = 1366 + 20 + 70, 988 .htotal = 1366 + 20 + 70, 989 .vdisplay = 768, 990 .vsync_start = 768 + 14, 991 .vsync_end = 768 + 14 + 42, 992 .vtotal = 768 + 14 + 42, 993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 994 }; 995 996 static const struct panel_desc auo_b101xtn01 = { 997 .modes = &auo_b101xtn01_mode, 998 .num_modes = 1, 999 .bpc = 6, 1000 .size = { 1001 .width = 223, 1002 .height = 125, 1003 }, 1004 }; 1005 1006 static const struct drm_display_mode auo_b116xw03_mode = { 1007 .clock = 70589, 1008 .hdisplay = 1366, 1009 .hsync_start = 1366 + 40, 1010 .hsync_end = 1366 + 40 + 40, 1011 .htotal = 1366 + 40 + 40 + 32, 1012 .vdisplay = 768, 1013 .vsync_start = 768 + 10, 1014 .vsync_end = 768 + 10 + 12, 1015 .vtotal = 768 + 10 + 12 + 6, 1016 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1017 }; 1018 1019 static const struct panel_desc auo_b116xw03 = { 1020 .modes = &auo_b116xw03_mode, 1021 .num_modes = 1, 1022 .bpc = 6, 1023 .size = { 1024 .width = 256, 1025 .height = 144, 1026 }, 1027 .delay = { 1028 .prepare = 1, 1029 .enable = 200, 1030 .disable = 200, 1031 .unprepare = 500, 1032 }, 1033 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1034 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1036 }; 1037 1038 static const struct display_timing auo_g070vvn01_timings = { 1039 .pixelclock = { 33300000, 34209000, 45000000 }, 1040 .hactive = { 800, 800, 800 }, 1041 .hfront_porch = { 20, 40, 200 }, 1042 .hback_porch = { 87, 40, 1 }, 1043 .hsync_len = { 1, 48, 87 }, 1044 .vactive = { 480, 480, 480 }, 1045 .vfront_porch = { 5, 13, 200 }, 1046 .vback_porch = { 31, 31, 29 }, 1047 .vsync_len = { 1, 1, 3 }, 1048 }; 1049 1050 static const struct panel_desc auo_g070vvn01 = { 1051 .timings = &auo_g070vvn01_timings, 1052 .num_timings = 1, 1053 .bpc = 8, 1054 .size = { 1055 .width = 152, 1056 .height = 91, 1057 }, 1058 .delay = { 1059 .prepare = 200, 1060 .enable = 50, 1061 .disable = 50, 1062 .unprepare = 1000, 1063 }, 1064 }; 1065 1066 static const struct display_timing auo_g101evn010_timing = { 1067 .pixelclock = { 64000000, 68930000, 85000000 }, 1068 .hactive = { 1280, 1280, 1280 }, 1069 .hfront_porch = { 8, 64, 256 }, 1070 .hback_porch = { 8, 64, 256 }, 1071 .hsync_len = { 40, 168, 767 }, 1072 .vactive = { 800, 800, 800 }, 1073 .vfront_porch = { 4, 8, 100 }, 1074 .vback_porch = { 4, 8, 100 }, 1075 .vsync_len = { 8, 16, 223 }, 1076 }; 1077 1078 static const struct panel_desc auo_g101evn010 = { 1079 .timings = &auo_g101evn010_timing, 1080 .num_timings = 1, 1081 .bpc = 6, 1082 .size = { 1083 .width = 216, 1084 .height = 135, 1085 }, 1086 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1087 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1088 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1089 }; 1090 1091 static const struct drm_display_mode auo_g104sn02_mode = { 1092 .clock = 40000, 1093 .hdisplay = 800, 1094 .hsync_start = 800 + 40, 1095 .hsync_end = 800 + 40 + 216, 1096 .htotal = 800 + 40 + 216 + 128, 1097 .vdisplay = 600, 1098 .vsync_start = 600 + 10, 1099 .vsync_end = 600 + 10 + 35, 1100 .vtotal = 600 + 10 + 35 + 2, 1101 }; 1102 1103 static const struct panel_desc auo_g104sn02 = { 1104 .modes = &auo_g104sn02_mode, 1105 .num_modes = 1, 1106 .bpc = 8, 1107 .size = { 1108 .width = 211, 1109 .height = 158, 1110 }, 1111 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1112 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1113 }; 1114 1115 static const struct drm_display_mode auo_g104stn01_mode = { 1116 .clock = 40000, 1117 .hdisplay = 800, 1118 .hsync_start = 800 + 40, 1119 .hsync_end = 800 + 40 + 88, 1120 .htotal = 800 + 40 + 88 + 128, 1121 .vdisplay = 600, 1122 .vsync_start = 600 + 1, 1123 .vsync_end = 600 + 1 + 23, 1124 .vtotal = 600 + 1 + 23 + 4, 1125 }; 1126 1127 static const struct panel_desc auo_g104stn01 = { 1128 .modes = &auo_g104stn01_mode, 1129 .num_modes = 1, 1130 .bpc = 8, 1131 .size = { 1132 .width = 211, 1133 .height = 158, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1136 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1137 }; 1138 1139 static const struct display_timing auo_g121ean01_timing = { 1140 .pixelclock = { 60000000, 74400000, 90000000 }, 1141 .hactive = { 1280, 1280, 1280 }, 1142 .hfront_porch = { 20, 50, 100 }, 1143 .hback_porch = { 20, 50, 100 }, 1144 .hsync_len = { 30, 100, 200 }, 1145 .vactive = { 800, 800, 800 }, 1146 .vfront_porch = { 2, 10, 25 }, 1147 .vback_porch = { 2, 10, 25 }, 1148 .vsync_len = { 4, 18, 50 }, 1149 }; 1150 1151 static const struct panel_desc auo_g121ean01 = { 1152 .timings = &auo_g121ean01_timing, 1153 .num_timings = 1, 1154 .bpc = 8, 1155 .size = { 1156 .width = 261, 1157 .height = 163, 1158 }, 1159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1161 }; 1162 1163 static const struct display_timing auo_g133han01_timings = { 1164 .pixelclock = { 134000000, 141200000, 149000000 }, 1165 .hactive = { 1920, 1920, 1920 }, 1166 .hfront_porch = { 39, 58, 77 }, 1167 .hback_porch = { 59, 88, 117 }, 1168 .hsync_len = { 28, 42, 56 }, 1169 .vactive = { 1080, 1080, 1080 }, 1170 .vfront_porch = { 3, 8, 11 }, 1171 .vback_porch = { 5, 14, 19 }, 1172 .vsync_len = { 4, 14, 19 }, 1173 }; 1174 1175 static const struct panel_desc auo_g133han01 = { 1176 .timings = &auo_g133han01_timings, 1177 .num_timings = 1, 1178 .bpc = 8, 1179 .size = { 1180 .width = 293, 1181 .height = 165, 1182 }, 1183 .delay = { 1184 .prepare = 200, 1185 .enable = 50, 1186 .disable = 50, 1187 .unprepare = 1000, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1191 }; 1192 1193 static const struct display_timing auo_g156han04_timings = { 1194 .pixelclock = { 137000000, 141000000, 146000000 }, 1195 .hactive = { 1920, 1920, 1920 }, 1196 .hfront_porch = { 60, 60, 60 }, 1197 .hback_porch = { 90, 92, 111 }, 1198 .hsync_len = { 32, 32, 32 }, 1199 .vactive = { 1080, 1080, 1080 }, 1200 .vfront_porch = { 12, 12, 12 }, 1201 .vback_porch = { 24, 36, 56 }, 1202 .vsync_len = { 8, 8, 8 }, 1203 }; 1204 1205 static const struct panel_desc auo_g156han04 = { 1206 .timings = &auo_g156han04_timings, 1207 .num_timings = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 344, 1211 .height = 194, 1212 }, 1213 .delay = { 1214 .prepare = 50, /* T2 */ 1215 .enable = 200, /* T3 */ 1216 .disable = 110, /* T10 */ 1217 .unprepare = 1000, /* T13 */ 1218 }, 1219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1220 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1221 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1222 }; 1223 1224 static const struct drm_display_mode auo_g156xtn01_mode = { 1225 .clock = 76000, 1226 .hdisplay = 1366, 1227 .hsync_start = 1366 + 33, 1228 .hsync_end = 1366 + 33 + 67, 1229 .htotal = 1560, 1230 .vdisplay = 768, 1231 .vsync_start = 768 + 4, 1232 .vsync_end = 768 + 4 + 4, 1233 .vtotal = 806, 1234 }; 1235 1236 static const struct panel_desc auo_g156xtn01 = { 1237 .modes = &auo_g156xtn01_mode, 1238 .num_modes = 1, 1239 .bpc = 8, 1240 .size = { 1241 .width = 344, 1242 .height = 194, 1243 }, 1244 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1246 }; 1247 1248 static const struct display_timing auo_g185han01_timings = { 1249 .pixelclock = { 120000000, 144000000, 175000000 }, 1250 .hactive = { 1920, 1920, 1920 }, 1251 .hfront_porch = { 36, 120, 148 }, 1252 .hback_porch = { 24, 88, 108 }, 1253 .hsync_len = { 20, 48, 64 }, 1254 .vactive = { 1080, 1080, 1080 }, 1255 .vfront_porch = { 6, 10, 40 }, 1256 .vback_porch = { 2, 5, 20 }, 1257 .vsync_len = { 2, 5, 20 }, 1258 }; 1259 1260 static const struct panel_desc auo_g185han01 = { 1261 .timings = &auo_g185han01_timings, 1262 .num_timings = 1, 1263 .bpc = 8, 1264 .size = { 1265 .width = 409, 1266 .height = 230, 1267 }, 1268 .delay = { 1269 .prepare = 50, 1270 .enable = 200, 1271 .disable = 110, 1272 .unprepare = 1000, 1273 }, 1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct display_timing auo_g190ean01_timings = { 1279 .pixelclock = { 90000000, 108000000, 135000000 }, 1280 .hactive = { 1280, 1280, 1280 }, 1281 .hfront_porch = { 126, 184, 1266 }, 1282 .hback_porch = { 84, 122, 844 }, 1283 .hsync_len = { 70, 102, 704 }, 1284 .vactive = { 1024, 1024, 1024 }, 1285 .vfront_porch = { 4, 26, 76 }, 1286 .vback_porch = { 2, 8, 25 }, 1287 .vsync_len = { 2, 8, 25 }, 1288 }; 1289 1290 static const struct panel_desc auo_g190ean01 = { 1291 .timings = &auo_g190ean01_timings, 1292 .num_timings = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 376, 1296 .height = 301, 1297 }, 1298 .delay = { 1299 .prepare = 50, 1300 .enable = 200, 1301 .disable = 110, 1302 .unprepare = 1000, 1303 }, 1304 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1305 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1306 }; 1307 1308 static const struct display_timing auo_p238han01_timings = { 1309 .pixelclock = { 107400000, 142400000, 180000000 }, 1310 .hactive = { 1920, 1920, 1920 }, 1311 .hfront_porch = { 30, 70, 650 }, 1312 .hback_porch = { 30, 70, 650 }, 1313 .hsync_len = { 20, 40, 136 }, 1314 .vactive = { 1080, 1080, 1080 }, 1315 .vfront_porch = { 5, 19, 318 }, 1316 .vback_porch = { 5, 19, 318 }, 1317 .vsync_len = { 4, 12, 120 }, 1318 }; 1319 1320 static const struct panel_desc auo_p238han01 = { 1321 .timings = &auo_p238han01_timings, 1322 .num_timings = 1, 1323 .bpc = 8, 1324 .size = { 1325 .width = 527, 1326 .height = 296, 1327 }, 1328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1329 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1330 }; 1331 1332 static const struct display_timing auo_p320hvn03_timings = { 1333 .pixelclock = { 106000000, 148500000, 164000000 }, 1334 .hactive = { 1920, 1920, 1920 }, 1335 .hfront_porch = { 25, 50, 130 }, 1336 .hback_porch = { 25, 50, 130 }, 1337 .hsync_len = { 20, 40, 105 }, 1338 .vactive = { 1080, 1080, 1080 }, 1339 .vfront_porch = { 8, 17, 150 }, 1340 .vback_porch = { 8, 17, 150 }, 1341 .vsync_len = { 4, 11, 100 }, 1342 }; 1343 1344 static const struct panel_desc auo_p320hvn03 = { 1345 .timings = &auo_p320hvn03_timings, 1346 .num_timings = 1, 1347 .bpc = 8, 1348 .size = { 1349 .width = 698, 1350 .height = 393, 1351 }, 1352 .delay = { 1353 .prepare = 1, 1354 .enable = 450, 1355 .unprepare = 500, 1356 }, 1357 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1358 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1359 }; 1360 1361 static const struct drm_display_mode auo_t215hvn01_mode = { 1362 .clock = 148800, 1363 .hdisplay = 1920, 1364 .hsync_start = 1920 + 88, 1365 .hsync_end = 1920 + 88 + 44, 1366 .htotal = 1920 + 88 + 44 + 148, 1367 .vdisplay = 1080, 1368 .vsync_start = 1080 + 4, 1369 .vsync_end = 1080 + 4 + 5, 1370 .vtotal = 1080 + 4 + 5 + 36, 1371 }; 1372 1373 static const struct panel_desc auo_t215hvn01 = { 1374 .modes = &auo_t215hvn01_mode, 1375 .num_modes = 1, 1376 .bpc = 8, 1377 .size = { 1378 .width = 430, 1379 .height = 270, 1380 }, 1381 .delay = { 1382 .disable = 5, 1383 .unprepare = 1000, 1384 }, 1385 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1386 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1387 }; 1388 1389 static const struct drm_display_mode avic_tm070ddh03_mode = { 1390 .clock = 51200, 1391 .hdisplay = 1024, 1392 .hsync_start = 1024 + 160, 1393 .hsync_end = 1024 + 160 + 4, 1394 .htotal = 1024 + 160 + 4 + 156, 1395 .vdisplay = 600, 1396 .vsync_start = 600 + 17, 1397 .vsync_end = 600 + 17 + 1, 1398 .vtotal = 600 + 17 + 1 + 17, 1399 }; 1400 1401 static const struct panel_desc avic_tm070ddh03 = { 1402 .modes = &avic_tm070ddh03_mode, 1403 .num_modes = 1, 1404 .bpc = 8, 1405 .size = { 1406 .width = 154, 1407 .height = 90, 1408 }, 1409 .delay = { 1410 .prepare = 20, 1411 .enable = 200, 1412 .disable = 200, 1413 }, 1414 }; 1415 1416 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1417 .clock = 30000, 1418 .hdisplay = 800, 1419 .hsync_start = 800 + 40, 1420 .hsync_end = 800 + 40 + 48, 1421 .htotal = 800 + 40 + 48 + 40, 1422 .vdisplay = 480, 1423 .vsync_start = 480 + 13, 1424 .vsync_end = 480 + 13 + 3, 1425 .vtotal = 480 + 13 + 3 + 29, 1426 }; 1427 1428 static const struct panel_desc bananapi_s070wv20_ct16 = { 1429 .modes = &bananapi_s070wv20_ct16_mode, 1430 .num_modes = 1, 1431 .bpc = 6, 1432 .size = { 1433 .width = 154, 1434 .height = 86, 1435 }, 1436 }; 1437 1438 static const struct display_timing boe_av101hdt_a10_timing = { 1439 .pixelclock = { 74210000, 75330000, 76780000, }, 1440 .hactive = { 1280, 1280, 1280, }, 1441 .hfront_porch = { 10, 42, 33, }, 1442 .hback_porch = { 10, 18, 33, }, 1443 .hsync_len = { 30, 10, 30, }, 1444 .vactive = { 720, 720, 720, }, 1445 .vfront_porch = { 200, 183, 200, }, 1446 .vback_porch = { 8, 8, 8, }, 1447 .vsync_len = { 2, 19, 2, }, 1448 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1449 }; 1450 1451 static const struct panel_desc boe_av101hdt_a10 = { 1452 .timings = &boe_av101hdt_a10_timing, 1453 .num_timings = 1, 1454 .bpc = 8, 1455 .size = { 1456 .width = 224, 1457 .height = 126, 1458 }, 1459 .delay = { 1460 .enable = 50, 1461 .disable = 50, 1462 }, 1463 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1464 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1465 }; 1466 1467 static const struct display_timing boe_av123z7m_n17_timing = { 1468 .pixelclock = { 86600000, 88000000, 90800000, }, 1469 .hactive = { 1920, 1920, 1920, }, 1470 .hfront_porch = { 10, 10, 10, }, 1471 .hback_porch = { 10, 10, 10, }, 1472 .hsync_len = { 9, 12, 25, }, 1473 .vactive = { 720, 720, 720, }, 1474 .vfront_porch = { 7, 10, 13, }, 1475 .vback_porch = { 7, 10, 13, }, 1476 .vsync_len = { 7, 11, 14, }, 1477 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1478 }; 1479 1480 static const struct panel_desc boe_av123z7m_n17 = { 1481 .timings = &boe_av123z7m_n17_timing, 1482 .bpc = 8, 1483 .num_timings = 1, 1484 .size = { 1485 .width = 292, 1486 .height = 110, 1487 }, 1488 .delay = { 1489 .prepare = 50, 1490 .disable = 50, 1491 }, 1492 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1493 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1494 }; 1495 1496 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1497 .clock = 78945, 1498 .hdisplay = 1280, 1499 .hsync_start = 1280 + 0, 1500 .hsync_end = 1280 + 0 + 2, 1501 .htotal = 1280 + 62 + 0 + 2, 1502 .vdisplay = 800, 1503 .vsync_start = 800 + 8, 1504 .vsync_end = 800 + 8 + 2, 1505 .vtotal = 800 + 6 + 8 + 2, 1506 }; 1507 1508 static const struct panel_desc boe_bp082wx1_100 = { 1509 .modes = &boe_bp101wx1_100_mode, 1510 .num_modes = 1, 1511 .bpc = 8, 1512 .size = { 1513 .width = 177, 1514 .height = 110, 1515 }, 1516 .delay = { 1517 .enable = 50, 1518 .disable = 50, 1519 }, 1520 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1521 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1522 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1523 }; 1524 1525 static const struct panel_desc boe_bp101wx1_100 = { 1526 .modes = &boe_bp101wx1_100_mode, 1527 .num_modes = 1, 1528 .bpc = 8, 1529 .size = { 1530 .width = 217, 1531 .height = 136, 1532 }, 1533 .delay = { 1534 .enable = 50, 1535 .disable = 50, 1536 }, 1537 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1538 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1539 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1540 }; 1541 1542 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1543 .pixelclock = { 69922000, 71000000, 72293000 }, 1544 .hactive = { 1280, 1280, 1280 }, 1545 .hfront_porch = { 48, 48, 48 }, 1546 .hback_porch = { 80, 80, 80 }, 1547 .hsync_len = { 32, 32, 32 }, 1548 .vactive = { 800, 800, 800 }, 1549 .vfront_porch = { 3, 3, 3 }, 1550 .vback_porch = { 14, 14, 14 }, 1551 .vsync_len = { 6, 6, 6 }, 1552 }; 1553 1554 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1555 .timings = &boe_ev121wxm_n10_1850_timing, 1556 .num_timings = 1, 1557 .bpc = 8, 1558 .size = { 1559 .width = 261, 1560 .height = 163, 1561 }, 1562 .delay = { 1563 .prepare = 9, 1564 .enable = 300, 1565 .unprepare = 300, 1566 .disable = 560, 1567 }, 1568 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1569 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1570 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1571 }; 1572 1573 static const struct drm_display_mode boe_hv070wsa_mode = { 1574 .clock = 42105, 1575 .hdisplay = 1024, 1576 .hsync_start = 1024 + 30, 1577 .hsync_end = 1024 + 30 + 30, 1578 .htotal = 1024 + 30 + 30 + 30, 1579 .vdisplay = 600, 1580 .vsync_start = 600 + 10, 1581 .vsync_end = 600 + 10 + 10, 1582 .vtotal = 600 + 10 + 10 + 10, 1583 }; 1584 1585 static const struct panel_desc boe_hv070wsa = { 1586 .modes = &boe_hv070wsa_mode, 1587 .num_modes = 1, 1588 .bpc = 8, 1589 .size = { 1590 .width = 154, 1591 .height = 90, 1592 }, 1593 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1594 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1595 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1596 }; 1597 1598 static const struct display_timing cct_cmt430b19n00_timing = { 1599 .pixelclock = { 8000000, 9000000, 12000000 }, 1600 .hactive = { 480, 480, 480 }, 1601 .hfront_porch = { 2, 8, 75 }, 1602 .hback_porch = { 3, 43, 43 }, 1603 .hsync_len = { 2, 4, 75 }, 1604 .vactive = { 272, 272, 272 }, 1605 .vfront_porch = { 2, 8, 37 }, 1606 .vback_porch = { 2, 12, 12 }, 1607 .vsync_len = { 2, 4, 37 }, 1608 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1609 }; 1610 1611 static const struct panel_desc cct_cmt430b19n00 = { 1612 .timings = &cct_cmt430b19n00_timing, 1613 .num_timings = 1, 1614 .bpc = 8, 1615 .size = { 1616 .width = 95, 1617 .height = 53, 1618 }, 1619 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1620 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1621 .connector_type = DRM_MODE_CONNECTOR_DPI, 1622 }; 1623 1624 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1625 .clock = 9000, 1626 .hdisplay = 480, 1627 .hsync_start = 480 + 5, 1628 .hsync_end = 480 + 5 + 5, 1629 .htotal = 480 + 5 + 5 + 40, 1630 .vdisplay = 272, 1631 .vsync_start = 272 + 8, 1632 .vsync_end = 272 + 8 + 8, 1633 .vtotal = 272 + 8 + 8 + 8, 1634 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1635 }; 1636 1637 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1638 .modes = &cdtech_s043wq26h_ct7_mode, 1639 .num_modes = 1, 1640 .bpc = 8, 1641 .size = { 1642 .width = 95, 1643 .height = 54, 1644 }, 1645 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1646 }; 1647 1648 /* S070PWS19HP-FC21 2017/04/22 */ 1649 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1650 .clock = 51200, 1651 .hdisplay = 1024, 1652 .hsync_start = 1024 + 160, 1653 .hsync_end = 1024 + 160 + 20, 1654 .htotal = 1024 + 160 + 20 + 140, 1655 .vdisplay = 600, 1656 .vsync_start = 600 + 12, 1657 .vsync_end = 600 + 12 + 3, 1658 .vtotal = 600 + 12 + 3 + 20, 1659 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1660 }; 1661 1662 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1663 .modes = &cdtech_s070pws19hp_fc21_mode, 1664 .num_modes = 1, 1665 .bpc = 6, 1666 .size = { 1667 .width = 154, 1668 .height = 86, 1669 }, 1670 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1672 .connector_type = DRM_MODE_CONNECTOR_DPI, 1673 }; 1674 1675 /* S070SWV29HG-DC44 2017/09/21 */ 1676 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1677 .clock = 33300, 1678 .hdisplay = 800, 1679 .hsync_start = 800 + 210, 1680 .hsync_end = 800 + 210 + 2, 1681 .htotal = 800 + 210 + 2 + 44, 1682 .vdisplay = 480, 1683 .vsync_start = 480 + 22, 1684 .vsync_end = 480 + 22 + 2, 1685 .vtotal = 480 + 22 + 2 + 21, 1686 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1687 }; 1688 1689 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1690 .modes = &cdtech_s070swv29hg_dc44_mode, 1691 .num_modes = 1, 1692 .bpc = 6, 1693 .size = { 1694 .width = 154, 1695 .height = 86, 1696 }, 1697 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1698 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1699 .connector_type = DRM_MODE_CONNECTOR_DPI, 1700 }; 1701 1702 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1703 .clock = 35000, 1704 .hdisplay = 800, 1705 .hsync_start = 800 + 40, 1706 .hsync_end = 800 + 40 + 40, 1707 .htotal = 800 + 40 + 40 + 48, 1708 .vdisplay = 480, 1709 .vsync_start = 480 + 29, 1710 .vsync_end = 480 + 29 + 13, 1711 .vtotal = 480 + 29 + 13 + 3, 1712 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1713 }; 1714 1715 static const struct panel_desc cdtech_s070wv95_ct16 = { 1716 .modes = &cdtech_s070wv95_ct16_mode, 1717 .num_modes = 1, 1718 .bpc = 8, 1719 .size = { 1720 .width = 154, 1721 .height = 85, 1722 }, 1723 }; 1724 1725 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1726 .pixelclock = { 68900000, 71100000, 73400000 }, 1727 .hactive = { 1280, 1280, 1280 }, 1728 .hfront_porch = { 65, 80, 95 }, 1729 .hback_porch = { 64, 79, 94 }, 1730 .hsync_len = { 1, 1, 1 }, 1731 .vactive = { 800, 800, 800 }, 1732 .vfront_porch = { 7, 11, 14 }, 1733 .vback_porch = { 7, 11, 14 }, 1734 .vsync_len = { 1, 1, 1 }, 1735 .flags = DISPLAY_FLAGS_DE_HIGH, 1736 }; 1737 1738 static const struct panel_desc chefree_ch101olhlwh_002 = { 1739 .timings = &chefree_ch101olhlwh_002_timing, 1740 .num_timings = 1, 1741 .bpc = 8, 1742 .size = { 1743 .width = 217, 1744 .height = 135, 1745 }, 1746 .delay = { 1747 .enable = 200, 1748 .disable = 200, 1749 }, 1750 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1751 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1752 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1753 }; 1754 1755 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1756 .clock = 66770, 1757 .hdisplay = 800, 1758 .hsync_start = 800 + 49, 1759 .hsync_end = 800 + 49 + 33, 1760 .htotal = 800 + 49 + 33 + 17, 1761 .vdisplay = 1280, 1762 .vsync_start = 1280 + 1, 1763 .vsync_end = 1280 + 1 + 7, 1764 .vtotal = 1280 + 1 + 7 + 15, 1765 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1766 }; 1767 1768 static const struct panel_desc chunghwa_claa070wp03xg = { 1769 .modes = &chunghwa_claa070wp03xg_mode, 1770 .num_modes = 1, 1771 .bpc = 6, 1772 .size = { 1773 .width = 94, 1774 .height = 150, 1775 }, 1776 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1777 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1778 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1779 }; 1780 1781 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1782 .clock = 72070, 1783 .hdisplay = 1366, 1784 .hsync_start = 1366 + 58, 1785 .hsync_end = 1366 + 58 + 58, 1786 .htotal = 1366 + 58 + 58 + 58, 1787 .vdisplay = 768, 1788 .vsync_start = 768 + 4, 1789 .vsync_end = 768 + 4 + 4, 1790 .vtotal = 768 + 4 + 4 + 4, 1791 }; 1792 1793 static const struct panel_desc chunghwa_claa101wa01a = { 1794 .modes = &chunghwa_claa101wa01a_mode, 1795 .num_modes = 1, 1796 .bpc = 6, 1797 .size = { 1798 .width = 220, 1799 .height = 120, 1800 }, 1801 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1802 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1803 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1804 }; 1805 1806 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1807 .clock = 69300, 1808 .hdisplay = 1366, 1809 .hsync_start = 1366 + 48, 1810 .hsync_end = 1366 + 48 + 32, 1811 .htotal = 1366 + 48 + 32 + 20, 1812 .vdisplay = 768, 1813 .vsync_start = 768 + 16, 1814 .vsync_end = 768 + 16 + 8, 1815 .vtotal = 768 + 16 + 8 + 16, 1816 }; 1817 1818 static const struct panel_desc chunghwa_claa101wb01 = { 1819 .modes = &chunghwa_claa101wb01_mode, 1820 .num_modes = 1, 1821 .bpc = 6, 1822 .size = { 1823 .width = 223, 1824 .height = 125, 1825 }, 1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1828 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1829 }; 1830 1831 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1832 .pixelclock = { 5000000, 9000000, 12000000 }, 1833 .hactive = { 480, 480, 480 }, 1834 .hfront_porch = { 12, 12, 12 }, 1835 .hback_porch = { 12, 12, 12 }, 1836 .hsync_len = { 21, 21, 21 }, 1837 .vactive = { 272, 272, 272 }, 1838 .vfront_porch = { 4, 4, 4 }, 1839 .vback_porch = { 4, 4, 4 }, 1840 .vsync_len = { 8, 8, 8 }, 1841 }; 1842 1843 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1844 .timings = &dataimage_fg040346dsswbg04_timing, 1845 .num_timings = 1, 1846 .bpc = 8, 1847 .size = { 1848 .width = 95, 1849 .height = 54, 1850 }, 1851 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1852 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1853 .connector_type = DRM_MODE_CONNECTOR_DPI, 1854 }; 1855 1856 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1857 .pixelclock = { 68900000, 71110000, 73400000 }, 1858 .hactive = { 1280, 1280, 1280 }, 1859 .vactive = { 800, 800, 800 }, 1860 .hback_porch = { 100, 100, 100 }, 1861 .hfront_porch = { 100, 100, 100 }, 1862 .vback_porch = { 5, 5, 5 }, 1863 .vfront_porch = { 5, 5, 5 }, 1864 .hsync_len = { 24, 24, 24 }, 1865 .vsync_len = { 3, 3, 3 }, 1866 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1867 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1868 }; 1869 1870 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1871 .timings = &dataimage_fg1001l0dsswmg01_timing, 1872 .num_timings = 1, 1873 .bpc = 8, 1874 .size = { 1875 .width = 217, 1876 .height = 136, 1877 }, 1878 }; 1879 1880 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1881 .clock = 33260, 1882 .hdisplay = 800, 1883 .hsync_start = 800 + 40, 1884 .hsync_end = 800 + 40 + 128, 1885 .htotal = 800 + 40 + 128 + 88, 1886 .vdisplay = 480, 1887 .vsync_start = 480 + 10, 1888 .vsync_end = 480 + 10 + 2, 1889 .vtotal = 480 + 10 + 2 + 33, 1890 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1891 }; 1892 1893 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1894 .modes = &dataimage_scf0700c48ggu18_mode, 1895 .num_modes = 1, 1896 .bpc = 8, 1897 .size = { 1898 .width = 152, 1899 .height = 91, 1900 }, 1901 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1902 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1903 }; 1904 1905 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1906 .pixelclock = { 45000000, 51200000, 57000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 100, 106, 113 }, 1909 .hback_porch = { 100, 106, 113 }, 1910 .hsync_len = { 100, 108, 114 }, 1911 .vactive = { 600, 600, 600 }, 1912 .vfront_porch = { 8, 11, 15 }, 1913 .vback_porch = { 8, 11, 15 }, 1914 .vsync_len = { 9, 13, 15 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916 }; 1917 1918 static const struct panel_desc dlc_dlc0700yzg_1 = { 1919 .timings = &dlc_dlc0700yzg_1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 154, 1924 .height = 86, 1925 }, 1926 .delay = { 1927 .prepare = 30, 1928 .enable = 200, 1929 .disable = 200, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1933 }; 1934 1935 static const struct display_timing dlc_dlc1010gig_timing = { 1936 .pixelclock = { 68900000, 71100000, 73400000 }, 1937 .hactive = { 1280, 1280, 1280 }, 1938 .hfront_porch = { 43, 53, 63 }, 1939 .hback_porch = { 43, 53, 63 }, 1940 .hsync_len = { 44, 54, 64 }, 1941 .vactive = { 800, 800, 800 }, 1942 .vfront_porch = { 5, 8, 11 }, 1943 .vback_porch = { 5, 8, 11 }, 1944 .vsync_len = { 5, 7, 11 }, 1945 .flags = DISPLAY_FLAGS_DE_HIGH, 1946 }; 1947 1948 static const struct panel_desc dlc_dlc1010gig = { 1949 .timings = &dlc_dlc1010gig_timing, 1950 .num_timings = 1, 1951 .bpc = 8, 1952 .size = { 1953 .width = 216, 1954 .height = 135, 1955 }, 1956 .delay = { 1957 .prepare = 60, 1958 .enable = 150, 1959 .disable = 100, 1960 .unprepare = 60, 1961 }, 1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1964 }; 1965 1966 static const struct drm_display_mode edt_et035012dm6_mode = { 1967 .clock = 6500, 1968 .hdisplay = 320, 1969 .hsync_start = 320 + 20, 1970 .hsync_end = 320 + 20 + 30, 1971 .htotal = 320 + 20 + 68, 1972 .vdisplay = 240, 1973 .vsync_start = 240 + 4, 1974 .vsync_end = 240 + 4 + 4, 1975 .vtotal = 240 + 4 + 4 + 14, 1976 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1977 }; 1978 1979 static const struct panel_desc edt_et035012dm6 = { 1980 .modes = &edt_et035012dm6_mode, 1981 .num_modes = 1, 1982 .bpc = 8, 1983 .size = { 1984 .width = 70, 1985 .height = 52, 1986 }, 1987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1988 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1989 }; 1990 1991 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1992 .clock = 6520, 1993 .hdisplay = 320, 1994 .hsync_start = 320 + 20, 1995 .hsync_end = 320 + 20 + 68, 1996 .htotal = 320 + 20 + 68, 1997 .vdisplay = 240, 1998 .vsync_start = 240 + 4, 1999 .vsync_end = 240 + 4 + 18, 2000 .vtotal = 240 + 4 + 18, 2001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2002 }; 2003 2004 static const struct panel_desc edt_etm0350g0dh6 = { 2005 .modes = &edt_etm0350g0dh6_mode, 2006 .num_modes = 1, 2007 .bpc = 6, 2008 .size = { 2009 .width = 70, 2010 .height = 53, 2011 }, 2012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2014 .connector_type = DRM_MODE_CONNECTOR_DPI, 2015 }; 2016 2017 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2018 .clock = 10870, 2019 .hdisplay = 480, 2020 .hsync_start = 480 + 8, 2021 .hsync_end = 480 + 8 + 4, 2022 .htotal = 480 + 8 + 4 + 41, 2023 2024 /* 2025 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2026 * fb_align 2027 */ 2028 2029 .vdisplay = 288, 2030 .vsync_start = 288 + 2, 2031 .vsync_end = 288 + 2 + 4, 2032 .vtotal = 288 + 2 + 4 + 10, 2033 }; 2034 2035 static const struct panel_desc edt_etm043080dh6gp = { 2036 .modes = &edt_etm043080dh6gp_mode, 2037 .num_modes = 1, 2038 .bpc = 8, 2039 .size = { 2040 .width = 100, 2041 .height = 65, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2044 .connector_type = DRM_MODE_CONNECTOR_DPI, 2045 }; 2046 2047 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2048 .clock = 9000, 2049 .hdisplay = 480, 2050 .hsync_start = 480 + 2, 2051 .hsync_end = 480 + 2 + 41, 2052 .htotal = 480 + 2 + 41 + 2, 2053 .vdisplay = 272, 2054 .vsync_start = 272 + 2, 2055 .vsync_end = 272 + 2 + 10, 2056 .vtotal = 272 + 2 + 10 + 2, 2057 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2058 }; 2059 2060 static const struct panel_desc edt_etm0430g0dh6 = { 2061 .modes = &edt_etm0430g0dh6_mode, 2062 .num_modes = 1, 2063 .bpc = 6, 2064 .size = { 2065 .width = 95, 2066 .height = 54, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2070 .connector_type = DRM_MODE_CONNECTOR_DPI, 2071 }; 2072 2073 static const struct drm_display_mode edt_et057090dhu_mode = { 2074 .clock = 25175, 2075 .hdisplay = 640, 2076 .hsync_start = 640 + 16, 2077 .hsync_end = 640 + 16 + 30, 2078 .htotal = 640 + 16 + 30 + 114, 2079 .vdisplay = 480, 2080 .vsync_start = 480 + 10, 2081 .vsync_end = 480 + 10 + 3, 2082 .vtotal = 480 + 10 + 3 + 32, 2083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2084 }; 2085 2086 static const struct panel_desc edt_et057090dhu = { 2087 .modes = &edt_et057090dhu_mode, 2088 .num_modes = 1, 2089 .bpc = 6, 2090 .size = { 2091 .width = 115, 2092 .height = 86, 2093 }, 2094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2096 .connector_type = DRM_MODE_CONNECTOR_DPI, 2097 }; 2098 2099 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2100 .clock = 33260, 2101 .hdisplay = 800, 2102 .hsync_start = 800 + 40, 2103 .hsync_end = 800 + 40 + 128, 2104 .htotal = 800 + 40 + 128 + 88, 2105 .vdisplay = 480, 2106 .vsync_start = 480 + 10, 2107 .vsync_end = 480 + 10 + 2, 2108 .vtotal = 480 + 10 + 2 + 33, 2109 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2110 }; 2111 2112 static const struct panel_desc edt_etm0700g0dh6 = { 2113 .modes = &edt_etm0700g0dh6_mode, 2114 .num_modes = 1, 2115 .bpc = 6, 2116 .size = { 2117 .width = 152, 2118 .height = 91, 2119 }, 2120 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2121 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2122 .connector_type = DRM_MODE_CONNECTOR_DPI, 2123 }; 2124 2125 static const struct panel_desc edt_etm0700g0bdh6 = { 2126 .modes = &edt_etm0700g0dh6_mode, 2127 .num_modes = 1, 2128 .bpc = 6, 2129 .size = { 2130 .width = 152, 2131 .height = 91, 2132 }, 2133 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2134 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2135 .connector_type = DRM_MODE_CONNECTOR_DPI, 2136 }; 2137 2138 static const struct display_timing edt_etml0700y5dha_timing = { 2139 .pixelclock = { 40800000, 51200000, 67200000 }, 2140 .hactive = { 1024, 1024, 1024 }, 2141 .hfront_porch = { 30, 106, 125 }, 2142 .hback_porch = { 30, 106, 125 }, 2143 .hsync_len = { 30, 108, 126 }, 2144 .vactive = { 600, 600, 600 }, 2145 .vfront_porch = { 3, 12, 67}, 2146 .vback_porch = { 3, 12, 67 }, 2147 .vsync_len = { 4, 11, 66 }, 2148 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2149 DISPLAY_FLAGS_DE_HIGH, 2150 }; 2151 2152 static const struct panel_desc edt_etml0700y5dha = { 2153 .timings = &edt_etml0700y5dha_timing, 2154 .num_timings = 1, 2155 .bpc = 8, 2156 .size = { 2157 .width = 155, 2158 .height = 86, 2159 }, 2160 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2161 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2162 }; 2163 2164 static const struct display_timing edt_etml1010g3dra_timing = { 2165 .pixelclock = { 66300000, 72400000, 78900000 }, 2166 .hactive = { 1280, 1280, 1280 }, 2167 .hfront_porch = { 12, 72, 132 }, 2168 .hback_porch = { 86, 86, 86 }, 2169 .hsync_len = { 2, 2, 2 }, 2170 .vactive = { 800, 800, 800 }, 2171 .vfront_porch = { 1, 15, 49 }, 2172 .vback_porch = { 21, 21, 21 }, 2173 .vsync_len = { 2, 2, 2 }, 2174 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2175 DISPLAY_FLAGS_DE_HIGH, 2176 }; 2177 2178 static const struct panel_desc edt_etml1010g3dra = { 2179 .timings = &edt_etml1010g3dra_timing, 2180 .num_timings = 1, 2181 .bpc = 8, 2182 .size = { 2183 .width = 216, 2184 .height = 135, 2185 }, 2186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2187 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2189 }; 2190 2191 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2192 .clock = 25175, 2193 .hdisplay = 640, 2194 .hsync_start = 640, 2195 .hsync_end = 640 + 16, 2196 .htotal = 640 + 16 + 30 + 114, 2197 .vdisplay = 480, 2198 .vsync_start = 480 + 10, 2199 .vsync_end = 480 + 10 + 3, 2200 .vtotal = 480 + 10 + 3 + 35, 2201 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2202 }; 2203 2204 static const struct panel_desc edt_etmv570g2dhu = { 2205 .modes = &edt_etmv570g2dhu_mode, 2206 .num_modes = 1, 2207 .bpc = 6, 2208 .size = { 2209 .width = 115, 2210 .height = 86, 2211 }, 2212 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2213 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2214 .connector_type = DRM_MODE_CONNECTOR_DPI, 2215 }; 2216 2217 static const struct display_timing eink_vb3300_kca_timing = { 2218 .pixelclock = { 40000000, 40000000, 40000000 }, 2219 .hactive = { 334, 334, 334 }, 2220 .hfront_porch = { 1, 1, 1 }, 2221 .hback_porch = { 1, 1, 1 }, 2222 .hsync_len = { 1, 1, 1 }, 2223 .vactive = { 1405, 1405, 1405 }, 2224 .vfront_porch = { 1, 1, 1 }, 2225 .vback_porch = { 1, 1, 1 }, 2226 .vsync_len = { 1, 1, 1 }, 2227 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2228 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2229 }; 2230 2231 static const struct panel_desc eink_vb3300_kca = { 2232 .timings = &eink_vb3300_kca_timing, 2233 .num_timings = 1, 2234 .bpc = 6, 2235 .size = { 2236 .width = 157, 2237 .height = 209, 2238 }, 2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2240 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2241 .connector_type = DRM_MODE_CONNECTOR_DPI, 2242 }; 2243 2244 static const struct display_timing evervision_vgg644804_timing = { 2245 .pixelclock = { 25175000, 25175000, 25175000 }, 2246 .hactive = { 640, 640, 640 }, 2247 .hfront_porch = { 16, 16, 16 }, 2248 .hback_porch = { 82, 114, 170 }, 2249 .hsync_len = { 5, 30, 30 }, 2250 .vactive = { 480, 480, 480 }, 2251 .vfront_porch = { 10, 10, 10 }, 2252 .vback_porch = { 30, 32, 34 }, 2253 .vsync_len = { 1, 3, 5 }, 2254 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2255 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2256 DISPLAY_FLAGS_SYNC_POSEDGE, 2257 }; 2258 2259 static const struct panel_desc evervision_vgg644804 = { 2260 .timings = &evervision_vgg644804_timing, 2261 .num_timings = 1, 2262 .bpc = 6, 2263 .size = { 2264 .width = 115, 2265 .height = 86, 2266 }, 2267 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2268 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2269 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2270 }; 2271 2272 static const struct display_timing evervision_vgg804821_timing = { 2273 .pixelclock = { 27600000, 33300000, 50000000 }, 2274 .hactive = { 800, 800, 800 }, 2275 .hfront_porch = { 40, 66, 70 }, 2276 .hback_porch = { 40, 67, 70 }, 2277 .hsync_len = { 40, 67, 70 }, 2278 .vactive = { 480, 480, 480 }, 2279 .vfront_porch = { 6, 10, 10 }, 2280 .vback_porch = { 7, 11, 11 }, 2281 .vsync_len = { 7, 11, 11 }, 2282 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2283 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2284 DISPLAY_FLAGS_SYNC_NEGEDGE, 2285 }; 2286 2287 static const struct panel_desc evervision_vgg804821 = { 2288 .timings = &evervision_vgg804821_timing, 2289 .num_timings = 1, 2290 .bpc = 8, 2291 .size = { 2292 .width = 108, 2293 .height = 64, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2296 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2297 }; 2298 2299 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2300 .clock = 32260, 2301 .hdisplay = 800, 2302 .hsync_start = 800 + 168, 2303 .hsync_end = 800 + 168 + 64, 2304 .htotal = 800 + 168 + 64 + 88, 2305 .vdisplay = 480, 2306 .vsync_start = 480 + 37, 2307 .vsync_end = 480 + 37 + 2, 2308 .vtotal = 480 + 37 + 2 + 8, 2309 }; 2310 2311 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2312 .modes = &foxlink_fl500wvr00_a0t_mode, 2313 .num_modes = 1, 2314 .bpc = 8, 2315 .size = { 2316 .width = 108, 2317 .height = 65, 2318 }, 2319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2320 }; 2321 2322 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2323 { /* 60 Hz */ 2324 .clock = 6000, 2325 .hdisplay = 320, 2326 .hsync_start = 320 + 44, 2327 .hsync_end = 320 + 44 + 16, 2328 .htotal = 320 + 44 + 16 + 20, 2329 .vdisplay = 240, 2330 .vsync_start = 240 + 2, 2331 .vsync_end = 240 + 2 + 6, 2332 .vtotal = 240 + 2 + 6 + 2, 2333 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2334 }, 2335 { /* 50 Hz */ 2336 .clock = 5400, 2337 .hdisplay = 320, 2338 .hsync_start = 320 + 56, 2339 .hsync_end = 320 + 56 + 16, 2340 .htotal = 320 + 56 + 16 + 40, 2341 .vdisplay = 240, 2342 .vsync_start = 240 + 2, 2343 .vsync_end = 240 + 2 + 6, 2344 .vtotal = 240 + 2 + 6 + 2, 2345 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2346 }, 2347 }; 2348 2349 static const struct panel_desc frida_frd350h54004 = { 2350 .modes = frida_frd350h54004_modes, 2351 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2352 .bpc = 8, 2353 .size = { 2354 .width = 77, 2355 .height = 64, 2356 }, 2357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2359 .connector_type = DRM_MODE_CONNECTOR_DPI, 2360 }; 2361 2362 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2363 .clock = 67185, 2364 .hdisplay = 800, 2365 .hsync_start = 800 + 20, 2366 .hsync_end = 800 + 20 + 24, 2367 .htotal = 800 + 20 + 24 + 20, 2368 .vdisplay = 1280, 2369 .vsync_start = 1280 + 4, 2370 .vsync_end = 1280 + 4 + 8, 2371 .vtotal = 1280 + 4 + 8 + 4, 2372 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2373 }; 2374 2375 static const struct panel_desc friendlyarm_hd702e = { 2376 .modes = &friendlyarm_hd702e_mode, 2377 .num_modes = 1, 2378 .size = { 2379 .width = 94, 2380 .height = 151, 2381 }, 2382 }; 2383 2384 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2385 .clock = 9000, 2386 .hdisplay = 480, 2387 .hsync_start = 480 + 5, 2388 .hsync_end = 480 + 5 + 1, 2389 .htotal = 480 + 5 + 1 + 40, 2390 .vdisplay = 272, 2391 .vsync_start = 272 + 8, 2392 .vsync_end = 272 + 8 + 1, 2393 .vtotal = 272 + 8 + 1 + 8, 2394 }; 2395 2396 static const struct panel_desc giantplus_gpg482739qs5 = { 2397 .modes = &giantplus_gpg482739qs5_mode, 2398 .num_modes = 1, 2399 .bpc = 8, 2400 .size = { 2401 .width = 95, 2402 .height = 54, 2403 }, 2404 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2405 }; 2406 2407 static const struct display_timing giantplus_gpm940b0_timing = { 2408 .pixelclock = { 13500000, 27000000, 27500000 }, 2409 .hactive = { 320, 320, 320 }, 2410 .hfront_porch = { 14, 686, 718 }, 2411 .hback_porch = { 50, 70, 255 }, 2412 .hsync_len = { 1, 1, 1 }, 2413 .vactive = { 240, 240, 240 }, 2414 .vfront_porch = { 1, 1, 179 }, 2415 .vback_porch = { 1, 21, 31 }, 2416 .vsync_len = { 1, 1, 6 }, 2417 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2418 }; 2419 2420 static const struct panel_desc giantplus_gpm940b0 = { 2421 .timings = &giantplus_gpm940b0_timing, 2422 .num_timings = 1, 2423 .bpc = 8, 2424 .size = { 2425 .width = 60, 2426 .height = 45, 2427 }, 2428 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2429 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2430 }; 2431 2432 static const struct display_timing hannstar_hsd070pww1_timing = { 2433 .pixelclock = { 64300000, 71100000, 82000000 }, 2434 .hactive = { 1280, 1280, 1280 }, 2435 .hfront_porch = { 1, 1, 10 }, 2436 .hback_porch = { 1, 1, 10 }, 2437 /* 2438 * According to the data sheet, the minimum horizontal blanking interval 2439 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2440 * minimum working horizontal blanking interval to be 60 clocks. 2441 */ 2442 .hsync_len = { 58, 158, 661 }, 2443 .vactive = { 800, 800, 800 }, 2444 .vfront_porch = { 1, 1, 10 }, 2445 .vback_porch = { 1, 1, 10 }, 2446 .vsync_len = { 1, 21, 203 }, 2447 .flags = DISPLAY_FLAGS_DE_HIGH, 2448 }; 2449 2450 static const struct panel_desc hannstar_hsd070pww1 = { 2451 .timings = &hannstar_hsd070pww1_timing, 2452 .num_timings = 1, 2453 .bpc = 6, 2454 .size = { 2455 .width = 151, 2456 .height = 94, 2457 }, 2458 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2459 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2460 }; 2461 2462 static const struct display_timing hannstar_hsd100pxn1_timing = { 2463 .pixelclock = { 55000000, 65000000, 75000000 }, 2464 .hactive = { 1024, 1024, 1024 }, 2465 .hfront_porch = { 40, 40, 40 }, 2466 .hback_porch = { 220, 220, 220 }, 2467 .hsync_len = { 20, 60, 100 }, 2468 .vactive = { 768, 768, 768 }, 2469 .vfront_porch = { 7, 7, 7 }, 2470 .vback_porch = { 21, 21, 21 }, 2471 .vsync_len = { 10, 10, 10 }, 2472 .flags = DISPLAY_FLAGS_DE_HIGH, 2473 }; 2474 2475 static const struct panel_desc hannstar_hsd100pxn1 = { 2476 .timings = &hannstar_hsd100pxn1_timing, 2477 .num_timings = 1, 2478 .bpc = 6, 2479 .size = { 2480 .width = 203, 2481 .height = 152, 2482 }, 2483 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2484 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2485 }; 2486 2487 static const struct display_timing hannstar_hsd101pww2_timing = { 2488 .pixelclock = { 64300000, 71100000, 82000000 }, 2489 .hactive = { 1280, 1280, 1280 }, 2490 .hfront_porch = { 1, 1, 10 }, 2491 .hback_porch = { 1, 1, 10 }, 2492 .hsync_len = { 58, 158, 661 }, 2493 .vactive = { 800, 800, 800 }, 2494 .vfront_porch = { 1, 1, 10 }, 2495 .vback_porch = { 1, 1, 10 }, 2496 .vsync_len = { 1, 21, 203 }, 2497 .flags = DISPLAY_FLAGS_DE_HIGH, 2498 }; 2499 2500 static const struct panel_desc hannstar_hsd101pww2 = { 2501 .timings = &hannstar_hsd101pww2_timing, 2502 .num_timings = 1, 2503 .bpc = 8, 2504 .size = { 2505 .width = 217, 2506 .height = 136, 2507 }, 2508 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2510 }; 2511 2512 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2513 .clock = 33333, 2514 .hdisplay = 800, 2515 .hsync_start = 800 + 85, 2516 .hsync_end = 800 + 85 + 86, 2517 .htotal = 800 + 85 + 86 + 85, 2518 .vdisplay = 480, 2519 .vsync_start = 480 + 16, 2520 .vsync_end = 480 + 16 + 13, 2521 .vtotal = 480 + 16 + 13 + 16, 2522 }; 2523 2524 static const struct panel_desc hitachi_tx23d38vm0caa = { 2525 .modes = &hitachi_tx23d38vm0caa_mode, 2526 .num_modes = 1, 2527 .bpc = 6, 2528 .size = { 2529 .width = 195, 2530 .height = 117, 2531 }, 2532 .delay = { 2533 .enable = 160, 2534 .disable = 160, 2535 }, 2536 }; 2537 2538 static const struct drm_display_mode innolux_at043tn24_mode = { 2539 .clock = 9000, 2540 .hdisplay = 480, 2541 .hsync_start = 480 + 2, 2542 .hsync_end = 480 + 2 + 41, 2543 .htotal = 480 + 2 + 41 + 2, 2544 .vdisplay = 272, 2545 .vsync_start = 272 + 2, 2546 .vsync_end = 272 + 2 + 10, 2547 .vtotal = 272 + 2 + 10 + 2, 2548 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2549 }; 2550 2551 static const struct panel_desc innolux_at043tn24 = { 2552 .modes = &innolux_at043tn24_mode, 2553 .num_modes = 1, 2554 .bpc = 8, 2555 .size = { 2556 .width = 95, 2557 .height = 54, 2558 }, 2559 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2560 .connector_type = DRM_MODE_CONNECTOR_DPI, 2561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2562 }; 2563 2564 static const struct drm_display_mode innolux_at070tn92_mode = { 2565 .clock = 33333, 2566 .hdisplay = 800, 2567 .hsync_start = 800 + 210, 2568 .hsync_end = 800 + 210 + 20, 2569 .htotal = 800 + 210 + 20 + 46, 2570 .vdisplay = 480, 2571 .vsync_start = 480 + 22, 2572 .vsync_end = 480 + 22 + 10, 2573 .vtotal = 480 + 22 + 23 + 10, 2574 }; 2575 2576 static const struct panel_desc innolux_at070tn92 = { 2577 .modes = &innolux_at070tn92_mode, 2578 .num_modes = 1, 2579 .size = { 2580 .width = 154, 2581 .height = 86, 2582 }, 2583 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2584 }; 2585 2586 static const struct display_timing innolux_g070ace_l01_timing = { 2587 .pixelclock = { 25200000, 35000000, 35700000 }, 2588 .hactive = { 800, 800, 800 }, 2589 .hfront_porch = { 30, 32, 87 }, 2590 .hback_porch = { 30, 32, 87 }, 2591 .hsync_len = { 1, 1, 1 }, 2592 .vactive = { 480, 480, 480 }, 2593 .vfront_porch = { 3, 3, 3 }, 2594 .vback_porch = { 13, 13, 13 }, 2595 .vsync_len = { 1, 1, 4 }, 2596 .flags = DISPLAY_FLAGS_DE_HIGH, 2597 }; 2598 2599 static const struct panel_desc innolux_g070ace_l01 = { 2600 .timings = &innolux_g070ace_l01_timing, 2601 .num_timings = 1, 2602 .bpc = 8, 2603 .size = { 2604 .width = 152, 2605 .height = 91, 2606 }, 2607 .delay = { 2608 .prepare = 10, 2609 .enable = 50, 2610 .disable = 50, 2611 .unprepare = 500, 2612 }, 2613 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2614 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2615 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2616 }; 2617 2618 static const struct display_timing innolux_g070y2_l01_timing = { 2619 .pixelclock = { 28000000, 29500000, 32000000 }, 2620 .hactive = { 800, 800, 800 }, 2621 .hfront_porch = { 61, 91, 141 }, 2622 .hback_porch = { 60, 90, 140 }, 2623 .hsync_len = { 12, 12, 12 }, 2624 .vactive = { 480, 480, 480 }, 2625 .vfront_porch = { 4, 9, 30 }, 2626 .vback_porch = { 4, 8, 28 }, 2627 .vsync_len = { 2, 2, 2 }, 2628 .flags = DISPLAY_FLAGS_DE_HIGH, 2629 }; 2630 2631 static const struct panel_desc innolux_g070y2_l01 = { 2632 .timings = &innolux_g070y2_l01_timing, 2633 .num_timings = 1, 2634 .bpc = 8, 2635 .size = { 2636 .width = 152, 2637 .height = 91, 2638 }, 2639 .delay = { 2640 .prepare = 10, 2641 .enable = 100, 2642 .disable = 100, 2643 .unprepare = 800, 2644 }, 2645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2646 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2647 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2648 }; 2649 2650 static const struct display_timing innolux_g070ace_lh3_timing = { 2651 .pixelclock = { 25200000, 25400000, 35700000 }, 2652 .hactive = { 800, 800, 800 }, 2653 .hfront_porch = { 30, 32, 87 }, 2654 .hback_porch = { 29, 31, 86 }, 2655 .hsync_len = { 1, 1, 1 }, 2656 .vactive = { 480, 480, 480 }, 2657 .vfront_porch = { 4, 5, 65 }, 2658 .vback_porch = { 3, 4, 65 }, 2659 .vsync_len = { 1, 1, 1 }, 2660 .flags = DISPLAY_FLAGS_DE_HIGH, 2661 }; 2662 2663 static const struct panel_desc innolux_g070ace_lh3 = { 2664 .timings = &innolux_g070ace_lh3_timing, 2665 .num_timings = 1, 2666 .bpc = 8, 2667 .size = { 2668 .width = 152, 2669 .height = 91, 2670 }, 2671 .delay = { 2672 .prepare = 10, 2673 .enable = 450, 2674 .disable = 200, 2675 .unprepare = 510, 2676 }, 2677 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2678 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2679 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2680 }; 2681 2682 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2683 .clock = 33333, 2684 .hdisplay = 800, 2685 .hsync_start = 800 + 210, 2686 .hsync_end = 800 + 210 + 20, 2687 .htotal = 800 + 210 + 20 + 46, 2688 .vdisplay = 480, 2689 .vsync_start = 480 + 22, 2690 .vsync_end = 480 + 22 + 10, 2691 .vtotal = 480 + 22 + 23 + 10, 2692 }; 2693 2694 static const struct panel_desc innolux_g070y2_t02 = { 2695 .modes = &innolux_g070y2_t02_mode, 2696 .num_modes = 1, 2697 .bpc = 8, 2698 .size = { 2699 .width = 152, 2700 .height = 92, 2701 }, 2702 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2703 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2704 .connector_type = DRM_MODE_CONNECTOR_DPI, 2705 }; 2706 2707 static const struct display_timing innolux_g101ice_l01_timing = { 2708 .pixelclock = { 60400000, 71100000, 74700000 }, 2709 .hactive = { 1280, 1280, 1280 }, 2710 .hfront_porch = { 30, 60, 70 }, 2711 .hback_porch = { 30, 60, 70 }, 2712 .hsync_len = { 22, 40, 60 }, 2713 .vactive = { 800, 800, 800 }, 2714 .vfront_porch = { 3, 8, 14 }, 2715 .vback_porch = { 3, 8, 14 }, 2716 .vsync_len = { 4, 7, 12 }, 2717 .flags = DISPLAY_FLAGS_DE_HIGH, 2718 }; 2719 2720 static const struct panel_desc innolux_g101ice_l01 = { 2721 .timings = &innolux_g101ice_l01_timing, 2722 .num_timings = 1, 2723 .bpc = 8, 2724 .size = { 2725 .width = 217, 2726 .height = 135, 2727 }, 2728 .delay = { 2729 .enable = 200, 2730 .disable = 200, 2731 }, 2732 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2733 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2734 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2735 }; 2736 2737 static const struct display_timing innolux_g121i1_l01_timing = { 2738 .pixelclock = { 67450000, 71000000, 74550000 }, 2739 .hactive = { 1280, 1280, 1280 }, 2740 .hfront_porch = { 40, 80, 160 }, 2741 .hback_porch = { 39, 79, 159 }, 2742 .hsync_len = { 1, 1, 1 }, 2743 .vactive = { 800, 800, 800 }, 2744 .vfront_porch = { 5, 11, 100 }, 2745 .vback_porch = { 4, 11, 99 }, 2746 .vsync_len = { 1, 1, 1 }, 2747 }; 2748 2749 static const struct panel_desc innolux_g121i1_l01 = { 2750 .timings = &innolux_g121i1_l01_timing, 2751 .num_timings = 1, 2752 .bpc = 6, 2753 .size = { 2754 .width = 261, 2755 .height = 163, 2756 }, 2757 .delay = { 2758 .enable = 200, 2759 .disable = 20, 2760 }, 2761 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2762 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2763 }; 2764 2765 static const struct display_timing innolux_g121x1_l03_timings = { 2766 .pixelclock = { 57500000, 64900000, 74400000 }, 2767 .hactive = { 1024, 1024, 1024 }, 2768 .hfront_porch = { 90, 140, 190 }, 2769 .hback_porch = { 90, 140, 190 }, 2770 .hsync_len = { 36, 40, 60 }, 2771 .vactive = { 768, 768, 768 }, 2772 .vfront_porch = { 2, 15, 30 }, 2773 .vback_porch = { 2, 15, 30 }, 2774 .vsync_len = { 2, 8, 20 }, 2775 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2776 }; 2777 2778 static const struct panel_desc innolux_g121x1_l03 = { 2779 .timings = &innolux_g121x1_l03_timings, 2780 .num_timings = 1, 2781 .bpc = 6, 2782 .size = { 2783 .width = 246, 2784 .height = 185, 2785 }, 2786 .delay = { 2787 .enable = 200, 2788 .unprepare = 200, 2789 .disable = 400, 2790 }, 2791 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2792 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2793 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2794 }; 2795 2796 static const struct panel_desc innolux_g121xce_l01 = { 2797 .timings = &innolux_g121x1_l03_timings, 2798 .num_timings = 1, 2799 .bpc = 8, 2800 .size = { 2801 .width = 246, 2802 .height = 185, 2803 }, 2804 .delay = { 2805 .enable = 200, 2806 .unprepare = 200, 2807 .disable = 400, 2808 }, 2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2810 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2811 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2812 }; 2813 2814 static const struct display_timing innolux_g156hce_l01_timings = { 2815 .pixelclock = { 120000000, 141860000, 150000000 }, 2816 .hactive = { 1920, 1920, 1920 }, 2817 .hfront_porch = { 80, 90, 100 }, 2818 .hback_porch = { 80, 90, 100 }, 2819 .hsync_len = { 20, 30, 30 }, 2820 .vactive = { 1080, 1080, 1080 }, 2821 .vfront_porch = { 3, 10, 20 }, 2822 .vback_porch = { 3, 10, 20 }, 2823 .vsync_len = { 4, 10, 10 }, 2824 }; 2825 2826 static const struct panel_desc innolux_g156hce_l01 = { 2827 .timings = &innolux_g156hce_l01_timings, 2828 .num_timings = 1, 2829 .bpc = 8, 2830 .size = { 2831 .width = 344, 2832 .height = 194, 2833 }, 2834 .delay = { 2835 .prepare = 1, /* T1+T2 */ 2836 .enable = 450, /* T5 */ 2837 .disable = 200, /* T6 */ 2838 .unprepare = 10, /* T3+T7 */ 2839 }, 2840 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2841 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2842 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2843 }; 2844 2845 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2846 .clock = 69300, 2847 .hdisplay = 1366, 2848 .hsync_start = 1366 + 16, 2849 .hsync_end = 1366 + 16 + 34, 2850 .htotal = 1366 + 16 + 34 + 50, 2851 .vdisplay = 768, 2852 .vsync_start = 768 + 2, 2853 .vsync_end = 768 + 2 + 6, 2854 .vtotal = 768 + 2 + 6 + 12, 2855 }; 2856 2857 static const struct panel_desc innolux_n156bge_l21 = { 2858 .modes = &innolux_n156bge_l21_mode, 2859 .num_modes = 1, 2860 .bpc = 6, 2861 .size = { 2862 .width = 344, 2863 .height = 193, 2864 }, 2865 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2866 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2867 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2868 }; 2869 2870 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2871 .clock = 51501, 2872 .hdisplay = 1024, 2873 .hsync_start = 1024 + 128, 2874 .hsync_end = 1024 + 128 + 64, 2875 .htotal = 1024 + 128 + 64 + 128, 2876 .vdisplay = 600, 2877 .vsync_start = 600 + 16, 2878 .vsync_end = 600 + 16 + 4, 2879 .vtotal = 600 + 16 + 4 + 16, 2880 }; 2881 2882 static const struct panel_desc innolux_zj070na_01p = { 2883 .modes = &innolux_zj070na_01p_mode, 2884 .num_modes = 1, 2885 .bpc = 6, 2886 .size = { 2887 .width = 154, 2888 .height = 90, 2889 }, 2890 }; 2891 2892 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2893 .pixelclock = { 5580000, 5850000, 6200000 }, 2894 .hactive = { 320, 320, 320 }, 2895 .hfront_porch = { 30, 30, 30 }, 2896 .hback_porch = { 30, 30, 30 }, 2897 .hsync_len = { 1, 5, 17 }, 2898 .vactive = { 240, 240, 240 }, 2899 .vfront_porch = { 6, 6, 6 }, 2900 .vback_porch = { 5, 5, 5 }, 2901 .vsync_len = { 1, 2, 11 }, 2902 .flags = DISPLAY_FLAGS_DE_HIGH, 2903 }; 2904 2905 static const struct panel_desc koe_tx14d24vm1bpa = { 2906 .timings = &koe_tx14d24vm1bpa_timing, 2907 .num_timings = 1, 2908 .bpc = 6, 2909 .size = { 2910 .width = 115, 2911 .height = 86, 2912 }, 2913 }; 2914 2915 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2916 .pixelclock = { 151820000, 156720000, 159780000 }, 2917 .hactive = { 1920, 1920, 1920 }, 2918 .hfront_porch = { 105, 130, 142 }, 2919 .hback_porch = { 45, 70, 82 }, 2920 .hsync_len = { 30, 30, 30 }, 2921 .vactive = { 1200, 1200, 1200}, 2922 .vfront_porch = { 3, 5, 10 }, 2923 .vback_porch = { 2, 5, 10 }, 2924 .vsync_len = { 5, 5, 5 }, 2925 .flags = DISPLAY_FLAGS_DE_HIGH, 2926 }; 2927 2928 static const struct panel_desc koe_tx26d202vm0bwa = { 2929 .timings = &koe_tx26d202vm0bwa_timing, 2930 .num_timings = 1, 2931 .bpc = 8, 2932 .size = { 2933 .width = 217, 2934 .height = 136, 2935 }, 2936 .delay = { 2937 .prepare = 1000, 2938 .enable = 1000, 2939 .unprepare = 1000, 2940 .disable = 1000, 2941 }, 2942 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2943 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2944 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2945 }; 2946 2947 static const struct display_timing koe_tx31d200vm0baa_timing = { 2948 .pixelclock = { 39600000, 43200000, 48000000 }, 2949 .hactive = { 1280, 1280, 1280 }, 2950 .hfront_porch = { 16, 36, 56 }, 2951 .hback_porch = { 16, 36, 56 }, 2952 .hsync_len = { 8, 8, 8 }, 2953 .vactive = { 480, 480, 480 }, 2954 .vfront_porch = { 6, 21, 33 }, 2955 .vback_porch = { 6, 21, 33 }, 2956 .vsync_len = { 8, 8, 8 }, 2957 .flags = DISPLAY_FLAGS_DE_HIGH, 2958 }; 2959 2960 static const struct panel_desc koe_tx31d200vm0baa = { 2961 .timings = &koe_tx31d200vm0baa_timing, 2962 .num_timings = 1, 2963 .bpc = 6, 2964 .size = { 2965 .width = 292, 2966 .height = 109, 2967 }, 2968 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2969 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2970 }; 2971 2972 static const struct display_timing kyo_tcg121xglp_timing = { 2973 .pixelclock = { 52000000, 65000000, 71000000 }, 2974 .hactive = { 1024, 1024, 1024 }, 2975 .hfront_porch = { 2, 2, 2 }, 2976 .hback_porch = { 2, 2, 2 }, 2977 .hsync_len = { 86, 124, 244 }, 2978 .vactive = { 768, 768, 768 }, 2979 .vfront_porch = { 2, 2, 2 }, 2980 .vback_porch = { 2, 2, 2 }, 2981 .vsync_len = { 6, 34, 73 }, 2982 .flags = DISPLAY_FLAGS_DE_HIGH, 2983 }; 2984 2985 static const struct panel_desc kyo_tcg121xglp = { 2986 .timings = &kyo_tcg121xglp_timing, 2987 .num_timings = 1, 2988 .bpc = 8, 2989 .size = { 2990 .width = 246, 2991 .height = 184, 2992 }, 2993 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2994 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2995 }; 2996 2997 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2998 .clock = 7000, 2999 .hdisplay = 320, 3000 .hsync_start = 320 + 20, 3001 .hsync_end = 320 + 20 + 30, 3002 .htotal = 320 + 20 + 30 + 38, 3003 .vdisplay = 240, 3004 .vsync_start = 240 + 4, 3005 .vsync_end = 240 + 4 + 3, 3006 .vtotal = 240 + 4 + 3 + 15, 3007 }; 3008 3009 static const struct panel_desc lemaker_bl035_rgb_002 = { 3010 .modes = &lemaker_bl035_rgb_002_mode, 3011 .num_modes = 1, 3012 .size = { 3013 .width = 70, 3014 .height = 52, 3015 }, 3016 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3017 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3018 }; 3019 3020 static const struct display_timing lg_lb070wv8_timing = { 3021 .pixelclock = { 31950000, 33260000, 34600000 }, 3022 .hactive = { 800, 800, 800 }, 3023 .hfront_porch = { 88, 88, 88 }, 3024 .hback_porch = { 88, 88, 88 }, 3025 .hsync_len = { 80, 80, 80 }, 3026 .vactive = { 480, 480, 480 }, 3027 .vfront_porch = { 10, 10, 10 }, 3028 .vback_porch = { 10, 10, 10 }, 3029 .vsync_len = { 25, 25, 25 }, 3030 }; 3031 3032 static const struct panel_desc lg_lb070wv8 = { 3033 .timings = &lg_lb070wv8_timing, 3034 .num_timings = 1, 3035 .bpc = 8, 3036 .size = { 3037 .width = 151, 3038 .height = 91, 3039 }, 3040 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3041 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3042 }; 3043 3044 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3045 .clock = 155127, 3046 .hdisplay = 1920, 3047 .hsync_start = 1920 + 128, 3048 .hsync_end = 1920 + 128 + 20, 3049 .htotal = 1920 + 128 + 20 + 12, 3050 .vdisplay = 1200, 3051 .vsync_start = 1200 + 19, 3052 .vsync_end = 1200 + 19 + 4, 3053 .vtotal = 1200 + 19 + 4 + 20, 3054 }; 3055 3056 static const struct panel_desc lincolntech_lcd185_101ct = { 3057 .modes = &lincolntech_lcd185_101ct_mode, 3058 .bpc = 8, 3059 .num_modes = 1, 3060 .size = { 3061 .width = 217, 3062 .height = 136, 3063 }, 3064 .delay = { 3065 .prepare = 50, 3066 .disable = 50, 3067 }, 3068 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3069 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3070 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3071 }; 3072 3073 static const struct display_timing logictechno_lt161010_2nh_timing = { 3074 .pixelclock = { 26400000, 33300000, 46800000 }, 3075 .hactive = { 800, 800, 800 }, 3076 .hfront_porch = { 16, 210, 354 }, 3077 .hback_porch = { 46, 46, 46 }, 3078 .hsync_len = { 1, 20, 40 }, 3079 .vactive = { 480, 480, 480 }, 3080 .vfront_porch = { 7, 22, 147 }, 3081 .vback_porch = { 23, 23, 23 }, 3082 .vsync_len = { 1, 10, 20 }, 3083 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3084 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3085 DISPLAY_FLAGS_SYNC_POSEDGE, 3086 }; 3087 3088 static const struct panel_desc logictechno_lt161010_2nh = { 3089 .timings = &logictechno_lt161010_2nh_timing, 3090 .num_timings = 1, 3091 .bpc = 6, 3092 .size = { 3093 .width = 154, 3094 .height = 86, 3095 }, 3096 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3097 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3098 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3099 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3100 .connector_type = DRM_MODE_CONNECTOR_DPI, 3101 }; 3102 3103 static const struct display_timing logictechno_lt170410_2whc_timing = { 3104 .pixelclock = { 68900000, 71100000, 73400000 }, 3105 .hactive = { 1280, 1280, 1280 }, 3106 .hfront_porch = { 23, 60, 71 }, 3107 .hback_porch = { 23, 60, 71 }, 3108 .hsync_len = { 15, 40, 47 }, 3109 .vactive = { 800, 800, 800 }, 3110 .vfront_porch = { 5, 7, 10 }, 3111 .vback_porch = { 5, 7, 10 }, 3112 .vsync_len = { 6, 9, 12 }, 3113 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3114 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3115 DISPLAY_FLAGS_SYNC_POSEDGE, 3116 }; 3117 3118 static const struct panel_desc logictechno_lt170410_2whc = { 3119 .timings = &logictechno_lt170410_2whc_timing, 3120 .num_timings = 1, 3121 .bpc = 8, 3122 .size = { 3123 .width = 217, 3124 .height = 136, 3125 }, 3126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3127 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3128 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3129 }; 3130 3131 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3132 .clock = 33000, 3133 .hdisplay = 800, 3134 .hsync_start = 800 + 112, 3135 .hsync_end = 800 + 112 + 3, 3136 .htotal = 800 + 112 + 3 + 85, 3137 .vdisplay = 480, 3138 .vsync_start = 480 + 38, 3139 .vsync_end = 480 + 38 + 3, 3140 .vtotal = 480 + 38 + 3 + 29, 3141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3142 }; 3143 3144 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3145 .modes = &logictechno_lttd800480070_l2rt_mode, 3146 .num_modes = 1, 3147 .bpc = 8, 3148 .size = { 3149 .width = 154, 3150 .height = 86, 3151 }, 3152 .delay = { 3153 .prepare = 45, 3154 .enable = 100, 3155 .disable = 100, 3156 .unprepare = 45 3157 }, 3158 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3159 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3160 .connector_type = DRM_MODE_CONNECTOR_DPI, 3161 }; 3162 3163 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3164 .clock = 33000, 3165 .hdisplay = 800, 3166 .hsync_start = 800 + 154, 3167 .hsync_end = 800 + 154 + 3, 3168 .htotal = 800 + 154 + 3 + 43, 3169 .vdisplay = 480, 3170 .vsync_start = 480 + 47, 3171 .vsync_end = 480 + 47 + 3, 3172 .vtotal = 480 + 47 + 3 + 20, 3173 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3174 }; 3175 3176 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3177 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3178 .num_modes = 1, 3179 .bpc = 8, 3180 .size = { 3181 .width = 154, 3182 .height = 86, 3183 }, 3184 .delay = { 3185 .prepare = 45, 3186 .enable = 100, 3187 .disable = 100, 3188 .unprepare = 45 3189 }, 3190 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3191 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3192 .connector_type = DRM_MODE_CONNECTOR_DPI, 3193 }; 3194 3195 static const struct drm_display_mode logicpd_type_28_mode = { 3196 .clock = 9107, 3197 .hdisplay = 480, 3198 .hsync_start = 480 + 3, 3199 .hsync_end = 480 + 3 + 42, 3200 .htotal = 480 + 3 + 42 + 2, 3201 3202 .vdisplay = 272, 3203 .vsync_start = 272 + 2, 3204 .vsync_end = 272 + 2 + 11, 3205 .vtotal = 272 + 2 + 11 + 3, 3206 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3207 }; 3208 3209 static const struct panel_desc logicpd_type_28 = { 3210 .modes = &logicpd_type_28_mode, 3211 .num_modes = 1, 3212 .bpc = 8, 3213 .size = { 3214 .width = 105, 3215 .height = 67, 3216 }, 3217 .delay = { 3218 .prepare = 200, 3219 .enable = 200, 3220 .unprepare = 200, 3221 .disable = 200, 3222 }, 3223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3224 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3225 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3226 .connector_type = DRM_MODE_CONNECTOR_DPI, 3227 }; 3228 3229 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3230 .clock = 150275, 3231 .hdisplay = 1920, 3232 .hsync_start = 1920 + 32, 3233 .hsync_end = 1920 + 32 + 52, 3234 .htotal = 1920 + 32 + 52 + 24, 3235 .vdisplay = 1200, 3236 .vsync_start = 1200 + 24, 3237 .vsync_end = 1200 + 24 + 8, 3238 .vtotal = 1200 + 24 + 8 + 3, 3239 }; 3240 3241 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3242 .modes = µtips_mf_101hiebcaf0_c_mode, 3243 .bpc = 8, 3244 .num_modes = 1, 3245 .size = { 3246 .width = 217, 3247 .height = 136, 3248 }, 3249 .delay = { 3250 .prepare = 50, 3251 .disable = 50, 3252 }, 3253 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3254 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3255 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3256 }; 3257 3258 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3259 .clock = 93301, 3260 .hdisplay = 1920, 3261 .hsync_start = 1920 + 72, 3262 .hsync_end = 1920 + 72 + 72, 3263 .htotal = 1920 + 72 + 72 + 72, 3264 .vdisplay = 720, 3265 .vsync_start = 720 + 3, 3266 .vsync_end = 720 + 3 + 3, 3267 .vtotal = 720 + 3 + 3 + 2, 3268 }; 3269 3270 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3271 .modes = µtips_mf_103hieb0ga0_mode, 3272 .bpc = 8, 3273 .num_modes = 1, 3274 .size = { 3275 .width = 244, 3276 .height = 92, 3277 }, 3278 .delay = { 3279 .prepare = 50, 3280 .disable = 50, 3281 }, 3282 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3283 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3284 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3285 }; 3286 3287 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3288 .clock = 30400, 3289 .hdisplay = 800, 3290 .hsync_start = 800 + 0, 3291 .hsync_end = 800 + 1, 3292 .htotal = 800 + 0 + 1 + 160, 3293 .vdisplay = 480, 3294 .vsync_start = 480 + 0, 3295 .vsync_end = 480 + 48 + 1, 3296 .vtotal = 480 + 48 + 1 + 0, 3297 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3298 }; 3299 3300 static const struct panel_desc mitsubishi_aa070mc01 = { 3301 .modes = &mitsubishi_aa070mc01_mode, 3302 .num_modes = 1, 3303 .bpc = 8, 3304 .size = { 3305 .width = 152, 3306 .height = 91, 3307 }, 3308 3309 .delay = { 3310 .enable = 200, 3311 .unprepare = 200, 3312 .disable = 400, 3313 }, 3314 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3315 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3316 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3317 }; 3318 3319 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3320 .clock = 56234, 3321 .hdisplay = 1024, 3322 .hsync_start = 1024 + 24, 3323 .hsync_end = 1024 + 24 + 63, 3324 .htotal = 1024 + 24 + 63 + 1, 3325 .vdisplay = 768, 3326 .vsync_start = 768 + 3, 3327 .vsync_end = 768 + 3 + 6, 3328 .vtotal = 768 + 3 + 6 + 1, 3329 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3330 }; 3331 3332 static const struct panel_desc mitsubishi_aa084xe01 = { 3333 .modes = &mitsubishi_aa084xe01_mode, 3334 .num_modes = 1, 3335 .bpc = 8, 3336 .size = { 3337 .width = 1024, 3338 .height = 768, 3339 }, 3340 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3341 .connector_type = DRM_MODE_CONNECTOR_DPI, 3342 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3343 }; 3344 3345 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3346 .pixelclock = { 26400000, 33000000, 46800000 }, 3347 .hactive = { 800, 800, 800 }, 3348 .hfront_porch = { 16, 204, 354 }, 3349 .hback_porch = { 46, 46, 46 }, 3350 .hsync_len = { 1, 6, 40 }, 3351 .vactive = { 480, 480, 480 }, 3352 .vfront_porch = { 7, 22, 147 }, 3353 .vback_porch = { 23, 23, 23 }, 3354 .vsync_len = { 1, 3, 20 }, 3355 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3356 DISPLAY_FLAGS_DE_HIGH, 3357 }; 3358 3359 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3360 .timings = &multi_inno_mi0700a2t_30_timing, 3361 .num_timings = 1, 3362 .bpc = 6, 3363 .size = { 3364 .width = 153, 3365 .height = 92, 3366 }, 3367 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3368 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3369 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3370 }; 3371 3372 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3373 .pixelclock = { 29000000, 33000000, 38000000 }, 3374 .hactive = { 800, 800, 800 }, 3375 .hfront_porch = { 180, 210, 240 }, 3376 .hback_porch = { 16, 16, 16 }, 3377 .hsync_len = { 30, 30, 30 }, 3378 .vactive = { 480, 480, 480 }, 3379 .vfront_porch = { 12, 22, 32 }, 3380 .vback_porch = { 10, 10, 10 }, 3381 .vsync_len = { 13, 13, 13 }, 3382 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3383 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3384 DISPLAY_FLAGS_SYNC_POSEDGE, 3385 }; 3386 3387 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3388 .timings = &multi_inno_mi0700s4t_6_timing, 3389 .num_timings = 1, 3390 .bpc = 8, 3391 .size = { 3392 .width = 154, 3393 .height = 86, 3394 }, 3395 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3396 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3397 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3398 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3399 .connector_type = DRM_MODE_CONNECTOR_DPI, 3400 }; 3401 3402 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3403 .pixelclock = { 32000000, 40000000, 50000000 }, 3404 .hactive = { 800, 800, 800 }, 3405 .hfront_porch = { 16, 210, 354 }, 3406 .hback_porch = { 6, 26, 45 }, 3407 .hsync_len = { 1, 20, 40 }, 3408 .vactive = { 600, 600, 600 }, 3409 .vfront_porch = { 1, 12, 77 }, 3410 .vback_porch = { 3, 13, 22 }, 3411 .vsync_len = { 1, 10, 20 }, 3412 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3413 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3414 DISPLAY_FLAGS_SYNC_POSEDGE, 3415 }; 3416 3417 static const struct panel_desc multi_inno_mi0800ft_9 = { 3418 .timings = &multi_inno_mi0800ft_9_timing, 3419 .num_timings = 1, 3420 .bpc = 8, 3421 .size = { 3422 .width = 162, 3423 .height = 122, 3424 }, 3425 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3426 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3427 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3428 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3429 .connector_type = DRM_MODE_CONNECTOR_DPI, 3430 }; 3431 3432 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3433 .pixelclock = { 68900000, 70000000, 73400000 }, 3434 .hactive = { 1280, 1280, 1280 }, 3435 .hfront_porch = { 30, 60, 71 }, 3436 .hback_porch = { 30, 60, 71 }, 3437 .hsync_len = { 10, 10, 48 }, 3438 .vactive = { 800, 800, 800 }, 3439 .vfront_porch = { 5, 10, 10 }, 3440 .vback_porch = { 5, 10, 10 }, 3441 .vsync_len = { 5, 6, 13 }, 3442 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3443 DISPLAY_FLAGS_DE_HIGH, 3444 }; 3445 3446 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3447 .timings = &multi_inno_mi1010ait_1cp_timing, 3448 .num_timings = 1, 3449 .bpc = 8, 3450 .size = { 3451 .width = 217, 3452 .height = 136, 3453 }, 3454 .delay = { 3455 .enable = 50, 3456 .disable = 50, 3457 }, 3458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3459 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3460 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3461 }; 3462 3463 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3464 .pixelclock = { 40800000, 51200000, 67200000 }, 3465 .hactive = { 1024, 1024, 1024 }, 3466 .hfront_porch = { 30, 110, 130 }, 3467 .hback_porch = { 30, 110, 130 }, 3468 .hsync_len = { 30, 100, 116 }, 3469 .vactive = { 600, 600, 600 }, 3470 .vfront_porch = { 4, 13, 80 }, 3471 .vback_porch = { 4, 13, 80 }, 3472 .vsync_len = { 2, 9, 40 }, 3473 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3474 DISPLAY_FLAGS_DE_HIGH, 3475 }; 3476 3477 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3478 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3479 .num_timings = 1, 3480 .bpc = 6, 3481 .size = { 3482 .width = 260, 3483 .height = 162, 3484 }, 3485 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3486 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3488 }; 3489 3490 static const struct display_timing nec_nl12880bc20_05_timing = { 3491 .pixelclock = { 67000000, 71000000, 75000000 }, 3492 .hactive = { 1280, 1280, 1280 }, 3493 .hfront_porch = { 2, 30, 30 }, 3494 .hback_porch = { 6, 100, 100 }, 3495 .hsync_len = { 2, 30, 30 }, 3496 .vactive = { 800, 800, 800 }, 3497 .vfront_porch = { 5, 5, 5 }, 3498 .vback_porch = { 11, 11, 11 }, 3499 .vsync_len = { 7, 7, 7 }, 3500 }; 3501 3502 static const struct panel_desc nec_nl12880bc20_05 = { 3503 .timings = &nec_nl12880bc20_05_timing, 3504 .num_timings = 1, 3505 .bpc = 8, 3506 .size = { 3507 .width = 261, 3508 .height = 163, 3509 }, 3510 .delay = { 3511 .enable = 50, 3512 .disable = 50, 3513 }, 3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3515 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3516 }; 3517 3518 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3519 .clock = 10870, 3520 .hdisplay = 480, 3521 .hsync_start = 480 + 2, 3522 .hsync_end = 480 + 2 + 41, 3523 .htotal = 480 + 2 + 41 + 2, 3524 .vdisplay = 272, 3525 .vsync_start = 272 + 2, 3526 .vsync_end = 272 + 2 + 4, 3527 .vtotal = 272 + 2 + 4 + 2, 3528 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3529 }; 3530 3531 static const struct panel_desc nec_nl4827hc19_05b = { 3532 .modes = &nec_nl4827hc19_05b_mode, 3533 .num_modes = 1, 3534 .bpc = 8, 3535 .size = { 3536 .width = 95, 3537 .height = 54, 3538 }, 3539 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3540 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3541 }; 3542 3543 static const struct drm_display_mode netron_dy_e231732_mode = { 3544 .clock = 66000, 3545 .hdisplay = 1024, 3546 .hsync_start = 1024 + 160, 3547 .hsync_end = 1024 + 160 + 70, 3548 .htotal = 1024 + 160 + 70 + 90, 3549 .vdisplay = 600, 3550 .vsync_start = 600 + 127, 3551 .vsync_end = 600 + 127 + 20, 3552 .vtotal = 600 + 127 + 20 + 3, 3553 }; 3554 3555 static const struct panel_desc netron_dy_e231732 = { 3556 .modes = &netron_dy_e231732_mode, 3557 .num_modes = 1, 3558 .size = { 3559 .width = 154, 3560 .height = 87, 3561 }, 3562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3563 }; 3564 3565 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3566 .clock = 9000, 3567 .hdisplay = 480, 3568 .hsync_start = 480 + 2, 3569 .hsync_end = 480 + 2 + 41, 3570 .htotal = 480 + 2 + 41 + 2, 3571 .vdisplay = 272, 3572 .vsync_start = 272 + 2, 3573 .vsync_end = 272 + 2 + 10, 3574 .vtotal = 272 + 2 + 10 + 2, 3575 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3576 }; 3577 3578 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3579 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3580 .num_modes = 1, 3581 .bpc = 8, 3582 .size = { 3583 .width = 95, 3584 .height = 54, 3585 }, 3586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3588 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3589 .connector_type = DRM_MODE_CONNECTOR_DPI, 3590 }; 3591 3592 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3593 .clock = 75400, 3594 .hdisplay = 1366, 3595 .hsync_start = 1366 + 14, 3596 .hsync_end = 1366 + 14 + 56, 3597 .htotal = 1366 + 14 + 56 + 64, 3598 .vdisplay = 768, 3599 .vsync_start = 768 + 1, 3600 .vsync_end = 768 + 1 + 3, 3601 .vtotal = 768 + 1 + 3 + 22, 3602 }; 3603 3604 static const struct panel_desc nlt_nl13676bc25_03f = { 3605 .modes = &nlt_nl13676bc25_03f_mode, 3606 .num_modes = 1, 3607 .bpc = 8, 3608 .size = { 3609 .width = 363, 3610 .height = 215, 3611 }, 3612 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3613 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3614 }; 3615 3616 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3617 .pixelclock = { 130000000, 148350000, 163000000 }, 3618 .hactive = { 1920, 1920, 1920 }, 3619 .hfront_porch = { 80, 100, 100 }, 3620 .hback_porch = { 100, 120, 120 }, 3621 .hsync_len = { 50, 60, 60 }, 3622 .vactive = { 1080, 1080, 1080 }, 3623 .vfront_porch = { 12, 30, 30 }, 3624 .vback_porch = { 4, 10, 10 }, 3625 .vsync_len = { 4, 5, 5 }, 3626 }; 3627 3628 static const struct panel_desc nlt_nl192108ac18_02d = { 3629 .timings = &nlt_nl192108ac18_02d_timing, 3630 .num_timings = 1, 3631 .bpc = 8, 3632 .size = { 3633 .width = 344, 3634 .height = 194, 3635 }, 3636 .delay = { 3637 .unprepare = 500, 3638 }, 3639 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3640 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3641 }; 3642 3643 static const struct drm_display_mode nvd_9128_mode = { 3644 .clock = 29500, 3645 .hdisplay = 800, 3646 .hsync_start = 800 + 130, 3647 .hsync_end = 800 + 130 + 98, 3648 .htotal = 800 + 0 + 130 + 98, 3649 .vdisplay = 480, 3650 .vsync_start = 480 + 10, 3651 .vsync_end = 480 + 10 + 50, 3652 .vtotal = 480 + 0 + 10 + 50, 3653 }; 3654 3655 static const struct panel_desc nvd_9128 = { 3656 .modes = &nvd_9128_mode, 3657 .num_modes = 1, 3658 .bpc = 8, 3659 .size = { 3660 .width = 156, 3661 .height = 88, 3662 }, 3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3664 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3665 }; 3666 3667 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3668 .pixelclock = { 30000000, 30000000, 40000000 }, 3669 .hactive = { 800, 800, 800 }, 3670 .hfront_porch = { 40, 40, 40 }, 3671 .hback_porch = { 40, 40, 40 }, 3672 .hsync_len = { 1, 48, 48 }, 3673 .vactive = { 480, 480, 480 }, 3674 .vfront_porch = { 13, 13, 13 }, 3675 .vback_porch = { 29, 29, 29 }, 3676 .vsync_len = { 3, 3, 3 }, 3677 .flags = DISPLAY_FLAGS_DE_HIGH, 3678 }; 3679 3680 static const struct panel_desc okaya_rs800480t_7x0gp = { 3681 .timings = &okaya_rs800480t_7x0gp_timing, 3682 .num_timings = 1, 3683 .bpc = 6, 3684 .size = { 3685 .width = 154, 3686 .height = 87, 3687 }, 3688 .delay = { 3689 .prepare = 41, 3690 .enable = 50, 3691 .unprepare = 41, 3692 .disable = 50, 3693 }, 3694 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3695 }; 3696 3697 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3698 .clock = 9000, 3699 .hdisplay = 480, 3700 .hsync_start = 480 + 5, 3701 .hsync_end = 480 + 5 + 30, 3702 .htotal = 480 + 5 + 30 + 10, 3703 .vdisplay = 272, 3704 .vsync_start = 272 + 8, 3705 .vsync_end = 272 + 8 + 5, 3706 .vtotal = 272 + 8 + 5 + 3, 3707 }; 3708 3709 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3710 .modes = &olimex_lcd_olinuxino_43ts_mode, 3711 .num_modes = 1, 3712 .size = { 3713 .width = 95, 3714 .height = 54, 3715 }, 3716 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3717 }; 3718 3719 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3720 .clock = 33300, 3721 .hdisplay = 800, 3722 .hsync_start = 800 + 210, 3723 .hsync_end = 800 + 210 + 20, 3724 .htotal = 800 + 210 + 20 + 26, 3725 .vdisplay = 480, 3726 .vsync_start = 480 + 22, 3727 .vsync_end = 480 + 22 + 10, 3728 .vtotal = 480 + 22 + 10 + 13, 3729 }; 3730 3731 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3732 .modes = &olimex_lcd_olinuxino_5cts_mode, 3733 .num_modes = 1, 3734 .size = { 3735 .width = 154, 3736 .height = 86, 3737 }, 3738 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3739 }; 3740 3741 3742 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3743 .pixelclock = { 30000000, 30000000, 50000000 }, 3744 .hactive = { 800, 800, 800 }, 3745 .hfront_porch = { 1, 40, 255 }, 3746 .hback_porch = { 1, 40, 87 }, 3747 .hsync_len = { 1, 48, 87 }, 3748 .vactive = { 480, 480, 480 }, 3749 .vfront_porch = { 1, 13, 255 }, 3750 .vback_porch = { 1, 29, 29 }, 3751 .vsync_len = { 3, 3, 31 }, 3752 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3753 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3754 }; 3755 3756 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3757 .timings = &ontat_kd50g21_40nt_a1_timing, 3758 .num_timings = 1, 3759 .bpc = 8, 3760 .size = { 3761 .width = 108, 3762 .height = 65, 3763 }, 3764 .delay = { 3765 .prepare = 147, /* 5 VSDs */ 3766 .enable = 147, /* 5 VSDs */ 3767 .disable = 88, /* 3 VSDs */ 3768 .unprepare = 117, /* 4 VSDs */ 3769 }, 3770 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3771 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3772 .connector_type = DRM_MODE_CONNECTOR_DPI, 3773 }; 3774 3775 /* 3776 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3777 * pixel clocks, but this is the timing that was being used in the Adafruit 3778 * installation instructions. 3779 */ 3780 static const struct drm_display_mode ontat_yx700wv03_mode = { 3781 .clock = 29500, 3782 .hdisplay = 800, 3783 .hsync_start = 824, 3784 .hsync_end = 896, 3785 .htotal = 992, 3786 .vdisplay = 480, 3787 .vsync_start = 483, 3788 .vsync_end = 493, 3789 .vtotal = 500, 3790 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3791 }; 3792 3793 /* 3794 * Specification at: 3795 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3796 */ 3797 static const struct panel_desc ontat_yx700wv03 = { 3798 .modes = &ontat_yx700wv03_mode, 3799 .num_modes = 1, 3800 .bpc = 8, 3801 .size = { 3802 .width = 154, 3803 .height = 83, 3804 }, 3805 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3806 }; 3807 3808 static const struct drm_display_mode ortustech_com37h3m_mode = { 3809 .clock = 22230, 3810 .hdisplay = 480, 3811 .hsync_start = 480 + 40, 3812 .hsync_end = 480 + 40 + 10, 3813 .htotal = 480 + 40 + 10 + 40, 3814 .vdisplay = 640, 3815 .vsync_start = 640 + 4, 3816 .vsync_end = 640 + 4 + 2, 3817 .vtotal = 640 + 4 + 2 + 4, 3818 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3819 }; 3820 3821 static const struct panel_desc ortustech_com37h3m = { 3822 .modes = &ortustech_com37h3m_mode, 3823 .num_modes = 1, 3824 .bpc = 8, 3825 .size = { 3826 .width = 56, /* 56.16mm */ 3827 .height = 75, /* 74.88mm */ 3828 }, 3829 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3830 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3831 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3832 }; 3833 3834 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3835 .clock = 25000, 3836 .hdisplay = 480, 3837 .hsync_start = 480 + 10, 3838 .hsync_end = 480 + 10 + 10, 3839 .htotal = 480 + 10 + 10 + 15, 3840 .vdisplay = 800, 3841 .vsync_start = 800 + 3, 3842 .vsync_end = 800 + 3 + 3, 3843 .vtotal = 800 + 3 + 3 + 3, 3844 }; 3845 3846 static const struct panel_desc ortustech_com43h4m85ulc = { 3847 .modes = &ortustech_com43h4m85ulc_mode, 3848 .num_modes = 1, 3849 .bpc = 6, 3850 .size = { 3851 .width = 56, 3852 .height = 93, 3853 }, 3854 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3855 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3856 .connector_type = DRM_MODE_CONNECTOR_DPI, 3857 }; 3858 3859 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3860 .clock = 33000, 3861 .hdisplay = 800, 3862 .hsync_start = 800 + 210, 3863 .hsync_end = 800 + 210 + 30, 3864 .htotal = 800 + 210 + 30 + 16, 3865 .vdisplay = 480, 3866 .vsync_start = 480 + 22, 3867 .vsync_end = 480 + 22 + 13, 3868 .vtotal = 480 + 22 + 13 + 10, 3869 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3870 }; 3871 3872 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3873 .modes = &osddisplays_osd070t1718_19ts_mode, 3874 .num_modes = 1, 3875 .bpc = 8, 3876 .size = { 3877 .width = 152, 3878 .height = 91, 3879 }, 3880 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3881 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3882 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3883 .connector_type = DRM_MODE_CONNECTOR_DPI, 3884 }; 3885 3886 static const struct drm_display_mode pda_91_00156_a0_mode = { 3887 .clock = 33300, 3888 .hdisplay = 800, 3889 .hsync_start = 800 + 1, 3890 .hsync_end = 800 + 1 + 64, 3891 .htotal = 800 + 1 + 64 + 64, 3892 .vdisplay = 480, 3893 .vsync_start = 480 + 1, 3894 .vsync_end = 480 + 1 + 23, 3895 .vtotal = 480 + 1 + 23 + 22, 3896 }; 3897 3898 static const struct panel_desc pda_91_00156_a0 = { 3899 .modes = &pda_91_00156_a0_mode, 3900 .num_modes = 1, 3901 .size = { 3902 .width = 152, 3903 .height = 91, 3904 }, 3905 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3906 }; 3907 3908 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3909 .clock = 71150, 3910 .hdisplay = 1280, 3911 .hsync_start = 1280 + 48, 3912 .hsync_end = 1280 + 48 + 32, 3913 .htotal = 1280 + 48 + 32 + 80, 3914 .vdisplay = 800, 3915 .vsync_start = 800 + 9, 3916 .vsync_end = 800 + 9 + 8, 3917 .vtotal = 800 + 9 + 8 + 6, 3918 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3919 }; 3920 3921 static const struct panel_desc powertip_ph128800t004_zza01 = { 3922 .modes = &powertip_ph128800t004_zza01_mode, 3923 .num_modes = 1, 3924 .bpc = 8, 3925 .size = { 3926 .width = 216, 3927 .height = 135, 3928 }, 3929 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3930 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3931 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3932 }; 3933 3934 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3935 .clock = 66500, 3936 .hdisplay = 1280, 3937 .hsync_start = 1280 + 12, 3938 .hsync_end = 1280 + 12 + 20, 3939 .htotal = 1280 + 12 + 20 + 56, 3940 .vdisplay = 800, 3941 .vsync_start = 800 + 1, 3942 .vsync_end = 800 + 1 + 3, 3943 .vtotal = 800 + 1 + 3 + 20, 3944 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3945 }; 3946 3947 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3948 .modes = &powertip_ph128800t006_zhc01_mode, 3949 .num_modes = 1, 3950 .bpc = 8, 3951 .size = { 3952 .width = 216, 3953 .height = 135, 3954 }, 3955 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3956 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3957 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3958 }; 3959 3960 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3961 .clock = 24750, 3962 .hdisplay = 800, 3963 .hsync_start = 800 + 54, 3964 .hsync_end = 800 + 54 + 2, 3965 .htotal = 800 + 54 + 2 + 44, 3966 .vdisplay = 480, 3967 .vsync_start = 480 + 49, 3968 .vsync_end = 480 + 49 + 2, 3969 .vtotal = 480 + 49 + 2 + 22, 3970 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3971 }; 3972 3973 static const struct panel_desc powertip_ph800480t013_idf02 = { 3974 .modes = &powertip_ph800480t013_idf02_mode, 3975 .num_modes = 1, 3976 .bpc = 8, 3977 .size = { 3978 .width = 152, 3979 .height = 91, 3980 }, 3981 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3982 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3983 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3984 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3985 .connector_type = DRM_MODE_CONNECTOR_DPI, 3986 }; 3987 3988 static const struct drm_display_mode primeview_pm070wl4_mode = { 3989 .clock = 32000, 3990 .hdisplay = 800, 3991 .hsync_start = 800 + 42, 3992 .hsync_end = 800 + 42 + 128, 3993 .htotal = 800 + 42 + 128 + 86, 3994 .vdisplay = 480, 3995 .vsync_start = 480 + 10, 3996 .vsync_end = 480 + 10 + 2, 3997 .vtotal = 480 + 10 + 2 + 33, 3998 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3999 }; 4000 4001 static const struct panel_desc primeview_pm070wl4 = { 4002 .modes = &primeview_pm070wl4_mode, 4003 .num_modes = 1, 4004 .bpc = 6, 4005 .size = { 4006 .width = 152, 4007 .height = 91, 4008 }, 4009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4010 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4011 .connector_type = DRM_MODE_CONNECTOR_DPI, 4012 }; 4013 4014 static const struct drm_display_mode qd43003c0_40_mode = { 4015 .clock = 9000, 4016 .hdisplay = 480, 4017 .hsync_start = 480 + 8, 4018 .hsync_end = 480 + 8 + 4, 4019 .htotal = 480 + 8 + 4 + 39, 4020 .vdisplay = 272, 4021 .vsync_start = 272 + 4, 4022 .vsync_end = 272 + 4 + 10, 4023 .vtotal = 272 + 4 + 10 + 2, 4024 }; 4025 4026 static const struct panel_desc qd43003c0_40 = { 4027 .modes = &qd43003c0_40_mode, 4028 .num_modes = 1, 4029 .bpc = 8, 4030 .size = { 4031 .width = 95, 4032 .height = 53, 4033 }, 4034 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4035 }; 4036 4037 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4038 { /* 60 Hz */ 4039 .clock = 10800, 4040 .hdisplay = 480, 4041 .hsync_start = 480 + 77, 4042 .hsync_end = 480 + 77 + 41, 4043 .htotal = 480 + 77 + 41 + 2, 4044 .vdisplay = 272, 4045 .vsync_start = 272 + 16, 4046 .vsync_end = 272 + 16 + 10, 4047 .vtotal = 272 + 16 + 10 + 2, 4048 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4049 }, 4050 { /* 50 Hz */ 4051 .clock = 10800, 4052 .hdisplay = 480, 4053 .hsync_start = 480 + 17, 4054 .hsync_end = 480 + 17 + 41, 4055 .htotal = 480 + 17 + 41 + 2, 4056 .vdisplay = 272, 4057 .vsync_start = 272 + 116, 4058 .vsync_end = 272 + 116 + 10, 4059 .vtotal = 272 + 116 + 10 + 2, 4060 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4061 }, 4062 }; 4063 4064 static const struct panel_desc qishenglong_gopher2b_lcd = { 4065 .modes = qishenglong_gopher2b_lcd_modes, 4066 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4067 .bpc = 8, 4068 .size = { 4069 .width = 95, 4070 .height = 54, 4071 }, 4072 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4073 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4074 .connector_type = DRM_MODE_CONNECTOR_DPI, 4075 }; 4076 4077 static const struct display_timing rocktech_rk043fn48h_timing = { 4078 .pixelclock = { 6000000, 9000000, 12000000 }, 4079 .hactive = { 480, 480, 480 }, 4080 .hback_porch = { 8, 43, 43 }, 4081 .hfront_porch = { 2, 8, 10 }, 4082 .hsync_len = { 1, 1, 1 }, 4083 .vactive = { 272, 272, 272 }, 4084 .vback_porch = { 2, 12, 26 }, 4085 .vfront_porch = { 1, 4, 4 }, 4086 .vsync_len = { 1, 10, 10 }, 4087 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4088 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4089 DISPLAY_FLAGS_SYNC_POSEDGE, 4090 }; 4091 4092 static const struct panel_desc rocktech_rk043fn48h = { 4093 .timings = &rocktech_rk043fn48h_timing, 4094 .num_timings = 1, 4095 .bpc = 8, 4096 .size = { 4097 .width = 95, 4098 .height = 54, 4099 }, 4100 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4101 .connector_type = DRM_MODE_CONNECTOR_DPI, 4102 }; 4103 4104 static const struct display_timing rocktech_rk070er9427_timing = { 4105 .pixelclock = { 26400000, 33300000, 46800000 }, 4106 .hactive = { 800, 800, 800 }, 4107 .hfront_porch = { 16, 210, 354 }, 4108 .hback_porch = { 46, 46, 46 }, 4109 .hsync_len = { 1, 1, 1 }, 4110 .vactive = { 480, 480, 480 }, 4111 .vfront_porch = { 7, 22, 147 }, 4112 .vback_porch = { 23, 23, 23 }, 4113 .vsync_len = { 1, 1, 1 }, 4114 .flags = DISPLAY_FLAGS_DE_HIGH, 4115 }; 4116 4117 static const struct panel_desc rocktech_rk070er9427 = { 4118 .timings = &rocktech_rk070er9427_timing, 4119 .num_timings = 1, 4120 .bpc = 6, 4121 .size = { 4122 .width = 154, 4123 .height = 86, 4124 }, 4125 .delay = { 4126 .prepare = 41, 4127 .enable = 50, 4128 .unprepare = 41, 4129 .disable = 50, 4130 }, 4131 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4132 }; 4133 4134 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4135 .clock = 71100, 4136 .hdisplay = 1280, 4137 .hsync_start = 1280 + 48, 4138 .hsync_end = 1280 + 48 + 32, 4139 .htotal = 1280 + 48 + 32 + 80, 4140 .vdisplay = 800, 4141 .vsync_start = 800 + 2, 4142 .vsync_end = 800 + 2 + 5, 4143 .vtotal = 800 + 2 + 5 + 16, 4144 }; 4145 4146 static const struct panel_desc rocktech_rk101ii01d_ct = { 4147 .modes = &rocktech_rk101ii01d_ct_mode, 4148 .bpc = 8, 4149 .num_modes = 1, 4150 .size = { 4151 .width = 217, 4152 .height = 136, 4153 }, 4154 .delay = { 4155 .prepare = 50, 4156 .disable = 50, 4157 }, 4158 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4161 }; 4162 4163 static const struct display_timing samsung_ltl101al01_timing = { 4164 .pixelclock = { 66663000, 66663000, 66663000 }, 4165 .hactive = { 1280, 1280, 1280 }, 4166 .hfront_porch = { 18, 18, 18 }, 4167 .hback_porch = { 36, 36, 36 }, 4168 .hsync_len = { 16, 16, 16 }, 4169 .vactive = { 800, 800, 800 }, 4170 .vfront_porch = { 4, 4, 4 }, 4171 .vback_porch = { 16, 16, 16 }, 4172 .vsync_len = { 3, 3, 3 }, 4173 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4174 }; 4175 4176 static const struct panel_desc samsung_ltl101al01 = { 4177 .timings = &samsung_ltl101al01_timing, 4178 .num_timings = 1, 4179 .bpc = 8, 4180 .size = { 4181 .width = 217, 4182 .height = 135, 4183 }, 4184 .delay = { 4185 .prepare = 40, 4186 .enable = 300, 4187 .disable = 200, 4188 .unprepare = 600, 4189 }, 4190 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4191 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4192 }; 4193 4194 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4195 .clock = 54030, 4196 .hdisplay = 1024, 4197 .hsync_start = 1024 + 24, 4198 .hsync_end = 1024 + 24 + 136, 4199 .htotal = 1024 + 24 + 136 + 160, 4200 .vdisplay = 600, 4201 .vsync_start = 600 + 3, 4202 .vsync_end = 600 + 3 + 6, 4203 .vtotal = 600 + 3 + 6 + 61, 4204 }; 4205 4206 static const struct panel_desc samsung_ltn101nt05 = { 4207 .modes = &samsung_ltn101nt05_mode, 4208 .num_modes = 1, 4209 .bpc = 6, 4210 .size = { 4211 .width = 223, 4212 .height = 125, 4213 }, 4214 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4215 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4216 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4217 }; 4218 4219 static const struct display_timing satoz_sat050at40h12r2_timing = { 4220 .pixelclock = {33300000, 33300000, 50000000}, 4221 .hactive = {800, 800, 800}, 4222 .hfront_porch = {16, 210, 354}, 4223 .hback_porch = {46, 46, 46}, 4224 .hsync_len = {1, 1, 40}, 4225 .vactive = {480, 480, 480}, 4226 .vfront_porch = {7, 22, 147}, 4227 .vback_porch = {23, 23, 23}, 4228 .vsync_len = {1, 1, 20}, 4229 }; 4230 4231 static const struct panel_desc satoz_sat050at40h12r2 = { 4232 .timings = &satoz_sat050at40h12r2_timing, 4233 .num_timings = 1, 4234 .bpc = 8, 4235 .size = { 4236 .width = 108, 4237 .height = 65, 4238 }, 4239 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4240 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4241 }; 4242 4243 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4244 .clock = 33260, 4245 .hdisplay = 800, 4246 .hsync_start = 800 + 64, 4247 .hsync_end = 800 + 64 + 128, 4248 .htotal = 800 + 64 + 128 + 64, 4249 .vdisplay = 480, 4250 .vsync_start = 480 + 8, 4251 .vsync_end = 480 + 8 + 2, 4252 .vtotal = 480 + 8 + 2 + 35, 4253 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4254 }; 4255 4256 static const struct panel_desc sharp_lq070y3dg3b = { 4257 .modes = &sharp_lq070y3dg3b_mode, 4258 .num_modes = 1, 4259 .bpc = 8, 4260 .size = { 4261 .width = 152, /* 152.4mm */ 4262 .height = 91, /* 91.4mm */ 4263 }, 4264 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4265 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4266 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4267 }; 4268 4269 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4270 .clock = 5500, 4271 .hdisplay = 240, 4272 .hsync_start = 240 + 16, 4273 .hsync_end = 240 + 16 + 7, 4274 .htotal = 240 + 16 + 7 + 5, 4275 .vdisplay = 320, 4276 .vsync_start = 320 + 9, 4277 .vsync_end = 320 + 9 + 1, 4278 .vtotal = 320 + 9 + 1 + 7, 4279 }; 4280 4281 static const struct panel_desc sharp_lq035q7db03 = { 4282 .modes = &sharp_lq035q7db03_mode, 4283 .num_modes = 1, 4284 .bpc = 6, 4285 .size = { 4286 .width = 54, 4287 .height = 72, 4288 }, 4289 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4290 }; 4291 4292 static const struct display_timing sharp_lq101k1ly04_timing = { 4293 .pixelclock = { 60000000, 65000000, 80000000 }, 4294 .hactive = { 1280, 1280, 1280 }, 4295 .hfront_porch = { 20, 20, 20 }, 4296 .hback_porch = { 20, 20, 20 }, 4297 .hsync_len = { 10, 10, 10 }, 4298 .vactive = { 800, 800, 800 }, 4299 .vfront_porch = { 4, 4, 4 }, 4300 .vback_porch = { 4, 4, 4 }, 4301 .vsync_len = { 4, 4, 4 }, 4302 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4303 }; 4304 4305 static const struct panel_desc sharp_lq101k1ly04 = { 4306 .timings = &sharp_lq101k1ly04_timing, 4307 .num_timings = 1, 4308 .bpc = 8, 4309 .size = { 4310 .width = 217, 4311 .height = 136, 4312 }, 4313 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4314 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4315 }; 4316 4317 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4318 { /* 50 Hz */ 4319 .clock = 3000, 4320 .hdisplay = 240, 4321 .hsync_start = 240 + 58, 4322 .hsync_end = 240 + 58 + 1, 4323 .htotal = 240 + 58 + 1 + 1, 4324 .vdisplay = 160, 4325 .vsync_start = 160 + 24, 4326 .vsync_end = 160 + 24 + 10, 4327 .vtotal = 160 + 24 + 10 + 6, 4328 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4329 }, 4330 { /* 60 Hz */ 4331 .clock = 3000, 4332 .hdisplay = 240, 4333 .hsync_start = 240 + 8, 4334 .hsync_end = 240 + 8 + 1, 4335 .htotal = 240 + 8 + 1 + 1, 4336 .vdisplay = 160, 4337 .vsync_start = 160 + 24, 4338 .vsync_end = 160 + 24 + 10, 4339 .vtotal = 160 + 24 + 10 + 6, 4340 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4341 }, 4342 }; 4343 4344 static const struct panel_desc sharp_ls020b1dd01d = { 4345 .modes = sharp_ls020b1dd01d_modes, 4346 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4347 .bpc = 6, 4348 .size = { 4349 .width = 42, 4350 .height = 28, 4351 }, 4352 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4353 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4354 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4355 | DRM_BUS_FLAG_SHARP_SIGNALS, 4356 }; 4357 4358 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4359 .clock = 33300, 4360 .hdisplay = 800, 4361 .hsync_start = 800 + 1, 4362 .hsync_end = 800 + 1 + 64, 4363 .htotal = 800 + 1 + 64 + 64, 4364 .vdisplay = 480, 4365 .vsync_start = 480 + 1, 4366 .vsync_end = 480 + 1 + 23, 4367 .vtotal = 480 + 1 + 23 + 22, 4368 }; 4369 4370 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4371 .modes = &shelly_sca07010_bfn_lnn_mode, 4372 .num_modes = 1, 4373 .size = { 4374 .width = 152, 4375 .height = 91, 4376 }, 4377 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4378 }; 4379 4380 static const struct drm_display_mode starry_kr070pe2t_mode = { 4381 .clock = 33000, 4382 .hdisplay = 800, 4383 .hsync_start = 800 + 209, 4384 .hsync_end = 800 + 209 + 1, 4385 .htotal = 800 + 209 + 1 + 45, 4386 .vdisplay = 480, 4387 .vsync_start = 480 + 22, 4388 .vsync_end = 480 + 22 + 1, 4389 .vtotal = 480 + 22 + 1 + 22, 4390 }; 4391 4392 static const struct panel_desc starry_kr070pe2t = { 4393 .modes = &starry_kr070pe2t_mode, 4394 .num_modes = 1, 4395 .bpc = 8, 4396 .size = { 4397 .width = 152, 4398 .height = 86, 4399 }, 4400 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4401 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4402 .connector_type = DRM_MODE_CONNECTOR_DPI, 4403 }; 4404 4405 static const struct display_timing startek_kd070wvfpa_mode = { 4406 .pixelclock = { 25200000, 27200000, 30500000 }, 4407 .hactive = { 800, 800, 800 }, 4408 .hfront_porch = { 19, 44, 115 }, 4409 .hback_porch = { 5, 16, 101 }, 4410 .hsync_len = { 1, 2, 100 }, 4411 .vactive = { 480, 480, 480 }, 4412 .vfront_porch = { 5, 43, 67 }, 4413 .vback_porch = { 5, 5, 67 }, 4414 .vsync_len = { 1, 2, 66 }, 4415 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4416 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4417 DISPLAY_FLAGS_SYNC_POSEDGE, 4418 }; 4419 4420 static const struct panel_desc startek_kd070wvfpa = { 4421 .timings = &startek_kd070wvfpa_mode, 4422 .num_timings = 1, 4423 .bpc = 8, 4424 .size = { 4425 .width = 152, 4426 .height = 91, 4427 }, 4428 .delay = { 4429 .prepare = 20, 4430 .enable = 200, 4431 .disable = 200, 4432 }, 4433 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4434 .connector_type = DRM_MODE_CONNECTOR_DPI, 4435 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4436 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4437 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4438 }; 4439 4440 static const struct display_timing tsd_tst043015cmhx_timing = { 4441 .pixelclock = { 5000000, 9000000, 12000000 }, 4442 .hactive = { 480, 480, 480 }, 4443 .hfront_porch = { 4, 5, 65 }, 4444 .hback_porch = { 36, 40, 255 }, 4445 .hsync_len = { 1, 1, 1 }, 4446 .vactive = { 272, 272, 272 }, 4447 .vfront_porch = { 2, 8, 97 }, 4448 .vback_porch = { 3, 8, 31 }, 4449 .vsync_len = { 1, 1, 1 }, 4450 4451 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4452 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4453 }; 4454 4455 static const struct panel_desc tsd_tst043015cmhx = { 4456 .timings = &tsd_tst043015cmhx_timing, 4457 .num_timings = 1, 4458 .bpc = 8, 4459 .size = { 4460 .width = 105, 4461 .height = 67, 4462 }, 4463 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4464 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4465 }; 4466 4467 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4468 .clock = 30000, 4469 .hdisplay = 800, 4470 .hsync_start = 800 + 39, 4471 .hsync_end = 800 + 39 + 47, 4472 .htotal = 800 + 39 + 47 + 39, 4473 .vdisplay = 480, 4474 .vsync_start = 480 + 13, 4475 .vsync_end = 480 + 13 + 2, 4476 .vtotal = 480 + 13 + 2 + 29, 4477 }; 4478 4479 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4480 .modes = &tfc_s9700rtwv43tr_01b_mode, 4481 .num_modes = 1, 4482 .bpc = 8, 4483 .size = { 4484 .width = 155, 4485 .height = 90, 4486 }, 4487 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4488 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4489 }; 4490 4491 static const struct display_timing tianma_tm070jdhg30_timing = { 4492 .pixelclock = { 62600000, 68200000, 78100000 }, 4493 .hactive = { 1280, 1280, 1280 }, 4494 .hfront_porch = { 15, 64, 159 }, 4495 .hback_porch = { 5, 5, 5 }, 4496 .hsync_len = { 1, 1, 256 }, 4497 .vactive = { 800, 800, 800 }, 4498 .vfront_porch = { 3, 40, 99 }, 4499 .vback_porch = { 2, 2, 2 }, 4500 .vsync_len = { 1, 1, 128 }, 4501 .flags = DISPLAY_FLAGS_DE_HIGH, 4502 }; 4503 4504 static const struct panel_desc tianma_tm070jdhg30 = { 4505 .timings = &tianma_tm070jdhg30_timing, 4506 .num_timings = 1, 4507 .bpc = 8, 4508 .size = { 4509 .width = 151, 4510 .height = 95, 4511 }, 4512 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4513 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4514 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4515 }; 4516 4517 static const struct panel_desc tianma_tm070jvhg33 = { 4518 .timings = &tianma_tm070jdhg30_timing, 4519 .num_timings = 1, 4520 .bpc = 8, 4521 .size = { 4522 .width = 150, 4523 .height = 94, 4524 }, 4525 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4526 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4527 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4528 }; 4529 4530 /* 4531 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4532 * front porch, not including sync pulse width. This is for both H and 4533 * V. To make the total blanking and period correct, subtract the pulse 4534 * width from the front porch. 4535 * 4536 * This works well for the Min and Typ values, but for Max values the sync 4537 * pulse width is higher than back porch + front porch, so work around that 4538 * by reducing the Max sync length value to 1 and then treating the Max 4539 * porches as in the Min and Typ cases. 4540 * 4541 * Exact datasheet values are added as a comment where they differ from the 4542 * ones implemented for the above reason. 4543 * 4544 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4545 * and total blanking time, however the resulting values are the same as 4546 * the TM070JDHG34-00. 4547 */ 4548 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4549 .pixelclock = { 68400000, 71900000, 78100000 }, 4550 .hactive = { 1280, 1280, 1280 }, 4551 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4552 .hback_porch = { 5, 5, 5 }, 4553 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4554 .vactive = { 800, 800, 800 }, 4555 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4556 .vback_porch = { 2, 2, 2 }, 4557 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4558 .flags = DISPLAY_FLAGS_DE_HIGH, 4559 }; 4560 4561 static const struct panel_desc tianma_tm070jdhg34_00 = { 4562 .timings = &tianma_tm070jdhg34_00_timing, 4563 .num_timings = 1, 4564 .bpc = 8, 4565 .size = { 4566 .width = 150, /* 149.76 */ 4567 .height = 94, /* 93.60 */ 4568 }, 4569 .delay = { 4570 .prepare = 15, /* Tp1 */ 4571 .enable = 150, /* Tp2 */ 4572 .disable = 150, /* Tp4 */ 4573 .unprepare = 120, /* Tp3 */ 4574 }, 4575 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4577 }; 4578 4579 static const struct panel_desc tianma_p0700wxf1mbaa = { 4580 .timings = &tianma_tm070jdhg34_00_timing, 4581 .num_timings = 1, 4582 .bpc = 8, 4583 .size = { 4584 .width = 150, /* 149.76 */ 4585 .height = 94, /* 93.60 */ 4586 }, 4587 .delay = { 4588 .prepare = 18, /* Tr + Tp1 */ 4589 .enable = 152, /* Tp2 + Tp5 */ 4590 .disable = 152, /* Tp6 + Tp4 */ 4591 .unprepare = 120, /* Tp3 */ 4592 }, 4593 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4595 }; 4596 4597 static const struct display_timing tianma_tm070rvhg71_timing = { 4598 .pixelclock = { 27700000, 29200000, 39600000 }, 4599 .hactive = { 800, 800, 800 }, 4600 .hfront_porch = { 12, 40, 212 }, 4601 .hback_porch = { 88, 88, 88 }, 4602 .hsync_len = { 1, 1, 40 }, 4603 .vactive = { 480, 480, 480 }, 4604 .vfront_porch = { 1, 13, 88 }, 4605 .vback_porch = { 32, 32, 32 }, 4606 .vsync_len = { 1, 1, 3 }, 4607 .flags = DISPLAY_FLAGS_DE_HIGH, 4608 }; 4609 4610 static const struct panel_desc tianma_tm070rvhg71 = { 4611 .timings = &tianma_tm070rvhg71_timing, 4612 .num_timings = 1, 4613 .bpc = 8, 4614 .size = { 4615 .width = 154, 4616 .height = 86, 4617 }, 4618 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4619 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4620 }; 4621 4622 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4623 { 4624 .clock = 10000, 4625 .hdisplay = 320, 4626 .hsync_start = 320 + 50, 4627 .hsync_end = 320 + 50 + 6, 4628 .htotal = 320 + 50 + 6 + 38, 4629 .vdisplay = 240, 4630 .vsync_start = 240 + 3, 4631 .vsync_end = 240 + 3 + 1, 4632 .vtotal = 240 + 3 + 1 + 17, 4633 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4634 }, 4635 }; 4636 4637 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4638 .modes = ti_nspire_cx_lcd_mode, 4639 .num_modes = 1, 4640 .bpc = 8, 4641 .size = { 4642 .width = 65, 4643 .height = 49, 4644 }, 4645 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4646 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4647 }; 4648 4649 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4650 { 4651 .clock = 10000, 4652 .hdisplay = 320, 4653 .hsync_start = 320 + 6, 4654 .hsync_end = 320 + 6 + 6, 4655 .htotal = 320 + 6 + 6 + 6, 4656 .vdisplay = 240, 4657 .vsync_start = 240 + 0, 4658 .vsync_end = 240 + 0 + 1, 4659 .vtotal = 240 + 0 + 1 + 0, 4660 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4661 }, 4662 }; 4663 4664 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4665 .modes = ti_nspire_classic_lcd_mode, 4666 .num_modes = 1, 4667 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4668 .bpc = 8, 4669 .size = { 4670 .width = 71, 4671 .height = 53, 4672 }, 4673 /* This is the grayscale bus format */ 4674 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4675 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4676 }; 4677 4678 static const struct display_timing topland_tian_g07017_01_timing = { 4679 .pixelclock = { 44900000, 51200000, 63000000 }, 4680 .hactive = { 1024, 1024, 1024 }, 4681 .hfront_porch = { 16, 160, 216 }, 4682 .hback_porch = { 160, 160, 160 }, 4683 .hsync_len = { 1, 1, 140 }, 4684 .vactive = { 600, 600, 600 }, 4685 .vfront_porch = { 1, 12, 127 }, 4686 .vback_porch = { 23, 23, 23 }, 4687 .vsync_len = { 1, 1, 20 }, 4688 }; 4689 4690 static const struct panel_desc topland_tian_g07017_01 = { 4691 .timings = &topland_tian_g07017_01_timing, 4692 .num_timings = 1, 4693 .bpc = 8, 4694 .size = { 4695 .width = 154, 4696 .height = 86, 4697 }, 4698 .delay = { 4699 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4700 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4701 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4702 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4703 }, 4704 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4705 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4706 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4707 }; 4708 4709 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4710 .clock = 79500, 4711 .hdisplay = 1280, 4712 .hsync_start = 1280 + 192, 4713 .hsync_end = 1280 + 192 + 128, 4714 .htotal = 1280 + 192 + 128 + 64, 4715 .vdisplay = 768, 4716 .vsync_start = 768 + 20, 4717 .vsync_end = 768 + 20 + 7, 4718 .vtotal = 768 + 20 + 7 + 3, 4719 }; 4720 4721 static const struct panel_desc toshiba_lt089ac29000 = { 4722 .modes = &toshiba_lt089ac29000_mode, 4723 .num_modes = 1, 4724 .size = { 4725 .width = 194, 4726 .height = 116, 4727 }, 4728 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4729 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4730 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4731 }; 4732 4733 static const struct drm_display_mode tpk_f07a_0102_mode = { 4734 .clock = 33260, 4735 .hdisplay = 800, 4736 .hsync_start = 800 + 40, 4737 .hsync_end = 800 + 40 + 128, 4738 .htotal = 800 + 40 + 128 + 88, 4739 .vdisplay = 480, 4740 .vsync_start = 480 + 10, 4741 .vsync_end = 480 + 10 + 2, 4742 .vtotal = 480 + 10 + 2 + 33, 4743 }; 4744 4745 static const struct panel_desc tpk_f07a_0102 = { 4746 .modes = &tpk_f07a_0102_mode, 4747 .num_modes = 1, 4748 .size = { 4749 .width = 152, 4750 .height = 91, 4751 }, 4752 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4753 }; 4754 4755 static const struct drm_display_mode tpk_f10a_0102_mode = { 4756 .clock = 45000, 4757 .hdisplay = 1024, 4758 .hsync_start = 1024 + 176, 4759 .hsync_end = 1024 + 176 + 5, 4760 .htotal = 1024 + 176 + 5 + 88, 4761 .vdisplay = 600, 4762 .vsync_start = 600 + 20, 4763 .vsync_end = 600 + 20 + 5, 4764 .vtotal = 600 + 20 + 5 + 25, 4765 }; 4766 4767 static const struct panel_desc tpk_f10a_0102 = { 4768 .modes = &tpk_f10a_0102_mode, 4769 .num_modes = 1, 4770 .size = { 4771 .width = 223, 4772 .height = 125, 4773 }, 4774 }; 4775 4776 static const struct display_timing urt_umsh_8596md_timing = { 4777 .pixelclock = { 33260000, 33260000, 33260000 }, 4778 .hactive = { 800, 800, 800 }, 4779 .hfront_porch = { 41, 41, 41 }, 4780 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4781 .hsync_len = { 71, 128, 128 }, 4782 .vactive = { 480, 480, 480 }, 4783 .vfront_porch = { 10, 10, 10 }, 4784 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4785 .vsync_len = { 2, 2, 2 }, 4786 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4787 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4788 }; 4789 4790 static const struct panel_desc urt_umsh_8596md_lvds = { 4791 .timings = &urt_umsh_8596md_timing, 4792 .num_timings = 1, 4793 .bpc = 6, 4794 .size = { 4795 .width = 152, 4796 .height = 91, 4797 }, 4798 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4799 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4800 }; 4801 4802 static const struct panel_desc urt_umsh_8596md_parallel = { 4803 .timings = &urt_umsh_8596md_timing, 4804 .num_timings = 1, 4805 .bpc = 6, 4806 .size = { 4807 .width = 152, 4808 .height = 91, 4809 }, 4810 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4811 }; 4812 4813 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4814 .clock = 60000, 4815 .hdisplay = 1024, 4816 .hsync_start = 1024 + 160, 4817 .hsync_end = 1024 + 160 + 100, 4818 .htotal = 1024 + 160 + 100 + 60, 4819 .vdisplay = 600, 4820 .vsync_start = 600 + 12, 4821 .vsync_end = 600 + 12 + 10, 4822 .vtotal = 600 + 12 + 10 + 13, 4823 }; 4824 4825 static const struct panel_desc vivax_tpc9150_panel = { 4826 .modes = &vivax_tpc9150_panel_mode, 4827 .num_modes = 1, 4828 .bpc = 6, 4829 .size = { 4830 .width = 200, 4831 .height = 115, 4832 }, 4833 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4834 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4835 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4836 }; 4837 4838 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4839 .clock = 33333, 4840 .hdisplay = 800, 4841 .hsync_start = 800 + 210, 4842 .hsync_end = 800 + 210 + 20, 4843 .htotal = 800 + 210 + 20 + 46, 4844 .vdisplay = 480, 4845 .vsync_start = 480 + 22, 4846 .vsync_end = 480 + 22 + 10, 4847 .vtotal = 480 + 22 + 10 + 23, 4848 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4849 }; 4850 4851 static const struct panel_desc vl050_8048nt_c01 = { 4852 .modes = &vl050_8048nt_c01_mode, 4853 .num_modes = 1, 4854 .bpc = 8, 4855 .size = { 4856 .width = 120, 4857 .height = 76, 4858 }, 4859 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4860 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4861 }; 4862 4863 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4864 .clock = 6410, 4865 .hdisplay = 320, 4866 .hsync_start = 320 + 20, 4867 .hsync_end = 320 + 20 + 30, 4868 .htotal = 320 + 20 + 30 + 38, 4869 .vdisplay = 240, 4870 .vsync_start = 240 + 4, 4871 .vsync_end = 240 + 4 + 3, 4872 .vtotal = 240 + 4 + 3 + 15, 4873 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4874 }; 4875 4876 static const struct panel_desc winstar_wf35ltiacd = { 4877 .modes = &winstar_wf35ltiacd_mode, 4878 .num_modes = 1, 4879 .bpc = 8, 4880 .size = { 4881 .width = 70, 4882 .height = 53, 4883 }, 4884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4885 }; 4886 4887 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4888 .clock = 51200, 4889 .hdisplay = 1024, 4890 .hsync_start = 1024 + 100, 4891 .hsync_end = 1024 + 100 + 100, 4892 .htotal = 1024 + 100 + 100 + 120, 4893 .vdisplay = 600, 4894 .vsync_start = 600 + 10, 4895 .vsync_end = 600 + 10 + 10, 4896 .vtotal = 600 + 10 + 10 + 15, 4897 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4898 }; 4899 4900 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4901 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4902 .num_modes = 1, 4903 .bpc = 8, 4904 .size = { 4905 .width = 154, 4906 .height = 90, 4907 }, 4908 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4909 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4910 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4911 }; 4912 4913 static const struct drm_display_mode mchp_ac69t88a_mode = { 4914 .clock = 25000, 4915 .hdisplay = 800, 4916 .hsync_start = 800 + 88, 4917 .hsync_end = 800 + 88 + 5, 4918 .htotal = 800 + 88 + 5 + 40, 4919 .vdisplay = 480, 4920 .vsync_start = 480 + 23, 4921 .vsync_end = 480 + 23 + 5, 4922 .vtotal = 480 + 23 + 5 + 1, 4923 }; 4924 4925 static const struct panel_desc mchp_ac69t88a = { 4926 .modes = &mchp_ac69t88a_mode, 4927 .num_modes = 1, 4928 .bpc = 8, 4929 .size = { 4930 .width = 108, 4931 .height = 65, 4932 }, 4933 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4934 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4935 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4936 }; 4937 4938 static const struct drm_display_mode arm_rtsm_mode[] = { 4939 { 4940 .clock = 65000, 4941 .hdisplay = 1024, 4942 .hsync_start = 1024 + 24, 4943 .hsync_end = 1024 + 24 + 136, 4944 .htotal = 1024 + 24 + 136 + 160, 4945 .vdisplay = 768, 4946 .vsync_start = 768 + 3, 4947 .vsync_end = 768 + 3 + 6, 4948 .vtotal = 768 + 3 + 6 + 29, 4949 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4950 }, 4951 }; 4952 4953 static const struct panel_desc arm_rtsm = { 4954 .modes = arm_rtsm_mode, 4955 .num_modes = 1, 4956 .bpc = 8, 4957 .size = { 4958 .width = 400, 4959 .height = 300, 4960 }, 4961 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4962 }; 4963 4964 static const struct of_device_id platform_of_match[] = { 4965 { 4966 .compatible = "ampire,am-1280800n3tzqw-t00h", 4967 .data = &ire_am_1280800n3tzqw_t00h, 4968 }, { 4969 .compatible = "ampire,am-480272h3tmqw-t01h", 4970 .data = &ire_am_480272h3tmqw_t01h, 4971 }, { 4972 .compatible = "ampire,am-800480l1tmqw-t00h", 4973 .data = &ire_am_800480l1tmqw_t00h, 4974 }, { 4975 .compatible = "ampire,am800480r3tmqwa1h", 4976 .data = &ire_am800480r3tmqwa1h, 4977 }, { 4978 .compatible = "ampire,am800600p5tmqw-tb8h", 4979 .data = &ire_am800600p5tmqwtb8h, 4980 }, { 4981 .compatible = "arm,rtsm-display", 4982 .data = &arm_rtsm, 4983 }, { 4984 .compatible = "armadeus,st0700-adapt", 4985 .data = &armadeus_st0700_adapt, 4986 }, { 4987 .compatible = "auo,b101aw03", 4988 .data = &auo_b101aw03, 4989 }, { 4990 .compatible = "auo,b101xtn01", 4991 .data = &auo_b101xtn01, 4992 }, { 4993 .compatible = "auo,b116xw03", 4994 .data = &auo_b116xw03, 4995 }, { 4996 .compatible = "auo,g070vvn01", 4997 .data = &auo_g070vvn01, 4998 }, { 4999 .compatible = "auo,g101evn010", 5000 .data = &auo_g101evn010, 5001 }, { 5002 .compatible = "auo,g104sn02", 5003 .data = &auo_g104sn02, 5004 }, { 5005 .compatible = "auo,g104stn01", 5006 .data = &auo_g104stn01, 5007 }, { 5008 .compatible = "auo,g121ean01", 5009 .data = &auo_g121ean01, 5010 }, { 5011 .compatible = "auo,g133han01", 5012 .data = &auo_g133han01, 5013 }, { 5014 .compatible = "auo,g156han04", 5015 .data = &auo_g156han04, 5016 }, { 5017 .compatible = "auo,g156xtn01", 5018 .data = &auo_g156xtn01, 5019 }, { 5020 .compatible = "auo,g185han01", 5021 .data = &auo_g185han01, 5022 }, { 5023 .compatible = "auo,g190ean01", 5024 .data = &auo_g190ean01, 5025 }, { 5026 .compatible = "auo,p238han01", 5027 .data = &auo_p238han01, 5028 }, { 5029 .compatible = "auo,p320hvn03", 5030 .data = &auo_p320hvn03, 5031 }, { 5032 .compatible = "auo,t215hvn01", 5033 .data = &auo_t215hvn01, 5034 }, { 5035 .compatible = "avic,tm070ddh03", 5036 .data = &avic_tm070ddh03, 5037 }, { 5038 .compatible = "bananapi,s070wv20-ct16", 5039 .data = &bananapi_s070wv20_ct16, 5040 }, { 5041 .compatible = "boe,av101hdt-a10", 5042 .data = &boe_av101hdt_a10, 5043 }, { 5044 .compatible = "boe,av123z7m-n17", 5045 .data = &boe_av123z7m_n17, 5046 }, { 5047 .compatible = "boe,bp082wx1-100", 5048 .data = &boe_bp082wx1_100, 5049 }, { 5050 .compatible = "boe,bp101wx1-100", 5051 .data = &boe_bp101wx1_100, 5052 }, { 5053 .compatible = "boe,ev121wxm-n10-1850", 5054 .data = &boe_ev121wxm_n10_1850, 5055 }, { 5056 .compatible = "boe,hv070wsa-100", 5057 .data = &boe_hv070wsa 5058 }, { 5059 .compatible = "cct,cmt430b19n00", 5060 .data = &cct_cmt430b19n00, 5061 }, { 5062 .compatible = "cdtech,s043wq26h-ct7", 5063 .data = &cdtech_s043wq26h_ct7, 5064 }, { 5065 .compatible = "cdtech,s070pws19hp-fc21", 5066 .data = &cdtech_s070pws19hp_fc21, 5067 }, { 5068 .compatible = "cdtech,s070swv29hg-dc44", 5069 .data = &cdtech_s070swv29hg_dc44, 5070 }, { 5071 .compatible = "cdtech,s070wv95-ct16", 5072 .data = &cdtech_s070wv95_ct16, 5073 }, { 5074 .compatible = "chefree,ch101olhlwh-002", 5075 .data = &chefree_ch101olhlwh_002, 5076 }, { 5077 .compatible = "chunghwa,claa070wp03xg", 5078 .data = &chunghwa_claa070wp03xg, 5079 }, { 5080 .compatible = "chunghwa,claa101wa01a", 5081 .data = &chunghwa_claa101wa01a 5082 }, { 5083 .compatible = "chunghwa,claa101wb01", 5084 .data = &chunghwa_claa101wb01 5085 }, { 5086 .compatible = "dataimage,fg040346dsswbg04", 5087 .data = &dataimage_fg040346dsswbg04, 5088 }, { 5089 .compatible = "dataimage,fg1001l0dsswmg01", 5090 .data = &dataimage_fg1001l0dsswmg01, 5091 }, { 5092 .compatible = "dataimage,scf0700c48ggu18", 5093 .data = &dataimage_scf0700c48ggu18, 5094 }, { 5095 .compatible = "dlc,dlc0700yzg-1", 5096 .data = &dlc_dlc0700yzg_1, 5097 }, { 5098 .compatible = "dlc,dlc1010gig", 5099 .data = &dlc_dlc1010gig, 5100 }, { 5101 .compatible = "edt,et035012dm6", 5102 .data = &edt_et035012dm6, 5103 }, { 5104 .compatible = "edt,etm0350g0dh6", 5105 .data = &edt_etm0350g0dh6, 5106 }, { 5107 .compatible = "edt,etm043080dh6gp", 5108 .data = &edt_etm043080dh6gp, 5109 }, { 5110 .compatible = "edt,etm0430g0dh6", 5111 .data = &edt_etm0430g0dh6, 5112 }, { 5113 .compatible = "edt,et057090dhu", 5114 .data = &edt_et057090dhu, 5115 }, { 5116 .compatible = "edt,et070080dh6", 5117 .data = &edt_etm0700g0dh6, 5118 }, { 5119 .compatible = "edt,etm0700g0dh6", 5120 .data = &edt_etm0700g0dh6, 5121 }, { 5122 .compatible = "edt,etm0700g0bdh6", 5123 .data = &edt_etm0700g0bdh6, 5124 }, { 5125 .compatible = "edt,etm0700g0edh6", 5126 .data = &edt_etm0700g0bdh6, 5127 }, { 5128 .compatible = "edt,etml0700y5dha", 5129 .data = &edt_etml0700y5dha, 5130 }, { 5131 .compatible = "edt,etml1010g3dra", 5132 .data = &edt_etml1010g3dra, 5133 }, { 5134 .compatible = "edt,etmv570g2dhu", 5135 .data = &edt_etmv570g2dhu, 5136 }, { 5137 .compatible = "eink,vb3300-kca", 5138 .data = &eink_vb3300_kca, 5139 }, { 5140 .compatible = "evervision,vgg644804", 5141 .data = &evervision_vgg644804, 5142 }, { 5143 .compatible = "evervision,vgg804821", 5144 .data = &evervision_vgg804821, 5145 }, { 5146 .compatible = "foxlink,fl500wvr00-a0t", 5147 .data = &foxlink_fl500wvr00_a0t, 5148 }, { 5149 .compatible = "frida,frd350h54004", 5150 .data = &frida_frd350h54004, 5151 }, { 5152 .compatible = "friendlyarm,hd702e", 5153 .data = &friendlyarm_hd702e, 5154 }, { 5155 .compatible = "giantplus,gpg482739qs5", 5156 .data = &giantplus_gpg482739qs5 5157 }, { 5158 .compatible = "giantplus,gpm940b0", 5159 .data = &giantplus_gpm940b0, 5160 }, { 5161 .compatible = "hannstar,hsd070pww1", 5162 .data = &hannstar_hsd070pww1, 5163 }, { 5164 .compatible = "hannstar,hsd100pxn1", 5165 .data = &hannstar_hsd100pxn1, 5166 }, { 5167 .compatible = "hannstar,hsd101pww2", 5168 .data = &hannstar_hsd101pww2, 5169 }, { 5170 .compatible = "hit,tx23d38vm0caa", 5171 .data = &hitachi_tx23d38vm0caa 5172 }, { 5173 .compatible = "innolux,at043tn24", 5174 .data = &innolux_at043tn24, 5175 }, { 5176 .compatible = "innolux,at070tn92", 5177 .data = &innolux_at070tn92, 5178 }, { 5179 .compatible = "innolux,g070ace-l01", 5180 .data = &innolux_g070ace_l01, 5181 }, { 5182 .compatible = "innolux,g070ace-lh3", 5183 .data = &innolux_g070ace_lh3, 5184 }, { 5185 .compatible = "innolux,g070y2-l01", 5186 .data = &innolux_g070y2_l01, 5187 }, { 5188 .compatible = "innolux,g070y2-t02", 5189 .data = &innolux_g070y2_t02, 5190 }, { 5191 .compatible = "innolux,g101ice-l01", 5192 .data = &innolux_g101ice_l01 5193 }, { 5194 .compatible = "innolux,g121i1-l01", 5195 .data = &innolux_g121i1_l01 5196 }, { 5197 .compatible = "innolux,g121x1-l03", 5198 .data = &innolux_g121x1_l03, 5199 }, { 5200 .compatible = "innolux,g121xce-l01", 5201 .data = &innolux_g121xce_l01, 5202 }, { 5203 .compatible = "innolux,g156hce-l01", 5204 .data = &innolux_g156hce_l01, 5205 }, { 5206 .compatible = "innolux,n156bge-l21", 5207 .data = &innolux_n156bge_l21, 5208 }, { 5209 .compatible = "innolux,zj070na-01p", 5210 .data = &innolux_zj070na_01p, 5211 }, { 5212 .compatible = "koe,tx14d24vm1bpa", 5213 .data = &koe_tx14d24vm1bpa, 5214 }, { 5215 .compatible = "koe,tx26d202vm0bwa", 5216 .data = &koe_tx26d202vm0bwa, 5217 }, { 5218 .compatible = "koe,tx31d200vm0baa", 5219 .data = &koe_tx31d200vm0baa, 5220 }, { 5221 .compatible = "kyo,tcg121xglp", 5222 .data = &kyo_tcg121xglp, 5223 }, { 5224 .compatible = "lemaker,bl035-rgb-002", 5225 .data = &lemaker_bl035_rgb_002, 5226 }, { 5227 .compatible = "lg,lb070wv8", 5228 .data = &lg_lb070wv8, 5229 }, { 5230 .compatible = "lincolntech,lcd185-101ct", 5231 .data = &lincolntech_lcd185_101ct, 5232 }, { 5233 .compatible = "logicpd,type28", 5234 .data = &logicpd_type_28, 5235 }, { 5236 .compatible = "logictechno,lt161010-2nhc", 5237 .data = &logictechno_lt161010_2nh, 5238 }, { 5239 .compatible = "logictechno,lt161010-2nhr", 5240 .data = &logictechno_lt161010_2nh, 5241 }, { 5242 .compatible = "logictechno,lt170410-2whc", 5243 .data = &logictechno_lt170410_2whc, 5244 }, { 5245 .compatible = "logictechno,lttd800480070-l2rt", 5246 .data = &logictechno_lttd800480070_l2rt, 5247 }, { 5248 .compatible = "logictechno,lttd800480070-l6wh-rt", 5249 .data = &logictechno_lttd800480070_l6wh_rt, 5250 }, { 5251 .compatible = "microtips,mf-101hiebcaf0", 5252 .data = µtips_mf_101hiebcaf0_c, 5253 }, { 5254 .compatible = "microtips,mf-103hieb0ga0", 5255 .data = µtips_mf_103hieb0ga0, 5256 }, { 5257 .compatible = "mitsubishi,aa070mc01-ca1", 5258 .data = &mitsubishi_aa070mc01, 5259 }, { 5260 .compatible = "mitsubishi,aa084xe01", 5261 .data = &mitsubishi_aa084xe01, 5262 }, { 5263 .compatible = "multi-inno,mi0700a2t-30", 5264 .data = &multi_inno_mi0700a2t_30, 5265 }, { 5266 .compatible = "multi-inno,mi0700s4t-6", 5267 .data = &multi_inno_mi0700s4t_6, 5268 }, { 5269 .compatible = "multi-inno,mi0800ft-9", 5270 .data = &multi_inno_mi0800ft_9, 5271 }, { 5272 .compatible = "multi-inno,mi1010ait-1cp", 5273 .data = &multi_inno_mi1010ait_1cp, 5274 }, { 5275 .compatible = "multi-inno,mi1010z1t-1cp11", 5276 .data = &multi_inno_mi1010z1t_1cp11, 5277 }, { 5278 .compatible = "nec,nl12880bc20-05", 5279 .data = &nec_nl12880bc20_05, 5280 }, { 5281 .compatible = "nec,nl4827hc19-05b", 5282 .data = &nec_nl4827hc19_05b, 5283 }, { 5284 .compatible = "netron-dy,e231732", 5285 .data = &netron_dy_e231732, 5286 }, { 5287 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5288 .data = &newhaven_nhd_43_480272ef_atxl, 5289 }, { 5290 .compatible = "nlt,nl13676bc25-03f", 5291 .data = &nlt_nl13676bc25_03f, 5292 }, { 5293 .compatible = "nlt,nl192108ac18-02d", 5294 .data = &nlt_nl192108ac18_02d, 5295 }, { 5296 .compatible = "nvd,9128", 5297 .data = &nvd_9128, 5298 }, { 5299 .compatible = "okaya,rs800480t-7x0gp", 5300 .data = &okaya_rs800480t_7x0gp, 5301 }, { 5302 .compatible = "olimex,lcd-olinuxino-43-ts", 5303 .data = &olimex_lcd_olinuxino_43ts, 5304 }, { 5305 .compatible = "olimex,lcd-olinuxino-5-cts", 5306 .data = &olimex_lcd_olinuxino_5cts, 5307 }, { 5308 .compatible = "ontat,kd50g21-40nt-a1", 5309 .data = &ontat_kd50g21_40nt_a1, 5310 }, { 5311 .compatible = "ontat,yx700wv03", 5312 .data = &ontat_yx700wv03, 5313 }, { 5314 .compatible = "ortustech,com37h3m05dtc", 5315 .data = &ortustech_com37h3m, 5316 }, { 5317 .compatible = "ortustech,com37h3m99dtc", 5318 .data = &ortustech_com37h3m, 5319 }, { 5320 .compatible = "ortustech,com43h4m85ulc", 5321 .data = &ortustech_com43h4m85ulc, 5322 }, { 5323 .compatible = "osddisplays,osd070t1718-19ts", 5324 .data = &osddisplays_osd070t1718_19ts, 5325 }, { 5326 .compatible = "pda,91-00156-a0", 5327 .data = &pda_91_00156_a0, 5328 }, { 5329 .compatible = "powertip,ph128800t004-zza01", 5330 .data = &powertip_ph128800t004_zza01, 5331 }, { 5332 .compatible = "powertip,ph128800t006-zhc01", 5333 .data = &powertip_ph128800t006_zhc01, 5334 }, { 5335 .compatible = "powertip,ph800480t013-idf02", 5336 .data = &powertip_ph800480t013_idf02, 5337 }, { 5338 .compatible = "primeview,pm070wl4", 5339 .data = &primeview_pm070wl4, 5340 }, { 5341 .compatible = "qiaodian,qd43003c0-40", 5342 .data = &qd43003c0_40, 5343 }, { 5344 .compatible = "qishenglong,gopher2b-lcd", 5345 .data = &qishenglong_gopher2b_lcd, 5346 }, { 5347 .compatible = "rocktech,rk043fn48h", 5348 .data = &rocktech_rk043fn48h, 5349 }, { 5350 .compatible = "rocktech,rk070er9427", 5351 .data = &rocktech_rk070er9427, 5352 }, { 5353 .compatible = "rocktech,rk101ii01d-ct", 5354 .data = &rocktech_rk101ii01d_ct, 5355 }, { 5356 .compatible = "samsung,ltl101al01", 5357 .data = &samsung_ltl101al01, 5358 }, { 5359 .compatible = "samsung,ltn101nt05", 5360 .data = &samsung_ltn101nt05, 5361 }, { 5362 .compatible = "satoz,sat050at40h12r2", 5363 .data = &satoz_sat050at40h12r2, 5364 }, { 5365 .compatible = "sharp,lq035q7db03", 5366 .data = &sharp_lq035q7db03, 5367 }, { 5368 .compatible = "sharp,lq070y3dg3b", 5369 .data = &sharp_lq070y3dg3b, 5370 }, { 5371 .compatible = "sharp,lq101k1ly04", 5372 .data = &sharp_lq101k1ly04, 5373 }, { 5374 .compatible = "sharp,ls020b1dd01d", 5375 .data = &sharp_ls020b1dd01d, 5376 }, { 5377 .compatible = "shelly,sca07010-bfn-lnn", 5378 .data = &shelly_sca07010_bfn_lnn, 5379 }, { 5380 .compatible = "starry,kr070pe2t", 5381 .data = &starry_kr070pe2t, 5382 }, { 5383 .compatible = "startek,kd070wvfpa", 5384 .data = &startek_kd070wvfpa, 5385 }, { 5386 .compatible = "team-source-display,tst043015cmhx", 5387 .data = &tsd_tst043015cmhx, 5388 }, { 5389 .compatible = "tfc,s9700rtwv43tr-01b", 5390 .data = &tfc_s9700rtwv43tr_01b, 5391 }, { 5392 .compatible = "tianma,p0700wxf1mbaa", 5393 .data = &tianma_p0700wxf1mbaa, 5394 }, { 5395 .compatible = "tianma,tm070jdhg30", 5396 .data = &tianma_tm070jdhg30, 5397 }, { 5398 .compatible = "tianma,tm070jdhg34-00", 5399 .data = &tianma_tm070jdhg34_00, 5400 }, { 5401 .compatible = "tianma,tm070jvhg33", 5402 .data = &tianma_tm070jvhg33, 5403 }, { 5404 .compatible = "tianma,tm070rvhg71", 5405 .data = &tianma_tm070rvhg71, 5406 }, { 5407 .compatible = "ti,nspire-cx-lcd-panel", 5408 .data = &ti_nspire_cx_lcd_panel, 5409 }, { 5410 .compatible = "ti,nspire-classic-lcd-panel", 5411 .data = &ti_nspire_classic_lcd_panel, 5412 }, { 5413 .compatible = "toshiba,lt089ac29000", 5414 .data = &toshiba_lt089ac29000, 5415 }, { 5416 .compatible = "topland,tian-g07017-01", 5417 .data = &topland_tian_g07017_01, 5418 }, { 5419 .compatible = "tpk,f07a-0102", 5420 .data = &tpk_f07a_0102, 5421 }, { 5422 .compatible = "tpk,f10a-0102", 5423 .data = &tpk_f10a_0102, 5424 }, { 5425 .compatible = "urt,umsh-8596md-t", 5426 .data = &urt_umsh_8596md_parallel, 5427 }, { 5428 .compatible = "urt,umsh-8596md-1t", 5429 .data = &urt_umsh_8596md_parallel, 5430 }, { 5431 .compatible = "urt,umsh-8596md-7t", 5432 .data = &urt_umsh_8596md_parallel, 5433 }, { 5434 .compatible = "urt,umsh-8596md-11t", 5435 .data = &urt_umsh_8596md_lvds, 5436 }, { 5437 .compatible = "urt,umsh-8596md-19t", 5438 .data = &urt_umsh_8596md_lvds, 5439 }, { 5440 .compatible = "urt,umsh-8596md-20t", 5441 .data = &urt_umsh_8596md_parallel, 5442 }, { 5443 .compatible = "vivax,tpc9150-panel", 5444 .data = &vivax_tpc9150_panel, 5445 }, { 5446 .compatible = "vxt,vl050-8048nt-c01", 5447 .data = &vl050_8048nt_c01, 5448 }, { 5449 .compatible = "winstar,wf35ltiacd", 5450 .data = &winstar_wf35ltiacd, 5451 }, { 5452 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5453 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5454 }, { 5455 .compatible = "microchip,ac69t88a", 5456 .data = &mchp_ac69t88a, 5457 }, { 5458 /* Must be the last entry */ 5459 .compatible = "panel-dpi", 5460 5461 /* 5462 * Explicitly NULL, the panel_desc structure will be 5463 * allocated by panel_dpi_probe(). 5464 */ 5465 .data = NULL, 5466 }, { 5467 /* sentinel */ 5468 } 5469 }; 5470 MODULE_DEVICE_TABLE(of, platform_of_match); 5471 5472 static int panel_simple_platform_probe(struct platform_device *pdev) 5473 { 5474 struct panel_simple *panel; 5475 5476 panel = panel_simple_probe(&pdev->dev); 5477 if (IS_ERR(panel)) 5478 return PTR_ERR(panel); 5479 5480 return 0; 5481 } 5482 5483 static void panel_simple_platform_remove(struct platform_device *pdev) 5484 { 5485 panel_simple_remove(&pdev->dev); 5486 } 5487 5488 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5489 { 5490 panel_simple_shutdown(&pdev->dev); 5491 } 5492 5493 static const struct dev_pm_ops panel_simple_pm_ops = { 5494 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5495 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5496 pm_runtime_force_resume) 5497 }; 5498 5499 static struct platform_driver panel_simple_platform_driver = { 5500 .driver = { 5501 .name = "panel-simple", 5502 .of_match_table = platform_of_match, 5503 .pm = &panel_simple_pm_ops, 5504 }, 5505 .probe = panel_simple_platform_probe, 5506 .remove = panel_simple_platform_remove, 5507 .shutdown = panel_simple_platform_shutdown, 5508 }; 5509 5510 static const struct drm_display_mode auo_b080uan01_mode = { 5511 .clock = 154500, 5512 .hdisplay = 1200, 5513 .hsync_start = 1200 + 62, 5514 .hsync_end = 1200 + 62 + 4, 5515 .htotal = 1200 + 62 + 4 + 62, 5516 .vdisplay = 1920, 5517 .vsync_start = 1920 + 9, 5518 .vsync_end = 1920 + 9 + 2, 5519 .vtotal = 1920 + 9 + 2 + 8, 5520 }; 5521 5522 static const struct panel_desc_dsi auo_b080uan01 = { 5523 .desc = { 5524 .modes = &auo_b080uan01_mode, 5525 .num_modes = 1, 5526 .bpc = 8, 5527 .size = { 5528 .width = 108, 5529 .height = 272, 5530 }, 5531 .connector_type = DRM_MODE_CONNECTOR_DSI, 5532 }, 5533 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5534 .format = MIPI_DSI_FMT_RGB888, 5535 .lanes = 4, 5536 }; 5537 5538 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5539 .clock = 160000, 5540 .hdisplay = 1200, 5541 .hsync_start = 1200 + 120, 5542 .hsync_end = 1200 + 120 + 20, 5543 .htotal = 1200 + 120 + 20 + 21, 5544 .vdisplay = 1920, 5545 .vsync_start = 1920 + 21, 5546 .vsync_end = 1920 + 21 + 3, 5547 .vtotal = 1920 + 21 + 3 + 18, 5548 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5549 }; 5550 5551 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5552 .desc = { 5553 .modes = &boe_tv080wum_nl0_mode, 5554 .num_modes = 1, 5555 .size = { 5556 .width = 107, 5557 .height = 172, 5558 }, 5559 .connector_type = DRM_MODE_CONNECTOR_DSI, 5560 }, 5561 .flags = MIPI_DSI_MODE_VIDEO | 5562 MIPI_DSI_MODE_VIDEO_BURST | 5563 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5564 .format = MIPI_DSI_FMT_RGB888, 5565 .lanes = 4, 5566 }; 5567 5568 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5569 .clock = 71000, 5570 .hdisplay = 800, 5571 .hsync_start = 800 + 32, 5572 .hsync_end = 800 + 32 + 1, 5573 .htotal = 800 + 32 + 1 + 57, 5574 .vdisplay = 1280, 5575 .vsync_start = 1280 + 28, 5576 .vsync_end = 1280 + 28 + 1, 5577 .vtotal = 1280 + 28 + 1 + 14, 5578 }; 5579 5580 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5581 .desc = { 5582 .modes = &lg_ld070wx3_sl01_mode, 5583 .num_modes = 1, 5584 .bpc = 8, 5585 .size = { 5586 .width = 94, 5587 .height = 151, 5588 }, 5589 .connector_type = DRM_MODE_CONNECTOR_DSI, 5590 }, 5591 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5592 .format = MIPI_DSI_FMT_RGB888, 5593 .lanes = 4, 5594 }; 5595 5596 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5597 .clock = 67000, 5598 .hdisplay = 720, 5599 .hsync_start = 720 + 12, 5600 .hsync_end = 720 + 12 + 4, 5601 .htotal = 720 + 12 + 4 + 112, 5602 .vdisplay = 1280, 5603 .vsync_start = 1280 + 8, 5604 .vsync_end = 1280 + 8 + 4, 5605 .vtotal = 1280 + 8 + 4 + 12, 5606 }; 5607 5608 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5609 .desc = { 5610 .modes = &lg_lh500wx1_sd03_mode, 5611 .num_modes = 1, 5612 .bpc = 8, 5613 .size = { 5614 .width = 62, 5615 .height = 110, 5616 }, 5617 .connector_type = DRM_MODE_CONNECTOR_DSI, 5618 }, 5619 .flags = MIPI_DSI_MODE_VIDEO, 5620 .format = MIPI_DSI_FMT_RGB888, 5621 .lanes = 4, 5622 }; 5623 5624 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5625 .clock = 157200, 5626 .hdisplay = 1920, 5627 .hsync_start = 1920 + 154, 5628 .hsync_end = 1920 + 154 + 16, 5629 .htotal = 1920 + 154 + 16 + 32, 5630 .vdisplay = 1200, 5631 .vsync_start = 1200 + 17, 5632 .vsync_end = 1200 + 17 + 2, 5633 .vtotal = 1200 + 17 + 2 + 16, 5634 }; 5635 5636 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5637 .desc = { 5638 .modes = &panasonic_vvx10f004b00_mode, 5639 .num_modes = 1, 5640 .bpc = 8, 5641 .size = { 5642 .width = 217, 5643 .height = 136, 5644 }, 5645 .connector_type = DRM_MODE_CONNECTOR_DSI, 5646 }, 5647 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5648 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5649 .format = MIPI_DSI_FMT_RGB888, 5650 .lanes = 4, 5651 }; 5652 5653 static const struct drm_display_mode lg_acx467akm_7_mode = { 5654 .clock = 150000, 5655 .hdisplay = 1080, 5656 .hsync_start = 1080 + 2, 5657 .hsync_end = 1080 + 2 + 2, 5658 .htotal = 1080 + 2 + 2 + 2, 5659 .vdisplay = 1920, 5660 .vsync_start = 1920 + 2, 5661 .vsync_end = 1920 + 2 + 2, 5662 .vtotal = 1920 + 2 + 2 + 2, 5663 }; 5664 5665 static const struct panel_desc_dsi lg_acx467akm_7 = { 5666 .desc = { 5667 .modes = &lg_acx467akm_7_mode, 5668 .num_modes = 1, 5669 .bpc = 8, 5670 .size = { 5671 .width = 62, 5672 .height = 110, 5673 }, 5674 .connector_type = DRM_MODE_CONNECTOR_DSI, 5675 }, 5676 .flags = 0, 5677 .format = MIPI_DSI_FMT_RGB888, 5678 .lanes = 4, 5679 }; 5680 5681 static const struct drm_display_mode osd101t2045_53ts_mode = { 5682 .clock = 154500, 5683 .hdisplay = 1920, 5684 .hsync_start = 1920 + 112, 5685 .hsync_end = 1920 + 112 + 16, 5686 .htotal = 1920 + 112 + 16 + 32, 5687 .vdisplay = 1200, 5688 .vsync_start = 1200 + 16, 5689 .vsync_end = 1200 + 16 + 2, 5690 .vtotal = 1200 + 16 + 2 + 16, 5691 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5692 }; 5693 5694 static const struct panel_desc_dsi osd101t2045_53ts = { 5695 .desc = { 5696 .modes = &osd101t2045_53ts_mode, 5697 .num_modes = 1, 5698 .bpc = 8, 5699 .size = { 5700 .width = 217, 5701 .height = 136, 5702 }, 5703 .connector_type = DRM_MODE_CONNECTOR_DSI, 5704 }, 5705 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5706 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5707 MIPI_DSI_MODE_NO_EOT_PACKET, 5708 .format = MIPI_DSI_FMT_RGB888, 5709 .lanes = 4, 5710 }; 5711 5712 static const struct of_device_id dsi_of_match[] = { 5713 { 5714 .compatible = "auo,b080uan01", 5715 .data = &auo_b080uan01 5716 }, { 5717 .compatible = "boe,tv080wum-nl0", 5718 .data = &boe_tv080wum_nl0 5719 }, { 5720 .compatible = "lg,ld070wx3-sl01", 5721 .data = &lg_ld070wx3_sl01 5722 }, { 5723 .compatible = "lg,lh500wx1-sd03", 5724 .data = &lg_lh500wx1_sd03 5725 }, { 5726 .compatible = "panasonic,vvx10f004b00", 5727 .data = &panasonic_vvx10f004b00 5728 }, { 5729 .compatible = "lg,acx467akm-7", 5730 .data = &lg_acx467akm_7 5731 }, { 5732 .compatible = "osddisplays,osd101t2045-53ts", 5733 .data = &osd101t2045_53ts 5734 }, { 5735 /* sentinel */ 5736 } 5737 }; 5738 MODULE_DEVICE_TABLE(of, dsi_of_match); 5739 5740 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5741 { 5742 const struct panel_desc_dsi *desc; 5743 struct panel_simple *panel; 5744 int err; 5745 5746 panel = panel_simple_probe(&dsi->dev); 5747 if (IS_ERR(panel)) 5748 return PTR_ERR(panel); 5749 5750 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5751 dsi->mode_flags = desc->flags; 5752 dsi->format = desc->format; 5753 dsi->lanes = desc->lanes; 5754 5755 err = mipi_dsi_attach(dsi); 5756 if (err) { 5757 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5758 5759 drm_panel_remove(&panel->base); 5760 } 5761 5762 return err; 5763 } 5764 5765 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5766 { 5767 int err; 5768 5769 err = mipi_dsi_detach(dsi); 5770 if (err < 0) 5771 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5772 5773 panel_simple_remove(&dsi->dev); 5774 } 5775 5776 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5777 { 5778 panel_simple_shutdown(&dsi->dev); 5779 } 5780 5781 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5782 .driver = { 5783 .name = "panel-simple-dsi", 5784 .of_match_table = dsi_of_match, 5785 .pm = &panel_simple_pm_ops, 5786 }, 5787 .probe = panel_simple_dsi_probe, 5788 .remove = panel_simple_dsi_remove, 5789 .shutdown = panel_simple_dsi_shutdown, 5790 }; 5791 5792 static int __init panel_simple_init(void) 5793 { 5794 int err; 5795 5796 err = platform_driver_register(&panel_simple_platform_driver); 5797 if (err < 0) 5798 return err; 5799 5800 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5801 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5802 if (err < 0) 5803 goto err_did_platform_register; 5804 } 5805 5806 return 0; 5807 5808 err_did_platform_register: 5809 platform_driver_unregister(&panel_simple_platform_driver); 5810 5811 return err; 5812 } 5813 module_init(panel_simple_init); 5814 5815 static void __exit panel_simple_exit(void) 5816 { 5817 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5818 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5819 5820 platform_driver_unregister(&panel_simple_platform_driver); 5821 } 5822 module_exit(panel_simple_exit); 5823 5824 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5825 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5826 MODULE_LICENSE("GPL and additional rights"); 5827