1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 583 if (!panel) 584 return -ENOMEM; 585 586 panel->desc = desc; 587 588 panel->supply = devm_regulator_get(dev, "power"); 589 if (IS_ERR(panel->supply)) 590 return PTR_ERR(panel->supply); 591 592 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 593 GPIOD_OUT_LOW); 594 if (IS_ERR(panel->enable_gpio)) 595 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 596 "failed to request GPIO\n"); 597 598 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 599 if (err) { 600 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 601 return err; 602 } 603 604 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 605 if (ddc) { 606 panel->ddc = of_find_i2c_adapter_by_node(ddc); 607 of_node_put(ddc); 608 609 if (!panel->ddc) 610 return -EPROBE_DEFER; 611 } 612 613 if (desc == &panel_dpi) { 614 /* Handle the generic panel-dpi binding */ 615 err = panel_dpi_probe(dev, panel); 616 if (err) 617 goto free_ddc; 618 desc = panel->desc; 619 } else { 620 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 621 panel_simple_parse_panel_timing_node(dev, panel, &dt); 622 } 623 624 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 625 /* Optional data-mapping property for overriding bus format */ 626 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 627 if (err) 628 goto free_ddc; 629 } 630 631 connector_type = desc->connector_type; 632 /* Catch common mistakes for panels. */ 633 switch (connector_type) { 634 case 0: 635 dev_warn(dev, "Specify missing connector_type\n"); 636 connector_type = DRM_MODE_CONNECTOR_DPI; 637 break; 638 case DRM_MODE_CONNECTOR_LVDS: 639 WARN_ON(desc->bus_flags & 640 ~(DRM_BUS_FLAG_DE_LOW | 641 DRM_BUS_FLAG_DE_HIGH | 642 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 643 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 644 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 645 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 647 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 648 desc->bpc != 6); 649 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 650 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 651 desc->bpc != 8); 652 break; 653 case DRM_MODE_CONNECTOR_eDP: 654 dev_warn(dev, "eDP panels moved to panel-edp\n"); 655 err = -EINVAL; 656 goto free_ddc; 657 case DRM_MODE_CONNECTOR_DSI: 658 if (desc->bpc != 6 && desc->bpc != 8) 659 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 660 break; 661 case DRM_MODE_CONNECTOR_DPI: 662 bus_flags = DRM_BUS_FLAG_DE_LOW | 663 DRM_BUS_FLAG_DE_HIGH | 664 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 666 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 667 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 668 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 669 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 670 if (desc->bus_flags & ~bus_flags) 671 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 672 if (!(desc->bus_flags & bus_flags)) 673 dev_warn(dev, "Specify missing bus_flags\n"); 674 if (desc->bus_format == 0) 675 dev_warn(dev, "Specify missing bus_format\n"); 676 if (desc->bpc != 6 && desc->bpc != 8) 677 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 678 break; 679 default: 680 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 681 connector_type = DRM_MODE_CONNECTOR_DPI; 682 break; 683 } 684 685 dev_set_drvdata(dev, panel); 686 687 /* 688 * We use runtime PM for prepare / unprepare since those power the panel 689 * on and off and those can be very slow operations. This is important 690 * to optimize powering the panel on briefly to read the EDID before 691 * fully enabling the panel. 692 */ 693 pm_runtime_enable(dev); 694 pm_runtime_set_autosuspend_delay(dev, 1000); 695 pm_runtime_use_autosuspend(dev); 696 697 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 698 699 err = drm_panel_of_backlight(&panel->base); 700 if (err) { 701 dev_err_probe(dev, err, "Could not find backlight\n"); 702 goto disable_pm_runtime; 703 } 704 705 drm_panel_add(&panel->base); 706 707 return 0; 708 709 disable_pm_runtime: 710 pm_runtime_dont_use_autosuspend(dev); 711 pm_runtime_disable(dev); 712 free_ddc: 713 if (panel->ddc) 714 put_device(&panel->ddc->dev); 715 716 return err; 717 } 718 719 static void panel_simple_shutdown(struct device *dev) 720 { 721 struct panel_simple *panel = dev_get_drvdata(dev); 722 723 /* 724 * NOTE: the following two calls don't really belong here. It is the 725 * responsibility of a correctly written DRM modeset driver to call 726 * drm_atomic_helper_shutdown() at shutdown time and that should 727 * cause the panel to be disabled / unprepared if needed. For now, 728 * however, we'll keep these calls due to the sheer number of 729 * different DRM modeset drivers used with panel-simple. The fact that 730 * we're calling these and _also_ the drm_atomic_helper_shutdown() 731 * will try to disable/unprepare means that we can get a warning about 732 * trying to disable/unprepare an already disabled/unprepared panel, 733 * but that's something we'll have to live with until we've confirmed 734 * that all DRM modeset drivers are properly calling 735 * drm_atomic_helper_shutdown(). 736 */ 737 drm_panel_disable(&panel->base); 738 drm_panel_unprepare(&panel->base); 739 } 740 741 static void panel_simple_remove(struct device *dev) 742 { 743 struct panel_simple *panel = dev_get_drvdata(dev); 744 745 drm_panel_remove(&panel->base); 746 panel_simple_shutdown(dev); 747 748 pm_runtime_dont_use_autosuspend(dev); 749 pm_runtime_disable(dev); 750 if (panel->ddc) 751 put_device(&panel->ddc->dev); 752 } 753 754 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 755 .clock = 71100, 756 .hdisplay = 1280, 757 .hsync_start = 1280 + 40, 758 .hsync_end = 1280 + 40 + 80, 759 .htotal = 1280 + 40 + 80 + 40, 760 .vdisplay = 800, 761 .vsync_start = 800 + 3, 762 .vsync_end = 800 + 3 + 10, 763 .vtotal = 800 + 3 + 10 + 10, 764 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 765 }; 766 767 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 768 .modes = &ire_am_1280800n3tzqw_t00h_mode, 769 .num_modes = 1, 770 .bpc = 8, 771 .size = { 772 .width = 217, 773 .height = 136, 774 }, 775 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 776 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 778 }; 779 780 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 781 .clock = 9000, 782 .hdisplay = 480, 783 .hsync_start = 480 + 2, 784 .hsync_end = 480 + 2 + 41, 785 .htotal = 480 + 2 + 41 + 2, 786 .vdisplay = 272, 787 .vsync_start = 272 + 2, 788 .vsync_end = 272 + 2 + 10, 789 .vtotal = 272 + 2 + 10 + 2, 790 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 791 }; 792 793 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 794 .modes = &ire_am_480272h3tmqw_t01h_mode, 795 .num_modes = 1, 796 .bpc = 8, 797 .size = { 798 .width = 99, 799 .height = 58, 800 }, 801 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 802 }; 803 804 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 805 .clock = 33333, 806 .hdisplay = 800, 807 .hsync_start = 800 + 0, 808 .hsync_end = 800 + 0 + 255, 809 .htotal = 800 + 0 + 255 + 0, 810 .vdisplay = 480, 811 .vsync_start = 480 + 2, 812 .vsync_end = 480 + 2 + 45, 813 .vtotal = 480 + 2 + 45 + 0, 814 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 815 }; 816 817 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 818 .pixelclock = { 29930000, 33260000, 36590000 }, 819 .hactive = { 800, 800, 800 }, 820 .hfront_porch = { 1, 40, 168 }, 821 .hback_porch = { 88, 88, 88 }, 822 .hsync_len = { 1, 128, 128 }, 823 .vactive = { 480, 480, 480 }, 824 .vfront_porch = { 1, 35, 37 }, 825 .vback_porch = { 8, 8, 8 }, 826 .vsync_len = { 1, 2, 2 }, 827 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 828 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 829 DISPLAY_FLAGS_SYNC_POSEDGE, 830 }; 831 832 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 833 .timings = &ire_am_800480l1tmqw_t00h_timing, 834 .num_timings = 1, 835 .bpc = 8, 836 .size = { 837 .width = 111, 838 .height = 67, 839 }, 840 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 841 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 842 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 843 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 844 .connector_type = DRM_MODE_CONNECTOR_DPI, 845 }; 846 847 static const struct panel_desc ampire_am800480r3tmqwa1h = { 848 .modes = &ire_am800480r3tmqwa1h_mode, 849 .num_modes = 1, 850 .bpc = 6, 851 .size = { 852 .width = 152, 853 .height = 91, 854 }, 855 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 856 }; 857 858 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 859 .pixelclock = { 34500000, 39600000, 50400000 }, 860 .hactive = { 800, 800, 800 }, 861 .hfront_porch = { 12, 112, 312 }, 862 .hback_porch = { 87, 87, 48 }, 863 .hsync_len = { 1, 1, 40 }, 864 .vactive = { 600, 600, 600 }, 865 .vfront_porch = { 1, 21, 61 }, 866 .vback_porch = { 38, 38, 19 }, 867 .vsync_len = { 1, 1, 20 }, 868 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 869 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 870 DISPLAY_FLAGS_SYNC_POSEDGE, 871 }; 872 873 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 874 .timings = &ire_am800600p5tmqw_tb8h_timing, 875 .num_timings = 1, 876 .bpc = 6, 877 .size = { 878 .width = 162, 879 .height = 122, 880 }, 881 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 882 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 883 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 884 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 885 .connector_type = DRM_MODE_CONNECTOR_DPI, 886 }; 887 888 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 889 .pixelclock = { 26400000, 33300000, 46800000 }, 890 .hactive = { 800, 800, 800 }, 891 .hfront_porch = { 16, 210, 354 }, 892 .hback_porch = { 45, 36, 6 }, 893 .hsync_len = { 1, 10, 40 }, 894 .vactive = { 480, 480, 480 }, 895 .vfront_porch = { 7, 22, 147 }, 896 .vback_porch = { 22, 13, 3 }, 897 .vsync_len = { 1, 10, 20 }, 898 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 899 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 900 }; 901 902 static const struct panel_desc armadeus_st0700_adapt = { 903 .timings = &santek_st0700i5y_rbslw_f_timing, 904 .num_timings = 1, 905 .bpc = 6, 906 .size = { 907 .width = 154, 908 .height = 86, 909 }, 910 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 911 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 912 }; 913 914 static const struct drm_display_mode auo_b101aw03_mode = { 915 .clock = 51450, 916 .hdisplay = 1024, 917 .hsync_start = 1024 + 156, 918 .hsync_end = 1024 + 156 + 8, 919 .htotal = 1024 + 156 + 8 + 156, 920 .vdisplay = 600, 921 .vsync_start = 600 + 16, 922 .vsync_end = 600 + 16 + 6, 923 .vtotal = 600 + 16 + 6 + 16, 924 }; 925 926 static const struct panel_desc auo_b101aw03 = { 927 .modes = &auo_b101aw03_mode, 928 .num_modes = 1, 929 .bpc = 6, 930 .size = { 931 .width = 223, 932 .height = 125, 933 }, 934 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 935 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 936 .connector_type = DRM_MODE_CONNECTOR_LVDS, 937 }; 938 939 static const struct drm_display_mode auo_b101xtn01_mode = { 940 .clock = 72000, 941 .hdisplay = 1366, 942 .hsync_start = 1366 + 20, 943 .hsync_end = 1366 + 20 + 70, 944 .htotal = 1366 + 20 + 70, 945 .vdisplay = 768, 946 .vsync_start = 768 + 14, 947 .vsync_end = 768 + 14 + 42, 948 .vtotal = 768 + 14 + 42, 949 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 950 }; 951 952 static const struct panel_desc auo_b101xtn01 = { 953 .modes = &auo_b101xtn01_mode, 954 .num_modes = 1, 955 .bpc = 6, 956 .size = { 957 .width = 223, 958 .height = 125, 959 }, 960 }; 961 962 static const struct drm_display_mode auo_b116xw03_mode = { 963 .clock = 70589, 964 .hdisplay = 1366, 965 .hsync_start = 1366 + 40, 966 .hsync_end = 1366 + 40 + 40, 967 .htotal = 1366 + 40 + 40 + 32, 968 .vdisplay = 768, 969 .vsync_start = 768 + 10, 970 .vsync_end = 768 + 10 + 12, 971 .vtotal = 768 + 10 + 12 + 6, 972 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 973 }; 974 975 static const struct panel_desc auo_b116xw03 = { 976 .modes = &auo_b116xw03_mode, 977 .num_modes = 1, 978 .bpc = 6, 979 .size = { 980 .width = 256, 981 .height = 144, 982 }, 983 .delay = { 984 .prepare = 1, 985 .enable = 200, 986 .disable = 200, 987 .unprepare = 500, 988 }, 989 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 990 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 991 .connector_type = DRM_MODE_CONNECTOR_LVDS, 992 }; 993 994 static const struct display_timing auo_g070vvn01_timings = { 995 .pixelclock = { 33300000, 34209000, 45000000 }, 996 .hactive = { 800, 800, 800 }, 997 .hfront_porch = { 20, 40, 200 }, 998 .hback_porch = { 87, 40, 1 }, 999 .hsync_len = { 1, 48, 87 }, 1000 .vactive = { 480, 480, 480 }, 1001 .vfront_porch = { 5, 13, 200 }, 1002 .vback_porch = { 31, 31, 29 }, 1003 .vsync_len = { 1, 1, 3 }, 1004 }; 1005 1006 static const struct panel_desc auo_g070vvn01 = { 1007 .timings = &auo_g070vvn01_timings, 1008 .num_timings = 1, 1009 .bpc = 8, 1010 .size = { 1011 .width = 152, 1012 .height = 91, 1013 }, 1014 .delay = { 1015 .prepare = 200, 1016 .enable = 50, 1017 .disable = 50, 1018 .unprepare = 1000, 1019 }, 1020 }; 1021 1022 static const struct drm_display_mode auo_g101evn010_mode = { 1023 .clock = 68930, 1024 .hdisplay = 1280, 1025 .hsync_start = 1280 + 82, 1026 .hsync_end = 1280 + 82 + 2, 1027 .htotal = 1280 + 82 + 2 + 84, 1028 .vdisplay = 800, 1029 .vsync_start = 800 + 8, 1030 .vsync_end = 800 + 8 + 2, 1031 .vtotal = 800 + 8 + 2 + 6, 1032 }; 1033 1034 static const struct panel_desc auo_g101evn010 = { 1035 .modes = &auo_g101evn010_mode, 1036 .num_modes = 1, 1037 .bpc = 6, 1038 .size = { 1039 .width = 216, 1040 .height = 135, 1041 }, 1042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1043 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1044 }; 1045 1046 static const struct drm_display_mode auo_g104sn02_mode = { 1047 .clock = 40000, 1048 .hdisplay = 800, 1049 .hsync_start = 800 + 40, 1050 .hsync_end = 800 + 40 + 216, 1051 .htotal = 800 + 40 + 216 + 128, 1052 .vdisplay = 600, 1053 .vsync_start = 600 + 10, 1054 .vsync_end = 600 + 10 + 35, 1055 .vtotal = 600 + 10 + 35 + 2, 1056 }; 1057 1058 static const struct panel_desc auo_g104sn02 = { 1059 .modes = &auo_g104sn02_mode, 1060 .num_modes = 1, 1061 .bpc = 8, 1062 .size = { 1063 .width = 211, 1064 .height = 158, 1065 }, 1066 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1067 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1068 }; 1069 1070 static const struct display_timing auo_g121ean01_timing = { 1071 .pixelclock = { 60000000, 74400000, 90000000 }, 1072 .hactive = { 1280, 1280, 1280 }, 1073 .hfront_porch = { 20, 50, 100 }, 1074 .hback_porch = { 20, 50, 100 }, 1075 .hsync_len = { 30, 100, 200 }, 1076 .vactive = { 800, 800, 800 }, 1077 .vfront_porch = { 2, 10, 25 }, 1078 .vback_porch = { 2, 10, 25 }, 1079 .vsync_len = { 4, 18, 50 }, 1080 }; 1081 1082 static const struct panel_desc auo_g121ean01 = { 1083 .timings = &auo_g121ean01_timing, 1084 .num_timings = 1, 1085 .bpc = 8, 1086 .size = { 1087 .width = 261, 1088 .height = 163, 1089 }, 1090 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1091 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1092 }; 1093 1094 static const struct display_timing auo_g133han01_timings = { 1095 .pixelclock = { 134000000, 141200000, 149000000 }, 1096 .hactive = { 1920, 1920, 1920 }, 1097 .hfront_porch = { 39, 58, 77 }, 1098 .hback_porch = { 59, 88, 117 }, 1099 .hsync_len = { 28, 42, 56 }, 1100 .vactive = { 1080, 1080, 1080 }, 1101 .vfront_porch = { 3, 8, 11 }, 1102 .vback_porch = { 5, 14, 19 }, 1103 .vsync_len = { 4, 14, 19 }, 1104 }; 1105 1106 static const struct panel_desc auo_g133han01 = { 1107 .timings = &auo_g133han01_timings, 1108 .num_timings = 1, 1109 .bpc = 8, 1110 .size = { 1111 .width = 293, 1112 .height = 165, 1113 }, 1114 .delay = { 1115 .prepare = 200, 1116 .enable = 50, 1117 .disable = 50, 1118 .unprepare = 1000, 1119 }, 1120 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1121 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1122 }; 1123 1124 static const struct display_timing auo_g156han04_timings = { 1125 .pixelclock = { 137000000, 141000000, 146000000 }, 1126 .hactive = { 1920, 1920, 1920 }, 1127 .hfront_porch = { 60, 60, 60 }, 1128 .hback_porch = { 90, 92, 111 }, 1129 .hsync_len = { 32, 32, 32 }, 1130 .vactive = { 1080, 1080, 1080 }, 1131 .vfront_porch = { 12, 12, 12 }, 1132 .vback_porch = { 24, 36, 56 }, 1133 .vsync_len = { 8, 8, 8 }, 1134 }; 1135 1136 static const struct panel_desc auo_g156han04 = { 1137 .timings = &auo_g156han04_timings, 1138 .num_timings = 1, 1139 .bpc = 8, 1140 .size = { 1141 .width = 344, 1142 .height = 194, 1143 }, 1144 .delay = { 1145 .prepare = 50, /* T2 */ 1146 .enable = 200, /* T3 */ 1147 .disable = 110, /* T10 */ 1148 .unprepare = 1000, /* T13 */ 1149 }, 1150 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1151 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1152 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1153 }; 1154 1155 static const struct drm_display_mode auo_g156xtn01_mode = { 1156 .clock = 76000, 1157 .hdisplay = 1366, 1158 .hsync_start = 1366 + 33, 1159 .hsync_end = 1366 + 33 + 67, 1160 .htotal = 1560, 1161 .vdisplay = 768, 1162 .vsync_start = 768 + 4, 1163 .vsync_end = 768 + 4 + 4, 1164 .vtotal = 806, 1165 }; 1166 1167 static const struct panel_desc auo_g156xtn01 = { 1168 .modes = &auo_g156xtn01_mode, 1169 .num_modes = 1, 1170 .bpc = 8, 1171 .size = { 1172 .width = 344, 1173 .height = 194, 1174 }, 1175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1177 }; 1178 1179 static const struct display_timing auo_g185han01_timings = { 1180 .pixelclock = { 120000000, 144000000, 175000000 }, 1181 .hactive = { 1920, 1920, 1920 }, 1182 .hfront_porch = { 36, 120, 148 }, 1183 .hback_porch = { 24, 88, 108 }, 1184 .hsync_len = { 20, 48, 64 }, 1185 .vactive = { 1080, 1080, 1080 }, 1186 .vfront_porch = { 6, 10, 40 }, 1187 .vback_porch = { 2, 5, 20 }, 1188 .vsync_len = { 2, 5, 20 }, 1189 }; 1190 1191 static const struct panel_desc auo_g185han01 = { 1192 .timings = &auo_g185han01_timings, 1193 .num_timings = 1, 1194 .bpc = 8, 1195 .size = { 1196 .width = 409, 1197 .height = 230, 1198 }, 1199 .delay = { 1200 .prepare = 50, 1201 .enable = 200, 1202 .disable = 110, 1203 .unprepare = 1000, 1204 }, 1205 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1206 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1207 }; 1208 1209 static const struct display_timing auo_g190ean01_timings = { 1210 .pixelclock = { 90000000, 108000000, 135000000 }, 1211 .hactive = { 1280, 1280, 1280 }, 1212 .hfront_porch = { 126, 184, 1266 }, 1213 .hback_porch = { 84, 122, 844 }, 1214 .hsync_len = { 70, 102, 704 }, 1215 .vactive = { 1024, 1024, 1024 }, 1216 .vfront_porch = { 4, 26, 76 }, 1217 .vback_porch = { 2, 8, 25 }, 1218 .vsync_len = { 2, 8, 25 }, 1219 }; 1220 1221 static const struct panel_desc auo_g190ean01 = { 1222 .timings = &auo_g190ean01_timings, 1223 .num_timings = 1, 1224 .bpc = 8, 1225 .size = { 1226 .width = 376, 1227 .height = 301, 1228 }, 1229 .delay = { 1230 .prepare = 50, 1231 .enable = 200, 1232 .disable = 110, 1233 .unprepare = 1000, 1234 }, 1235 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1236 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1237 }; 1238 1239 static const struct display_timing auo_p320hvn03_timings = { 1240 .pixelclock = { 106000000, 148500000, 164000000 }, 1241 .hactive = { 1920, 1920, 1920 }, 1242 .hfront_porch = { 25, 50, 130 }, 1243 .hback_porch = { 25, 50, 130 }, 1244 .hsync_len = { 20, 40, 105 }, 1245 .vactive = { 1080, 1080, 1080 }, 1246 .vfront_porch = { 8, 17, 150 }, 1247 .vback_porch = { 8, 17, 150 }, 1248 .vsync_len = { 4, 11, 100 }, 1249 }; 1250 1251 static const struct panel_desc auo_p320hvn03 = { 1252 .timings = &auo_p320hvn03_timings, 1253 .num_timings = 1, 1254 .bpc = 8, 1255 .size = { 1256 .width = 698, 1257 .height = 393, 1258 }, 1259 .delay = { 1260 .prepare = 1, 1261 .enable = 450, 1262 .unprepare = 500, 1263 }, 1264 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1265 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1266 }; 1267 1268 static const struct drm_display_mode auo_t215hvn01_mode = { 1269 .clock = 148800, 1270 .hdisplay = 1920, 1271 .hsync_start = 1920 + 88, 1272 .hsync_end = 1920 + 88 + 44, 1273 .htotal = 1920 + 88 + 44 + 148, 1274 .vdisplay = 1080, 1275 .vsync_start = 1080 + 4, 1276 .vsync_end = 1080 + 4 + 5, 1277 .vtotal = 1080 + 4 + 5 + 36, 1278 }; 1279 1280 static const struct panel_desc auo_t215hvn01 = { 1281 .modes = &auo_t215hvn01_mode, 1282 .num_modes = 1, 1283 .bpc = 8, 1284 .size = { 1285 .width = 430, 1286 .height = 270, 1287 }, 1288 .delay = { 1289 .disable = 5, 1290 .unprepare = 1000, 1291 }, 1292 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1293 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1294 }; 1295 1296 static const struct drm_display_mode avic_tm070ddh03_mode = { 1297 .clock = 51200, 1298 .hdisplay = 1024, 1299 .hsync_start = 1024 + 160, 1300 .hsync_end = 1024 + 160 + 4, 1301 .htotal = 1024 + 160 + 4 + 156, 1302 .vdisplay = 600, 1303 .vsync_start = 600 + 17, 1304 .vsync_end = 600 + 17 + 1, 1305 .vtotal = 600 + 17 + 1 + 17, 1306 }; 1307 1308 static const struct panel_desc avic_tm070ddh03 = { 1309 .modes = &avic_tm070ddh03_mode, 1310 .num_modes = 1, 1311 .bpc = 8, 1312 .size = { 1313 .width = 154, 1314 .height = 90, 1315 }, 1316 .delay = { 1317 .prepare = 20, 1318 .enable = 200, 1319 .disable = 200, 1320 }, 1321 }; 1322 1323 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1324 .clock = 30000, 1325 .hdisplay = 800, 1326 .hsync_start = 800 + 40, 1327 .hsync_end = 800 + 40 + 48, 1328 .htotal = 800 + 40 + 48 + 40, 1329 .vdisplay = 480, 1330 .vsync_start = 480 + 13, 1331 .vsync_end = 480 + 13 + 3, 1332 .vtotal = 480 + 13 + 3 + 29, 1333 }; 1334 1335 static const struct panel_desc bananapi_s070wv20_ct16 = { 1336 .modes = &bananapi_s070wv20_ct16_mode, 1337 .num_modes = 1, 1338 .bpc = 6, 1339 .size = { 1340 .width = 154, 1341 .height = 86, 1342 }, 1343 }; 1344 1345 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1346 .clock = 78945, 1347 .hdisplay = 1280, 1348 .hsync_start = 1280 + 0, 1349 .hsync_end = 1280 + 0 + 2, 1350 .htotal = 1280 + 62 + 0 + 2, 1351 .vdisplay = 800, 1352 .vsync_start = 800 + 8, 1353 .vsync_end = 800 + 8 + 2, 1354 .vtotal = 800 + 6 + 8 + 2, 1355 }; 1356 1357 static const struct panel_desc boe_bp082wx1_100 = { 1358 .modes = &boe_bp101wx1_100_mode, 1359 .num_modes = 1, 1360 .bpc = 8, 1361 .size = { 1362 .width = 177, 1363 .height = 110, 1364 }, 1365 .delay = { 1366 .enable = 50, 1367 .disable = 50, 1368 }, 1369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1370 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1371 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1372 }; 1373 1374 static const struct panel_desc boe_bp101wx1_100 = { 1375 .modes = &boe_bp101wx1_100_mode, 1376 .num_modes = 1, 1377 .bpc = 8, 1378 .size = { 1379 .width = 217, 1380 .height = 136, 1381 }, 1382 .delay = { 1383 .enable = 50, 1384 .disable = 50, 1385 }, 1386 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1387 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1388 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1389 }; 1390 1391 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1392 .pixelclock = { 69922000, 71000000, 72293000 }, 1393 .hactive = { 1280, 1280, 1280 }, 1394 .hfront_porch = { 48, 48, 48 }, 1395 .hback_porch = { 80, 80, 80 }, 1396 .hsync_len = { 32, 32, 32 }, 1397 .vactive = { 800, 800, 800 }, 1398 .vfront_porch = { 3, 3, 3 }, 1399 .vback_porch = { 14, 14, 14 }, 1400 .vsync_len = { 6, 6, 6 }, 1401 }; 1402 1403 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1404 .timings = &boe_ev121wxm_n10_1850_timing, 1405 .num_timings = 1, 1406 .bpc = 8, 1407 .size = { 1408 .width = 261, 1409 .height = 163, 1410 }, 1411 .delay = { 1412 .prepare = 9, 1413 .enable = 300, 1414 .unprepare = 300, 1415 .disable = 560, 1416 }, 1417 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1418 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1419 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1420 }; 1421 1422 static const struct drm_display_mode boe_hv070wsa_mode = { 1423 .clock = 42105, 1424 .hdisplay = 1024, 1425 .hsync_start = 1024 + 30, 1426 .hsync_end = 1024 + 30 + 30, 1427 .htotal = 1024 + 30 + 30 + 30, 1428 .vdisplay = 600, 1429 .vsync_start = 600 + 10, 1430 .vsync_end = 600 + 10 + 10, 1431 .vtotal = 600 + 10 + 10 + 10, 1432 }; 1433 1434 static const struct panel_desc boe_hv070wsa = { 1435 .modes = &boe_hv070wsa_mode, 1436 .num_modes = 1, 1437 .bpc = 8, 1438 .size = { 1439 .width = 154, 1440 .height = 90, 1441 }, 1442 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1443 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1444 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1445 }; 1446 1447 static const struct display_timing cct_cmt430b19n00_timing = { 1448 .pixelclock = { 8000000, 9000000, 12000000 }, 1449 .hactive = { 480, 480, 480 }, 1450 .hfront_porch = { 2, 8, 75 }, 1451 .hback_porch = { 3, 43, 43 }, 1452 .hsync_len = { 2, 4, 75 }, 1453 .vactive = { 272, 272, 272 }, 1454 .vfront_porch = { 2, 8, 37 }, 1455 .vback_porch = { 2, 12, 12 }, 1456 .vsync_len = { 2, 4, 37 }, 1457 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1458 }; 1459 1460 static const struct panel_desc cct_cmt430b19n00 = { 1461 .timings = &cct_cmt430b19n00_timing, 1462 .num_timings = 1, 1463 .bpc = 8, 1464 .size = { 1465 .width = 95, 1466 .height = 53, 1467 }, 1468 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1469 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1470 .connector_type = DRM_MODE_CONNECTOR_DPI, 1471 }; 1472 1473 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1474 .clock = 9000, 1475 .hdisplay = 480, 1476 .hsync_start = 480 + 5, 1477 .hsync_end = 480 + 5 + 5, 1478 .htotal = 480 + 5 + 5 + 40, 1479 .vdisplay = 272, 1480 .vsync_start = 272 + 8, 1481 .vsync_end = 272 + 8 + 8, 1482 .vtotal = 272 + 8 + 8 + 8, 1483 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1484 }; 1485 1486 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1487 .modes = &cdtech_s043wq26h_ct7_mode, 1488 .num_modes = 1, 1489 .bpc = 8, 1490 .size = { 1491 .width = 95, 1492 .height = 54, 1493 }, 1494 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1495 }; 1496 1497 /* S070PWS19HP-FC21 2017/04/22 */ 1498 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1499 .clock = 51200, 1500 .hdisplay = 1024, 1501 .hsync_start = 1024 + 160, 1502 .hsync_end = 1024 + 160 + 20, 1503 .htotal = 1024 + 160 + 20 + 140, 1504 .vdisplay = 600, 1505 .vsync_start = 600 + 12, 1506 .vsync_end = 600 + 12 + 3, 1507 .vtotal = 600 + 12 + 3 + 20, 1508 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1509 }; 1510 1511 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1512 .modes = &cdtech_s070pws19hp_fc21_mode, 1513 .num_modes = 1, 1514 .bpc = 6, 1515 .size = { 1516 .width = 154, 1517 .height = 86, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1521 .connector_type = DRM_MODE_CONNECTOR_DPI, 1522 }; 1523 1524 /* S070SWV29HG-DC44 2017/09/21 */ 1525 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1526 .clock = 33300, 1527 .hdisplay = 800, 1528 .hsync_start = 800 + 210, 1529 .hsync_end = 800 + 210 + 2, 1530 .htotal = 800 + 210 + 2 + 44, 1531 .vdisplay = 480, 1532 .vsync_start = 480 + 22, 1533 .vsync_end = 480 + 22 + 2, 1534 .vtotal = 480 + 22 + 2 + 21, 1535 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1536 }; 1537 1538 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1539 .modes = &cdtech_s070swv29hg_dc44_mode, 1540 .num_modes = 1, 1541 .bpc = 6, 1542 .size = { 1543 .width = 154, 1544 .height = 86, 1545 }, 1546 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1547 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1548 .connector_type = DRM_MODE_CONNECTOR_DPI, 1549 }; 1550 1551 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1552 .clock = 35000, 1553 .hdisplay = 800, 1554 .hsync_start = 800 + 40, 1555 .hsync_end = 800 + 40 + 40, 1556 .htotal = 800 + 40 + 40 + 48, 1557 .vdisplay = 480, 1558 .vsync_start = 480 + 29, 1559 .vsync_end = 480 + 29 + 13, 1560 .vtotal = 480 + 29 + 13 + 3, 1561 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1562 }; 1563 1564 static const struct panel_desc cdtech_s070wv95_ct16 = { 1565 .modes = &cdtech_s070wv95_ct16_mode, 1566 .num_modes = 1, 1567 .bpc = 8, 1568 .size = { 1569 .width = 154, 1570 .height = 85, 1571 }, 1572 }; 1573 1574 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1575 .pixelclock = { 68900000, 71100000, 73400000 }, 1576 .hactive = { 1280, 1280, 1280 }, 1577 .hfront_porch = { 65, 80, 95 }, 1578 .hback_porch = { 64, 79, 94 }, 1579 .hsync_len = { 1, 1, 1 }, 1580 .vactive = { 800, 800, 800 }, 1581 .vfront_porch = { 7, 11, 14 }, 1582 .vback_porch = { 7, 11, 14 }, 1583 .vsync_len = { 1, 1, 1 }, 1584 .flags = DISPLAY_FLAGS_DE_HIGH, 1585 }; 1586 1587 static const struct panel_desc chefree_ch101olhlwh_002 = { 1588 .timings = &chefree_ch101olhlwh_002_timing, 1589 .num_timings = 1, 1590 .bpc = 8, 1591 .size = { 1592 .width = 217, 1593 .height = 135, 1594 }, 1595 .delay = { 1596 .enable = 200, 1597 .disable = 200, 1598 }, 1599 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1600 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1601 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1602 }; 1603 1604 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1605 .clock = 66770, 1606 .hdisplay = 800, 1607 .hsync_start = 800 + 49, 1608 .hsync_end = 800 + 49 + 33, 1609 .htotal = 800 + 49 + 33 + 17, 1610 .vdisplay = 1280, 1611 .vsync_start = 1280 + 1, 1612 .vsync_end = 1280 + 1 + 7, 1613 .vtotal = 1280 + 1 + 7 + 15, 1614 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1615 }; 1616 1617 static const struct panel_desc chunghwa_claa070wp03xg = { 1618 .modes = &chunghwa_claa070wp03xg_mode, 1619 .num_modes = 1, 1620 .bpc = 6, 1621 .size = { 1622 .width = 94, 1623 .height = 150, 1624 }, 1625 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1626 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1627 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1628 }; 1629 1630 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1631 .clock = 72070, 1632 .hdisplay = 1366, 1633 .hsync_start = 1366 + 58, 1634 .hsync_end = 1366 + 58 + 58, 1635 .htotal = 1366 + 58 + 58 + 58, 1636 .vdisplay = 768, 1637 .vsync_start = 768 + 4, 1638 .vsync_end = 768 + 4 + 4, 1639 .vtotal = 768 + 4 + 4 + 4, 1640 }; 1641 1642 static const struct panel_desc chunghwa_claa101wa01a = { 1643 .modes = &chunghwa_claa101wa01a_mode, 1644 .num_modes = 1, 1645 .bpc = 6, 1646 .size = { 1647 .width = 220, 1648 .height = 120, 1649 }, 1650 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1651 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1652 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1653 }; 1654 1655 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1656 .clock = 69300, 1657 .hdisplay = 1366, 1658 .hsync_start = 1366 + 48, 1659 .hsync_end = 1366 + 48 + 32, 1660 .htotal = 1366 + 48 + 32 + 20, 1661 .vdisplay = 768, 1662 .vsync_start = 768 + 16, 1663 .vsync_end = 768 + 16 + 8, 1664 .vtotal = 768 + 16 + 8 + 16, 1665 }; 1666 1667 static const struct panel_desc chunghwa_claa101wb01 = { 1668 .modes = &chunghwa_claa101wb01_mode, 1669 .num_modes = 1, 1670 .bpc = 6, 1671 .size = { 1672 .width = 223, 1673 .height = 125, 1674 }, 1675 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1676 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1677 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1678 }; 1679 1680 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1681 .pixelclock = { 5000000, 9000000, 12000000 }, 1682 .hactive = { 480, 480, 480 }, 1683 .hfront_porch = { 12, 12, 12 }, 1684 .hback_porch = { 12, 12, 12 }, 1685 .hsync_len = { 21, 21, 21 }, 1686 .vactive = { 272, 272, 272 }, 1687 .vfront_porch = { 4, 4, 4 }, 1688 .vback_porch = { 4, 4, 4 }, 1689 .vsync_len = { 8, 8, 8 }, 1690 }; 1691 1692 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1693 .timings = &dataimage_fg040346dsswbg04_timing, 1694 .num_timings = 1, 1695 .bpc = 8, 1696 .size = { 1697 .width = 95, 1698 .height = 54, 1699 }, 1700 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1701 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1702 .connector_type = DRM_MODE_CONNECTOR_DPI, 1703 }; 1704 1705 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1706 .pixelclock = { 68900000, 71110000, 73400000 }, 1707 .hactive = { 1280, 1280, 1280 }, 1708 .vactive = { 800, 800, 800 }, 1709 .hback_porch = { 100, 100, 100 }, 1710 .hfront_porch = { 100, 100, 100 }, 1711 .vback_porch = { 5, 5, 5 }, 1712 .vfront_porch = { 5, 5, 5 }, 1713 .hsync_len = { 24, 24, 24 }, 1714 .vsync_len = { 3, 3, 3 }, 1715 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1716 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1717 }; 1718 1719 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1720 .timings = &dataimage_fg1001l0dsswmg01_timing, 1721 .num_timings = 1, 1722 .bpc = 8, 1723 .size = { 1724 .width = 217, 1725 .height = 136, 1726 }, 1727 }; 1728 1729 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1730 .clock = 33260, 1731 .hdisplay = 800, 1732 .hsync_start = 800 + 40, 1733 .hsync_end = 800 + 40 + 128, 1734 .htotal = 800 + 40 + 128 + 88, 1735 .vdisplay = 480, 1736 .vsync_start = 480 + 10, 1737 .vsync_end = 480 + 10 + 2, 1738 .vtotal = 480 + 10 + 2 + 33, 1739 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1740 }; 1741 1742 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1743 .modes = &dataimage_scf0700c48ggu18_mode, 1744 .num_modes = 1, 1745 .bpc = 8, 1746 .size = { 1747 .width = 152, 1748 .height = 91, 1749 }, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1751 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1752 }; 1753 1754 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1755 .pixelclock = { 45000000, 51200000, 57000000 }, 1756 .hactive = { 1024, 1024, 1024 }, 1757 .hfront_porch = { 100, 106, 113 }, 1758 .hback_porch = { 100, 106, 113 }, 1759 .hsync_len = { 100, 108, 114 }, 1760 .vactive = { 600, 600, 600 }, 1761 .vfront_porch = { 8, 11, 15 }, 1762 .vback_porch = { 8, 11, 15 }, 1763 .vsync_len = { 9, 13, 15 }, 1764 .flags = DISPLAY_FLAGS_DE_HIGH, 1765 }; 1766 1767 static const struct panel_desc dlc_dlc0700yzg_1 = { 1768 .timings = &dlc_dlc0700yzg_1_timing, 1769 .num_timings = 1, 1770 .bpc = 6, 1771 .size = { 1772 .width = 154, 1773 .height = 86, 1774 }, 1775 .delay = { 1776 .prepare = 30, 1777 .enable = 200, 1778 .disable = 200, 1779 }, 1780 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1781 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1782 }; 1783 1784 static const struct display_timing dlc_dlc1010gig_timing = { 1785 .pixelclock = { 68900000, 71100000, 73400000 }, 1786 .hactive = { 1280, 1280, 1280 }, 1787 .hfront_porch = { 43, 53, 63 }, 1788 .hback_porch = { 43, 53, 63 }, 1789 .hsync_len = { 44, 54, 64 }, 1790 .vactive = { 800, 800, 800 }, 1791 .vfront_porch = { 5, 8, 11 }, 1792 .vback_porch = { 5, 8, 11 }, 1793 .vsync_len = { 5, 7, 11 }, 1794 .flags = DISPLAY_FLAGS_DE_HIGH, 1795 }; 1796 1797 static const struct panel_desc dlc_dlc1010gig = { 1798 .timings = &dlc_dlc1010gig_timing, 1799 .num_timings = 1, 1800 .bpc = 8, 1801 .size = { 1802 .width = 216, 1803 .height = 135, 1804 }, 1805 .delay = { 1806 .prepare = 60, 1807 .enable = 150, 1808 .disable = 100, 1809 .unprepare = 60, 1810 }, 1811 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1812 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1813 }; 1814 1815 static const struct drm_display_mode edt_et035012dm6_mode = { 1816 .clock = 6500, 1817 .hdisplay = 320, 1818 .hsync_start = 320 + 20, 1819 .hsync_end = 320 + 20 + 30, 1820 .htotal = 320 + 20 + 68, 1821 .vdisplay = 240, 1822 .vsync_start = 240 + 4, 1823 .vsync_end = 240 + 4 + 4, 1824 .vtotal = 240 + 4 + 4 + 14, 1825 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1826 }; 1827 1828 static const struct panel_desc edt_et035012dm6 = { 1829 .modes = &edt_et035012dm6_mode, 1830 .num_modes = 1, 1831 .bpc = 8, 1832 .size = { 1833 .width = 70, 1834 .height = 52, 1835 }, 1836 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1837 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1838 }; 1839 1840 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1841 .clock = 6520, 1842 .hdisplay = 320, 1843 .hsync_start = 320 + 20, 1844 .hsync_end = 320 + 20 + 68, 1845 .htotal = 320 + 20 + 68, 1846 .vdisplay = 240, 1847 .vsync_start = 240 + 4, 1848 .vsync_end = 240 + 4 + 18, 1849 .vtotal = 240 + 4 + 18, 1850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1851 }; 1852 1853 static const struct panel_desc edt_etm0350g0dh6 = { 1854 .modes = &edt_etm0350g0dh6_mode, 1855 .num_modes = 1, 1856 .bpc = 6, 1857 .size = { 1858 .width = 70, 1859 .height = 53, 1860 }, 1861 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1862 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1863 .connector_type = DRM_MODE_CONNECTOR_DPI, 1864 }; 1865 1866 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1867 .clock = 10870, 1868 .hdisplay = 480, 1869 .hsync_start = 480 + 8, 1870 .hsync_end = 480 + 8 + 4, 1871 .htotal = 480 + 8 + 4 + 41, 1872 1873 /* 1874 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1875 * fb_align 1876 */ 1877 1878 .vdisplay = 288, 1879 .vsync_start = 288 + 2, 1880 .vsync_end = 288 + 2 + 4, 1881 .vtotal = 288 + 2 + 4 + 10, 1882 }; 1883 1884 static const struct panel_desc edt_etm043080dh6gp = { 1885 .modes = &edt_etm043080dh6gp_mode, 1886 .num_modes = 1, 1887 .bpc = 8, 1888 .size = { 1889 .width = 100, 1890 .height = 65, 1891 }, 1892 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1893 .connector_type = DRM_MODE_CONNECTOR_DPI, 1894 }; 1895 1896 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1897 .clock = 9000, 1898 .hdisplay = 480, 1899 .hsync_start = 480 + 2, 1900 .hsync_end = 480 + 2 + 41, 1901 .htotal = 480 + 2 + 41 + 2, 1902 .vdisplay = 272, 1903 .vsync_start = 272 + 2, 1904 .vsync_end = 272 + 2 + 10, 1905 .vtotal = 272 + 2 + 10 + 2, 1906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1907 }; 1908 1909 static const struct panel_desc edt_etm0430g0dh6 = { 1910 .modes = &edt_etm0430g0dh6_mode, 1911 .num_modes = 1, 1912 .bpc = 6, 1913 .size = { 1914 .width = 95, 1915 .height = 54, 1916 }, 1917 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1918 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1919 .connector_type = DRM_MODE_CONNECTOR_DPI, 1920 }; 1921 1922 static const struct drm_display_mode edt_et057090dhu_mode = { 1923 .clock = 25175, 1924 .hdisplay = 640, 1925 .hsync_start = 640 + 16, 1926 .hsync_end = 640 + 16 + 30, 1927 .htotal = 640 + 16 + 30 + 114, 1928 .vdisplay = 480, 1929 .vsync_start = 480 + 10, 1930 .vsync_end = 480 + 10 + 3, 1931 .vtotal = 480 + 10 + 3 + 32, 1932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1933 }; 1934 1935 static const struct panel_desc edt_et057090dhu = { 1936 .modes = &edt_et057090dhu_mode, 1937 .num_modes = 1, 1938 .bpc = 6, 1939 .size = { 1940 .width = 115, 1941 .height = 86, 1942 }, 1943 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1944 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1945 .connector_type = DRM_MODE_CONNECTOR_DPI, 1946 }; 1947 1948 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1949 .clock = 33260, 1950 .hdisplay = 800, 1951 .hsync_start = 800 + 40, 1952 .hsync_end = 800 + 40 + 128, 1953 .htotal = 800 + 40 + 128 + 88, 1954 .vdisplay = 480, 1955 .vsync_start = 480 + 10, 1956 .vsync_end = 480 + 10 + 2, 1957 .vtotal = 480 + 10 + 2 + 33, 1958 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1959 }; 1960 1961 static const struct panel_desc edt_etm0700g0dh6 = { 1962 .modes = &edt_etm0700g0dh6_mode, 1963 .num_modes = 1, 1964 .bpc = 6, 1965 .size = { 1966 .width = 152, 1967 .height = 91, 1968 }, 1969 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1970 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1971 .connector_type = DRM_MODE_CONNECTOR_DPI, 1972 }; 1973 1974 static const struct panel_desc edt_etm0700g0bdh6 = { 1975 .modes = &edt_etm0700g0dh6_mode, 1976 .num_modes = 1, 1977 .bpc = 6, 1978 .size = { 1979 .width = 152, 1980 .height = 91, 1981 }, 1982 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1983 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1984 .connector_type = DRM_MODE_CONNECTOR_DPI, 1985 }; 1986 1987 static const struct display_timing edt_etml0700y5dha_timing = { 1988 .pixelclock = { 40800000, 51200000, 67200000 }, 1989 .hactive = { 1024, 1024, 1024 }, 1990 .hfront_porch = { 30, 106, 125 }, 1991 .hback_porch = { 30, 106, 125 }, 1992 .hsync_len = { 30, 108, 126 }, 1993 .vactive = { 600, 600, 600 }, 1994 .vfront_porch = { 3, 12, 67}, 1995 .vback_porch = { 3, 12, 67 }, 1996 .vsync_len = { 4, 11, 66 }, 1997 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1998 DISPLAY_FLAGS_DE_HIGH, 1999 }; 2000 2001 static const struct panel_desc edt_etml0700y5dha = { 2002 .timings = &edt_etml0700y5dha_timing, 2003 .num_timings = 1, 2004 .bpc = 8, 2005 .size = { 2006 .width = 155, 2007 .height = 86, 2008 }, 2009 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2010 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2011 }; 2012 2013 static const struct display_timing edt_etml1010g3dra_timing = { 2014 .pixelclock = { 66300000, 72400000, 78900000 }, 2015 .hactive = { 1280, 1280, 1280 }, 2016 .hfront_porch = { 12, 72, 132 }, 2017 .hback_porch = { 86, 86, 86 }, 2018 .hsync_len = { 2, 2, 2 }, 2019 .vactive = { 800, 800, 800 }, 2020 .vfront_porch = { 1, 15, 49 }, 2021 .vback_porch = { 21, 21, 21 }, 2022 .vsync_len = { 2, 2, 2 }, 2023 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2024 DISPLAY_FLAGS_DE_HIGH, 2025 }; 2026 2027 static const struct panel_desc edt_etml1010g3dra = { 2028 .timings = &edt_etml1010g3dra_timing, 2029 .num_timings = 1, 2030 .bpc = 8, 2031 .size = { 2032 .width = 216, 2033 .height = 135, 2034 }, 2035 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2036 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2037 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2038 }; 2039 2040 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2041 .clock = 25175, 2042 .hdisplay = 640, 2043 .hsync_start = 640, 2044 .hsync_end = 640 + 16, 2045 .htotal = 640 + 16 + 30 + 114, 2046 .vdisplay = 480, 2047 .vsync_start = 480 + 10, 2048 .vsync_end = 480 + 10 + 3, 2049 .vtotal = 480 + 10 + 3 + 35, 2050 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2051 }; 2052 2053 static const struct panel_desc edt_etmv570g2dhu = { 2054 .modes = &edt_etmv570g2dhu_mode, 2055 .num_modes = 1, 2056 .bpc = 6, 2057 .size = { 2058 .width = 115, 2059 .height = 86, 2060 }, 2061 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2062 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2063 .connector_type = DRM_MODE_CONNECTOR_DPI, 2064 }; 2065 2066 static const struct display_timing eink_vb3300_kca_timing = { 2067 .pixelclock = { 40000000, 40000000, 40000000 }, 2068 .hactive = { 334, 334, 334 }, 2069 .hfront_porch = { 1, 1, 1 }, 2070 .hback_porch = { 1, 1, 1 }, 2071 .hsync_len = { 1, 1, 1 }, 2072 .vactive = { 1405, 1405, 1405 }, 2073 .vfront_porch = { 1, 1, 1 }, 2074 .vback_porch = { 1, 1, 1 }, 2075 .vsync_len = { 1, 1, 1 }, 2076 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2077 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2078 }; 2079 2080 static const struct panel_desc eink_vb3300_kca = { 2081 .timings = &eink_vb3300_kca_timing, 2082 .num_timings = 1, 2083 .bpc = 6, 2084 .size = { 2085 .width = 157, 2086 .height = 209, 2087 }, 2088 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2089 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2090 .connector_type = DRM_MODE_CONNECTOR_DPI, 2091 }; 2092 2093 static const struct display_timing evervision_vgg644804_timing = { 2094 .pixelclock = { 25175000, 25175000, 25175000 }, 2095 .hactive = { 640, 640, 640 }, 2096 .hfront_porch = { 16, 16, 16 }, 2097 .hback_porch = { 82, 114, 170 }, 2098 .hsync_len = { 5, 30, 30 }, 2099 .vactive = { 480, 480, 480 }, 2100 .vfront_porch = { 10, 10, 10 }, 2101 .vback_porch = { 30, 32, 34 }, 2102 .vsync_len = { 1, 3, 5 }, 2103 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2104 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2105 DISPLAY_FLAGS_SYNC_POSEDGE, 2106 }; 2107 2108 static const struct panel_desc evervision_vgg644804 = { 2109 .timings = &evervision_vgg644804_timing, 2110 .num_timings = 1, 2111 .bpc = 8, 2112 .size = { 2113 .width = 115, 2114 .height = 86, 2115 }, 2116 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2117 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2118 }; 2119 2120 static const struct display_timing evervision_vgg804821_timing = { 2121 .pixelclock = { 27600000, 33300000, 50000000 }, 2122 .hactive = { 800, 800, 800 }, 2123 .hfront_porch = { 40, 66, 70 }, 2124 .hback_porch = { 40, 67, 70 }, 2125 .hsync_len = { 40, 67, 70 }, 2126 .vactive = { 480, 480, 480 }, 2127 .vfront_porch = { 6, 10, 10 }, 2128 .vback_porch = { 7, 11, 11 }, 2129 .vsync_len = { 7, 11, 11 }, 2130 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2131 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2132 DISPLAY_FLAGS_SYNC_NEGEDGE, 2133 }; 2134 2135 static const struct panel_desc evervision_vgg804821 = { 2136 .timings = &evervision_vgg804821_timing, 2137 .num_timings = 1, 2138 .bpc = 8, 2139 .size = { 2140 .width = 108, 2141 .height = 64, 2142 }, 2143 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2144 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2145 }; 2146 2147 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2148 .clock = 32260, 2149 .hdisplay = 800, 2150 .hsync_start = 800 + 168, 2151 .hsync_end = 800 + 168 + 64, 2152 .htotal = 800 + 168 + 64 + 88, 2153 .vdisplay = 480, 2154 .vsync_start = 480 + 37, 2155 .vsync_end = 480 + 37 + 2, 2156 .vtotal = 480 + 37 + 2 + 8, 2157 }; 2158 2159 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2160 .modes = &foxlink_fl500wvr00_a0t_mode, 2161 .num_modes = 1, 2162 .bpc = 8, 2163 .size = { 2164 .width = 108, 2165 .height = 65, 2166 }, 2167 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2168 }; 2169 2170 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2171 { /* 60 Hz */ 2172 .clock = 6000, 2173 .hdisplay = 320, 2174 .hsync_start = 320 + 44, 2175 .hsync_end = 320 + 44 + 16, 2176 .htotal = 320 + 44 + 16 + 20, 2177 .vdisplay = 240, 2178 .vsync_start = 240 + 2, 2179 .vsync_end = 240 + 2 + 6, 2180 .vtotal = 240 + 2 + 6 + 2, 2181 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2182 }, 2183 { /* 50 Hz */ 2184 .clock = 5400, 2185 .hdisplay = 320, 2186 .hsync_start = 320 + 56, 2187 .hsync_end = 320 + 56 + 16, 2188 .htotal = 320 + 56 + 16 + 40, 2189 .vdisplay = 240, 2190 .vsync_start = 240 + 2, 2191 .vsync_end = 240 + 2 + 6, 2192 .vtotal = 240 + 2 + 6 + 2, 2193 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2194 }, 2195 }; 2196 2197 static const struct panel_desc frida_frd350h54004 = { 2198 .modes = frida_frd350h54004_modes, 2199 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2200 .bpc = 8, 2201 .size = { 2202 .width = 77, 2203 .height = 64, 2204 }, 2205 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2206 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2207 .connector_type = DRM_MODE_CONNECTOR_DPI, 2208 }; 2209 2210 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2211 .clock = 67185, 2212 .hdisplay = 800, 2213 .hsync_start = 800 + 20, 2214 .hsync_end = 800 + 20 + 24, 2215 .htotal = 800 + 20 + 24 + 20, 2216 .vdisplay = 1280, 2217 .vsync_start = 1280 + 4, 2218 .vsync_end = 1280 + 4 + 8, 2219 .vtotal = 1280 + 4 + 8 + 4, 2220 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2221 }; 2222 2223 static const struct panel_desc friendlyarm_hd702e = { 2224 .modes = &friendlyarm_hd702e_mode, 2225 .num_modes = 1, 2226 .size = { 2227 .width = 94, 2228 .height = 151, 2229 }, 2230 }; 2231 2232 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2233 .clock = 9000, 2234 .hdisplay = 480, 2235 .hsync_start = 480 + 5, 2236 .hsync_end = 480 + 5 + 1, 2237 .htotal = 480 + 5 + 1 + 40, 2238 .vdisplay = 272, 2239 .vsync_start = 272 + 8, 2240 .vsync_end = 272 + 8 + 1, 2241 .vtotal = 272 + 8 + 1 + 8, 2242 }; 2243 2244 static const struct panel_desc giantplus_gpg482739qs5 = { 2245 .modes = &giantplus_gpg482739qs5_mode, 2246 .num_modes = 1, 2247 .bpc = 8, 2248 .size = { 2249 .width = 95, 2250 .height = 54, 2251 }, 2252 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2253 }; 2254 2255 static const struct display_timing giantplus_gpm940b0_timing = { 2256 .pixelclock = { 13500000, 27000000, 27500000 }, 2257 .hactive = { 320, 320, 320 }, 2258 .hfront_porch = { 14, 686, 718 }, 2259 .hback_porch = { 50, 70, 255 }, 2260 .hsync_len = { 1, 1, 1 }, 2261 .vactive = { 240, 240, 240 }, 2262 .vfront_porch = { 1, 1, 179 }, 2263 .vback_porch = { 1, 21, 31 }, 2264 .vsync_len = { 1, 1, 6 }, 2265 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2266 }; 2267 2268 static const struct panel_desc giantplus_gpm940b0 = { 2269 .timings = &giantplus_gpm940b0_timing, 2270 .num_timings = 1, 2271 .bpc = 8, 2272 .size = { 2273 .width = 60, 2274 .height = 45, 2275 }, 2276 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2277 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2278 }; 2279 2280 static const struct display_timing hannstar_hsd070pww1_timing = { 2281 .pixelclock = { 64300000, 71100000, 82000000 }, 2282 .hactive = { 1280, 1280, 1280 }, 2283 .hfront_porch = { 1, 1, 10 }, 2284 .hback_porch = { 1, 1, 10 }, 2285 /* 2286 * According to the data sheet, the minimum horizontal blanking interval 2287 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2288 * minimum working horizontal blanking interval to be 60 clocks. 2289 */ 2290 .hsync_len = { 58, 158, 661 }, 2291 .vactive = { 800, 800, 800 }, 2292 .vfront_porch = { 1, 1, 10 }, 2293 .vback_porch = { 1, 1, 10 }, 2294 .vsync_len = { 1, 21, 203 }, 2295 .flags = DISPLAY_FLAGS_DE_HIGH, 2296 }; 2297 2298 static const struct panel_desc hannstar_hsd070pww1 = { 2299 .timings = &hannstar_hsd070pww1_timing, 2300 .num_timings = 1, 2301 .bpc = 6, 2302 .size = { 2303 .width = 151, 2304 .height = 94, 2305 }, 2306 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2307 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2308 }; 2309 2310 static const struct display_timing hannstar_hsd100pxn1_timing = { 2311 .pixelclock = { 55000000, 65000000, 75000000 }, 2312 .hactive = { 1024, 1024, 1024 }, 2313 .hfront_porch = { 40, 40, 40 }, 2314 .hback_porch = { 220, 220, 220 }, 2315 .hsync_len = { 20, 60, 100 }, 2316 .vactive = { 768, 768, 768 }, 2317 .vfront_porch = { 7, 7, 7 }, 2318 .vback_porch = { 21, 21, 21 }, 2319 .vsync_len = { 10, 10, 10 }, 2320 .flags = DISPLAY_FLAGS_DE_HIGH, 2321 }; 2322 2323 static const struct panel_desc hannstar_hsd100pxn1 = { 2324 .timings = &hannstar_hsd100pxn1_timing, 2325 .num_timings = 1, 2326 .bpc = 6, 2327 .size = { 2328 .width = 203, 2329 .height = 152, 2330 }, 2331 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2332 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2333 }; 2334 2335 static const struct display_timing hannstar_hsd101pww2_timing = { 2336 .pixelclock = { 64300000, 71100000, 82000000 }, 2337 .hactive = { 1280, 1280, 1280 }, 2338 .hfront_porch = { 1, 1, 10 }, 2339 .hback_porch = { 1, 1, 10 }, 2340 .hsync_len = { 58, 158, 661 }, 2341 .vactive = { 800, 800, 800 }, 2342 .vfront_porch = { 1, 1, 10 }, 2343 .vback_porch = { 1, 1, 10 }, 2344 .vsync_len = { 1, 21, 203 }, 2345 .flags = DISPLAY_FLAGS_DE_HIGH, 2346 }; 2347 2348 static const struct panel_desc hannstar_hsd101pww2 = { 2349 .timings = &hannstar_hsd101pww2_timing, 2350 .num_timings = 1, 2351 .bpc = 8, 2352 .size = { 2353 .width = 217, 2354 .height = 136, 2355 }, 2356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2358 }; 2359 2360 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2361 .clock = 33333, 2362 .hdisplay = 800, 2363 .hsync_start = 800 + 85, 2364 .hsync_end = 800 + 85 + 86, 2365 .htotal = 800 + 85 + 86 + 85, 2366 .vdisplay = 480, 2367 .vsync_start = 480 + 16, 2368 .vsync_end = 480 + 16 + 13, 2369 .vtotal = 480 + 16 + 13 + 16, 2370 }; 2371 2372 static const struct panel_desc hitachi_tx23d38vm0caa = { 2373 .modes = &hitachi_tx23d38vm0caa_mode, 2374 .num_modes = 1, 2375 .bpc = 6, 2376 .size = { 2377 .width = 195, 2378 .height = 117, 2379 }, 2380 .delay = { 2381 .enable = 160, 2382 .disable = 160, 2383 }, 2384 }; 2385 2386 static const struct drm_display_mode innolux_at043tn24_mode = { 2387 .clock = 9000, 2388 .hdisplay = 480, 2389 .hsync_start = 480 + 2, 2390 .hsync_end = 480 + 2 + 41, 2391 .htotal = 480 + 2 + 41 + 2, 2392 .vdisplay = 272, 2393 .vsync_start = 272 + 2, 2394 .vsync_end = 272 + 2 + 10, 2395 .vtotal = 272 + 2 + 10 + 2, 2396 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2397 }; 2398 2399 static const struct panel_desc innolux_at043tn24 = { 2400 .modes = &innolux_at043tn24_mode, 2401 .num_modes = 1, 2402 .bpc = 8, 2403 .size = { 2404 .width = 95, 2405 .height = 54, 2406 }, 2407 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2408 .connector_type = DRM_MODE_CONNECTOR_DPI, 2409 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2410 }; 2411 2412 static const struct drm_display_mode innolux_at070tn92_mode = { 2413 .clock = 33333, 2414 .hdisplay = 800, 2415 .hsync_start = 800 + 210, 2416 .hsync_end = 800 + 210 + 20, 2417 .htotal = 800 + 210 + 20 + 46, 2418 .vdisplay = 480, 2419 .vsync_start = 480 + 22, 2420 .vsync_end = 480 + 22 + 10, 2421 .vtotal = 480 + 22 + 23 + 10, 2422 }; 2423 2424 static const struct panel_desc innolux_at070tn92 = { 2425 .modes = &innolux_at070tn92_mode, 2426 .num_modes = 1, 2427 .size = { 2428 .width = 154, 2429 .height = 86, 2430 }, 2431 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2432 }; 2433 2434 static const struct display_timing innolux_g070ace_l01_timing = { 2435 .pixelclock = { 25200000, 35000000, 35700000 }, 2436 .hactive = { 800, 800, 800 }, 2437 .hfront_porch = { 30, 32, 87 }, 2438 .hback_porch = { 30, 32, 87 }, 2439 .hsync_len = { 1, 1, 1 }, 2440 .vactive = { 480, 480, 480 }, 2441 .vfront_porch = { 3, 3, 3 }, 2442 .vback_porch = { 13, 13, 13 }, 2443 .vsync_len = { 1, 1, 4 }, 2444 .flags = DISPLAY_FLAGS_DE_HIGH, 2445 }; 2446 2447 static const struct panel_desc innolux_g070ace_l01 = { 2448 .timings = &innolux_g070ace_l01_timing, 2449 .num_timings = 1, 2450 .bpc = 8, 2451 .size = { 2452 .width = 152, 2453 .height = 91, 2454 }, 2455 .delay = { 2456 .prepare = 10, 2457 .enable = 50, 2458 .disable = 50, 2459 .unprepare = 500, 2460 }, 2461 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2462 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2464 }; 2465 2466 static const struct display_timing innolux_g070y2_l01_timing = { 2467 .pixelclock = { 28000000, 29500000, 32000000 }, 2468 .hactive = { 800, 800, 800 }, 2469 .hfront_porch = { 61, 91, 141 }, 2470 .hback_porch = { 60, 90, 140 }, 2471 .hsync_len = { 12, 12, 12 }, 2472 .vactive = { 480, 480, 480 }, 2473 .vfront_porch = { 4, 9, 30 }, 2474 .vback_porch = { 4, 8, 28 }, 2475 .vsync_len = { 2, 2, 2 }, 2476 .flags = DISPLAY_FLAGS_DE_HIGH, 2477 }; 2478 2479 static const struct panel_desc innolux_g070y2_l01 = { 2480 .timings = &innolux_g070y2_l01_timing, 2481 .num_timings = 1, 2482 .bpc = 8, 2483 .size = { 2484 .width = 152, 2485 .height = 91, 2486 }, 2487 .delay = { 2488 .prepare = 10, 2489 .enable = 100, 2490 .disable = 100, 2491 .unprepare = 800, 2492 }, 2493 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2494 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2495 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2496 }; 2497 2498 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2499 .clock = 33333, 2500 .hdisplay = 800, 2501 .hsync_start = 800 + 210, 2502 .hsync_end = 800 + 210 + 20, 2503 .htotal = 800 + 210 + 20 + 46, 2504 .vdisplay = 480, 2505 .vsync_start = 480 + 22, 2506 .vsync_end = 480 + 22 + 10, 2507 .vtotal = 480 + 22 + 23 + 10, 2508 }; 2509 2510 static const struct panel_desc innolux_g070y2_t02 = { 2511 .modes = &innolux_g070y2_t02_mode, 2512 .num_modes = 1, 2513 .bpc = 8, 2514 .size = { 2515 .width = 152, 2516 .height = 92, 2517 }, 2518 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2519 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2520 .connector_type = DRM_MODE_CONNECTOR_DPI, 2521 }; 2522 2523 static const struct display_timing innolux_g101ice_l01_timing = { 2524 .pixelclock = { 60400000, 71100000, 74700000 }, 2525 .hactive = { 1280, 1280, 1280 }, 2526 .hfront_porch = { 30, 60, 70 }, 2527 .hback_porch = { 30, 60, 70 }, 2528 .hsync_len = { 22, 40, 60 }, 2529 .vactive = { 800, 800, 800 }, 2530 .vfront_porch = { 3, 8, 14 }, 2531 .vback_porch = { 3, 8, 14 }, 2532 .vsync_len = { 4, 7, 12 }, 2533 .flags = DISPLAY_FLAGS_DE_HIGH, 2534 }; 2535 2536 static const struct panel_desc innolux_g101ice_l01 = { 2537 .timings = &innolux_g101ice_l01_timing, 2538 .num_timings = 1, 2539 .bpc = 8, 2540 .size = { 2541 .width = 217, 2542 .height = 135, 2543 }, 2544 .delay = { 2545 .enable = 200, 2546 .disable = 200, 2547 }, 2548 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2549 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2551 }; 2552 2553 static const struct display_timing innolux_g121i1_l01_timing = { 2554 .pixelclock = { 67450000, 71000000, 74550000 }, 2555 .hactive = { 1280, 1280, 1280 }, 2556 .hfront_porch = { 40, 80, 160 }, 2557 .hback_porch = { 39, 79, 159 }, 2558 .hsync_len = { 1, 1, 1 }, 2559 .vactive = { 800, 800, 800 }, 2560 .vfront_porch = { 5, 11, 100 }, 2561 .vback_porch = { 4, 11, 99 }, 2562 .vsync_len = { 1, 1, 1 }, 2563 }; 2564 2565 static const struct panel_desc innolux_g121i1_l01 = { 2566 .timings = &innolux_g121i1_l01_timing, 2567 .num_timings = 1, 2568 .bpc = 6, 2569 .size = { 2570 .width = 261, 2571 .height = 163, 2572 }, 2573 .delay = { 2574 .enable = 200, 2575 .disable = 20, 2576 }, 2577 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2578 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2579 }; 2580 2581 static const struct display_timing innolux_g121x1_l03_timings = { 2582 .pixelclock = { 57500000, 64900000, 74400000 }, 2583 .hactive = { 1024, 1024, 1024 }, 2584 .hfront_porch = { 90, 140, 190 }, 2585 .hback_porch = { 90, 140, 190 }, 2586 .hsync_len = { 36, 40, 60 }, 2587 .vactive = { 768, 768, 768 }, 2588 .vfront_porch = { 2, 15, 30 }, 2589 .vback_porch = { 2, 15, 30 }, 2590 .vsync_len = { 2, 8, 20 }, 2591 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2592 }; 2593 2594 static const struct panel_desc innolux_g121x1_l03 = { 2595 .timings = &innolux_g121x1_l03_timings, 2596 .num_timings = 1, 2597 .bpc = 6, 2598 .size = { 2599 .width = 246, 2600 .height = 185, 2601 }, 2602 .delay = { 2603 .enable = 200, 2604 .unprepare = 200, 2605 .disable = 400, 2606 }, 2607 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2608 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2609 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2610 }; 2611 2612 static const struct panel_desc innolux_g121xce_l01 = { 2613 .timings = &innolux_g121x1_l03_timings, 2614 .num_timings = 1, 2615 .bpc = 8, 2616 .size = { 2617 .width = 246, 2618 .height = 185, 2619 }, 2620 .delay = { 2621 .enable = 200, 2622 .unprepare = 200, 2623 .disable = 400, 2624 }, 2625 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2626 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2627 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2628 }; 2629 2630 static const struct display_timing innolux_g156hce_l01_timings = { 2631 .pixelclock = { 120000000, 141860000, 150000000 }, 2632 .hactive = { 1920, 1920, 1920 }, 2633 .hfront_porch = { 80, 90, 100 }, 2634 .hback_porch = { 80, 90, 100 }, 2635 .hsync_len = { 20, 30, 30 }, 2636 .vactive = { 1080, 1080, 1080 }, 2637 .vfront_porch = { 3, 10, 20 }, 2638 .vback_porch = { 3, 10, 20 }, 2639 .vsync_len = { 4, 10, 10 }, 2640 }; 2641 2642 static const struct panel_desc innolux_g156hce_l01 = { 2643 .timings = &innolux_g156hce_l01_timings, 2644 .num_timings = 1, 2645 .bpc = 8, 2646 .size = { 2647 .width = 344, 2648 .height = 194, 2649 }, 2650 .delay = { 2651 .prepare = 1, /* T1+T2 */ 2652 .enable = 450, /* T5 */ 2653 .disable = 200, /* T6 */ 2654 .unprepare = 10, /* T3+T7 */ 2655 }, 2656 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2657 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2658 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2659 }; 2660 2661 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2662 .clock = 69300, 2663 .hdisplay = 1366, 2664 .hsync_start = 1366 + 16, 2665 .hsync_end = 1366 + 16 + 34, 2666 .htotal = 1366 + 16 + 34 + 50, 2667 .vdisplay = 768, 2668 .vsync_start = 768 + 2, 2669 .vsync_end = 768 + 2 + 6, 2670 .vtotal = 768 + 2 + 6 + 12, 2671 }; 2672 2673 static const struct panel_desc innolux_n156bge_l21 = { 2674 .modes = &innolux_n156bge_l21_mode, 2675 .num_modes = 1, 2676 .bpc = 6, 2677 .size = { 2678 .width = 344, 2679 .height = 193, 2680 }, 2681 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2682 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2683 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2684 }; 2685 2686 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2687 .clock = 51501, 2688 .hdisplay = 1024, 2689 .hsync_start = 1024 + 128, 2690 .hsync_end = 1024 + 128 + 64, 2691 .htotal = 1024 + 128 + 64 + 128, 2692 .vdisplay = 600, 2693 .vsync_start = 600 + 16, 2694 .vsync_end = 600 + 16 + 4, 2695 .vtotal = 600 + 16 + 4 + 16, 2696 }; 2697 2698 static const struct panel_desc innolux_zj070na_01p = { 2699 .modes = &innolux_zj070na_01p_mode, 2700 .num_modes = 1, 2701 .bpc = 6, 2702 .size = { 2703 .width = 154, 2704 .height = 90, 2705 }, 2706 }; 2707 2708 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2709 .pixelclock = { 5580000, 5850000, 6200000 }, 2710 .hactive = { 320, 320, 320 }, 2711 .hfront_porch = { 30, 30, 30 }, 2712 .hback_porch = { 30, 30, 30 }, 2713 .hsync_len = { 1, 5, 17 }, 2714 .vactive = { 240, 240, 240 }, 2715 .vfront_porch = { 6, 6, 6 }, 2716 .vback_porch = { 5, 5, 5 }, 2717 .vsync_len = { 1, 2, 11 }, 2718 .flags = DISPLAY_FLAGS_DE_HIGH, 2719 }; 2720 2721 static const struct panel_desc koe_tx14d24vm1bpa = { 2722 .timings = &koe_tx14d24vm1bpa_timing, 2723 .num_timings = 1, 2724 .bpc = 6, 2725 .size = { 2726 .width = 115, 2727 .height = 86, 2728 }, 2729 }; 2730 2731 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2732 .pixelclock = { 151820000, 156720000, 159780000 }, 2733 .hactive = { 1920, 1920, 1920 }, 2734 .hfront_porch = { 105, 130, 142 }, 2735 .hback_porch = { 45, 70, 82 }, 2736 .hsync_len = { 30, 30, 30 }, 2737 .vactive = { 1200, 1200, 1200}, 2738 .vfront_porch = { 3, 5, 10 }, 2739 .vback_porch = { 2, 5, 10 }, 2740 .vsync_len = { 5, 5, 5 }, 2741 }; 2742 2743 static const struct panel_desc koe_tx26d202vm0bwa = { 2744 .timings = &koe_tx26d202vm0bwa_timing, 2745 .num_timings = 1, 2746 .bpc = 8, 2747 .size = { 2748 .width = 217, 2749 .height = 136, 2750 }, 2751 .delay = { 2752 .prepare = 1000, 2753 .enable = 1000, 2754 .unprepare = 1000, 2755 .disable = 1000, 2756 }, 2757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2758 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2759 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2760 }; 2761 2762 static const struct display_timing koe_tx31d200vm0baa_timing = { 2763 .pixelclock = { 39600000, 43200000, 48000000 }, 2764 .hactive = { 1280, 1280, 1280 }, 2765 .hfront_porch = { 16, 36, 56 }, 2766 .hback_porch = { 16, 36, 56 }, 2767 .hsync_len = { 8, 8, 8 }, 2768 .vactive = { 480, 480, 480 }, 2769 .vfront_porch = { 6, 21, 33 }, 2770 .vback_porch = { 6, 21, 33 }, 2771 .vsync_len = { 8, 8, 8 }, 2772 .flags = DISPLAY_FLAGS_DE_HIGH, 2773 }; 2774 2775 static const struct panel_desc koe_tx31d200vm0baa = { 2776 .timings = &koe_tx31d200vm0baa_timing, 2777 .num_timings = 1, 2778 .bpc = 6, 2779 .size = { 2780 .width = 292, 2781 .height = 109, 2782 }, 2783 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2785 }; 2786 2787 static const struct display_timing kyo_tcg121xglp_timing = { 2788 .pixelclock = { 52000000, 65000000, 71000000 }, 2789 .hactive = { 1024, 1024, 1024 }, 2790 .hfront_porch = { 2, 2, 2 }, 2791 .hback_porch = { 2, 2, 2 }, 2792 .hsync_len = { 86, 124, 244 }, 2793 .vactive = { 768, 768, 768 }, 2794 .vfront_porch = { 2, 2, 2 }, 2795 .vback_porch = { 2, 2, 2 }, 2796 .vsync_len = { 6, 34, 73 }, 2797 .flags = DISPLAY_FLAGS_DE_HIGH, 2798 }; 2799 2800 static const struct panel_desc kyo_tcg121xglp = { 2801 .timings = &kyo_tcg121xglp_timing, 2802 .num_timings = 1, 2803 .bpc = 8, 2804 .size = { 2805 .width = 246, 2806 .height = 184, 2807 }, 2808 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2809 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2810 }; 2811 2812 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2813 .clock = 7000, 2814 .hdisplay = 320, 2815 .hsync_start = 320 + 20, 2816 .hsync_end = 320 + 20 + 30, 2817 .htotal = 320 + 20 + 30 + 38, 2818 .vdisplay = 240, 2819 .vsync_start = 240 + 4, 2820 .vsync_end = 240 + 4 + 3, 2821 .vtotal = 240 + 4 + 3 + 15, 2822 }; 2823 2824 static const struct panel_desc lemaker_bl035_rgb_002 = { 2825 .modes = &lemaker_bl035_rgb_002_mode, 2826 .num_modes = 1, 2827 .size = { 2828 .width = 70, 2829 .height = 52, 2830 }, 2831 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2832 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2833 }; 2834 2835 static const struct display_timing lg_lb070wv8_timing = { 2836 .pixelclock = { 31950000, 33260000, 34600000 }, 2837 .hactive = { 800, 800, 800 }, 2838 .hfront_porch = { 88, 88, 88 }, 2839 .hback_porch = { 88, 88, 88 }, 2840 .hsync_len = { 80, 80, 80 }, 2841 .vactive = { 480, 480, 480 }, 2842 .vfront_porch = { 10, 10, 10 }, 2843 .vback_porch = { 10, 10, 10 }, 2844 .vsync_len = { 25, 25, 25 }, 2845 }; 2846 2847 static const struct panel_desc lg_lb070wv8 = { 2848 .timings = &lg_lb070wv8_timing, 2849 .num_timings = 1, 2850 .bpc = 8, 2851 .size = { 2852 .width = 151, 2853 .height = 91, 2854 }, 2855 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2856 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2857 }; 2858 2859 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 2860 .clock = 155127, 2861 .hdisplay = 1920, 2862 .hsync_start = 1920 + 128, 2863 .hsync_end = 1920 + 128 + 20, 2864 .htotal = 1920 + 128 + 20 + 12, 2865 .vdisplay = 1200, 2866 .vsync_start = 1200 + 19, 2867 .vsync_end = 1200 + 19 + 4, 2868 .vtotal = 1200 + 19 + 4 + 20, 2869 }; 2870 2871 static const struct panel_desc lincolntech_lcd185_101ct = { 2872 .modes = &lincolntech_lcd185_101ct_mode, 2873 .bpc = 8, 2874 .num_modes = 1, 2875 .size = { 2876 .width = 217, 2877 .height = 136, 2878 }, 2879 .delay = { 2880 .prepare = 50, 2881 .disable = 50, 2882 }, 2883 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2884 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2885 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2886 }; 2887 2888 static const struct display_timing logictechno_lt161010_2nh_timing = { 2889 .pixelclock = { 26400000, 33300000, 46800000 }, 2890 .hactive = { 800, 800, 800 }, 2891 .hfront_porch = { 16, 210, 354 }, 2892 .hback_porch = { 46, 46, 46 }, 2893 .hsync_len = { 1, 20, 40 }, 2894 .vactive = { 480, 480, 480 }, 2895 .vfront_porch = { 7, 22, 147 }, 2896 .vback_porch = { 23, 23, 23 }, 2897 .vsync_len = { 1, 10, 20 }, 2898 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2899 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2900 DISPLAY_FLAGS_SYNC_POSEDGE, 2901 }; 2902 2903 static const struct panel_desc logictechno_lt161010_2nh = { 2904 .timings = &logictechno_lt161010_2nh_timing, 2905 .num_timings = 1, 2906 .bpc = 6, 2907 .size = { 2908 .width = 154, 2909 .height = 86, 2910 }, 2911 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2912 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2913 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2914 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2915 .connector_type = DRM_MODE_CONNECTOR_DPI, 2916 }; 2917 2918 static const struct display_timing logictechno_lt170410_2whc_timing = { 2919 .pixelclock = { 68900000, 71100000, 73400000 }, 2920 .hactive = { 1280, 1280, 1280 }, 2921 .hfront_porch = { 23, 60, 71 }, 2922 .hback_porch = { 23, 60, 71 }, 2923 .hsync_len = { 15, 40, 47 }, 2924 .vactive = { 800, 800, 800 }, 2925 .vfront_porch = { 5, 7, 10 }, 2926 .vback_porch = { 5, 7, 10 }, 2927 .vsync_len = { 6, 9, 12 }, 2928 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2929 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2930 DISPLAY_FLAGS_SYNC_POSEDGE, 2931 }; 2932 2933 static const struct panel_desc logictechno_lt170410_2whc = { 2934 .timings = &logictechno_lt170410_2whc_timing, 2935 .num_timings = 1, 2936 .bpc = 8, 2937 .size = { 2938 .width = 217, 2939 .height = 136, 2940 }, 2941 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2942 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2943 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2944 }; 2945 2946 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2947 .clock = 33000, 2948 .hdisplay = 800, 2949 .hsync_start = 800 + 112, 2950 .hsync_end = 800 + 112 + 3, 2951 .htotal = 800 + 112 + 3 + 85, 2952 .vdisplay = 480, 2953 .vsync_start = 480 + 38, 2954 .vsync_end = 480 + 38 + 3, 2955 .vtotal = 480 + 38 + 3 + 29, 2956 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2957 }; 2958 2959 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2960 .modes = &logictechno_lttd800480070_l2rt_mode, 2961 .num_modes = 1, 2962 .bpc = 8, 2963 .size = { 2964 .width = 154, 2965 .height = 86, 2966 }, 2967 .delay = { 2968 .prepare = 45, 2969 .enable = 100, 2970 .disable = 100, 2971 .unprepare = 45 2972 }, 2973 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2974 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2975 .connector_type = DRM_MODE_CONNECTOR_DPI, 2976 }; 2977 2978 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2979 .clock = 33000, 2980 .hdisplay = 800, 2981 .hsync_start = 800 + 154, 2982 .hsync_end = 800 + 154 + 3, 2983 .htotal = 800 + 154 + 3 + 43, 2984 .vdisplay = 480, 2985 .vsync_start = 480 + 47, 2986 .vsync_end = 480 + 47 + 3, 2987 .vtotal = 480 + 47 + 3 + 20, 2988 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2989 }; 2990 2991 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2992 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2993 .num_modes = 1, 2994 .bpc = 8, 2995 .size = { 2996 .width = 154, 2997 .height = 86, 2998 }, 2999 .delay = { 3000 .prepare = 45, 3001 .enable = 100, 3002 .disable = 100, 3003 .unprepare = 45 3004 }, 3005 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3006 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3007 .connector_type = DRM_MODE_CONNECTOR_DPI, 3008 }; 3009 3010 static const struct drm_display_mode logicpd_type_28_mode = { 3011 .clock = 9107, 3012 .hdisplay = 480, 3013 .hsync_start = 480 + 3, 3014 .hsync_end = 480 + 3 + 42, 3015 .htotal = 480 + 3 + 42 + 2, 3016 3017 .vdisplay = 272, 3018 .vsync_start = 272 + 2, 3019 .vsync_end = 272 + 2 + 11, 3020 .vtotal = 272 + 2 + 11 + 3, 3021 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3022 }; 3023 3024 static const struct panel_desc logicpd_type_28 = { 3025 .modes = &logicpd_type_28_mode, 3026 .num_modes = 1, 3027 .bpc = 8, 3028 .size = { 3029 .width = 105, 3030 .height = 67, 3031 }, 3032 .delay = { 3033 .prepare = 200, 3034 .enable = 200, 3035 .unprepare = 200, 3036 .disable = 200, 3037 }, 3038 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3039 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3040 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3041 .connector_type = DRM_MODE_CONNECTOR_DPI, 3042 }; 3043 3044 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3045 .clock = 150275, 3046 .hdisplay = 1920, 3047 .hsync_start = 1920 + 32, 3048 .hsync_end = 1920 + 32 + 52, 3049 .htotal = 1920 + 32 + 52 + 24, 3050 .vdisplay = 1200, 3051 .vsync_start = 1200 + 24, 3052 .vsync_end = 1200 + 24 + 8, 3053 .vtotal = 1200 + 24 + 8 + 3, 3054 }; 3055 3056 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3057 .modes = µtips_mf_101hiebcaf0_c_mode, 3058 .bpc = 8, 3059 .num_modes = 1, 3060 .size = { 3061 .width = 217, 3062 .height = 136, 3063 }, 3064 .delay = { 3065 .prepare = 50, 3066 .disable = 50, 3067 }, 3068 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3069 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3070 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3071 }; 3072 3073 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3074 .clock = 93301, 3075 .hdisplay = 1920, 3076 .hsync_start = 1920 + 72, 3077 .hsync_end = 1920 + 72 + 72, 3078 .htotal = 1920 + 72 + 72 + 72, 3079 .vdisplay = 720, 3080 .vsync_start = 720 + 3, 3081 .vsync_end = 720 + 3 + 3, 3082 .vtotal = 720 + 3 + 3 + 2, 3083 }; 3084 3085 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3086 .modes = µtips_mf_103hieb0ga0_mode, 3087 .bpc = 8, 3088 .num_modes = 1, 3089 .size = { 3090 .width = 244, 3091 .height = 92, 3092 }, 3093 .delay = { 3094 .prepare = 50, 3095 .disable = 50, 3096 }, 3097 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3098 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3100 }; 3101 3102 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3103 .clock = 30400, 3104 .hdisplay = 800, 3105 .hsync_start = 800 + 0, 3106 .hsync_end = 800 + 1, 3107 .htotal = 800 + 0 + 1 + 160, 3108 .vdisplay = 480, 3109 .vsync_start = 480 + 0, 3110 .vsync_end = 480 + 48 + 1, 3111 .vtotal = 480 + 48 + 1 + 0, 3112 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3113 }; 3114 3115 static const struct panel_desc mitsubishi_aa070mc01 = { 3116 .modes = &mitsubishi_aa070mc01_mode, 3117 .num_modes = 1, 3118 .bpc = 8, 3119 .size = { 3120 .width = 152, 3121 .height = 91, 3122 }, 3123 3124 .delay = { 3125 .enable = 200, 3126 .unprepare = 200, 3127 .disable = 400, 3128 }, 3129 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3130 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3131 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3132 }; 3133 3134 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3135 .clock = 56234, 3136 .hdisplay = 1024, 3137 .hsync_start = 1024 + 24, 3138 .hsync_end = 1024 + 24 + 63, 3139 .htotal = 1024 + 24 + 63 + 1, 3140 .vdisplay = 768, 3141 .vsync_start = 768 + 3, 3142 .vsync_end = 768 + 3 + 6, 3143 .vtotal = 768 + 3 + 6 + 1, 3144 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3145 }; 3146 3147 static const struct panel_desc mitsubishi_aa084xe01 = { 3148 .modes = &mitsubishi_aa084xe01_mode, 3149 .num_modes = 1, 3150 .bpc = 8, 3151 .size = { 3152 .width = 1024, 3153 .height = 768, 3154 }, 3155 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3156 .connector_type = DRM_MODE_CONNECTOR_DPI, 3157 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3158 }; 3159 3160 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3161 .pixelclock = { 29000000, 33000000, 38000000 }, 3162 .hactive = { 800, 800, 800 }, 3163 .hfront_porch = { 180, 210, 240 }, 3164 .hback_porch = { 16, 16, 16 }, 3165 .hsync_len = { 30, 30, 30 }, 3166 .vactive = { 480, 480, 480 }, 3167 .vfront_porch = { 12, 22, 32 }, 3168 .vback_porch = { 10, 10, 10 }, 3169 .vsync_len = { 13, 13, 13 }, 3170 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3171 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3172 DISPLAY_FLAGS_SYNC_POSEDGE, 3173 }; 3174 3175 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3176 .timings = &multi_inno_mi0700s4t_6_timing, 3177 .num_timings = 1, 3178 .bpc = 8, 3179 .size = { 3180 .width = 154, 3181 .height = 86, 3182 }, 3183 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3184 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3185 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3186 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3187 .connector_type = DRM_MODE_CONNECTOR_DPI, 3188 }; 3189 3190 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3191 .pixelclock = { 32000000, 40000000, 50000000 }, 3192 .hactive = { 800, 800, 800 }, 3193 .hfront_porch = { 16, 210, 354 }, 3194 .hback_porch = { 6, 26, 45 }, 3195 .hsync_len = { 1, 20, 40 }, 3196 .vactive = { 600, 600, 600 }, 3197 .vfront_porch = { 1, 12, 77 }, 3198 .vback_porch = { 3, 13, 22 }, 3199 .vsync_len = { 1, 10, 20 }, 3200 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3201 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3202 DISPLAY_FLAGS_SYNC_POSEDGE, 3203 }; 3204 3205 static const struct panel_desc multi_inno_mi0800ft_9 = { 3206 .timings = &multi_inno_mi0800ft_9_timing, 3207 .num_timings = 1, 3208 .bpc = 8, 3209 .size = { 3210 .width = 162, 3211 .height = 122, 3212 }, 3213 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3214 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3215 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3216 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3217 .connector_type = DRM_MODE_CONNECTOR_DPI, 3218 }; 3219 3220 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3221 .pixelclock = { 68900000, 70000000, 73400000 }, 3222 .hactive = { 1280, 1280, 1280 }, 3223 .hfront_porch = { 30, 60, 71 }, 3224 .hback_porch = { 30, 60, 71 }, 3225 .hsync_len = { 10, 10, 48 }, 3226 .vactive = { 800, 800, 800 }, 3227 .vfront_porch = { 5, 10, 10 }, 3228 .vback_porch = { 5, 10, 10 }, 3229 .vsync_len = { 5, 6, 13 }, 3230 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3231 DISPLAY_FLAGS_DE_HIGH, 3232 }; 3233 3234 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3235 .timings = &multi_inno_mi1010ait_1cp_timing, 3236 .num_timings = 1, 3237 .bpc = 8, 3238 .size = { 3239 .width = 217, 3240 .height = 136, 3241 }, 3242 .delay = { 3243 .enable = 50, 3244 .disable = 50, 3245 }, 3246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3247 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3248 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3249 }; 3250 3251 static const struct display_timing nec_nl12880bc20_05_timing = { 3252 .pixelclock = { 67000000, 71000000, 75000000 }, 3253 .hactive = { 1280, 1280, 1280 }, 3254 .hfront_porch = { 2, 30, 30 }, 3255 .hback_porch = { 6, 100, 100 }, 3256 .hsync_len = { 2, 30, 30 }, 3257 .vactive = { 800, 800, 800 }, 3258 .vfront_porch = { 5, 5, 5 }, 3259 .vback_porch = { 11, 11, 11 }, 3260 .vsync_len = { 7, 7, 7 }, 3261 }; 3262 3263 static const struct panel_desc nec_nl12880bc20_05 = { 3264 .timings = &nec_nl12880bc20_05_timing, 3265 .num_timings = 1, 3266 .bpc = 8, 3267 .size = { 3268 .width = 261, 3269 .height = 163, 3270 }, 3271 .delay = { 3272 .enable = 50, 3273 .disable = 50, 3274 }, 3275 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3276 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3277 }; 3278 3279 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3280 .clock = 10870, 3281 .hdisplay = 480, 3282 .hsync_start = 480 + 2, 3283 .hsync_end = 480 + 2 + 41, 3284 .htotal = 480 + 2 + 41 + 2, 3285 .vdisplay = 272, 3286 .vsync_start = 272 + 2, 3287 .vsync_end = 272 + 2 + 4, 3288 .vtotal = 272 + 2 + 4 + 2, 3289 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3290 }; 3291 3292 static const struct panel_desc nec_nl4827hc19_05b = { 3293 .modes = &nec_nl4827hc19_05b_mode, 3294 .num_modes = 1, 3295 .bpc = 8, 3296 .size = { 3297 .width = 95, 3298 .height = 54, 3299 }, 3300 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3301 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3302 }; 3303 3304 static const struct drm_display_mode netron_dy_e231732_mode = { 3305 .clock = 66000, 3306 .hdisplay = 1024, 3307 .hsync_start = 1024 + 160, 3308 .hsync_end = 1024 + 160 + 70, 3309 .htotal = 1024 + 160 + 70 + 90, 3310 .vdisplay = 600, 3311 .vsync_start = 600 + 127, 3312 .vsync_end = 600 + 127 + 20, 3313 .vtotal = 600 + 127 + 20 + 3, 3314 }; 3315 3316 static const struct panel_desc netron_dy_e231732 = { 3317 .modes = &netron_dy_e231732_mode, 3318 .num_modes = 1, 3319 .size = { 3320 .width = 154, 3321 .height = 87, 3322 }, 3323 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3324 }; 3325 3326 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3327 .clock = 9000, 3328 .hdisplay = 480, 3329 .hsync_start = 480 + 2, 3330 .hsync_end = 480 + 2 + 41, 3331 .htotal = 480 + 2 + 41 + 2, 3332 .vdisplay = 272, 3333 .vsync_start = 272 + 2, 3334 .vsync_end = 272 + 2 + 10, 3335 .vtotal = 272 + 2 + 10 + 2, 3336 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3337 }; 3338 3339 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3340 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3341 .num_modes = 1, 3342 .bpc = 8, 3343 .size = { 3344 .width = 95, 3345 .height = 54, 3346 }, 3347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3348 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3349 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3350 .connector_type = DRM_MODE_CONNECTOR_DPI, 3351 }; 3352 3353 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3354 .pixelclock = { 130000000, 148350000, 163000000 }, 3355 .hactive = { 1920, 1920, 1920 }, 3356 .hfront_porch = { 80, 100, 100 }, 3357 .hback_porch = { 100, 120, 120 }, 3358 .hsync_len = { 50, 60, 60 }, 3359 .vactive = { 1080, 1080, 1080 }, 3360 .vfront_porch = { 12, 30, 30 }, 3361 .vback_porch = { 4, 10, 10 }, 3362 .vsync_len = { 4, 5, 5 }, 3363 }; 3364 3365 static const struct panel_desc nlt_nl192108ac18_02d = { 3366 .timings = &nlt_nl192108ac18_02d_timing, 3367 .num_timings = 1, 3368 .bpc = 8, 3369 .size = { 3370 .width = 344, 3371 .height = 194, 3372 }, 3373 .delay = { 3374 .unprepare = 500, 3375 }, 3376 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3377 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3378 }; 3379 3380 static const struct drm_display_mode nvd_9128_mode = { 3381 .clock = 29500, 3382 .hdisplay = 800, 3383 .hsync_start = 800 + 130, 3384 .hsync_end = 800 + 130 + 98, 3385 .htotal = 800 + 0 + 130 + 98, 3386 .vdisplay = 480, 3387 .vsync_start = 480 + 10, 3388 .vsync_end = 480 + 10 + 50, 3389 .vtotal = 480 + 0 + 10 + 50, 3390 }; 3391 3392 static const struct panel_desc nvd_9128 = { 3393 .modes = &nvd_9128_mode, 3394 .num_modes = 1, 3395 .bpc = 8, 3396 .size = { 3397 .width = 156, 3398 .height = 88, 3399 }, 3400 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3402 }; 3403 3404 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3405 .pixelclock = { 30000000, 30000000, 40000000 }, 3406 .hactive = { 800, 800, 800 }, 3407 .hfront_porch = { 40, 40, 40 }, 3408 .hback_porch = { 40, 40, 40 }, 3409 .hsync_len = { 1, 48, 48 }, 3410 .vactive = { 480, 480, 480 }, 3411 .vfront_porch = { 13, 13, 13 }, 3412 .vback_porch = { 29, 29, 29 }, 3413 .vsync_len = { 3, 3, 3 }, 3414 .flags = DISPLAY_FLAGS_DE_HIGH, 3415 }; 3416 3417 static const struct panel_desc okaya_rs800480t_7x0gp = { 3418 .timings = &okaya_rs800480t_7x0gp_timing, 3419 .num_timings = 1, 3420 .bpc = 6, 3421 .size = { 3422 .width = 154, 3423 .height = 87, 3424 }, 3425 .delay = { 3426 .prepare = 41, 3427 .enable = 50, 3428 .unprepare = 41, 3429 .disable = 50, 3430 }, 3431 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3432 }; 3433 3434 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3435 .clock = 9000, 3436 .hdisplay = 480, 3437 .hsync_start = 480 + 5, 3438 .hsync_end = 480 + 5 + 30, 3439 .htotal = 480 + 5 + 30 + 10, 3440 .vdisplay = 272, 3441 .vsync_start = 272 + 8, 3442 .vsync_end = 272 + 8 + 5, 3443 .vtotal = 272 + 8 + 5 + 3, 3444 }; 3445 3446 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3447 .modes = &olimex_lcd_olinuxino_43ts_mode, 3448 .num_modes = 1, 3449 .size = { 3450 .width = 95, 3451 .height = 54, 3452 }, 3453 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3454 }; 3455 3456 /* 3457 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3458 * pixel clocks, but this is the timing that was being used in the Adafruit 3459 * installation instructions. 3460 */ 3461 static const struct drm_display_mode ontat_yx700wv03_mode = { 3462 .clock = 29500, 3463 .hdisplay = 800, 3464 .hsync_start = 824, 3465 .hsync_end = 896, 3466 .htotal = 992, 3467 .vdisplay = 480, 3468 .vsync_start = 483, 3469 .vsync_end = 493, 3470 .vtotal = 500, 3471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3472 }; 3473 3474 /* 3475 * Specification at: 3476 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3477 */ 3478 static const struct panel_desc ontat_yx700wv03 = { 3479 .modes = &ontat_yx700wv03_mode, 3480 .num_modes = 1, 3481 .bpc = 8, 3482 .size = { 3483 .width = 154, 3484 .height = 83, 3485 }, 3486 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3487 }; 3488 3489 static const struct drm_display_mode ortustech_com37h3m_mode = { 3490 .clock = 22230, 3491 .hdisplay = 480, 3492 .hsync_start = 480 + 40, 3493 .hsync_end = 480 + 40 + 10, 3494 .htotal = 480 + 40 + 10 + 40, 3495 .vdisplay = 640, 3496 .vsync_start = 640 + 4, 3497 .vsync_end = 640 + 4 + 2, 3498 .vtotal = 640 + 4 + 2 + 4, 3499 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3500 }; 3501 3502 static const struct panel_desc ortustech_com37h3m = { 3503 .modes = &ortustech_com37h3m_mode, 3504 .num_modes = 1, 3505 .bpc = 8, 3506 .size = { 3507 .width = 56, /* 56.16mm */ 3508 .height = 75, /* 74.88mm */ 3509 }, 3510 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3511 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3512 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3513 }; 3514 3515 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3516 .clock = 25000, 3517 .hdisplay = 480, 3518 .hsync_start = 480 + 10, 3519 .hsync_end = 480 + 10 + 10, 3520 .htotal = 480 + 10 + 10 + 15, 3521 .vdisplay = 800, 3522 .vsync_start = 800 + 3, 3523 .vsync_end = 800 + 3 + 3, 3524 .vtotal = 800 + 3 + 3 + 3, 3525 }; 3526 3527 static const struct panel_desc ortustech_com43h4m85ulc = { 3528 .modes = &ortustech_com43h4m85ulc_mode, 3529 .num_modes = 1, 3530 .bpc = 6, 3531 .size = { 3532 .width = 56, 3533 .height = 93, 3534 }, 3535 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3536 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3537 .connector_type = DRM_MODE_CONNECTOR_DPI, 3538 }; 3539 3540 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3541 .clock = 33000, 3542 .hdisplay = 800, 3543 .hsync_start = 800 + 210, 3544 .hsync_end = 800 + 210 + 30, 3545 .htotal = 800 + 210 + 30 + 16, 3546 .vdisplay = 480, 3547 .vsync_start = 480 + 22, 3548 .vsync_end = 480 + 22 + 13, 3549 .vtotal = 480 + 22 + 13 + 10, 3550 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3551 }; 3552 3553 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3554 .modes = &osddisplays_osd070t1718_19ts_mode, 3555 .num_modes = 1, 3556 .bpc = 8, 3557 .size = { 3558 .width = 152, 3559 .height = 91, 3560 }, 3561 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3562 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3563 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3564 .connector_type = DRM_MODE_CONNECTOR_DPI, 3565 }; 3566 3567 static const struct drm_display_mode pda_91_00156_a0_mode = { 3568 .clock = 33300, 3569 .hdisplay = 800, 3570 .hsync_start = 800 + 1, 3571 .hsync_end = 800 + 1 + 64, 3572 .htotal = 800 + 1 + 64 + 64, 3573 .vdisplay = 480, 3574 .vsync_start = 480 + 1, 3575 .vsync_end = 480 + 1 + 23, 3576 .vtotal = 480 + 1 + 23 + 22, 3577 }; 3578 3579 static const struct panel_desc pda_91_00156_a0 = { 3580 .modes = &pda_91_00156_a0_mode, 3581 .num_modes = 1, 3582 .size = { 3583 .width = 152, 3584 .height = 91, 3585 }, 3586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3587 }; 3588 3589 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3590 .clock = 66500, 3591 .hdisplay = 1280, 3592 .hsync_start = 1280 + 12, 3593 .hsync_end = 1280 + 12 + 20, 3594 .htotal = 1280 + 12 + 20 + 56, 3595 .vdisplay = 800, 3596 .vsync_start = 800 + 1, 3597 .vsync_end = 800 + 1 + 3, 3598 .vtotal = 800 + 1 + 3 + 20, 3599 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3600 }; 3601 3602 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3603 .modes = &powertip_ph128800t006_zhc01_mode, 3604 .num_modes = 1, 3605 .bpc = 8, 3606 .size = { 3607 .width = 216, 3608 .height = 135, 3609 }, 3610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3611 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3612 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3613 }; 3614 3615 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3616 .clock = 24750, 3617 .hdisplay = 800, 3618 .hsync_start = 800 + 54, 3619 .hsync_end = 800 + 54 + 2, 3620 .htotal = 800 + 54 + 2 + 44, 3621 .vdisplay = 480, 3622 .vsync_start = 480 + 49, 3623 .vsync_end = 480 + 49 + 2, 3624 .vtotal = 480 + 49 + 2 + 22, 3625 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3626 }; 3627 3628 static const struct panel_desc powertip_ph800480t013_idf02 = { 3629 .modes = &powertip_ph800480t013_idf02_mode, 3630 .num_modes = 1, 3631 .bpc = 8, 3632 .size = { 3633 .width = 152, 3634 .height = 91, 3635 }, 3636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3637 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3638 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3639 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3640 .connector_type = DRM_MODE_CONNECTOR_DPI, 3641 }; 3642 3643 static const struct drm_display_mode primeview_pm070wl4_mode = { 3644 .clock = 32000, 3645 .hdisplay = 800, 3646 .hsync_start = 800 + 42, 3647 .hsync_end = 800 + 42 + 128, 3648 .htotal = 800 + 42 + 128 + 86, 3649 .vdisplay = 480, 3650 .vsync_start = 480 + 10, 3651 .vsync_end = 480 + 10 + 2, 3652 .vtotal = 480 + 10 + 2 + 33, 3653 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3654 }; 3655 3656 static const struct panel_desc primeview_pm070wl4 = { 3657 .modes = &primeview_pm070wl4_mode, 3658 .num_modes = 1, 3659 .bpc = 6, 3660 .size = { 3661 .width = 152, 3662 .height = 91, 3663 }, 3664 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3665 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3666 .connector_type = DRM_MODE_CONNECTOR_DPI, 3667 }; 3668 3669 static const struct drm_display_mode qd43003c0_40_mode = { 3670 .clock = 9000, 3671 .hdisplay = 480, 3672 .hsync_start = 480 + 8, 3673 .hsync_end = 480 + 8 + 4, 3674 .htotal = 480 + 8 + 4 + 39, 3675 .vdisplay = 272, 3676 .vsync_start = 272 + 4, 3677 .vsync_end = 272 + 4 + 10, 3678 .vtotal = 272 + 4 + 10 + 2, 3679 }; 3680 3681 static const struct panel_desc qd43003c0_40 = { 3682 .modes = &qd43003c0_40_mode, 3683 .num_modes = 1, 3684 .bpc = 8, 3685 .size = { 3686 .width = 95, 3687 .height = 53, 3688 }, 3689 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3690 }; 3691 3692 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3693 { /* 60 Hz */ 3694 .clock = 10800, 3695 .hdisplay = 480, 3696 .hsync_start = 480 + 77, 3697 .hsync_end = 480 + 77 + 41, 3698 .htotal = 480 + 77 + 41 + 2, 3699 .vdisplay = 272, 3700 .vsync_start = 272 + 16, 3701 .vsync_end = 272 + 16 + 10, 3702 .vtotal = 272 + 16 + 10 + 2, 3703 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3704 }, 3705 { /* 50 Hz */ 3706 .clock = 10800, 3707 .hdisplay = 480, 3708 .hsync_start = 480 + 17, 3709 .hsync_end = 480 + 17 + 41, 3710 .htotal = 480 + 17 + 41 + 2, 3711 .vdisplay = 272, 3712 .vsync_start = 272 + 116, 3713 .vsync_end = 272 + 116 + 10, 3714 .vtotal = 272 + 116 + 10 + 2, 3715 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3716 }, 3717 }; 3718 3719 static const struct panel_desc qishenglong_gopher2b_lcd = { 3720 .modes = qishenglong_gopher2b_lcd_modes, 3721 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3722 .bpc = 8, 3723 .size = { 3724 .width = 95, 3725 .height = 54, 3726 }, 3727 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3728 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3729 .connector_type = DRM_MODE_CONNECTOR_DPI, 3730 }; 3731 3732 static const struct display_timing rocktech_rk043fn48h_timing = { 3733 .pixelclock = { 6000000, 9000000, 12000000 }, 3734 .hactive = { 480, 480, 480 }, 3735 .hback_porch = { 8, 43, 43 }, 3736 .hfront_porch = { 2, 8, 10 }, 3737 .hsync_len = { 1, 1, 1 }, 3738 .vactive = { 272, 272, 272 }, 3739 .vback_porch = { 2, 12, 26 }, 3740 .vfront_porch = { 1, 4, 4 }, 3741 .vsync_len = { 1, 10, 10 }, 3742 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3743 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3744 DISPLAY_FLAGS_SYNC_POSEDGE, 3745 }; 3746 3747 static const struct panel_desc rocktech_rk043fn48h = { 3748 .timings = &rocktech_rk043fn48h_timing, 3749 .num_timings = 1, 3750 .bpc = 8, 3751 .size = { 3752 .width = 95, 3753 .height = 54, 3754 }, 3755 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3756 .connector_type = DRM_MODE_CONNECTOR_DPI, 3757 }; 3758 3759 static const struct display_timing rocktech_rk070er9427_timing = { 3760 .pixelclock = { 26400000, 33300000, 46800000 }, 3761 .hactive = { 800, 800, 800 }, 3762 .hfront_porch = { 16, 210, 354 }, 3763 .hback_porch = { 46, 46, 46 }, 3764 .hsync_len = { 1, 1, 1 }, 3765 .vactive = { 480, 480, 480 }, 3766 .vfront_porch = { 7, 22, 147 }, 3767 .vback_porch = { 23, 23, 23 }, 3768 .vsync_len = { 1, 1, 1 }, 3769 .flags = DISPLAY_FLAGS_DE_HIGH, 3770 }; 3771 3772 static const struct panel_desc rocktech_rk070er9427 = { 3773 .timings = &rocktech_rk070er9427_timing, 3774 .num_timings = 1, 3775 .bpc = 6, 3776 .size = { 3777 .width = 154, 3778 .height = 86, 3779 }, 3780 .delay = { 3781 .prepare = 41, 3782 .enable = 50, 3783 .unprepare = 41, 3784 .disable = 50, 3785 }, 3786 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3787 }; 3788 3789 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3790 .clock = 71100, 3791 .hdisplay = 1280, 3792 .hsync_start = 1280 + 48, 3793 .hsync_end = 1280 + 48 + 32, 3794 .htotal = 1280 + 48 + 32 + 80, 3795 .vdisplay = 800, 3796 .vsync_start = 800 + 2, 3797 .vsync_end = 800 + 2 + 5, 3798 .vtotal = 800 + 2 + 5 + 16, 3799 }; 3800 3801 static const struct panel_desc rocktech_rk101ii01d_ct = { 3802 .modes = &rocktech_rk101ii01d_ct_mode, 3803 .bpc = 8, 3804 .num_modes = 1, 3805 .size = { 3806 .width = 217, 3807 .height = 136, 3808 }, 3809 .delay = { 3810 .prepare = 50, 3811 .disable = 50, 3812 }, 3813 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3814 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3815 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3816 }; 3817 3818 static const struct display_timing samsung_ltl101al01_timing = { 3819 .pixelclock = { 66663000, 66663000, 66663000 }, 3820 .hactive = { 1280, 1280, 1280 }, 3821 .hfront_porch = { 18, 18, 18 }, 3822 .hback_porch = { 36, 36, 36 }, 3823 .hsync_len = { 16, 16, 16 }, 3824 .vactive = { 800, 800, 800 }, 3825 .vfront_porch = { 4, 4, 4 }, 3826 .vback_porch = { 16, 16, 16 }, 3827 .vsync_len = { 3, 3, 3 }, 3828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3829 }; 3830 3831 static const struct panel_desc samsung_ltl101al01 = { 3832 .timings = &samsung_ltl101al01_timing, 3833 .num_timings = 1, 3834 .bpc = 8, 3835 .size = { 3836 .width = 217, 3837 .height = 135, 3838 }, 3839 .delay = { 3840 .prepare = 40, 3841 .enable = 300, 3842 .disable = 200, 3843 .unprepare = 600, 3844 }, 3845 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3846 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3847 }; 3848 3849 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3850 .clock = 54030, 3851 .hdisplay = 1024, 3852 .hsync_start = 1024 + 24, 3853 .hsync_end = 1024 + 24 + 136, 3854 .htotal = 1024 + 24 + 136 + 160, 3855 .vdisplay = 600, 3856 .vsync_start = 600 + 3, 3857 .vsync_end = 600 + 3 + 6, 3858 .vtotal = 600 + 3 + 6 + 61, 3859 }; 3860 3861 static const struct panel_desc samsung_ltn101nt05 = { 3862 .modes = &samsung_ltn101nt05_mode, 3863 .num_modes = 1, 3864 .bpc = 6, 3865 .size = { 3866 .width = 223, 3867 .height = 125, 3868 }, 3869 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3870 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3872 }; 3873 3874 static const struct display_timing satoz_sat050at40h12r2_timing = { 3875 .pixelclock = {33300000, 33300000, 50000000}, 3876 .hactive = {800, 800, 800}, 3877 .hfront_porch = {16, 210, 354}, 3878 .hback_porch = {46, 46, 46}, 3879 .hsync_len = {1, 1, 40}, 3880 .vactive = {480, 480, 480}, 3881 .vfront_porch = {7, 22, 147}, 3882 .vback_porch = {23, 23, 23}, 3883 .vsync_len = {1, 1, 20}, 3884 }; 3885 3886 static const struct panel_desc satoz_sat050at40h12r2 = { 3887 .timings = &satoz_sat050at40h12r2_timing, 3888 .num_timings = 1, 3889 .bpc = 8, 3890 .size = { 3891 .width = 108, 3892 .height = 65, 3893 }, 3894 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3895 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3896 }; 3897 3898 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3899 .clock = 33260, 3900 .hdisplay = 800, 3901 .hsync_start = 800 + 64, 3902 .hsync_end = 800 + 64 + 128, 3903 .htotal = 800 + 64 + 128 + 64, 3904 .vdisplay = 480, 3905 .vsync_start = 480 + 8, 3906 .vsync_end = 480 + 8 + 2, 3907 .vtotal = 480 + 8 + 2 + 35, 3908 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3909 }; 3910 3911 static const struct panel_desc sharp_lq070y3dg3b = { 3912 .modes = &sharp_lq070y3dg3b_mode, 3913 .num_modes = 1, 3914 .bpc = 8, 3915 .size = { 3916 .width = 152, /* 152.4mm */ 3917 .height = 91, /* 91.4mm */ 3918 }, 3919 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3920 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3921 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3922 }; 3923 3924 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3925 .clock = 5500, 3926 .hdisplay = 240, 3927 .hsync_start = 240 + 16, 3928 .hsync_end = 240 + 16 + 7, 3929 .htotal = 240 + 16 + 7 + 5, 3930 .vdisplay = 320, 3931 .vsync_start = 320 + 9, 3932 .vsync_end = 320 + 9 + 1, 3933 .vtotal = 320 + 9 + 1 + 7, 3934 }; 3935 3936 static const struct panel_desc sharp_lq035q7db03 = { 3937 .modes = &sharp_lq035q7db03_mode, 3938 .num_modes = 1, 3939 .bpc = 6, 3940 .size = { 3941 .width = 54, 3942 .height = 72, 3943 }, 3944 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3945 }; 3946 3947 static const struct display_timing sharp_lq101k1ly04_timing = { 3948 .pixelclock = { 60000000, 65000000, 80000000 }, 3949 .hactive = { 1280, 1280, 1280 }, 3950 .hfront_porch = { 20, 20, 20 }, 3951 .hback_porch = { 20, 20, 20 }, 3952 .hsync_len = { 10, 10, 10 }, 3953 .vactive = { 800, 800, 800 }, 3954 .vfront_porch = { 4, 4, 4 }, 3955 .vback_porch = { 4, 4, 4 }, 3956 .vsync_len = { 4, 4, 4 }, 3957 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3958 }; 3959 3960 static const struct panel_desc sharp_lq101k1ly04 = { 3961 .timings = &sharp_lq101k1ly04_timing, 3962 .num_timings = 1, 3963 .bpc = 8, 3964 .size = { 3965 .width = 217, 3966 .height = 136, 3967 }, 3968 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3969 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3970 }; 3971 3972 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3973 { /* 50 Hz */ 3974 .clock = 3000, 3975 .hdisplay = 240, 3976 .hsync_start = 240 + 58, 3977 .hsync_end = 240 + 58 + 1, 3978 .htotal = 240 + 58 + 1 + 1, 3979 .vdisplay = 160, 3980 .vsync_start = 160 + 24, 3981 .vsync_end = 160 + 24 + 10, 3982 .vtotal = 160 + 24 + 10 + 6, 3983 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3984 }, 3985 { /* 60 Hz */ 3986 .clock = 3000, 3987 .hdisplay = 240, 3988 .hsync_start = 240 + 8, 3989 .hsync_end = 240 + 8 + 1, 3990 .htotal = 240 + 8 + 1 + 1, 3991 .vdisplay = 160, 3992 .vsync_start = 160 + 24, 3993 .vsync_end = 160 + 24 + 10, 3994 .vtotal = 160 + 24 + 10 + 6, 3995 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3996 }, 3997 }; 3998 3999 static const struct panel_desc sharp_ls020b1dd01d = { 4000 .modes = sharp_ls020b1dd01d_modes, 4001 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4002 .bpc = 6, 4003 .size = { 4004 .width = 42, 4005 .height = 28, 4006 }, 4007 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4008 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4009 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4010 | DRM_BUS_FLAG_SHARP_SIGNALS, 4011 }; 4012 4013 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4014 .clock = 33300, 4015 .hdisplay = 800, 4016 .hsync_start = 800 + 1, 4017 .hsync_end = 800 + 1 + 64, 4018 .htotal = 800 + 1 + 64 + 64, 4019 .vdisplay = 480, 4020 .vsync_start = 480 + 1, 4021 .vsync_end = 480 + 1 + 23, 4022 .vtotal = 480 + 1 + 23 + 22, 4023 }; 4024 4025 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4026 .modes = &shelly_sca07010_bfn_lnn_mode, 4027 .num_modes = 1, 4028 .size = { 4029 .width = 152, 4030 .height = 91, 4031 }, 4032 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4033 }; 4034 4035 static const struct drm_display_mode starry_kr070pe2t_mode = { 4036 .clock = 33000, 4037 .hdisplay = 800, 4038 .hsync_start = 800 + 209, 4039 .hsync_end = 800 + 209 + 1, 4040 .htotal = 800 + 209 + 1 + 45, 4041 .vdisplay = 480, 4042 .vsync_start = 480 + 22, 4043 .vsync_end = 480 + 22 + 1, 4044 .vtotal = 480 + 22 + 1 + 22, 4045 }; 4046 4047 static const struct panel_desc starry_kr070pe2t = { 4048 .modes = &starry_kr070pe2t_mode, 4049 .num_modes = 1, 4050 .bpc = 8, 4051 .size = { 4052 .width = 152, 4053 .height = 86, 4054 }, 4055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4056 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4057 .connector_type = DRM_MODE_CONNECTOR_DPI, 4058 }; 4059 4060 static const struct display_timing startek_kd070wvfpa_mode = { 4061 .pixelclock = { 25200000, 27200000, 30500000 }, 4062 .hactive = { 800, 800, 800 }, 4063 .hfront_porch = { 19, 44, 115 }, 4064 .hback_porch = { 5, 16, 101 }, 4065 .hsync_len = { 1, 2, 100 }, 4066 .vactive = { 480, 480, 480 }, 4067 .vfront_porch = { 5, 43, 67 }, 4068 .vback_porch = { 5, 5, 67 }, 4069 .vsync_len = { 1, 2, 66 }, 4070 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4071 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4072 DISPLAY_FLAGS_SYNC_POSEDGE, 4073 }; 4074 4075 static const struct panel_desc startek_kd070wvfpa = { 4076 .timings = &startek_kd070wvfpa_mode, 4077 .num_timings = 1, 4078 .bpc = 8, 4079 .size = { 4080 .width = 152, 4081 .height = 91, 4082 }, 4083 .delay = { 4084 .prepare = 20, 4085 .enable = 200, 4086 .disable = 200, 4087 }, 4088 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4089 .connector_type = DRM_MODE_CONNECTOR_DPI, 4090 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4091 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4092 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4093 }; 4094 4095 static const struct display_timing tsd_tst043015cmhx_timing = { 4096 .pixelclock = { 5000000, 9000000, 12000000 }, 4097 .hactive = { 480, 480, 480 }, 4098 .hfront_porch = { 4, 5, 65 }, 4099 .hback_porch = { 36, 40, 255 }, 4100 .hsync_len = { 1, 1, 1 }, 4101 .vactive = { 272, 272, 272 }, 4102 .vfront_porch = { 2, 8, 97 }, 4103 .vback_porch = { 3, 8, 31 }, 4104 .vsync_len = { 1, 1, 1 }, 4105 4106 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4107 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4108 }; 4109 4110 static const struct panel_desc tsd_tst043015cmhx = { 4111 .timings = &tsd_tst043015cmhx_timing, 4112 .num_timings = 1, 4113 .bpc = 8, 4114 .size = { 4115 .width = 105, 4116 .height = 67, 4117 }, 4118 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4119 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4120 }; 4121 4122 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4123 .clock = 30000, 4124 .hdisplay = 800, 4125 .hsync_start = 800 + 39, 4126 .hsync_end = 800 + 39 + 47, 4127 .htotal = 800 + 39 + 47 + 39, 4128 .vdisplay = 480, 4129 .vsync_start = 480 + 13, 4130 .vsync_end = 480 + 13 + 2, 4131 .vtotal = 480 + 13 + 2 + 29, 4132 }; 4133 4134 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4135 .modes = &tfc_s9700rtwv43tr_01b_mode, 4136 .num_modes = 1, 4137 .bpc = 8, 4138 .size = { 4139 .width = 155, 4140 .height = 90, 4141 }, 4142 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4143 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4144 }; 4145 4146 static const struct display_timing tianma_tm070jdhg30_timing = { 4147 .pixelclock = { 62600000, 68200000, 78100000 }, 4148 .hactive = { 1280, 1280, 1280 }, 4149 .hfront_porch = { 15, 64, 159 }, 4150 .hback_porch = { 5, 5, 5 }, 4151 .hsync_len = { 1, 1, 256 }, 4152 .vactive = { 800, 800, 800 }, 4153 .vfront_porch = { 3, 40, 99 }, 4154 .vback_porch = { 2, 2, 2 }, 4155 .vsync_len = { 1, 1, 128 }, 4156 .flags = DISPLAY_FLAGS_DE_HIGH, 4157 }; 4158 4159 static const struct panel_desc tianma_tm070jdhg30 = { 4160 .timings = &tianma_tm070jdhg30_timing, 4161 .num_timings = 1, 4162 .bpc = 8, 4163 .size = { 4164 .width = 151, 4165 .height = 95, 4166 }, 4167 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4168 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4169 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4170 }; 4171 4172 static const struct panel_desc tianma_tm070jvhg33 = { 4173 .timings = &tianma_tm070jdhg30_timing, 4174 .num_timings = 1, 4175 .bpc = 8, 4176 .size = { 4177 .width = 150, 4178 .height = 94, 4179 }, 4180 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4181 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4182 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4183 }; 4184 4185 static const struct display_timing tianma_tm070rvhg71_timing = { 4186 .pixelclock = { 27700000, 29200000, 39600000 }, 4187 .hactive = { 800, 800, 800 }, 4188 .hfront_porch = { 12, 40, 212 }, 4189 .hback_porch = { 88, 88, 88 }, 4190 .hsync_len = { 1, 1, 40 }, 4191 .vactive = { 480, 480, 480 }, 4192 .vfront_porch = { 1, 13, 88 }, 4193 .vback_porch = { 32, 32, 32 }, 4194 .vsync_len = { 1, 1, 3 }, 4195 .flags = DISPLAY_FLAGS_DE_HIGH, 4196 }; 4197 4198 static const struct panel_desc tianma_tm070rvhg71 = { 4199 .timings = &tianma_tm070rvhg71_timing, 4200 .num_timings = 1, 4201 .bpc = 8, 4202 .size = { 4203 .width = 154, 4204 .height = 86, 4205 }, 4206 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4207 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4208 }; 4209 4210 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4211 { 4212 .clock = 10000, 4213 .hdisplay = 320, 4214 .hsync_start = 320 + 50, 4215 .hsync_end = 320 + 50 + 6, 4216 .htotal = 320 + 50 + 6 + 38, 4217 .vdisplay = 240, 4218 .vsync_start = 240 + 3, 4219 .vsync_end = 240 + 3 + 1, 4220 .vtotal = 240 + 3 + 1 + 17, 4221 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4222 }, 4223 }; 4224 4225 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4226 .modes = ti_nspire_cx_lcd_mode, 4227 .num_modes = 1, 4228 .bpc = 8, 4229 .size = { 4230 .width = 65, 4231 .height = 49, 4232 }, 4233 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4234 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4235 }; 4236 4237 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4238 { 4239 .clock = 10000, 4240 .hdisplay = 320, 4241 .hsync_start = 320 + 6, 4242 .hsync_end = 320 + 6 + 6, 4243 .htotal = 320 + 6 + 6 + 6, 4244 .vdisplay = 240, 4245 .vsync_start = 240 + 0, 4246 .vsync_end = 240 + 0 + 1, 4247 .vtotal = 240 + 0 + 1 + 0, 4248 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4249 }, 4250 }; 4251 4252 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4253 .modes = ti_nspire_classic_lcd_mode, 4254 .num_modes = 1, 4255 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4256 .bpc = 8, 4257 .size = { 4258 .width = 71, 4259 .height = 53, 4260 }, 4261 /* This is the grayscale bus format */ 4262 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4263 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4264 }; 4265 4266 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4267 .clock = 79500, 4268 .hdisplay = 1280, 4269 .hsync_start = 1280 + 192, 4270 .hsync_end = 1280 + 192 + 128, 4271 .htotal = 1280 + 192 + 128 + 64, 4272 .vdisplay = 768, 4273 .vsync_start = 768 + 20, 4274 .vsync_end = 768 + 20 + 7, 4275 .vtotal = 768 + 20 + 7 + 3, 4276 }; 4277 4278 static const struct panel_desc toshiba_lt089ac29000 = { 4279 .modes = &toshiba_lt089ac29000_mode, 4280 .num_modes = 1, 4281 .size = { 4282 .width = 194, 4283 .height = 116, 4284 }, 4285 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4286 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4287 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4288 }; 4289 4290 static const struct drm_display_mode tpk_f07a_0102_mode = { 4291 .clock = 33260, 4292 .hdisplay = 800, 4293 .hsync_start = 800 + 40, 4294 .hsync_end = 800 + 40 + 128, 4295 .htotal = 800 + 40 + 128 + 88, 4296 .vdisplay = 480, 4297 .vsync_start = 480 + 10, 4298 .vsync_end = 480 + 10 + 2, 4299 .vtotal = 480 + 10 + 2 + 33, 4300 }; 4301 4302 static const struct panel_desc tpk_f07a_0102 = { 4303 .modes = &tpk_f07a_0102_mode, 4304 .num_modes = 1, 4305 .size = { 4306 .width = 152, 4307 .height = 91, 4308 }, 4309 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4310 }; 4311 4312 static const struct drm_display_mode tpk_f10a_0102_mode = { 4313 .clock = 45000, 4314 .hdisplay = 1024, 4315 .hsync_start = 1024 + 176, 4316 .hsync_end = 1024 + 176 + 5, 4317 .htotal = 1024 + 176 + 5 + 88, 4318 .vdisplay = 600, 4319 .vsync_start = 600 + 20, 4320 .vsync_end = 600 + 20 + 5, 4321 .vtotal = 600 + 20 + 5 + 25, 4322 }; 4323 4324 static const struct panel_desc tpk_f10a_0102 = { 4325 .modes = &tpk_f10a_0102_mode, 4326 .num_modes = 1, 4327 .size = { 4328 .width = 223, 4329 .height = 125, 4330 }, 4331 }; 4332 4333 static const struct display_timing urt_umsh_8596md_timing = { 4334 .pixelclock = { 33260000, 33260000, 33260000 }, 4335 .hactive = { 800, 800, 800 }, 4336 .hfront_porch = { 41, 41, 41 }, 4337 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4338 .hsync_len = { 71, 128, 128 }, 4339 .vactive = { 480, 480, 480 }, 4340 .vfront_porch = { 10, 10, 10 }, 4341 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4342 .vsync_len = { 2, 2, 2 }, 4343 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4344 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4345 }; 4346 4347 static const struct panel_desc urt_umsh_8596md_lvds = { 4348 .timings = &urt_umsh_8596md_timing, 4349 .num_timings = 1, 4350 .bpc = 6, 4351 .size = { 4352 .width = 152, 4353 .height = 91, 4354 }, 4355 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4356 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4357 }; 4358 4359 static const struct panel_desc urt_umsh_8596md_parallel = { 4360 .timings = &urt_umsh_8596md_timing, 4361 .num_timings = 1, 4362 .bpc = 6, 4363 .size = { 4364 .width = 152, 4365 .height = 91, 4366 }, 4367 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4368 }; 4369 4370 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4371 .clock = 60000, 4372 .hdisplay = 1024, 4373 .hsync_start = 1024 + 160, 4374 .hsync_end = 1024 + 160 + 100, 4375 .htotal = 1024 + 160 + 100 + 60, 4376 .vdisplay = 600, 4377 .vsync_start = 600 + 12, 4378 .vsync_end = 600 + 12 + 10, 4379 .vtotal = 600 + 12 + 10 + 13, 4380 }; 4381 4382 static const struct panel_desc vivax_tpc9150_panel = { 4383 .modes = &vivax_tpc9150_panel_mode, 4384 .num_modes = 1, 4385 .bpc = 6, 4386 .size = { 4387 .width = 200, 4388 .height = 115, 4389 }, 4390 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4391 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4392 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4393 }; 4394 4395 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4396 .clock = 33333, 4397 .hdisplay = 800, 4398 .hsync_start = 800 + 210, 4399 .hsync_end = 800 + 210 + 20, 4400 .htotal = 800 + 210 + 20 + 46, 4401 .vdisplay = 480, 4402 .vsync_start = 480 + 22, 4403 .vsync_end = 480 + 22 + 10, 4404 .vtotal = 480 + 22 + 10 + 23, 4405 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4406 }; 4407 4408 static const struct panel_desc vl050_8048nt_c01 = { 4409 .modes = &vl050_8048nt_c01_mode, 4410 .num_modes = 1, 4411 .bpc = 8, 4412 .size = { 4413 .width = 120, 4414 .height = 76, 4415 }, 4416 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4417 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4418 }; 4419 4420 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4421 .clock = 6410, 4422 .hdisplay = 320, 4423 .hsync_start = 320 + 20, 4424 .hsync_end = 320 + 20 + 30, 4425 .htotal = 320 + 20 + 30 + 38, 4426 .vdisplay = 240, 4427 .vsync_start = 240 + 4, 4428 .vsync_end = 240 + 4 + 3, 4429 .vtotal = 240 + 4 + 3 + 15, 4430 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4431 }; 4432 4433 static const struct panel_desc winstar_wf35ltiacd = { 4434 .modes = &winstar_wf35ltiacd_mode, 4435 .num_modes = 1, 4436 .bpc = 8, 4437 .size = { 4438 .width = 70, 4439 .height = 53, 4440 }, 4441 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4442 }; 4443 4444 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4445 .clock = 51200, 4446 .hdisplay = 1024, 4447 .hsync_start = 1024 + 100, 4448 .hsync_end = 1024 + 100 + 100, 4449 .htotal = 1024 + 100 + 100 + 120, 4450 .vdisplay = 600, 4451 .vsync_start = 600 + 10, 4452 .vsync_end = 600 + 10 + 10, 4453 .vtotal = 600 + 10 + 10 + 15, 4454 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4455 }; 4456 4457 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4458 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4459 .num_modes = 1, 4460 .bpc = 8, 4461 .size = { 4462 .width = 154, 4463 .height = 90, 4464 }, 4465 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4467 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4468 }; 4469 4470 static const struct drm_display_mode arm_rtsm_mode[] = { 4471 { 4472 .clock = 65000, 4473 .hdisplay = 1024, 4474 .hsync_start = 1024 + 24, 4475 .hsync_end = 1024 + 24 + 136, 4476 .htotal = 1024 + 24 + 136 + 160, 4477 .vdisplay = 768, 4478 .vsync_start = 768 + 3, 4479 .vsync_end = 768 + 3 + 6, 4480 .vtotal = 768 + 3 + 6 + 29, 4481 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4482 }, 4483 }; 4484 4485 static const struct panel_desc arm_rtsm = { 4486 .modes = arm_rtsm_mode, 4487 .num_modes = 1, 4488 .bpc = 8, 4489 .size = { 4490 .width = 400, 4491 .height = 300, 4492 }, 4493 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4494 }; 4495 4496 static const struct of_device_id platform_of_match[] = { 4497 { 4498 .compatible = "ampire,am-1280800n3tzqw-t00h", 4499 .data = &ire_am_1280800n3tzqw_t00h, 4500 }, { 4501 .compatible = "ampire,am-480272h3tmqw-t01h", 4502 .data = &ire_am_480272h3tmqw_t01h, 4503 }, { 4504 .compatible = "ampire,am-800480l1tmqw-t00h", 4505 .data = &ire_am_800480l1tmqw_t00h, 4506 }, { 4507 .compatible = "ampire,am800480r3tmqwa1h", 4508 .data = &ire_am800480r3tmqwa1h, 4509 }, { 4510 .compatible = "ampire,am800600p5tmqw-tb8h", 4511 .data = &ire_am800600p5tmqwtb8h, 4512 }, { 4513 .compatible = "arm,rtsm-display", 4514 .data = &arm_rtsm, 4515 }, { 4516 .compatible = "armadeus,st0700-adapt", 4517 .data = &armadeus_st0700_adapt, 4518 }, { 4519 .compatible = "auo,b101aw03", 4520 .data = &auo_b101aw03, 4521 }, { 4522 .compatible = "auo,b101xtn01", 4523 .data = &auo_b101xtn01, 4524 }, { 4525 .compatible = "auo,b116xw03", 4526 .data = &auo_b116xw03, 4527 }, { 4528 .compatible = "auo,g070vvn01", 4529 .data = &auo_g070vvn01, 4530 }, { 4531 .compatible = "auo,g101evn010", 4532 .data = &auo_g101evn010, 4533 }, { 4534 .compatible = "auo,g104sn02", 4535 .data = &auo_g104sn02, 4536 }, { 4537 .compatible = "auo,g121ean01", 4538 .data = &auo_g121ean01, 4539 }, { 4540 .compatible = "auo,g133han01", 4541 .data = &auo_g133han01, 4542 }, { 4543 .compatible = "auo,g156han04", 4544 .data = &auo_g156han04, 4545 }, { 4546 .compatible = "auo,g156xtn01", 4547 .data = &auo_g156xtn01, 4548 }, { 4549 .compatible = "auo,g185han01", 4550 .data = &auo_g185han01, 4551 }, { 4552 .compatible = "auo,g190ean01", 4553 .data = &auo_g190ean01, 4554 }, { 4555 .compatible = "auo,p320hvn03", 4556 .data = &auo_p320hvn03, 4557 }, { 4558 .compatible = "auo,t215hvn01", 4559 .data = &auo_t215hvn01, 4560 }, { 4561 .compatible = "avic,tm070ddh03", 4562 .data = &avic_tm070ddh03, 4563 }, { 4564 .compatible = "bananapi,s070wv20-ct16", 4565 .data = &bananapi_s070wv20_ct16, 4566 }, { 4567 .compatible = "boe,bp082wx1-100", 4568 .data = &boe_bp082wx1_100, 4569 }, { 4570 .compatible = "boe,bp101wx1-100", 4571 .data = &boe_bp101wx1_100, 4572 }, { 4573 .compatible = "boe,ev121wxm-n10-1850", 4574 .data = &boe_ev121wxm_n10_1850, 4575 }, { 4576 .compatible = "boe,hv070wsa-100", 4577 .data = &boe_hv070wsa 4578 }, { 4579 .compatible = "cct,cmt430b19n00", 4580 .data = &cct_cmt430b19n00, 4581 }, { 4582 .compatible = "cdtech,s043wq26h-ct7", 4583 .data = &cdtech_s043wq26h_ct7, 4584 }, { 4585 .compatible = "cdtech,s070pws19hp-fc21", 4586 .data = &cdtech_s070pws19hp_fc21, 4587 }, { 4588 .compatible = "cdtech,s070swv29hg-dc44", 4589 .data = &cdtech_s070swv29hg_dc44, 4590 }, { 4591 .compatible = "cdtech,s070wv95-ct16", 4592 .data = &cdtech_s070wv95_ct16, 4593 }, { 4594 .compatible = "chefree,ch101olhlwh-002", 4595 .data = &chefree_ch101olhlwh_002, 4596 }, { 4597 .compatible = "chunghwa,claa070wp03xg", 4598 .data = &chunghwa_claa070wp03xg, 4599 }, { 4600 .compatible = "chunghwa,claa101wa01a", 4601 .data = &chunghwa_claa101wa01a 4602 }, { 4603 .compatible = "chunghwa,claa101wb01", 4604 .data = &chunghwa_claa101wb01 4605 }, { 4606 .compatible = "dataimage,fg040346dsswbg04", 4607 .data = &dataimage_fg040346dsswbg04, 4608 }, { 4609 .compatible = "dataimage,fg1001l0dsswmg01", 4610 .data = &dataimage_fg1001l0dsswmg01, 4611 }, { 4612 .compatible = "dataimage,scf0700c48ggu18", 4613 .data = &dataimage_scf0700c48ggu18, 4614 }, { 4615 .compatible = "dlc,dlc0700yzg-1", 4616 .data = &dlc_dlc0700yzg_1, 4617 }, { 4618 .compatible = "dlc,dlc1010gig", 4619 .data = &dlc_dlc1010gig, 4620 }, { 4621 .compatible = "edt,et035012dm6", 4622 .data = &edt_et035012dm6, 4623 }, { 4624 .compatible = "edt,etm0350g0dh6", 4625 .data = &edt_etm0350g0dh6, 4626 }, { 4627 .compatible = "edt,etm043080dh6gp", 4628 .data = &edt_etm043080dh6gp, 4629 }, { 4630 .compatible = "edt,etm0430g0dh6", 4631 .data = &edt_etm0430g0dh6, 4632 }, { 4633 .compatible = "edt,et057090dhu", 4634 .data = &edt_et057090dhu, 4635 }, { 4636 .compatible = "edt,et070080dh6", 4637 .data = &edt_etm0700g0dh6, 4638 }, { 4639 .compatible = "edt,etm0700g0dh6", 4640 .data = &edt_etm0700g0dh6, 4641 }, { 4642 .compatible = "edt,etm0700g0bdh6", 4643 .data = &edt_etm0700g0bdh6, 4644 }, { 4645 .compatible = "edt,etm0700g0edh6", 4646 .data = &edt_etm0700g0bdh6, 4647 }, { 4648 .compatible = "edt,etml0700y5dha", 4649 .data = &edt_etml0700y5dha, 4650 }, { 4651 .compatible = "edt,etml1010g3dra", 4652 .data = &edt_etml1010g3dra, 4653 }, { 4654 .compatible = "edt,etmv570g2dhu", 4655 .data = &edt_etmv570g2dhu, 4656 }, { 4657 .compatible = "eink,vb3300-kca", 4658 .data = &eink_vb3300_kca, 4659 }, { 4660 .compatible = "evervision,vgg644804", 4661 .data = &evervision_vgg644804, 4662 }, { 4663 .compatible = "evervision,vgg804821", 4664 .data = &evervision_vgg804821, 4665 }, { 4666 .compatible = "foxlink,fl500wvr00-a0t", 4667 .data = &foxlink_fl500wvr00_a0t, 4668 }, { 4669 .compatible = "frida,frd350h54004", 4670 .data = &frida_frd350h54004, 4671 }, { 4672 .compatible = "friendlyarm,hd702e", 4673 .data = &friendlyarm_hd702e, 4674 }, { 4675 .compatible = "giantplus,gpg482739qs5", 4676 .data = &giantplus_gpg482739qs5 4677 }, { 4678 .compatible = "giantplus,gpm940b0", 4679 .data = &giantplus_gpm940b0, 4680 }, { 4681 .compatible = "hannstar,hsd070pww1", 4682 .data = &hannstar_hsd070pww1, 4683 }, { 4684 .compatible = "hannstar,hsd100pxn1", 4685 .data = &hannstar_hsd100pxn1, 4686 }, { 4687 .compatible = "hannstar,hsd101pww2", 4688 .data = &hannstar_hsd101pww2, 4689 }, { 4690 .compatible = "hit,tx23d38vm0caa", 4691 .data = &hitachi_tx23d38vm0caa 4692 }, { 4693 .compatible = "innolux,at043tn24", 4694 .data = &innolux_at043tn24, 4695 }, { 4696 .compatible = "innolux,at070tn92", 4697 .data = &innolux_at070tn92, 4698 }, { 4699 .compatible = "innolux,g070ace-l01", 4700 .data = &innolux_g070ace_l01, 4701 }, { 4702 .compatible = "innolux,g070y2-l01", 4703 .data = &innolux_g070y2_l01, 4704 }, { 4705 .compatible = "innolux,g070y2-t02", 4706 .data = &innolux_g070y2_t02, 4707 }, { 4708 .compatible = "innolux,g101ice-l01", 4709 .data = &innolux_g101ice_l01 4710 }, { 4711 .compatible = "innolux,g121i1-l01", 4712 .data = &innolux_g121i1_l01 4713 }, { 4714 .compatible = "innolux,g121x1-l03", 4715 .data = &innolux_g121x1_l03, 4716 }, { 4717 .compatible = "innolux,g121xce-l01", 4718 .data = &innolux_g121xce_l01, 4719 }, { 4720 .compatible = "innolux,g156hce-l01", 4721 .data = &innolux_g156hce_l01, 4722 }, { 4723 .compatible = "innolux,n156bge-l21", 4724 .data = &innolux_n156bge_l21, 4725 }, { 4726 .compatible = "innolux,zj070na-01p", 4727 .data = &innolux_zj070na_01p, 4728 }, { 4729 .compatible = "koe,tx14d24vm1bpa", 4730 .data = &koe_tx14d24vm1bpa, 4731 }, { 4732 .compatible = "koe,tx26d202vm0bwa", 4733 .data = &koe_tx26d202vm0bwa, 4734 }, { 4735 .compatible = "koe,tx31d200vm0baa", 4736 .data = &koe_tx31d200vm0baa, 4737 }, { 4738 .compatible = "kyo,tcg121xglp", 4739 .data = &kyo_tcg121xglp, 4740 }, { 4741 .compatible = "lemaker,bl035-rgb-002", 4742 .data = &lemaker_bl035_rgb_002, 4743 }, { 4744 .compatible = "lg,lb070wv8", 4745 .data = &lg_lb070wv8, 4746 }, { 4747 .compatible = "lincolntech,lcd185-101ct", 4748 .data = &lincolntech_lcd185_101ct, 4749 }, { 4750 .compatible = "logicpd,type28", 4751 .data = &logicpd_type_28, 4752 }, { 4753 .compatible = "logictechno,lt161010-2nhc", 4754 .data = &logictechno_lt161010_2nh, 4755 }, { 4756 .compatible = "logictechno,lt161010-2nhr", 4757 .data = &logictechno_lt161010_2nh, 4758 }, { 4759 .compatible = "logictechno,lt170410-2whc", 4760 .data = &logictechno_lt170410_2whc, 4761 }, { 4762 .compatible = "logictechno,lttd800480070-l2rt", 4763 .data = &logictechno_lttd800480070_l2rt, 4764 }, { 4765 .compatible = "logictechno,lttd800480070-l6wh-rt", 4766 .data = &logictechno_lttd800480070_l6wh_rt, 4767 }, { 4768 .compatible = "microtips,mf-101hiebcaf0", 4769 .data = µtips_mf_101hiebcaf0_c, 4770 }, { 4771 .compatible = "microtips,mf-103hieb0ga0", 4772 .data = µtips_mf_103hieb0ga0, 4773 }, { 4774 .compatible = "mitsubishi,aa070mc01-ca1", 4775 .data = &mitsubishi_aa070mc01, 4776 }, { 4777 .compatible = "mitsubishi,aa084xe01", 4778 .data = &mitsubishi_aa084xe01, 4779 }, { 4780 .compatible = "multi-inno,mi0700s4t-6", 4781 .data = &multi_inno_mi0700s4t_6, 4782 }, { 4783 .compatible = "multi-inno,mi0800ft-9", 4784 .data = &multi_inno_mi0800ft_9, 4785 }, { 4786 .compatible = "multi-inno,mi1010ait-1cp", 4787 .data = &multi_inno_mi1010ait_1cp, 4788 }, { 4789 .compatible = "nec,nl12880bc20-05", 4790 .data = &nec_nl12880bc20_05, 4791 }, { 4792 .compatible = "nec,nl4827hc19-05b", 4793 .data = &nec_nl4827hc19_05b, 4794 }, { 4795 .compatible = "netron-dy,e231732", 4796 .data = &netron_dy_e231732, 4797 }, { 4798 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4799 .data = &newhaven_nhd_43_480272ef_atxl, 4800 }, { 4801 .compatible = "nlt,nl192108ac18-02d", 4802 .data = &nlt_nl192108ac18_02d, 4803 }, { 4804 .compatible = "nvd,9128", 4805 .data = &nvd_9128, 4806 }, { 4807 .compatible = "okaya,rs800480t-7x0gp", 4808 .data = &okaya_rs800480t_7x0gp, 4809 }, { 4810 .compatible = "olimex,lcd-olinuxino-43-ts", 4811 .data = &olimex_lcd_olinuxino_43ts, 4812 }, { 4813 .compatible = "ontat,yx700wv03", 4814 .data = &ontat_yx700wv03, 4815 }, { 4816 .compatible = "ortustech,com37h3m05dtc", 4817 .data = &ortustech_com37h3m, 4818 }, { 4819 .compatible = "ortustech,com37h3m99dtc", 4820 .data = &ortustech_com37h3m, 4821 }, { 4822 .compatible = "ortustech,com43h4m85ulc", 4823 .data = &ortustech_com43h4m85ulc, 4824 }, { 4825 .compatible = "osddisplays,osd070t1718-19ts", 4826 .data = &osddisplays_osd070t1718_19ts, 4827 }, { 4828 .compatible = "pda,91-00156-a0", 4829 .data = &pda_91_00156_a0, 4830 }, { 4831 .compatible = "powertip,ph128800t006-zhc01", 4832 .data = &powertip_ph128800t006_zhc01, 4833 }, { 4834 .compatible = "powertip,ph800480t013-idf02", 4835 .data = &powertip_ph800480t013_idf02, 4836 }, { 4837 .compatible = "primeview,pm070wl4", 4838 .data = &primeview_pm070wl4, 4839 }, { 4840 .compatible = "qiaodian,qd43003c0-40", 4841 .data = &qd43003c0_40, 4842 }, { 4843 .compatible = "qishenglong,gopher2b-lcd", 4844 .data = &qishenglong_gopher2b_lcd, 4845 }, { 4846 .compatible = "rocktech,rk043fn48h", 4847 .data = &rocktech_rk043fn48h, 4848 }, { 4849 .compatible = "rocktech,rk070er9427", 4850 .data = &rocktech_rk070er9427, 4851 }, { 4852 .compatible = "rocktech,rk101ii01d-ct", 4853 .data = &rocktech_rk101ii01d_ct, 4854 }, { 4855 .compatible = "samsung,ltl101al01", 4856 .data = &samsung_ltl101al01, 4857 }, { 4858 .compatible = "samsung,ltn101nt05", 4859 .data = &samsung_ltn101nt05, 4860 }, { 4861 .compatible = "satoz,sat050at40h12r2", 4862 .data = &satoz_sat050at40h12r2, 4863 }, { 4864 .compatible = "sharp,lq035q7db03", 4865 .data = &sharp_lq035q7db03, 4866 }, { 4867 .compatible = "sharp,lq070y3dg3b", 4868 .data = &sharp_lq070y3dg3b, 4869 }, { 4870 .compatible = "sharp,lq101k1ly04", 4871 .data = &sharp_lq101k1ly04, 4872 }, { 4873 .compatible = "sharp,ls020b1dd01d", 4874 .data = &sharp_ls020b1dd01d, 4875 }, { 4876 .compatible = "shelly,sca07010-bfn-lnn", 4877 .data = &shelly_sca07010_bfn_lnn, 4878 }, { 4879 .compatible = "starry,kr070pe2t", 4880 .data = &starry_kr070pe2t, 4881 }, { 4882 .compatible = "startek,kd070wvfpa", 4883 .data = &startek_kd070wvfpa, 4884 }, { 4885 .compatible = "team-source-display,tst043015cmhx", 4886 .data = &tsd_tst043015cmhx, 4887 }, { 4888 .compatible = "tfc,s9700rtwv43tr-01b", 4889 .data = &tfc_s9700rtwv43tr_01b, 4890 }, { 4891 .compatible = "tianma,tm070jdhg30", 4892 .data = &tianma_tm070jdhg30, 4893 }, { 4894 .compatible = "tianma,tm070jvhg33", 4895 .data = &tianma_tm070jvhg33, 4896 }, { 4897 .compatible = "tianma,tm070rvhg71", 4898 .data = &tianma_tm070rvhg71, 4899 }, { 4900 .compatible = "ti,nspire-cx-lcd-panel", 4901 .data = &ti_nspire_cx_lcd_panel, 4902 }, { 4903 .compatible = "ti,nspire-classic-lcd-panel", 4904 .data = &ti_nspire_classic_lcd_panel, 4905 }, { 4906 .compatible = "toshiba,lt089ac29000", 4907 .data = &toshiba_lt089ac29000, 4908 }, { 4909 .compatible = "tpk,f07a-0102", 4910 .data = &tpk_f07a_0102, 4911 }, { 4912 .compatible = "tpk,f10a-0102", 4913 .data = &tpk_f10a_0102, 4914 }, { 4915 .compatible = "urt,umsh-8596md-t", 4916 .data = &urt_umsh_8596md_parallel, 4917 }, { 4918 .compatible = "urt,umsh-8596md-1t", 4919 .data = &urt_umsh_8596md_parallel, 4920 }, { 4921 .compatible = "urt,umsh-8596md-7t", 4922 .data = &urt_umsh_8596md_parallel, 4923 }, { 4924 .compatible = "urt,umsh-8596md-11t", 4925 .data = &urt_umsh_8596md_lvds, 4926 }, { 4927 .compatible = "urt,umsh-8596md-19t", 4928 .data = &urt_umsh_8596md_lvds, 4929 }, { 4930 .compatible = "urt,umsh-8596md-20t", 4931 .data = &urt_umsh_8596md_parallel, 4932 }, { 4933 .compatible = "vivax,tpc9150-panel", 4934 .data = &vivax_tpc9150_panel, 4935 }, { 4936 .compatible = "vxt,vl050-8048nt-c01", 4937 .data = &vl050_8048nt_c01, 4938 }, { 4939 .compatible = "winstar,wf35ltiacd", 4940 .data = &winstar_wf35ltiacd, 4941 }, { 4942 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4943 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4944 }, { 4945 /* Must be the last entry */ 4946 .compatible = "panel-dpi", 4947 .data = &panel_dpi, 4948 }, { 4949 /* sentinel */ 4950 } 4951 }; 4952 MODULE_DEVICE_TABLE(of, platform_of_match); 4953 4954 static int panel_simple_platform_probe(struct platform_device *pdev) 4955 { 4956 const struct panel_desc *desc; 4957 4958 desc = of_device_get_match_data(&pdev->dev); 4959 if (!desc) 4960 return -ENODEV; 4961 4962 return panel_simple_probe(&pdev->dev, desc); 4963 } 4964 4965 static void panel_simple_platform_remove(struct platform_device *pdev) 4966 { 4967 panel_simple_remove(&pdev->dev); 4968 } 4969 4970 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4971 { 4972 panel_simple_shutdown(&pdev->dev); 4973 } 4974 4975 static const struct dev_pm_ops panel_simple_pm_ops = { 4976 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4977 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4978 pm_runtime_force_resume) 4979 }; 4980 4981 static struct platform_driver panel_simple_platform_driver = { 4982 .driver = { 4983 .name = "panel-simple", 4984 .of_match_table = platform_of_match, 4985 .pm = &panel_simple_pm_ops, 4986 }, 4987 .probe = panel_simple_platform_probe, 4988 .remove_new = panel_simple_platform_remove, 4989 .shutdown = panel_simple_platform_shutdown, 4990 }; 4991 4992 struct panel_desc_dsi { 4993 struct panel_desc desc; 4994 4995 unsigned long flags; 4996 enum mipi_dsi_pixel_format format; 4997 unsigned int lanes; 4998 }; 4999 5000 static const struct drm_display_mode auo_b080uan01_mode = { 5001 .clock = 154500, 5002 .hdisplay = 1200, 5003 .hsync_start = 1200 + 62, 5004 .hsync_end = 1200 + 62 + 4, 5005 .htotal = 1200 + 62 + 4 + 62, 5006 .vdisplay = 1920, 5007 .vsync_start = 1920 + 9, 5008 .vsync_end = 1920 + 9 + 2, 5009 .vtotal = 1920 + 9 + 2 + 8, 5010 }; 5011 5012 static const struct panel_desc_dsi auo_b080uan01 = { 5013 .desc = { 5014 .modes = &auo_b080uan01_mode, 5015 .num_modes = 1, 5016 .bpc = 8, 5017 .size = { 5018 .width = 108, 5019 .height = 272, 5020 }, 5021 .connector_type = DRM_MODE_CONNECTOR_DSI, 5022 }, 5023 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5024 .format = MIPI_DSI_FMT_RGB888, 5025 .lanes = 4, 5026 }; 5027 5028 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5029 .clock = 160000, 5030 .hdisplay = 1200, 5031 .hsync_start = 1200 + 120, 5032 .hsync_end = 1200 + 120 + 20, 5033 .htotal = 1200 + 120 + 20 + 21, 5034 .vdisplay = 1920, 5035 .vsync_start = 1920 + 21, 5036 .vsync_end = 1920 + 21 + 3, 5037 .vtotal = 1920 + 21 + 3 + 18, 5038 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5039 }; 5040 5041 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5042 .desc = { 5043 .modes = &boe_tv080wum_nl0_mode, 5044 .num_modes = 1, 5045 .size = { 5046 .width = 107, 5047 .height = 172, 5048 }, 5049 .connector_type = DRM_MODE_CONNECTOR_DSI, 5050 }, 5051 .flags = MIPI_DSI_MODE_VIDEO | 5052 MIPI_DSI_MODE_VIDEO_BURST | 5053 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5054 .format = MIPI_DSI_FMT_RGB888, 5055 .lanes = 4, 5056 }; 5057 5058 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5059 .clock = 71000, 5060 .hdisplay = 800, 5061 .hsync_start = 800 + 32, 5062 .hsync_end = 800 + 32 + 1, 5063 .htotal = 800 + 32 + 1 + 57, 5064 .vdisplay = 1280, 5065 .vsync_start = 1280 + 28, 5066 .vsync_end = 1280 + 28 + 1, 5067 .vtotal = 1280 + 28 + 1 + 14, 5068 }; 5069 5070 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5071 .desc = { 5072 .modes = &lg_ld070wx3_sl01_mode, 5073 .num_modes = 1, 5074 .bpc = 8, 5075 .size = { 5076 .width = 94, 5077 .height = 151, 5078 }, 5079 .connector_type = DRM_MODE_CONNECTOR_DSI, 5080 }, 5081 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5082 .format = MIPI_DSI_FMT_RGB888, 5083 .lanes = 4, 5084 }; 5085 5086 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5087 .clock = 67000, 5088 .hdisplay = 720, 5089 .hsync_start = 720 + 12, 5090 .hsync_end = 720 + 12 + 4, 5091 .htotal = 720 + 12 + 4 + 112, 5092 .vdisplay = 1280, 5093 .vsync_start = 1280 + 8, 5094 .vsync_end = 1280 + 8 + 4, 5095 .vtotal = 1280 + 8 + 4 + 12, 5096 }; 5097 5098 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5099 .desc = { 5100 .modes = &lg_lh500wx1_sd03_mode, 5101 .num_modes = 1, 5102 .bpc = 8, 5103 .size = { 5104 .width = 62, 5105 .height = 110, 5106 }, 5107 .connector_type = DRM_MODE_CONNECTOR_DSI, 5108 }, 5109 .flags = MIPI_DSI_MODE_VIDEO, 5110 .format = MIPI_DSI_FMT_RGB888, 5111 .lanes = 4, 5112 }; 5113 5114 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5115 .clock = 157200, 5116 .hdisplay = 1920, 5117 .hsync_start = 1920 + 154, 5118 .hsync_end = 1920 + 154 + 16, 5119 .htotal = 1920 + 154 + 16 + 32, 5120 .vdisplay = 1200, 5121 .vsync_start = 1200 + 17, 5122 .vsync_end = 1200 + 17 + 2, 5123 .vtotal = 1200 + 17 + 2 + 16, 5124 }; 5125 5126 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5127 .desc = { 5128 .modes = &panasonic_vvx10f004b00_mode, 5129 .num_modes = 1, 5130 .bpc = 8, 5131 .size = { 5132 .width = 217, 5133 .height = 136, 5134 }, 5135 .connector_type = DRM_MODE_CONNECTOR_DSI, 5136 }, 5137 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5138 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5139 .format = MIPI_DSI_FMT_RGB888, 5140 .lanes = 4, 5141 }; 5142 5143 static const struct drm_display_mode lg_acx467akm_7_mode = { 5144 .clock = 150000, 5145 .hdisplay = 1080, 5146 .hsync_start = 1080 + 2, 5147 .hsync_end = 1080 + 2 + 2, 5148 .htotal = 1080 + 2 + 2 + 2, 5149 .vdisplay = 1920, 5150 .vsync_start = 1920 + 2, 5151 .vsync_end = 1920 + 2 + 2, 5152 .vtotal = 1920 + 2 + 2 + 2, 5153 }; 5154 5155 static const struct panel_desc_dsi lg_acx467akm_7 = { 5156 .desc = { 5157 .modes = &lg_acx467akm_7_mode, 5158 .num_modes = 1, 5159 .bpc = 8, 5160 .size = { 5161 .width = 62, 5162 .height = 110, 5163 }, 5164 .connector_type = DRM_MODE_CONNECTOR_DSI, 5165 }, 5166 .flags = 0, 5167 .format = MIPI_DSI_FMT_RGB888, 5168 .lanes = 4, 5169 }; 5170 5171 static const struct drm_display_mode osd101t2045_53ts_mode = { 5172 .clock = 154500, 5173 .hdisplay = 1920, 5174 .hsync_start = 1920 + 112, 5175 .hsync_end = 1920 + 112 + 16, 5176 .htotal = 1920 + 112 + 16 + 32, 5177 .vdisplay = 1200, 5178 .vsync_start = 1200 + 16, 5179 .vsync_end = 1200 + 16 + 2, 5180 .vtotal = 1200 + 16 + 2 + 16, 5181 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5182 }; 5183 5184 static const struct panel_desc_dsi osd101t2045_53ts = { 5185 .desc = { 5186 .modes = &osd101t2045_53ts_mode, 5187 .num_modes = 1, 5188 .bpc = 8, 5189 .size = { 5190 .width = 217, 5191 .height = 136, 5192 }, 5193 .connector_type = DRM_MODE_CONNECTOR_DSI, 5194 }, 5195 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5196 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5197 MIPI_DSI_MODE_NO_EOT_PACKET, 5198 .format = MIPI_DSI_FMT_RGB888, 5199 .lanes = 4, 5200 }; 5201 5202 static const struct of_device_id dsi_of_match[] = { 5203 { 5204 .compatible = "auo,b080uan01", 5205 .data = &auo_b080uan01 5206 }, { 5207 .compatible = "boe,tv080wum-nl0", 5208 .data = &boe_tv080wum_nl0 5209 }, { 5210 .compatible = "lg,ld070wx3-sl01", 5211 .data = &lg_ld070wx3_sl01 5212 }, { 5213 .compatible = "lg,lh500wx1-sd03", 5214 .data = &lg_lh500wx1_sd03 5215 }, { 5216 .compatible = "panasonic,vvx10f004b00", 5217 .data = &panasonic_vvx10f004b00 5218 }, { 5219 .compatible = "lg,acx467akm-7", 5220 .data = &lg_acx467akm_7 5221 }, { 5222 .compatible = "osddisplays,osd101t2045-53ts", 5223 .data = &osd101t2045_53ts 5224 }, { 5225 /* sentinel */ 5226 } 5227 }; 5228 MODULE_DEVICE_TABLE(of, dsi_of_match); 5229 5230 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5231 { 5232 const struct panel_desc_dsi *desc; 5233 int err; 5234 5235 desc = of_device_get_match_data(&dsi->dev); 5236 if (!desc) 5237 return -ENODEV; 5238 5239 err = panel_simple_probe(&dsi->dev, &desc->desc); 5240 if (err < 0) 5241 return err; 5242 5243 dsi->mode_flags = desc->flags; 5244 dsi->format = desc->format; 5245 dsi->lanes = desc->lanes; 5246 5247 err = mipi_dsi_attach(dsi); 5248 if (err) { 5249 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5250 5251 drm_panel_remove(&panel->base); 5252 } 5253 5254 return err; 5255 } 5256 5257 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5258 { 5259 int err; 5260 5261 err = mipi_dsi_detach(dsi); 5262 if (err < 0) 5263 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5264 5265 panel_simple_remove(&dsi->dev); 5266 } 5267 5268 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5269 { 5270 panel_simple_shutdown(&dsi->dev); 5271 } 5272 5273 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5274 .driver = { 5275 .name = "panel-simple-dsi", 5276 .of_match_table = dsi_of_match, 5277 .pm = &panel_simple_pm_ops, 5278 }, 5279 .probe = panel_simple_dsi_probe, 5280 .remove = panel_simple_dsi_remove, 5281 .shutdown = panel_simple_dsi_shutdown, 5282 }; 5283 5284 static int __init panel_simple_init(void) 5285 { 5286 int err; 5287 5288 err = platform_driver_register(&panel_simple_platform_driver); 5289 if (err < 0) 5290 return err; 5291 5292 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5293 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5294 if (err < 0) 5295 goto err_did_platform_register; 5296 } 5297 5298 return 0; 5299 5300 err_did_platform_register: 5301 platform_driver_unregister(&panel_simple_platform_driver); 5302 5303 return err; 5304 } 5305 module_init(panel_simple_init); 5306 5307 static void __exit panel_simple_exit(void) 5308 { 5309 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5310 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5311 5312 platform_driver_unregister(&panel_simple_platform_driver); 5313 } 5314 module_exit(panel_simple_exit); 5315 5316 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5317 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5318 MODULE_LICENSE("GPL and additional rights"); 5319