1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744 disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747 free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752 } 753 754 static void panel_simple_shutdown(struct device *dev) 755 { 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782 } 783 784 static void panel_simple_remove(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795 } 796 797 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808 }; 809 810 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821 }; 822 823 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 824 .clock = 9000, 825 .hdisplay = 480, 826 .hsync_start = 480 + 2, 827 .hsync_end = 480 + 2 + 41, 828 .htotal = 480 + 2 + 41 + 2, 829 .vdisplay = 272, 830 .vsync_start = 272 + 2, 831 .vsync_end = 272 + 2 + 10, 832 .vtotal = 272 + 2 + 10 + 2, 833 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 834 }; 835 836 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 837 .modes = &ire_am_480272h3tmqw_t01h_mode, 838 .num_modes = 1, 839 .bpc = 8, 840 .size = { 841 .width = 99, 842 .height = 58, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 845 }; 846 847 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 848 .clock = 33333, 849 .hdisplay = 800, 850 .hsync_start = 800 + 0, 851 .hsync_end = 800 + 0 + 255, 852 .htotal = 800 + 0 + 255 + 0, 853 .vdisplay = 480, 854 .vsync_start = 480 + 2, 855 .vsync_end = 480 + 2 + 45, 856 .vtotal = 480 + 2 + 45 + 0, 857 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 858 }; 859 860 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 861 .pixelclock = { 29930000, 33260000, 36590000 }, 862 .hactive = { 800, 800, 800 }, 863 .hfront_porch = { 1, 40, 168 }, 864 .hback_porch = { 88, 88, 88 }, 865 .hsync_len = { 1, 128, 128 }, 866 .vactive = { 480, 480, 480 }, 867 .vfront_porch = { 1, 35, 37 }, 868 .vback_porch = { 8, 8, 8 }, 869 .vsync_len = { 1, 2, 2 }, 870 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 871 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 872 DISPLAY_FLAGS_SYNC_POSEDGE, 873 }; 874 875 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 876 .timings = &ire_am_800480l1tmqw_t00h_timing, 877 .num_timings = 1, 878 .bpc = 8, 879 .size = { 880 .width = 111, 881 .height = 67, 882 }, 883 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 884 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 885 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 886 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 887 .connector_type = DRM_MODE_CONNECTOR_DPI, 888 }; 889 890 static const struct panel_desc ampire_am800480r3tmqwa1h = { 891 .modes = &ire_am800480r3tmqwa1h_mode, 892 .num_modes = 1, 893 .bpc = 6, 894 .size = { 895 .width = 152, 896 .height = 91, 897 }, 898 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 899 }; 900 901 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 902 .pixelclock = { 34500000, 39600000, 50400000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 12, 112, 312 }, 905 .hback_porch = { 87, 87, 48 }, 906 .hsync_len = { 1, 1, 40 }, 907 .vactive = { 600, 600, 600 }, 908 .vfront_porch = { 1, 21, 61 }, 909 .vback_porch = { 38, 38, 19 }, 910 .vsync_len = { 1, 1, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 913 DISPLAY_FLAGS_SYNC_POSEDGE, 914 }; 915 916 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 917 .timings = &ire_am800600p5tmqw_tb8h_timing, 918 .num_timings = 1, 919 .bpc = 6, 920 .size = { 921 .width = 162, 922 .height = 122, 923 }, 924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 926 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 927 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 928 .connector_type = DRM_MODE_CONNECTOR_DPI, 929 }; 930 931 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 932 .pixelclock = { 26400000, 33300000, 46800000 }, 933 .hactive = { 800, 800, 800 }, 934 .hfront_porch = { 16, 210, 354 }, 935 .hback_porch = { 45, 36, 6 }, 936 .hsync_len = { 1, 10, 40 }, 937 .vactive = { 480, 480, 480 }, 938 .vfront_porch = { 7, 22, 147 }, 939 .vback_porch = { 22, 13, 3 }, 940 .vsync_len = { 1, 10, 20 }, 941 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 942 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 943 }; 944 945 static const struct panel_desc armadeus_st0700_adapt = { 946 .timings = &santek_st0700i5y_rbslw_f_timing, 947 .num_timings = 1, 948 .bpc = 6, 949 .size = { 950 .width = 154, 951 .height = 86, 952 }, 953 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 954 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 955 }; 956 957 static const struct drm_display_mode auo_b101aw03_mode = { 958 .clock = 51450, 959 .hdisplay = 1024, 960 .hsync_start = 1024 + 156, 961 .hsync_end = 1024 + 156 + 8, 962 .htotal = 1024 + 156 + 8 + 156, 963 .vdisplay = 600, 964 .vsync_start = 600 + 16, 965 .vsync_end = 600 + 16 + 6, 966 .vtotal = 600 + 16 + 6 + 16, 967 }; 968 969 static const struct panel_desc auo_b101aw03 = { 970 .modes = &auo_b101aw03_mode, 971 .num_modes = 1, 972 .bpc = 6, 973 .size = { 974 .width = 223, 975 .height = 125, 976 }, 977 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 978 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 980 }; 981 982 static const struct drm_display_mode auo_b101xtn01_mode = { 983 .clock = 72000, 984 .hdisplay = 1366, 985 .hsync_start = 1366 + 20, 986 .hsync_end = 1366 + 20 + 70, 987 .htotal = 1366 + 20 + 70, 988 .vdisplay = 768, 989 .vsync_start = 768 + 14, 990 .vsync_end = 768 + 14 + 42, 991 .vtotal = 768 + 14 + 42, 992 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 993 }; 994 995 static const struct panel_desc auo_b101xtn01 = { 996 .modes = &auo_b101xtn01_mode, 997 .num_modes = 1, 998 .bpc = 6, 999 .size = { 1000 .width = 223, 1001 .height = 125, 1002 }, 1003 }; 1004 1005 static const struct drm_display_mode auo_b116xw03_mode = { 1006 .clock = 70589, 1007 .hdisplay = 1366, 1008 .hsync_start = 1366 + 40, 1009 .hsync_end = 1366 + 40 + 40, 1010 .htotal = 1366 + 40 + 40 + 32, 1011 .vdisplay = 768, 1012 .vsync_start = 768 + 10, 1013 .vsync_end = 768 + 10 + 12, 1014 .vtotal = 768 + 10 + 12 + 6, 1015 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1016 }; 1017 1018 static const struct panel_desc auo_b116xw03 = { 1019 .modes = &auo_b116xw03_mode, 1020 .num_modes = 1, 1021 .bpc = 6, 1022 .size = { 1023 .width = 256, 1024 .height = 144, 1025 }, 1026 .delay = { 1027 .prepare = 1, 1028 .enable = 200, 1029 .disable = 200, 1030 .unprepare = 500, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1035 }; 1036 1037 static const struct display_timing auo_g070vvn01_timings = { 1038 .pixelclock = { 33300000, 34209000, 45000000 }, 1039 .hactive = { 800, 800, 800 }, 1040 .hfront_porch = { 20, 40, 200 }, 1041 .hback_porch = { 87, 40, 1 }, 1042 .hsync_len = { 1, 48, 87 }, 1043 .vactive = { 480, 480, 480 }, 1044 .vfront_porch = { 5, 13, 200 }, 1045 .vback_porch = { 31, 31, 29 }, 1046 .vsync_len = { 1, 1, 3 }, 1047 }; 1048 1049 static const struct panel_desc auo_g070vvn01 = { 1050 .timings = &auo_g070vvn01_timings, 1051 .num_timings = 1, 1052 .bpc = 8, 1053 .size = { 1054 .width = 152, 1055 .height = 91, 1056 }, 1057 .delay = { 1058 .prepare = 200, 1059 .enable = 50, 1060 .disable = 50, 1061 .unprepare = 1000, 1062 }, 1063 }; 1064 1065 static const struct display_timing auo_g101evn010_timing = { 1066 .pixelclock = { 64000000, 68930000, 85000000 }, 1067 .hactive = { 1280, 1280, 1280 }, 1068 .hfront_porch = { 8, 64, 256 }, 1069 .hback_porch = { 8, 64, 256 }, 1070 .hsync_len = { 40, 168, 767 }, 1071 .vactive = { 800, 800, 800 }, 1072 .vfront_porch = { 4, 8, 100 }, 1073 .vback_porch = { 4, 8, 100 }, 1074 .vsync_len = { 8, 16, 223 }, 1075 }; 1076 1077 static const struct panel_desc auo_g101evn010 = { 1078 .timings = &auo_g101evn010_timing, 1079 .num_timings = 1, 1080 .bpc = 6, 1081 .size = { 1082 .width = 216, 1083 .height = 135, 1084 }, 1085 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1086 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1087 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1088 }; 1089 1090 static const struct drm_display_mode auo_g104sn02_mode = { 1091 .clock = 40000, 1092 .hdisplay = 800, 1093 .hsync_start = 800 + 40, 1094 .hsync_end = 800 + 40 + 216, 1095 .htotal = 800 + 40 + 216 + 128, 1096 .vdisplay = 600, 1097 .vsync_start = 600 + 10, 1098 .vsync_end = 600 + 10 + 35, 1099 .vtotal = 600 + 10 + 35 + 2, 1100 }; 1101 1102 static const struct panel_desc auo_g104sn02 = { 1103 .modes = &auo_g104sn02_mode, 1104 .num_modes = 1, 1105 .bpc = 8, 1106 .size = { 1107 .width = 211, 1108 .height = 158, 1109 }, 1110 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1111 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1112 }; 1113 1114 static const struct drm_display_mode auo_g104stn01_mode = { 1115 .clock = 40000, 1116 .hdisplay = 800, 1117 .hsync_start = 800 + 40, 1118 .hsync_end = 800 + 40 + 88, 1119 .htotal = 800 + 40 + 88 + 128, 1120 .vdisplay = 600, 1121 .vsync_start = 600 + 1, 1122 .vsync_end = 600 + 1 + 23, 1123 .vtotal = 600 + 1 + 23 + 4, 1124 }; 1125 1126 static const struct panel_desc auo_g104stn01 = { 1127 .modes = &auo_g104stn01_mode, 1128 .num_modes = 1, 1129 .bpc = 8, 1130 .size = { 1131 .width = 211, 1132 .height = 158, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136 }; 1137 1138 static const struct display_timing auo_g121ean01_timing = { 1139 .pixelclock = { 60000000, 74400000, 90000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 20, 50, 100 }, 1142 .hback_porch = { 20, 50, 100 }, 1143 .hsync_len = { 30, 100, 200 }, 1144 .vactive = { 800, 800, 800 }, 1145 .vfront_porch = { 2, 10, 25 }, 1146 .vback_porch = { 2, 10, 25 }, 1147 .vsync_len = { 4, 18, 50 }, 1148 }; 1149 1150 static const struct panel_desc auo_g121ean01 = { 1151 .timings = &auo_g121ean01_timing, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 261, 1156 .height = 163, 1157 }, 1158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1160 }; 1161 1162 static const struct display_timing auo_g133han01_timings = { 1163 .pixelclock = { 134000000, 141200000, 149000000 }, 1164 .hactive = { 1920, 1920, 1920 }, 1165 .hfront_porch = { 39, 58, 77 }, 1166 .hback_porch = { 59, 88, 117 }, 1167 .hsync_len = { 28, 42, 56 }, 1168 .vactive = { 1080, 1080, 1080 }, 1169 .vfront_porch = { 3, 8, 11 }, 1170 .vback_porch = { 5, 14, 19 }, 1171 .vsync_len = { 4, 14, 19 }, 1172 }; 1173 1174 static const struct panel_desc auo_g133han01 = { 1175 .timings = &auo_g133han01_timings, 1176 .num_timings = 1, 1177 .bpc = 8, 1178 .size = { 1179 .width = 293, 1180 .height = 165, 1181 }, 1182 .delay = { 1183 .prepare = 200, 1184 .enable = 50, 1185 .disable = 50, 1186 .unprepare = 1000, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190 }; 1191 1192 static const struct display_timing auo_g156han04_timings = { 1193 .pixelclock = { 137000000, 141000000, 146000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 60, 60, 60 }, 1196 .hback_porch = { 90, 92, 111 }, 1197 .hsync_len = { 32, 32, 32 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 12, 12, 12 }, 1200 .vback_porch = { 24, 36, 56 }, 1201 .vsync_len = { 8, 8, 8 }, 1202 }; 1203 1204 static const struct panel_desc auo_g156han04 = { 1205 .timings = &auo_g156han04_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 344, 1210 .height = 194, 1211 }, 1212 .delay = { 1213 .prepare = 50, /* T2 */ 1214 .enable = 200, /* T3 */ 1215 .disable = 110, /* T10 */ 1216 .unprepare = 1000, /* T13 */ 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1221 }; 1222 1223 static const struct drm_display_mode auo_g156xtn01_mode = { 1224 .clock = 76000, 1225 .hdisplay = 1366, 1226 .hsync_start = 1366 + 33, 1227 .hsync_end = 1366 + 33 + 67, 1228 .htotal = 1560, 1229 .vdisplay = 768, 1230 .vsync_start = 768 + 4, 1231 .vsync_end = 768 + 4 + 4, 1232 .vtotal = 806, 1233 }; 1234 1235 static const struct panel_desc auo_g156xtn01 = { 1236 .modes = &auo_g156xtn01_mode, 1237 .num_modes = 1, 1238 .bpc = 8, 1239 .size = { 1240 .width = 344, 1241 .height = 194, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245 }; 1246 1247 static const struct display_timing auo_g185han01_timings = { 1248 .pixelclock = { 120000000, 144000000, 175000000 }, 1249 .hactive = { 1920, 1920, 1920 }, 1250 .hfront_porch = { 36, 120, 148 }, 1251 .hback_porch = { 24, 88, 108 }, 1252 .hsync_len = { 20, 48, 64 }, 1253 .vactive = { 1080, 1080, 1080 }, 1254 .vfront_porch = { 6, 10, 40 }, 1255 .vback_porch = { 2, 5, 20 }, 1256 .vsync_len = { 2, 5, 20 }, 1257 }; 1258 1259 static const struct panel_desc auo_g185han01 = { 1260 .timings = &auo_g185han01_timings, 1261 .num_timings = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 409, 1265 .height = 230, 1266 }, 1267 .delay = { 1268 .prepare = 50, 1269 .enable = 200, 1270 .disable = 110, 1271 .unprepare = 1000, 1272 }, 1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1274 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1275 }; 1276 1277 static const struct display_timing auo_g190ean01_timings = { 1278 .pixelclock = { 90000000, 108000000, 135000000 }, 1279 .hactive = { 1280, 1280, 1280 }, 1280 .hfront_porch = { 126, 184, 1266 }, 1281 .hback_porch = { 84, 122, 844 }, 1282 .hsync_len = { 70, 102, 704 }, 1283 .vactive = { 1024, 1024, 1024 }, 1284 .vfront_porch = { 4, 26, 76 }, 1285 .vback_porch = { 2, 8, 25 }, 1286 .vsync_len = { 2, 8, 25 }, 1287 }; 1288 1289 static const struct panel_desc auo_g190ean01 = { 1290 .timings = &auo_g190ean01_timings, 1291 .num_timings = 1, 1292 .bpc = 8, 1293 .size = { 1294 .width = 376, 1295 .height = 301, 1296 }, 1297 .delay = { 1298 .prepare = 50, 1299 .enable = 200, 1300 .disable = 110, 1301 .unprepare = 1000, 1302 }, 1303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1304 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1305 }; 1306 1307 static const struct display_timing auo_p238han01_timings = { 1308 .pixelclock = { 107400000, 142400000, 180000000 }, 1309 .hactive = { 1920, 1920, 1920 }, 1310 .hfront_porch = { 30, 70, 650 }, 1311 .hback_porch = { 30, 70, 650 }, 1312 .hsync_len = { 20, 40, 136 }, 1313 .vactive = { 1080, 1080, 1080 }, 1314 .vfront_porch = { 5, 19, 318 }, 1315 .vback_porch = { 5, 19, 318 }, 1316 .vsync_len = { 4, 12, 120 }, 1317 }; 1318 1319 static const struct panel_desc auo_p238han01 = { 1320 .timings = &auo_p238han01_timings, 1321 .num_timings = 1, 1322 .bpc = 8, 1323 .size = { 1324 .width = 527, 1325 .height = 296, 1326 }, 1327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1329 }; 1330 1331 static const struct display_timing auo_p320hvn03_timings = { 1332 .pixelclock = { 106000000, 148500000, 164000000 }, 1333 .hactive = { 1920, 1920, 1920 }, 1334 .hfront_porch = { 25, 50, 130 }, 1335 .hback_porch = { 25, 50, 130 }, 1336 .hsync_len = { 20, 40, 105 }, 1337 .vactive = { 1080, 1080, 1080 }, 1338 .vfront_porch = { 8, 17, 150 }, 1339 .vback_porch = { 8, 17, 150 }, 1340 .vsync_len = { 4, 11, 100 }, 1341 }; 1342 1343 static const struct panel_desc auo_p320hvn03 = { 1344 .timings = &auo_p320hvn03_timings, 1345 .num_timings = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 698, 1349 .height = 393, 1350 }, 1351 .delay = { 1352 .prepare = 1, 1353 .enable = 450, 1354 .unprepare = 500, 1355 }, 1356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1358 }; 1359 1360 static const struct drm_display_mode auo_t215hvn01_mode = { 1361 .clock = 148800, 1362 .hdisplay = 1920, 1363 .hsync_start = 1920 + 88, 1364 .hsync_end = 1920 + 88 + 44, 1365 .htotal = 1920 + 88 + 44 + 148, 1366 .vdisplay = 1080, 1367 .vsync_start = 1080 + 4, 1368 .vsync_end = 1080 + 4 + 5, 1369 .vtotal = 1080 + 4 + 5 + 36, 1370 }; 1371 1372 static const struct panel_desc auo_t215hvn01 = { 1373 .modes = &auo_t215hvn01_mode, 1374 .num_modes = 1, 1375 .bpc = 8, 1376 .size = { 1377 .width = 430, 1378 .height = 270, 1379 }, 1380 .delay = { 1381 .disable = 5, 1382 .unprepare = 1000, 1383 }, 1384 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1386 }; 1387 1388 static const struct drm_display_mode avic_tm070ddh03_mode = { 1389 .clock = 51200, 1390 .hdisplay = 1024, 1391 .hsync_start = 1024 + 160, 1392 .hsync_end = 1024 + 160 + 4, 1393 .htotal = 1024 + 160 + 4 + 156, 1394 .vdisplay = 600, 1395 .vsync_start = 600 + 17, 1396 .vsync_end = 600 + 17 + 1, 1397 .vtotal = 600 + 17 + 1 + 17, 1398 }; 1399 1400 static const struct panel_desc avic_tm070ddh03 = { 1401 .modes = &avic_tm070ddh03_mode, 1402 .num_modes = 1, 1403 .bpc = 8, 1404 .size = { 1405 .width = 154, 1406 .height = 90, 1407 }, 1408 .delay = { 1409 .prepare = 20, 1410 .enable = 200, 1411 .disable = 200, 1412 }, 1413 }; 1414 1415 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1416 .clock = 30000, 1417 .hdisplay = 800, 1418 .hsync_start = 800 + 40, 1419 .hsync_end = 800 + 40 + 48, 1420 .htotal = 800 + 40 + 48 + 40, 1421 .vdisplay = 480, 1422 .vsync_start = 480 + 13, 1423 .vsync_end = 480 + 13 + 3, 1424 .vtotal = 480 + 13 + 3 + 29, 1425 }; 1426 1427 static const struct panel_desc bananapi_s070wv20_ct16 = { 1428 .modes = &bananapi_s070wv20_ct16_mode, 1429 .num_modes = 1, 1430 .bpc = 6, 1431 .size = { 1432 .width = 154, 1433 .height = 86, 1434 }, 1435 }; 1436 1437 static const struct display_timing boe_av101hdt_a10_timing = { 1438 .pixelclock = { 74210000, 75330000, 76780000, }, 1439 .hactive = { 1280, 1280, 1280, }, 1440 .hfront_porch = { 10, 42, 33, }, 1441 .hback_porch = { 10, 18, 33, }, 1442 .hsync_len = { 30, 10, 30, }, 1443 .vactive = { 720, 720, 720, }, 1444 .vfront_porch = { 200, 183, 200, }, 1445 .vback_porch = { 8, 8, 8, }, 1446 .vsync_len = { 2, 19, 2, }, 1447 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1448 }; 1449 1450 static const struct panel_desc boe_av101hdt_a10 = { 1451 .timings = &boe_av101hdt_a10_timing, 1452 .num_timings = 1, 1453 .bpc = 8, 1454 .size = { 1455 .width = 224, 1456 .height = 126, 1457 }, 1458 .delay = { 1459 .enable = 50, 1460 .disable = 50, 1461 }, 1462 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1464 }; 1465 1466 static const struct display_timing boe_av123z7m_n17_timing = { 1467 .pixelclock = { 86600000, 88000000, 90800000, }, 1468 .hactive = { 1920, 1920, 1920, }, 1469 .hfront_porch = { 10, 10, 10, }, 1470 .hback_porch = { 10, 10, 10, }, 1471 .hsync_len = { 9, 12, 25, }, 1472 .vactive = { 720, 720, 720, }, 1473 .vfront_porch = { 7, 10, 13, }, 1474 .vback_porch = { 7, 10, 13, }, 1475 .vsync_len = { 7, 11, 14, }, 1476 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1477 }; 1478 1479 static const struct panel_desc boe_av123z7m_n17 = { 1480 .timings = &boe_av123z7m_n17_timing, 1481 .bpc = 8, 1482 .num_timings = 1, 1483 .size = { 1484 .width = 292, 1485 .height = 110, 1486 }, 1487 .delay = { 1488 .prepare = 50, 1489 .disable = 50, 1490 }, 1491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1493 }; 1494 1495 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1496 .clock = 78945, 1497 .hdisplay = 1280, 1498 .hsync_start = 1280 + 0, 1499 .hsync_end = 1280 + 0 + 2, 1500 .htotal = 1280 + 62 + 0 + 2, 1501 .vdisplay = 800, 1502 .vsync_start = 800 + 8, 1503 .vsync_end = 800 + 8 + 2, 1504 .vtotal = 800 + 6 + 8 + 2, 1505 }; 1506 1507 static const struct panel_desc boe_bp082wx1_100 = { 1508 .modes = &boe_bp101wx1_100_mode, 1509 .num_modes = 1, 1510 .bpc = 8, 1511 .size = { 1512 .width = 177, 1513 .height = 110, 1514 }, 1515 .delay = { 1516 .enable = 50, 1517 .disable = 50, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1522 }; 1523 1524 static const struct panel_desc boe_bp101wx1_100 = { 1525 .modes = &boe_bp101wx1_100_mode, 1526 .num_modes = 1, 1527 .bpc = 8, 1528 .size = { 1529 .width = 217, 1530 .height = 136, 1531 }, 1532 .delay = { 1533 .enable = 50, 1534 .disable = 50, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1537 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1538 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1539 }; 1540 1541 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1542 .pixelclock = { 69922000, 71000000, 72293000 }, 1543 .hactive = { 1280, 1280, 1280 }, 1544 .hfront_porch = { 48, 48, 48 }, 1545 .hback_porch = { 80, 80, 80 }, 1546 .hsync_len = { 32, 32, 32 }, 1547 .vactive = { 800, 800, 800 }, 1548 .vfront_porch = { 3, 3, 3 }, 1549 .vback_porch = { 14, 14, 14 }, 1550 .vsync_len = { 6, 6, 6 }, 1551 }; 1552 1553 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1554 .timings = &boe_ev121wxm_n10_1850_timing, 1555 .num_timings = 1, 1556 .bpc = 8, 1557 .size = { 1558 .width = 261, 1559 .height = 163, 1560 }, 1561 .delay = { 1562 .prepare = 9, 1563 .enable = 300, 1564 .unprepare = 300, 1565 .disable = 560, 1566 }, 1567 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1568 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1569 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1570 }; 1571 1572 static const struct drm_display_mode boe_hv070wsa_mode = { 1573 .clock = 42105, 1574 .hdisplay = 1024, 1575 .hsync_start = 1024 + 30, 1576 .hsync_end = 1024 + 30 + 30, 1577 .htotal = 1024 + 30 + 30 + 30, 1578 .vdisplay = 600, 1579 .vsync_start = 600 + 10, 1580 .vsync_end = 600 + 10 + 10, 1581 .vtotal = 600 + 10 + 10 + 10, 1582 }; 1583 1584 static const struct panel_desc boe_hv070wsa = { 1585 .modes = &boe_hv070wsa_mode, 1586 .num_modes = 1, 1587 .bpc = 8, 1588 .size = { 1589 .width = 154, 1590 .height = 90, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1595 }; 1596 1597 static const struct display_timing cct_cmt430b19n00_timing = { 1598 .pixelclock = { 8000000, 9000000, 12000000 }, 1599 .hactive = { 480, 480, 480 }, 1600 .hfront_porch = { 2, 8, 75 }, 1601 .hback_porch = { 3, 43, 43 }, 1602 .hsync_len = { 2, 4, 75 }, 1603 .vactive = { 272, 272, 272 }, 1604 .vfront_porch = { 2, 8, 37 }, 1605 .vback_porch = { 2, 12, 12 }, 1606 .vsync_len = { 2, 4, 37 }, 1607 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1608 }; 1609 1610 static const struct panel_desc cct_cmt430b19n00 = { 1611 .timings = &cct_cmt430b19n00_timing, 1612 .num_timings = 1, 1613 .bpc = 8, 1614 .size = { 1615 .width = 95, 1616 .height = 53, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621 }; 1622 1623 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1624 .clock = 9000, 1625 .hdisplay = 480, 1626 .hsync_start = 480 + 5, 1627 .hsync_end = 480 + 5 + 5, 1628 .htotal = 480 + 5 + 5 + 40, 1629 .vdisplay = 272, 1630 .vsync_start = 272 + 8, 1631 .vsync_end = 272 + 8 + 8, 1632 .vtotal = 272 + 8 + 8 + 8, 1633 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1634 }; 1635 1636 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1637 .modes = &cdtech_s043wq26h_ct7_mode, 1638 .num_modes = 1, 1639 .bpc = 8, 1640 .size = { 1641 .width = 95, 1642 .height = 54, 1643 }, 1644 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1645 }; 1646 1647 /* S070PWS19HP-FC21 2017/04/22 */ 1648 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1649 .clock = 51200, 1650 .hdisplay = 1024, 1651 .hsync_start = 1024 + 160, 1652 .hsync_end = 1024 + 160 + 20, 1653 .htotal = 1024 + 160 + 20 + 140, 1654 .vdisplay = 600, 1655 .vsync_start = 600 + 12, 1656 .vsync_end = 600 + 12 + 3, 1657 .vtotal = 600 + 12 + 3 + 20, 1658 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1659 }; 1660 1661 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1662 .modes = &cdtech_s070pws19hp_fc21_mode, 1663 .num_modes = 1, 1664 .bpc = 6, 1665 .size = { 1666 .width = 154, 1667 .height = 86, 1668 }, 1669 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1671 .connector_type = DRM_MODE_CONNECTOR_DPI, 1672 }; 1673 1674 /* S070SWV29HG-DC44 2017/09/21 */ 1675 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1676 .clock = 33300, 1677 .hdisplay = 800, 1678 .hsync_start = 800 + 210, 1679 .hsync_end = 800 + 210 + 2, 1680 .htotal = 800 + 210 + 2 + 44, 1681 .vdisplay = 480, 1682 .vsync_start = 480 + 22, 1683 .vsync_end = 480 + 22 + 2, 1684 .vtotal = 480 + 22 + 2 + 21, 1685 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1686 }; 1687 1688 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1689 .modes = &cdtech_s070swv29hg_dc44_mode, 1690 .num_modes = 1, 1691 .bpc = 6, 1692 .size = { 1693 .width = 154, 1694 .height = 86, 1695 }, 1696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1698 .connector_type = DRM_MODE_CONNECTOR_DPI, 1699 }; 1700 1701 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1702 .clock = 35000, 1703 .hdisplay = 800, 1704 .hsync_start = 800 + 40, 1705 .hsync_end = 800 + 40 + 40, 1706 .htotal = 800 + 40 + 40 + 48, 1707 .vdisplay = 480, 1708 .vsync_start = 480 + 29, 1709 .vsync_end = 480 + 29 + 13, 1710 .vtotal = 480 + 29 + 13 + 3, 1711 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1712 }; 1713 1714 static const struct panel_desc cdtech_s070wv95_ct16 = { 1715 .modes = &cdtech_s070wv95_ct16_mode, 1716 .num_modes = 1, 1717 .bpc = 8, 1718 .size = { 1719 .width = 154, 1720 .height = 85, 1721 }, 1722 }; 1723 1724 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1725 .pixelclock = { 68900000, 71100000, 73400000 }, 1726 .hactive = { 1280, 1280, 1280 }, 1727 .hfront_porch = { 65, 80, 95 }, 1728 .hback_porch = { 64, 79, 94 }, 1729 .hsync_len = { 1, 1, 1 }, 1730 .vactive = { 800, 800, 800 }, 1731 .vfront_porch = { 7, 11, 14 }, 1732 .vback_porch = { 7, 11, 14 }, 1733 .vsync_len = { 1, 1, 1 }, 1734 .flags = DISPLAY_FLAGS_DE_HIGH, 1735 }; 1736 1737 static const struct panel_desc chefree_ch101olhlwh_002 = { 1738 .timings = &chefree_ch101olhlwh_002_timing, 1739 .num_timings = 1, 1740 .bpc = 8, 1741 .size = { 1742 .width = 217, 1743 .height = 135, 1744 }, 1745 .delay = { 1746 .enable = 200, 1747 .disable = 200, 1748 }, 1749 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752 }; 1753 1754 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1755 .clock = 66770, 1756 .hdisplay = 800, 1757 .hsync_start = 800 + 49, 1758 .hsync_end = 800 + 49 + 33, 1759 .htotal = 800 + 49 + 33 + 17, 1760 .vdisplay = 1280, 1761 .vsync_start = 1280 + 1, 1762 .vsync_end = 1280 + 1 + 7, 1763 .vtotal = 1280 + 1 + 7 + 15, 1764 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1765 }; 1766 1767 static const struct panel_desc chunghwa_claa070wp03xg = { 1768 .modes = &chunghwa_claa070wp03xg_mode, 1769 .num_modes = 1, 1770 .bpc = 6, 1771 .size = { 1772 .width = 94, 1773 .height = 150, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1776 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1778 }; 1779 1780 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1781 .clock = 72070, 1782 .hdisplay = 1366, 1783 .hsync_start = 1366 + 58, 1784 .hsync_end = 1366 + 58 + 58, 1785 .htotal = 1366 + 58 + 58 + 58, 1786 .vdisplay = 768, 1787 .vsync_start = 768 + 4, 1788 .vsync_end = 768 + 4 + 4, 1789 .vtotal = 768 + 4 + 4 + 4, 1790 }; 1791 1792 static const struct panel_desc chunghwa_claa101wa01a = { 1793 .modes = &chunghwa_claa101wa01a_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 220, 1798 .height = 120, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1802 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1803 }; 1804 1805 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1806 .clock = 69300, 1807 .hdisplay = 1366, 1808 .hsync_start = 1366 + 48, 1809 .hsync_end = 1366 + 48 + 32, 1810 .htotal = 1366 + 48 + 32 + 20, 1811 .vdisplay = 768, 1812 .vsync_start = 768 + 16, 1813 .vsync_end = 768 + 16 + 8, 1814 .vtotal = 768 + 16 + 8 + 16, 1815 }; 1816 1817 static const struct panel_desc chunghwa_claa101wb01 = { 1818 .modes = &chunghwa_claa101wb01_mode, 1819 .num_modes = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 223, 1823 .height = 125, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1828 }; 1829 1830 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1831 .pixelclock = { 5000000, 9000000, 12000000 }, 1832 .hactive = { 480, 480, 480 }, 1833 .hfront_porch = { 12, 12, 12 }, 1834 .hback_porch = { 12, 12, 12 }, 1835 .hsync_len = { 21, 21, 21 }, 1836 .vactive = { 272, 272, 272 }, 1837 .vfront_porch = { 4, 4, 4 }, 1838 .vback_porch = { 4, 4, 4 }, 1839 .vsync_len = { 8, 8, 8 }, 1840 }; 1841 1842 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1843 .timings = &dataimage_fg040346dsswbg04_timing, 1844 .num_timings = 1, 1845 .bpc = 8, 1846 .size = { 1847 .width = 95, 1848 .height = 54, 1849 }, 1850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1851 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1852 .connector_type = DRM_MODE_CONNECTOR_DPI, 1853 }; 1854 1855 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1856 .pixelclock = { 68900000, 71110000, 73400000 }, 1857 .hactive = { 1280, 1280, 1280 }, 1858 .vactive = { 800, 800, 800 }, 1859 .hback_porch = { 100, 100, 100 }, 1860 .hfront_porch = { 100, 100, 100 }, 1861 .vback_porch = { 5, 5, 5 }, 1862 .vfront_porch = { 5, 5, 5 }, 1863 .hsync_len = { 24, 24, 24 }, 1864 .vsync_len = { 3, 3, 3 }, 1865 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1866 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1867 }; 1868 1869 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1870 .timings = &dataimage_fg1001l0dsswmg01_timing, 1871 .num_timings = 1, 1872 .bpc = 8, 1873 .size = { 1874 .width = 217, 1875 .height = 136, 1876 }, 1877 }; 1878 1879 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1880 .clock = 33260, 1881 .hdisplay = 800, 1882 .hsync_start = 800 + 40, 1883 .hsync_end = 800 + 40 + 128, 1884 .htotal = 800 + 40 + 128 + 88, 1885 .vdisplay = 480, 1886 .vsync_start = 480 + 10, 1887 .vsync_end = 480 + 10 + 2, 1888 .vtotal = 480 + 10 + 2 + 33, 1889 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1890 }; 1891 1892 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1893 .modes = &dataimage_scf0700c48ggu18_mode, 1894 .num_modes = 1, 1895 .bpc = 8, 1896 .size = { 1897 .width = 152, 1898 .height = 91, 1899 }, 1900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1902 .connector_type = DRM_MODE_CONNECTOR_DPI, 1903 }; 1904 1905 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1906 .pixelclock = { 45000000, 51200000, 57000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 100, 106, 113 }, 1909 .hback_porch = { 100, 106, 113 }, 1910 .hsync_len = { 100, 108, 114 }, 1911 .vactive = { 600, 600, 600 }, 1912 .vfront_porch = { 8, 11, 15 }, 1913 .vback_porch = { 8, 11, 15 }, 1914 .vsync_len = { 9, 13, 15 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916 }; 1917 1918 static const struct panel_desc dlc_dlc0700yzg_1 = { 1919 .timings = &dlc_dlc0700yzg_1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 154, 1924 .height = 86, 1925 }, 1926 .delay = { 1927 .prepare = 30, 1928 .enable = 200, 1929 .disable = 200, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1933 }; 1934 1935 static const struct display_timing dlc_dlc1010gig_timing = { 1936 .pixelclock = { 68900000, 71100000, 73400000 }, 1937 .hactive = { 1280, 1280, 1280 }, 1938 .hfront_porch = { 43, 53, 63 }, 1939 .hback_porch = { 43, 53, 63 }, 1940 .hsync_len = { 44, 54, 64 }, 1941 .vactive = { 800, 800, 800 }, 1942 .vfront_porch = { 5, 8, 11 }, 1943 .vback_porch = { 5, 8, 11 }, 1944 .vsync_len = { 5, 7, 11 }, 1945 .flags = DISPLAY_FLAGS_DE_HIGH, 1946 }; 1947 1948 static const struct panel_desc dlc_dlc1010gig = { 1949 .timings = &dlc_dlc1010gig_timing, 1950 .num_timings = 1, 1951 .bpc = 8, 1952 .size = { 1953 .width = 216, 1954 .height = 135, 1955 }, 1956 .delay = { 1957 .prepare = 60, 1958 .enable = 150, 1959 .disable = 100, 1960 .unprepare = 60, 1961 }, 1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1964 }; 1965 1966 static const struct drm_display_mode edt_et035012dm6_mode = { 1967 .clock = 6500, 1968 .hdisplay = 320, 1969 .hsync_start = 320 + 20, 1970 .hsync_end = 320 + 20 + 30, 1971 .htotal = 320 + 20 + 68, 1972 .vdisplay = 240, 1973 .vsync_start = 240 + 4, 1974 .vsync_end = 240 + 4 + 4, 1975 .vtotal = 240 + 4 + 4 + 14, 1976 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1977 }; 1978 1979 static const struct panel_desc edt_et035012dm6 = { 1980 .modes = &edt_et035012dm6_mode, 1981 .num_modes = 1, 1982 .bpc = 8, 1983 .size = { 1984 .width = 70, 1985 .height = 52, 1986 }, 1987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1988 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1989 }; 1990 1991 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1992 .clock = 6520, 1993 .hdisplay = 320, 1994 .hsync_start = 320 + 20, 1995 .hsync_end = 320 + 20 + 68, 1996 .htotal = 320 + 20 + 68, 1997 .vdisplay = 240, 1998 .vsync_start = 240 + 4, 1999 .vsync_end = 240 + 4 + 18, 2000 .vtotal = 240 + 4 + 18, 2001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2002 }; 2003 2004 static const struct panel_desc edt_etm0350g0dh6 = { 2005 .modes = &edt_etm0350g0dh6_mode, 2006 .num_modes = 1, 2007 .bpc = 6, 2008 .size = { 2009 .width = 70, 2010 .height = 53, 2011 }, 2012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2014 .connector_type = DRM_MODE_CONNECTOR_DPI, 2015 }; 2016 2017 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2018 .clock = 10870, 2019 .hdisplay = 480, 2020 .hsync_start = 480 + 8, 2021 .hsync_end = 480 + 8 + 4, 2022 .htotal = 480 + 8 + 4 + 41, 2023 2024 /* 2025 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2026 * fb_align 2027 */ 2028 2029 .vdisplay = 288, 2030 .vsync_start = 288 + 2, 2031 .vsync_end = 288 + 2 + 4, 2032 .vtotal = 288 + 2 + 4 + 10, 2033 }; 2034 2035 static const struct panel_desc edt_etm043080dh6gp = { 2036 .modes = &edt_etm043080dh6gp_mode, 2037 .num_modes = 1, 2038 .bpc = 8, 2039 .size = { 2040 .width = 100, 2041 .height = 65, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2044 .connector_type = DRM_MODE_CONNECTOR_DPI, 2045 }; 2046 2047 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2048 .clock = 9000, 2049 .hdisplay = 480, 2050 .hsync_start = 480 + 2, 2051 .hsync_end = 480 + 2 + 41, 2052 .htotal = 480 + 2 + 41 + 2, 2053 .vdisplay = 272, 2054 .vsync_start = 272 + 2, 2055 .vsync_end = 272 + 2 + 10, 2056 .vtotal = 272 + 2 + 10 + 2, 2057 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2058 }; 2059 2060 static const struct panel_desc edt_etm0430g0dh6 = { 2061 .modes = &edt_etm0430g0dh6_mode, 2062 .num_modes = 1, 2063 .bpc = 6, 2064 .size = { 2065 .width = 95, 2066 .height = 54, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2070 .connector_type = DRM_MODE_CONNECTOR_DPI, 2071 }; 2072 2073 static const struct drm_display_mode edt_et057090dhu_mode = { 2074 .clock = 25175, 2075 .hdisplay = 640, 2076 .hsync_start = 640 + 16, 2077 .hsync_end = 640 + 16 + 30, 2078 .htotal = 640 + 16 + 30 + 114, 2079 .vdisplay = 480, 2080 .vsync_start = 480 + 10, 2081 .vsync_end = 480 + 10 + 3, 2082 .vtotal = 480 + 10 + 3 + 32, 2083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2084 }; 2085 2086 static const struct panel_desc edt_et057090dhu = { 2087 .modes = &edt_et057090dhu_mode, 2088 .num_modes = 1, 2089 .bpc = 6, 2090 .size = { 2091 .width = 115, 2092 .height = 86, 2093 }, 2094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2096 .connector_type = DRM_MODE_CONNECTOR_DPI, 2097 }; 2098 2099 static const struct display_timing edt_et057023udba_timing = { 2100 .pixelclock = { 23200000, 24190000, 39640000 }, 2101 .hactive = { 640, 640, 640 }, 2102 .hfront_porch = { 20, 40, 200 }, 2103 .hback_porch = { 87, 40, 1 }, 2104 .hsync_len = { 1, 48, 87 }, 2105 .vactive = { 480, 480, 480 }, 2106 .vfront_porch = { 5, 13, 200 }, 2107 .vback_porch = { 31, 31, 29 }, 2108 .vsync_len = { 1, 1, 3 }, 2109 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2110 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2111 DISPLAY_FLAGS_SYNC_POSEDGE, 2112 }; 2113 2114 static const struct panel_desc edt_et057023udba = { 2115 .timings = &edt_et057023udba_timing, 2116 .num_timings = 1, 2117 .bpc = 8, 2118 .size = { 2119 .width = 115, 2120 .height = 86, 2121 }, 2122 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2123 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2124 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2125 .connector_type = DRM_MODE_CONNECTOR_DPI, 2126 }; 2127 2128 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2129 .clock = 33260, 2130 .hdisplay = 800, 2131 .hsync_start = 800 + 40, 2132 .hsync_end = 800 + 40 + 128, 2133 .htotal = 800 + 40 + 128 + 88, 2134 .vdisplay = 480, 2135 .vsync_start = 480 + 10, 2136 .vsync_end = 480 + 10 + 2, 2137 .vtotal = 480 + 10 + 2 + 33, 2138 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2139 }; 2140 2141 static const struct panel_desc edt_etm0700g0dh6 = { 2142 .modes = &edt_etm0700g0dh6_mode, 2143 .num_modes = 1, 2144 .bpc = 6, 2145 .size = { 2146 .width = 152, 2147 .height = 91, 2148 }, 2149 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2150 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2151 .connector_type = DRM_MODE_CONNECTOR_DPI, 2152 }; 2153 2154 static const struct panel_desc edt_etm0700g0bdh6 = { 2155 .modes = &edt_etm0700g0dh6_mode, 2156 .num_modes = 1, 2157 .bpc = 6, 2158 .size = { 2159 .width = 152, 2160 .height = 91, 2161 }, 2162 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2163 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2164 .connector_type = DRM_MODE_CONNECTOR_DPI, 2165 }; 2166 2167 static const struct display_timing edt_etml0700y5dha_timing = { 2168 .pixelclock = { 40800000, 51200000, 67200000 }, 2169 .hactive = { 1024, 1024, 1024 }, 2170 .hfront_porch = { 30, 106, 125 }, 2171 .hback_porch = { 30, 106, 125 }, 2172 .hsync_len = { 30, 108, 126 }, 2173 .vactive = { 600, 600, 600 }, 2174 .vfront_porch = { 3, 12, 67}, 2175 .vback_porch = { 3, 12, 67 }, 2176 .vsync_len = { 4, 11, 66 }, 2177 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2178 DISPLAY_FLAGS_DE_HIGH, 2179 }; 2180 2181 static const struct panel_desc edt_etml0700y5dha = { 2182 .timings = &edt_etml0700y5dha_timing, 2183 .num_timings = 1, 2184 .bpc = 8, 2185 .size = { 2186 .width = 155, 2187 .height = 86, 2188 }, 2189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2191 }; 2192 2193 static const struct display_timing edt_etml1010g3dra_timing = { 2194 .pixelclock = { 66300000, 72400000, 78900000 }, 2195 .hactive = { 1280, 1280, 1280 }, 2196 .hfront_porch = { 12, 72, 132 }, 2197 .hback_porch = { 86, 86, 86 }, 2198 .hsync_len = { 2, 2, 2 }, 2199 .vactive = { 800, 800, 800 }, 2200 .vfront_porch = { 1, 15, 49 }, 2201 .vback_porch = { 21, 21, 21 }, 2202 .vsync_len = { 2, 2, 2 }, 2203 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2204 DISPLAY_FLAGS_DE_HIGH, 2205 }; 2206 2207 static const struct panel_desc edt_etml1010g3dra = { 2208 .timings = &edt_etml1010g3dra_timing, 2209 .num_timings = 1, 2210 .bpc = 8, 2211 .size = { 2212 .width = 216, 2213 .height = 135, 2214 }, 2215 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2216 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2217 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2218 }; 2219 2220 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2221 .clock = 25175, 2222 .hdisplay = 640, 2223 .hsync_start = 640, 2224 .hsync_end = 640 + 16, 2225 .htotal = 640 + 16 + 30 + 114, 2226 .vdisplay = 480, 2227 .vsync_start = 480 + 10, 2228 .vsync_end = 480 + 10 + 3, 2229 .vtotal = 480 + 10 + 3 + 35, 2230 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2231 }; 2232 2233 static const struct panel_desc edt_etmv570g2dhu = { 2234 .modes = &edt_etmv570g2dhu_mode, 2235 .num_modes = 1, 2236 .bpc = 6, 2237 .size = { 2238 .width = 115, 2239 .height = 86, 2240 }, 2241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2242 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2243 .connector_type = DRM_MODE_CONNECTOR_DPI, 2244 }; 2245 2246 static const struct display_timing eink_vb3300_kca_timing = { 2247 .pixelclock = { 40000000, 40000000, 40000000 }, 2248 .hactive = { 334, 334, 334 }, 2249 .hfront_porch = { 1, 1, 1 }, 2250 .hback_porch = { 1, 1, 1 }, 2251 .hsync_len = { 1, 1, 1 }, 2252 .vactive = { 1405, 1405, 1405 }, 2253 .vfront_porch = { 1, 1, 1 }, 2254 .vback_porch = { 1, 1, 1 }, 2255 .vsync_len = { 1, 1, 1 }, 2256 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2257 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2258 }; 2259 2260 static const struct panel_desc eink_vb3300_kca = { 2261 .timings = &eink_vb3300_kca_timing, 2262 .num_timings = 1, 2263 .bpc = 6, 2264 .size = { 2265 .width = 157, 2266 .height = 209, 2267 }, 2268 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2269 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2270 .connector_type = DRM_MODE_CONNECTOR_DPI, 2271 }; 2272 2273 static const struct display_timing evervision_vgg644804_timing = { 2274 .pixelclock = { 25175000, 25175000, 25175000 }, 2275 .hactive = { 640, 640, 640 }, 2276 .hfront_porch = { 16, 16, 16 }, 2277 .hback_porch = { 82, 114, 170 }, 2278 .hsync_len = { 5, 30, 30 }, 2279 .vactive = { 480, 480, 480 }, 2280 .vfront_porch = { 10, 10, 10 }, 2281 .vback_porch = { 30, 32, 34 }, 2282 .vsync_len = { 1, 3, 5 }, 2283 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2284 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2285 DISPLAY_FLAGS_SYNC_POSEDGE, 2286 }; 2287 2288 static const struct panel_desc evervision_vgg644804 = { 2289 .timings = &evervision_vgg644804_timing, 2290 .num_timings = 1, 2291 .bpc = 6, 2292 .size = { 2293 .width = 115, 2294 .height = 86, 2295 }, 2296 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2299 }; 2300 2301 static const struct display_timing evervision_vgg804821_timing = { 2302 .pixelclock = { 27600000, 33300000, 50000000 }, 2303 .hactive = { 800, 800, 800 }, 2304 .hfront_porch = { 40, 66, 70 }, 2305 .hback_porch = { 40, 67, 70 }, 2306 .hsync_len = { 40, 67, 70 }, 2307 .vactive = { 480, 480, 480 }, 2308 .vfront_porch = { 6, 10, 10 }, 2309 .vback_porch = { 7, 11, 11 }, 2310 .vsync_len = { 7, 11, 11 }, 2311 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2312 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2313 DISPLAY_FLAGS_SYNC_NEGEDGE, 2314 }; 2315 2316 static const struct panel_desc evervision_vgg804821 = { 2317 .timings = &evervision_vgg804821_timing, 2318 .num_timings = 1, 2319 .bpc = 8, 2320 .size = { 2321 .width = 108, 2322 .height = 64, 2323 }, 2324 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2325 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2326 }; 2327 2328 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2329 .clock = 32260, 2330 .hdisplay = 800, 2331 .hsync_start = 800 + 168, 2332 .hsync_end = 800 + 168 + 64, 2333 .htotal = 800 + 168 + 64 + 88, 2334 .vdisplay = 480, 2335 .vsync_start = 480 + 37, 2336 .vsync_end = 480 + 37 + 2, 2337 .vtotal = 480 + 37 + 2 + 8, 2338 }; 2339 2340 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2341 .modes = &foxlink_fl500wvr00_a0t_mode, 2342 .num_modes = 1, 2343 .bpc = 8, 2344 .size = { 2345 .width = 108, 2346 .height = 65, 2347 }, 2348 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2349 }; 2350 2351 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2352 { /* 60 Hz */ 2353 .clock = 6000, 2354 .hdisplay = 320, 2355 .hsync_start = 320 + 44, 2356 .hsync_end = 320 + 44 + 16, 2357 .htotal = 320 + 44 + 16 + 20, 2358 .vdisplay = 240, 2359 .vsync_start = 240 + 2, 2360 .vsync_end = 240 + 2 + 6, 2361 .vtotal = 240 + 2 + 6 + 2, 2362 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2363 }, 2364 { /* 50 Hz */ 2365 .clock = 5400, 2366 .hdisplay = 320, 2367 .hsync_start = 320 + 56, 2368 .hsync_end = 320 + 56 + 16, 2369 .htotal = 320 + 56 + 16 + 40, 2370 .vdisplay = 240, 2371 .vsync_start = 240 + 2, 2372 .vsync_end = 240 + 2 + 6, 2373 .vtotal = 240 + 2 + 6 + 2, 2374 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2375 }, 2376 }; 2377 2378 static const struct panel_desc frida_frd350h54004 = { 2379 .modes = frida_frd350h54004_modes, 2380 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2381 .bpc = 8, 2382 .size = { 2383 .width = 77, 2384 .height = 64, 2385 }, 2386 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2387 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2388 .connector_type = DRM_MODE_CONNECTOR_DPI, 2389 }; 2390 2391 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2392 .clock = 9000, 2393 .hdisplay = 480, 2394 .hsync_start = 480 + 5, 2395 .hsync_end = 480 + 5 + 1, 2396 .htotal = 480 + 5 + 1 + 40, 2397 .vdisplay = 272, 2398 .vsync_start = 272 + 8, 2399 .vsync_end = 272 + 8 + 1, 2400 .vtotal = 272 + 8 + 1 + 8, 2401 }; 2402 2403 static const struct panel_desc giantplus_gpg482739qs5 = { 2404 .modes = &giantplus_gpg482739qs5_mode, 2405 .num_modes = 1, 2406 .bpc = 8, 2407 .size = { 2408 .width = 95, 2409 .height = 54, 2410 }, 2411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2412 }; 2413 2414 static const struct display_timing giantplus_gpm940b0_timing = { 2415 .pixelclock = { 13500000, 27000000, 27500000 }, 2416 .hactive = { 320, 320, 320 }, 2417 .hfront_porch = { 14, 686, 718 }, 2418 .hback_porch = { 50, 70, 255 }, 2419 .hsync_len = { 1, 1, 1 }, 2420 .vactive = { 240, 240, 240 }, 2421 .vfront_porch = { 1, 1, 179 }, 2422 .vback_porch = { 1, 21, 31 }, 2423 .vsync_len = { 1, 1, 6 }, 2424 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2425 }; 2426 2427 static const struct panel_desc giantplus_gpm940b0 = { 2428 .timings = &giantplus_gpm940b0_timing, 2429 .num_timings = 1, 2430 .bpc = 8, 2431 .size = { 2432 .width = 60, 2433 .height = 45, 2434 }, 2435 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2436 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2437 }; 2438 2439 static const struct display_timing hannstar_hsd070pww1_timing = { 2440 .pixelclock = { 64300000, 71100000, 82000000 }, 2441 .hactive = { 1280, 1280, 1280 }, 2442 .hfront_porch = { 1, 1, 10 }, 2443 .hback_porch = { 1, 1, 10 }, 2444 /* 2445 * According to the data sheet, the minimum horizontal blanking interval 2446 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2447 * minimum working horizontal blanking interval to be 60 clocks. 2448 */ 2449 .hsync_len = { 58, 158, 661 }, 2450 .vactive = { 800, 800, 800 }, 2451 .vfront_porch = { 1, 1, 10 }, 2452 .vback_porch = { 1, 1, 10 }, 2453 .vsync_len = { 1, 21, 203 }, 2454 .flags = DISPLAY_FLAGS_DE_HIGH, 2455 }; 2456 2457 static const struct panel_desc hannstar_hsd070pww1 = { 2458 .timings = &hannstar_hsd070pww1_timing, 2459 .num_timings = 1, 2460 .bpc = 6, 2461 .size = { 2462 .width = 151, 2463 .height = 94, 2464 }, 2465 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2466 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2467 }; 2468 2469 static const struct display_timing hannstar_hsd100pxn1_timing = { 2470 .pixelclock = { 55000000, 65000000, 75000000 }, 2471 .hactive = { 1024, 1024, 1024 }, 2472 .hfront_porch = { 40, 40, 40 }, 2473 .hback_porch = { 220, 220, 220 }, 2474 .hsync_len = { 20, 60, 100 }, 2475 .vactive = { 768, 768, 768 }, 2476 .vfront_porch = { 7, 7, 7 }, 2477 .vback_porch = { 21, 21, 21 }, 2478 .vsync_len = { 10, 10, 10 }, 2479 .flags = DISPLAY_FLAGS_DE_HIGH, 2480 }; 2481 2482 static const struct panel_desc hannstar_hsd100pxn1 = { 2483 .timings = &hannstar_hsd100pxn1_timing, 2484 .num_timings = 1, 2485 .bpc = 6, 2486 .size = { 2487 .width = 203, 2488 .height = 152, 2489 }, 2490 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2491 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2492 }; 2493 2494 static const struct display_timing hannstar_hsd101pww2_timing = { 2495 .pixelclock = { 64300000, 71100000, 82000000 }, 2496 .hactive = { 1280, 1280, 1280 }, 2497 .hfront_porch = { 1, 1, 10 }, 2498 .hback_porch = { 1, 1, 10 }, 2499 .hsync_len = { 58, 158, 661 }, 2500 .vactive = { 800, 800, 800 }, 2501 .vfront_porch = { 1, 1, 10 }, 2502 .vback_porch = { 1, 1, 10 }, 2503 .vsync_len = { 1, 21, 203 }, 2504 .flags = DISPLAY_FLAGS_DE_HIGH, 2505 }; 2506 2507 static const struct panel_desc hannstar_hsd101pww2 = { 2508 .timings = &hannstar_hsd101pww2_timing, 2509 .num_timings = 1, 2510 .bpc = 8, 2511 .size = { 2512 .width = 217, 2513 .height = 136, 2514 }, 2515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2516 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2517 }; 2518 2519 static const struct display_timing hannstar_hsd156juw2_timing = { 2520 .pixelclock = { 66000000, 72800000, 80500000 }, 2521 .hactive = { 1920, 1920, 1920 }, 2522 .hfront_porch = { 20, 30, 30 }, 2523 .hback_porch = { 20, 30, 30 }, 2524 .hsync_len = { 50, 60, 90 }, 2525 .vactive = { 1080, 1080, 1080 }, 2526 .vfront_porch = { 1, 2, 4 }, 2527 .vback_porch = { 1, 2, 4 }, 2528 .vsync_len = { 3, 40, 80 }, 2529 .flags = DISPLAY_FLAGS_DE_HIGH, 2530 }; 2531 2532 static const struct panel_desc hannstar_hsd156juw2 = { 2533 .timings = &hannstar_hsd156juw2_timing, 2534 .num_timings = 1, 2535 .bpc = 8, 2536 .size = { 2537 .width = 344, 2538 .height = 194, 2539 }, 2540 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2541 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2542 }; 2543 2544 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2545 .clock = 33333, 2546 .hdisplay = 800, 2547 .hsync_start = 800 + 85, 2548 .hsync_end = 800 + 85 + 86, 2549 .htotal = 800 + 85 + 86 + 85, 2550 .vdisplay = 480, 2551 .vsync_start = 480 + 16, 2552 .vsync_end = 480 + 16 + 13, 2553 .vtotal = 480 + 16 + 13 + 16, 2554 }; 2555 2556 static const struct panel_desc hitachi_tx23d38vm0caa = { 2557 .modes = &hitachi_tx23d38vm0caa_mode, 2558 .num_modes = 1, 2559 .bpc = 6, 2560 .size = { 2561 .width = 195, 2562 .height = 117, 2563 }, 2564 .delay = { 2565 .enable = 160, 2566 .disable = 160, 2567 }, 2568 }; 2569 2570 static const struct drm_display_mode innolux_at043tn24_mode = { 2571 .clock = 9000, 2572 .hdisplay = 480, 2573 .hsync_start = 480 + 2, 2574 .hsync_end = 480 + 2 + 41, 2575 .htotal = 480 + 2 + 41 + 2, 2576 .vdisplay = 272, 2577 .vsync_start = 272 + 2, 2578 .vsync_end = 272 + 2 + 10, 2579 .vtotal = 272 + 2 + 10 + 2, 2580 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2581 }; 2582 2583 static const struct panel_desc innolux_at043tn24 = { 2584 .modes = &innolux_at043tn24_mode, 2585 .num_modes = 1, 2586 .bpc = 8, 2587 .size = { 2588 .width = 95, 2589 .height = 54, 2590 }, 2591 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2592 .connector_type = DRM_MODE_CONNECTOR_DPI, 2593 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2594 }; 2595 2596 static const struct drm_display_mode innolux_at070tn92_mode = { 2597 .clock = 33333, 2598 .hdisplay = 800, 2599 .hsync_start = 800 + 210, 2600 .hsync_end = 800 + 210 + 20, 2601 .htotal = 800 + 210 + 20 + 46, 2602 .vdisplay = 480, 2603 .vsync_start = 480 + 22, 2604 .vsync_end = 480 + 22 + 10, 2605 .vtotal = 480 + 22 + 23 + 10, 2606 }; 2607 2608 static const struct panel_desc innolux_at070tn92 = { 2609 .modes = &innolux_at070tn92_mode, 2610 .num_modes = 1, 2611 .size = { 2612 .width = 154, 2613 .height = 86, 2614 }, 2615 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2616 }; 2617 2618 static const struct display_timing innolux_g070ace_l01_timing = { 2619 .pixelclock = { 25200000, 35000000, 35700000 }, 2620 .hactive = { 800, 800, 800 }, 2621 .hfront_porch = { 30, 32, 87 }, 2622 .hback_porch = { 30, 32, 87 }, 2623 .hsync_len = { 1, 1, 1 }, 2624 .vactive = { 480, 480, 480 }, 2625 .vfront_porch = { 3, 3, 3 }, 2626 .vback_porch = { 13, 13, 13 }, 2627 .vsync_len = { 1, 1, 4 }, 2628 .flags = DISPLAY_FLAGS_DE_HIGH, 2629 }; 2630 2631 static const struct panel_desc innolux_g070ace_l01 = { 2632 .timings = &innolux_g070ace_l01_timing, 2633 .num_timings = 1, 2634 .bpc = 8, 2635 .size = { 2636 .width = 152, 2637 .height = 91, 2638 }, 2639 .delay = { 2640 .prepare = 10, 2641 .enable = 50, 2642 .disable = 50, 2643 .unprepare = 500, 2644 }, 2645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2646 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2647 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2648 }; 2649 2650 static const struct display_timing innolux_g070y2_l01_timing = { 2651 .pixelclock = { 28000000, 29500000, 32000000 }, 2652 .hactive = { 800, 800, 800 }, 2653 .hfront_porch = { 61, 91, 141 }, 2654 .hback_porch = { 60, 90, 140 }, 2655 .hsync_len = { 12, 12, 12 }, 2656 .vactive = { 480, 480, 480 }, 2657 .vfront_porch = { 4, 9, 30 }, 2658 .vback_porch = { 4, 8, 28 }, 2659 .vsync_len = { 2, 2, 2 }, 2660 .flags = DISPLAY_FLAGS_DE_HIGH, 2661 }; 2662 2663 static const struct panel_desc innolux_g070y2_l01 = { 2664 .timings = &innolux_g070y2_l01_timing, 2665 .num_timings = 1, 2666 .bpc = 8, 2667 .size = { 2668 .width = 152, 2669 .height = 91, 2670 }, 2671 .delay = { 2672 .prepare = 10, 2673 .enable = 100, 2674 .disable = 100, 2675 .unprepare = 800, 2676 }, 2677 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2678 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2679 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2680 }; 2681 2682 static const struct display_timing innolux_g070ace_lh3_timing = { 2683 .pixelclock = { 25200000, 25400000, 35700000 }, 2684 .hactive = { 800, 800, 800 }, 2685 .hfront_porch = { 30, 32, 87 }, 2686 .hback_porch = { 29, 31, 86 }, 2687 .hsync_len = { 1, 1, 1 }, 2688 .vactive = { 480, 480, 480 }, 2689 .vfront_porch = { 4, 5, 65 }, 2690 .vback_porch = { 3, 4, 65 }, 2691 .vsync_len = { 1, 1, 1 }, 2692 .flags = DISPLAY_FLAGS_DE_HIGH, 2693 }; 2694 2695 static const struct panel_desc innolux_g070ace_lh3 = { 2696 .timings = &innolux_g070ace_lh3_timing, 2697 .num_timings = 1, 2698 .bpc = 8, 2699 .size = { 2700 .width = 152, 2701 .height = 91, 2702 }, 2703 .delay = { 2704 .prepare = 10, 2705 .enable = 450, 2706 .disable = 200, 2707 .unprepare = 510, 2708 }, 2709 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2710 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2711 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2712 }; 2713 2714 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2715 .clock = 33333, 2716 .hdisplay = 800, 2717 .hsync_start = 800 + 210, 2718 .hsync_end = 800 + 210 + 20, 2719 .htotal = 800 + 210 + 20 + 46, 2720 .vdisplay = 480, 2721 .vsync_start = 480 + 22, 2722 .vsync_end = 480 + 22 + 10, 2723 .vtotal = 480 + 22 + 23 + 10, 2724 }; 2725 2726 static const struct panel_desc innolux_g070y2_t02 = { 2727 .modes = &innolux_g070y2_t02_mode, 2728 .num_modes = 1, 2729 .bpc = 8, 2730 .size = { 2731 .width = 152, 2732 .height = 92, 2733 }, 2734 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2735 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2736 .connector_type = DRM_MODE_CONNECTOR_DPI, 2737 }; 2738 2739 static const struct display_timing innolux_g101ice_l01_timing = { 2740 .pixelclock = { 60400000, 71100000, 74700000 }, 2741 .hactive = { 1280, 1280, 1280 }, 2742 .hfront_porch = { 30, 60, 70 }, 2743 .hback_porch = { 30, 60, 70 }, 2744 .hsync_len = { 22, 40, 60 }, 2745 .vactive = { 800, 800, 800 }, 2746 .vfront_porch = { 3, 8, 14 }, 2747 .vback_porch = { 3, 8, 14 }, 2748 .vsync_len = { 4, 7, 12 }, 2749 .flags = DISPLAY_FLAGS_DE_HIGH, 2750 }; 2751 2752 static const struct panel_desc innolux_g101ice_l01 = { 2753 .timings = &innolux_g101ice_l01_timing, 2754 .num_timings = 1, 2755 .bpc = 8, 2756 .size = { 2757 .width = 217, 2758 .height = 135, 2759 }, 2760 .delay = { 2761 .enable = 200, 2762 .disable = 200, 2763 }, 2764 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2765 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2766 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2767 }; 2768 2769 static const struct display_timing innolux_g121i1_l01_timing = { 2770 .pixelclock = { 67450000, 71000000, 74550000 }, 2771 .hactive = { 1280, 1280, 1280 }, 2772 .hfront_porch = { 40, 80, 160 }, 2773 .hback_porch = { 39, 79, 159 }, 2774 .hsync_len = { 1, 1, 1 }, 2775 .vactive = { 800, 800, 800 }, 2776 .vfront_porch = { 5, 11, 100 }, 2777 .vback_porch = { 4, 11, 99 }, 2778 .vsync_len = { 1, 1, 1 }, 2779 }; 2780 2781 static const struct panel_desc innolux_g121i1_l01 = { 2782 .timings = &innolux_g121i1_l01_timing, 2783 .num_timings = 1, 2784 .bpc = 6, 2785 .size = { 2786 .width = 261, 2787 .height = 163, 2788 }, 2789 .delay = { 2790 .enable = 200, 2791 .disable = 20, 2792 }, 2793 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2794 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2795 }; 2796 2797 static const struct display_timing innolux_g121x1_l03_timings = { 2798 .pixelclock = { 57500000, 64900000, 74400000 }, 2799 .hactive = { 1024, 1024, 1024 }, 2800 .hfront_porch = { 90, 140, 190 }, 2801 .hback_porch = { 90, 140, 190 }, 2802 .hsync_len = { 36, 40, 60 }, 2803 .vactive = { 768, 768, 768 }, 2804 .vfront_porch = { 2, 15, 30 }, 2805 .vback_porch = { 2, 15, 30 }, 2806 .vsync_len = { 2, 8, 20 }, 2807 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2808 }; 2809 2810 static const struct panel_desc innolux_g121x1_l03 = { 2811 .timings = &innolux_g121x1_l03_timings, 2812 .num_timings = 1, 2813 .bpc = 6, 2814 .size = { 2815 .width = 246, 2816 .height = 185, 2817 }, 2818 .delay = { 2819 .enable = 200, 2820 .unprepare = 200, 2821 .disable = 400, 2822 }, 2823 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2824 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2825 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2826 }; 2827 2828 static const struct panel_desc innolux_g121xce_l01 = { 2829 .timings = &innolux_g121x1_l03_timings, 2830 .num_timings = 1, 2831 .bpc = 8, 2832 .size = { 2833 .width = 246, 2834 .height = 185, 2835 }, 2836 .delay = { 2837 .enable = 200, 2838 .unprepare = 200, 2839 .disable = 400, 2840 }, 2841 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2842 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2843 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2844 }; 2845 2846 static const struct display_timing innolux_g150xge_l05_timing = { 2847 .pixelclock = { 53350000, 65000000, 80000000 }, 2848 .hactive = { 1024, 1024, 1024 }, 2849 .hfront_porch = { 58, 160, 288 }, 2850 .hback_porch = { 58, 160, 288 }, 2851 .hsync_len = { 1, 1, 1 }, 2852 .vactive = { 768, 768, 768 }, 2853 .vfront_porch = { 6, 19, 216 }, 2854 .vback_porch = { 6, 19, 216 }, 2855 .vsync_len = { 1, 1, 1 }, 2856 .flags = DISPLAY_FLAGS_DE_HIGH, 2857 }; 2858 2859 static const struct panel_desc innolux_g150xge_l05 = { 2860 .timings = &innolux_g150xge_l05_timing, 2861 .num_timings = 1, 2862 .bpc = 8, 2863 .size = { 2864 .width = 304, 2865 .height = 228, 2866 }, 2867 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2868 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2869 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2870 }; 2871 2872 static const struct display_timing innolux_g156hce_l01_timings = { 2873 .pixelclock = { 120000000, 141860000, 150000000 }, 2874 .hactive = { 1920, 1920, 1920 }, 2875 .hfront_porch = { 80, 90, 100 }, 2876 .hback_porch = { 80, 90, 100 }, 2877 .hsync_len = { 20, 30, 30 }, 2878 .vactive = { 1080, 1080, 1080 }, 2879 .vfront_porch = { 3, 10, 20 }, 2880 .vback_porch = { 3, 10, 20 }, 2881 .vsync_len = { 4, 10, 10 }, 2882 }; 2883 2884 static const struct panel_desc innolux_g156hce_l01 = { 2885 .timings = &innolux_g156hce_l01_timings, 2886 .num_timings = 1, 2887 .bpc = 8, 2888 .size = { 2889 .width = 344, 2890 .height = 194, 2891 }, 2892 .delay = { 2893 .prepare = 1, /* T1+T2 */ 2894 .enable = 450, /* T5 */ 2895 .disable = 200, /* T6 */ 2896 .unprepare = 10, /* T3+T7 */ 2897 }, 2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2899 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2900 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2901 }; 2902 2903 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2904 .clock = 69300, 2905 .hdisplay = 1366, 2906 .hsync_start = 1366 + 16, 2907 .hsync_end = 1366 + 16 + 34, 2908 .htotal = 1366 + 16 + 34 + 50, 2909 .vdisplay = 768, 2910 .vsync_start = 768 + 2, 2911 .vsync_end = 768 + 2 + 6, 2912 .vtotal = 768 + 2 + 6 + 12, 2913 }; 2914 2915 static const struct panel_desc innolux_n156bge_l21 = { 2916 .modes = &innolux_n156bge_l21_mode, 2917 .num_modes = 1, 2918 .bpc = 6, 2919 .size = { 2920 .width = 344, 2921 .height = 193, 2922 }, 2923 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2924 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2925 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2926 }; 2927 2928 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2929 .clock = 51501, 2930 .hdisplay = 1024, 2931 .hsync_start = 1024 + 128, 2932 .hsync_end = 1024 + 128 + 64, 2933 .htotal = 1024 + 128 + 64 + 128, 2934 .vdisplay = 600, 2935 .vsync_start = 600 + 16, 2936 .vsync_end = 600 + 16 + 4, 2937 .vtotal = 600 + 16 + 4 + 16, 2938 }; 2939 2940 static const struct panel_desc innolux_zj070na_01p = { 2941 .modes = &innolux_zj070na_01p_mode, 2942 .num_modes = 1, 2943 .bpc = 6, 2944 .size = { 2945 .width = 154, 2946 .height = 90, 2947 }, 2948 }; 2949 2950 static const struct display_timing jutouch_jt101tm023_timing = { 2951 .pixelclock = { 66300000, 72400000, 78900000 }, 2952 .hactive = { 1280, 1280, 1280 }, 2953 .hfront_porch = { 12, 72, 132 }, 2954 .hback_porch = { 88, 88, 88 }, 2955 .hsync_len = { 10, 10, 48 }, 2956 .vactive = { 800, 800, 800 }, 2957 .vfront_porch = { 1, 15, 49 }, 2958 .vback_porch = { 23, 23, 23 }, 2959 .vsync_len = { 5, 6, 13 }, 2960 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2961 DISPLAY_FLAGS_DE_HIGH, 2962 }; 2963 2964 static const struct panel_desc jutouch_jt101tm023 = { 2965 .timings = &jutouch_jt101tm023_timing, 2966 .num_timings = 1, 2967 .bpc = 8, 2968 .size = { 2969 .width = 217, 2970 .height = 136, 2971 }, 2972 .delay = { 2973 .enable = 50, 2974 .disable = 50, 2975 }, 2976 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2977 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2978 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2979 }; 2980 2981 2982 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2983 .pixelclock = { 5580000, 5850000, 6200000 }, 2984 .hactive = { 320, 320, 320 }, 2985 .hfront_porch = { 30, 30, 30 }, 2986 .hback_porch = { 30, 30, 30 }, 2987 .hsync_len = { 1, 5, 17 }, 2988 .vactive = { 240, 240, 240 }, 2989 .vfront_porch = { 6, 6, 6 }, 2990 .vback_porch = { 5, 5, 5 }, 2991 .vsync_len = { 1, 2, 11 }, 2992 .flags = DISPLAY_FLAGS_DE_HIGH, 2993 }; 2994 2995 static const struct panel_desc koe_tx14d24vm1bpa = { 2996 .timings = &koe_tx14d24vm1bpa_timing, 2997 .num_timings = 1, 2998 .bpc = 6, 2999 .size = { 3000 .width = 115, 3001 .height = 86, 3002 }, 3003 }; 3004 3005 static const struct display_timing koe_tx26d202vm0bwa_timing = { 3006 .pixelclock = { 151820000, 156720000, 159780000 }, 3007 .hactive = { 1920, 1920, 1920 }, 3008 .hfront_porch = { 105, 130, 142 }, 3009 .hback_porch = { 45, 70, 82 }, 3010 .hsync_len = { 30, 30, 30 }, 3011 .vactive = { 1200, 1200, 1200}, 3012 .vfront_porch = { 3, 5, 10 }, 3013 .vback_porch = { 2, 5, 10 }, 3014 .vsync_len = { 5, 5, 5 }, 3015 .flags = DISPLAY_FLAGS_DE_HIGH, 3016 }; 3017 3018 static const struct panel_desc koe_tx26d202vm0bwa = { 3019 .timings = &koe_tx26d202vm0bwa_timing, 3020 .num_timings = 1, 3021 .bpc = 8, 3022 .size = { 3023 .width = 217, 3024 .height = 136, 3025 }, 3026 .delay = { 3027 .prepare = 1000, 3028 .enable = 1000, 3029 .unprepare = 1000, 3030 .disable = 1000, 3031 }, 3032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3035 }; 3036 3037 static const struct display_timing koe_tx31d200vm0baa_timing = { 3038 .pixelclock = { 39600000, 43200000, 48000000 }, 3039 .hactive = { 1280, 1280, 1280 }, 3040 .hfront_porch = { 16, 36, 56 }, 3041 .hback_porch = { 16, 36, 56 }, 3042 .hsync_len = { 8, 8, 8 }, 3043 .vactive = { 480, 480, 480 }, 3044 .vfront_porch = { 6, 21, 33 }, 3045 .vback_porch = { 6, 21, 33 }, 3046 .vsync_len = { 8, 8, 8 }, 3047 .flags = DISPLAY_FLAGS_DE_HIGH, 3048 }; 3049 3050 static const struct panel_desc koe_tx31d200vm0baa = { 3051 .timings = &koe_tx31d200vm0baa_timing, 3052 .num_timings = 1, 3053 .bpc = 6, 3054 .size = { 3055 .width = 292, 3056 .height = 109, 3057 }, 3058 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3059 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3060 }; 3061 3062 static const struct display_timing kyo_tcg121xglp_timing = { 3063 .pixelclock = { 52000000, 65000000, 71000000 }, 3064 .hactive = { 1024, 1024, 1024 }, 3065 .hfront_porch = { 2, 2, 2 }, 3066 .hback_porch = { 2, 2, 2 }, 3067 .hsync_len = { 86, 124, 244 }, 3068 .vactive = { 768, 768, 768 }, 3069 .vfront_porch = { 2, 2, 2 }, 3070 .vback_porch = { 2, 2, 2 }, 3071 .vsync_len = { 6, 34, 73 }, 3072 .flags = DISPLAY_FLAGS_DE_HIGH, 3073 }; 3074 3075 static const struct panel_desc kyo_tcg121xglp = { 3076 .timings = &kyo_tcg121xglp_timing, 3077 .num_timings = 1, 3078 .bpc = 8, 3079 .size = { 3080 .width = 246, 3081 .height = 184, 3082 }, 3083 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3084 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3085 }; 3086 3087 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3088 .clock = 7000, 3089 .hdisplay = 320, 3090 .hsync_start = 320 + 20, 3091 .hsync_end = 320 + 20 + 30, 3092 .htotal = 320 + 20 + 30 + 38, 3093 .vdisplay = 240, 3094 .vsync_start = 240 + 4, 3095 .vsync_end = 240 + 4 + 3, 3096 .vtotal = 240 + 4 + 3 + 15, 3097 }; 3098 3099 static const struct panel_desc lemaker_bl035_rgb_002 = { 3100 .modes = &lemaker_bl035_rgb_002_mode, 3101 .num_modes = 1, 3102 .size = { 3103 .width = 70, 3104 .height = 52, 3105 }, 3106 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3107 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3108 }; 3109 3110 static const struct display_timing lg_lb070wv8_timing = { 3111 .pixelclock = { 31950000, 33260000, 34600000 }, 3112 .hactive = { 800, 800, 800 }, 3113 .hfront_porch = { 88, 88, 88 }, 3114 .hback_porch = { 88, 88, 88 }, 3115 .hsync_len = { 80, 80, 80 }, 3116 .vactive = { 480, 480, 480 }, 3117 .vfront_porch = { 10, 10, 10 }, 3118 .vback_porch = { 10, 10, 10 }, 3119 .vsync_len = { 25, 25, 25 }, 3120 }; 3121 3122 static const struct panel_desc lg_lb070wv8 = { 3123 .timings = &lg_lb070wv8_timing, 3124 .num_timings = 1, 3125 .bpc = 8, 3126 .size = { 3127 .width = 151, 3128 .height = 91, 3129 }, 3130 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3131 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3132 }; 3133 3134 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3135 .clock = 155127, 3136 .hdisplay = 1920, 3137 .hsync_start = 1920 + 128, 3138 .hsync_end = 1920 + 128 + 20, 3139 .htotal = 1920 + 128 + 20 + 12, 3140 .vdisplay = 1200, 3141 .vsync_start = 1200 + 19, 3142 .vsync_end = 1200 + 19 + 4, 3143 .vtotal = 1200 + 19 + 4 + 20, 3144 }; 3145 3146 static const struct panel_desc lincolntech_lcd185_101ct = { 3147 .modes = &lincolntech_lcd185_101ct_mode, 3148 .bpc = 8, 3149 .num_modes = 1, 3150 .size = { 3151 .width = 217, 3152 .height = 136, 3153 }, 3154 .delay = { 3155 .prepare = 50, 3156 .disable = 50, 3157 }, 3158 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3161 }; 3162 3163 static const struct display_timing logictechno_lt161010_2nh_timing = { 3164 .pixelclock = { 26400000, 33300000, 46800000 }, 3165 .hactive = { 800, 800, 800 }, 3166 .hfront_porch = { 16, 210, 354 }, 3167 .hback_porch = { 46, 46, 46 }, 3168 .hsync_len = { 1, 20, 40 }, 3169 .vactive = { 480, 480, 480 }, 3170 .vfront_porch = { 7, 22, 147 }, 3171 .vback_porch = { 23, 23, 23 }, 3172 .vsync_len = { 1, 10, 20 }, 3173 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3174 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3175 DISPLAY_FLAGS_SYNC_POSEDGE, 3176 }; 3177 3178 static const struct panel_desc logictechno_lt161010_2nh = { 3179 .timings = &logictechno_lt161010_2nh_timing, 3180 .num_timings = 1, 3181 .bpc = 6, 3182 .size = { 3183 .width = 154, 3184 .height = 86, 3185 }, 3186 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3187 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3188 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3189 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3190 .connector_type = DRM_MODE_CONNECTOR_DPI, 3191 }; 3192 3193 static const struct display_timing logictechno_lt170410_2whc_timing = { 3194 .pixelclock = { 68900000, 71100000, 73400000 }, 3195 .hactive = { 1280, 1280, 1280 }, 3196 .hfront_porch = { 23, 60, 71 }, 3197 .hback_porch = { 23, 60, 71 }, 3198 .hsync_len = { 15, 40, 47 }, 3199 .vactive = { 800, 800, 800 }, 3200 .vfront_porch = { 5, 7, 10 }, 3201 .vback_porch = { 5, 7, 10 }, 3202 .vsync_len = { 6, 9, 12 }, 3203 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3204 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3205 DISPLAY_FLAGS_SYNC_POSEDGE, 3206 }; 3207 3208 static const struct panel_desc logictechno_lt170410_2whc = { 3209 .timings = &logictechno_lt170410_2whc_timing, 3210 .num_timings = 1, 3211 .bpc = 8, 3212 .size = { 3213 .width = 217, 3214 .height = 136, 3215 }, 3216 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3217 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3218 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3219 }; 3220 3221 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3222 .clock = 33000, 3223 .hdisplay = 800, 3224 .hsync_start = 800 + 112, 3225 .hsync_end = 800 + 112 + 3, 3226 .htotal = 800 + 112 + 3 + 85, 3227 .vdisplay = 480, 3228 .vsync_start = 480 + 38, 3229 .vsync_end = 480 + 38 + 3, 3230 .vtotal = 480 + 38 + 3 + 29, 3231 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3232 }; 3233 3234 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3235 .modes = &logictechno_lttd800480070_l2rt_mode, 3236 .num_modes = 1, 3237 .bpc = 8, 3238 .size = { 3239 .width = 154, 3240 .height = 86, 3241 }, 3242 .delay = { 3243 .prepare = 45, 3244 .enable = 100, 3245 .disable = 100, 3246 .unprepare = 45 3247 }, 3248 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3249 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3250 .connector_type = DRM_MODE_CONNECTOR_DPI, 3251 }; 3252 3253 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3254 .clock = 33000, 3255 .hdisplay = 800, 3256 .hsync_start = 800 + 154, 3257 .hsync_end = 800 + 154 + 3, 3258 .htotal = 800 + 154 + 3 + 43, 3259 .vdisplay = 480, 3260 .vsync_start = 480 + 47, 3261 .vsync_end = 480 + 47 + 3, 3262 .vtotal = 480 + 47 + 3 + 20, 3263 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3264 }; 3265 3266 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3267 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3268 .num_modes = 1, 3269 .bpc = 8, 3270 .size = { 3271 .width = 154, 3272 .height = 86, 3273 }, 3274 .delay = { 3275 .prepare = 45, 3276 .enable = 100, 3277 .disable = 100, 3278 .unprepare = 45 3279 }, 3280 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3281 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3282 .connector_type = DRM_MODE_CONNECTOR_DPI, 3283 }; 3284 3285 static const struct drm_display_mode logicpd_type_28_mode = { 3286 .clock = 9107, 3287 .hdisplay = 480, 3288 .hsync_start = 480 + 3, 3289 .hsync_end = 480 + 3 + 42, 3290 .htotal = 480 + 3 + 42 + 2, 3291 3292 .vdisplay = 272, 3293 .vsync_start = 272 + 2, 3294 .vsync_end = 272 + 2 + 11, 3295 .vtotal = 272 + 2 + 11 + 3, 3296 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3297 }; 3298 3299 static const struct panel_desc logicpd_type_28 = { 3300 .modes = &logicpd_type_28_mode, 3301 .num_modes = 1, 3302 .bpc = 8, 3303 .size = { 3304 .width = 105, 3305 .height = 67, 3306 }, 3307 .delay = { 3308 .prepare = 200, 3309 .enable = 200, 3310 .unprepare = 200, 3311 .disable = 200, 3312 }, 3313 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3314 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3315 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3316 .connector_type = DRM_MODE_CONNECTOR_DPI, 3317 }; 3318 3319 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3320 .clock = 150275, 3321 .hdisplay = 1920, 3322 .hsync_start = 1920 + 32, 3323 .hsync_end = 1920 + 32 + 52, 3324 .htotal = 1920 + 32 + 52 + 24, 3325 .vdisplay = 1200, 3326 .vsync_start = 1200 + 24, 3327 .vsync_end = 1200 + 24 + 8, 3328 .vtotal = 1200 + 24 + 8 + 3, 3329 }; 3330 3331 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3332 .modes = µtips_mf_101hiebcaf0_c_mode, 3333 .bpc = 8, 3334 .num_modes = 1, 3335 .size = { 3336 .width = 217, 3337 .height = 136, 3338 }, 3339 .delay = { 3340 .prepare = 50, 3341 .disable = 50, 3342 }, 3343 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3344 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3345 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3346 }; 3347 3348 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3349 .clock = 93301, 3350 .hdisplay = 1920, 3351 .hsync_start = 1920 + 72, 3352 .hsync_end = 1920 + 72 + 72, 3353 .htotal = 1920 + 72 + 72 + 72, 3354 .vdisplay = 720, 3355 .vsync_start = 720 + 3, 3356 .vsync_end = 720 + 3 + 3, 3357 .vtotal = 720 + 3 + 3 + 2, 3358 }; 3359 3360 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3361 .modes = µtips_mf_103hieb0ga0_mode, 3362 .bpc = 8, 3363 .num_modes = 1, 3364 .size = { 3365 .width = 244, 3366 .height = 92, 3367 }, 3368 .delay = { 3369 .prepare = 50, 3370 .disable = 50, 3371 }, 3372 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3373 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3374 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3375 }; 3376 3377 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3378 .clock = 30400, 3379 .hdisplay = 800, 3380 .hsync_start = 800 + 0, 3381 .hsync_end = 800 + 1, 3382 .htotal = 800 + 0 + 1 + 160, 3383 .vdisplay = 480, 3384 .vsync_start = 480 + 0, 3385 .vsync_end = 480 + 48 + 1, 3386 .vtotal = 480 + 48 + 1 + 0, 3387 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3388 }; 3389 3390 static const struct panel_desc mitsubishi_aa070mc01 = { 3391 .modes = &mitsubishi_aa070mc01_mode, 3392 .num_modes = 1, 3393 .bpc = 8, 3394 .size = { 3395 .width = 152, 3396 .height = 91, 3397 }, 3398 3399 .delay = { 3400 .enable = 200, 3401 .unprepare = 200, 3402 .disable = 400, 3403 }, 3404 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3405 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3406 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3407 }; 3408 3409 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3410 .clock = 56234, 3411 .hdisplay = 1024, 3412 .hsync_start = 1024 + 24, 3413 .hsync_end = 1024 + 24 + 63, 3414 .htotal = 1024 + 24 + 63 + 1, 3415 .vdisplay = 768, 3416 .vsync_start = 768 + 3, 3417 .vsync_end = 768 + 3 + 6, 3418 .vtotal = 768 + 3 + 6 + 1, 3419 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3420 }; 3421 3422 static const struct panel_desc mitsubishi_aa084xe01 = { 3423 .modes = &mitsubishi_aa084xe01_mode, 3424 .num_modes = 1, 3425 .bpc = 8, 3426 .size = { 3427 .width = 1024, 3428 .height = 768, 3429 }, 3430 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3431 .connector_type = DRM_MODE_CONNECTOR_DPI, 3432 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3433 }; 3434 3435 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3436 .pixelclock = { 26400000, 33000000, 46800000 }, 3437 .hactive = { 800, 800, 800 }, 3438 .hfront_porch = { 16, 204, 354 }, 3439 .hback_porch = { 46, 46, 46 }, 3440 .hsync_len = { 1, 6, 40 }, 3441 .vactive = { 480, 480, 480 }, 3442 .vfront_porch = { 7, 22, 147 }, 3443 .vback_porch = { 23, 23, 23 }, 3444 .vsync_len = { 1, 3, 20 }, 3445 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3446 DISPLAY_FLAGS_DE_HIGH, 3447 }; 3448 3449 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3450 .timings = &multi_inno_mi0700a2t_30_timing, 3451 .num_timings = 1, 3452 .bpc = 6, 3453 .size = { 3454 .width = 153, 3455 .height = 92, 3456 }, 3457 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3458 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3459 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3460 }; 3461 3462 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3463 .pixelclock = { 29000000, 33000000, 38000000 }, 3464 .hactive = { 800, 800, 800 }, 3465 .hfront_porch = { 180, 210, 240 }, 3466 .hback_porch = { 16, 16, 16 }, 3467 .hsync_len = { 30, 30, 30 }, 3468 .vactive = { 480, 480, 480 }, 3469 .vfront_porch = { 12, 22, 32 }, 3470 .vback_porch = { 10, 10, 10 }, 3471 .vsync_len = { 13, 13, 13 }, 3472 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3473 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3474 DISPLAY_FLAGS_SYNC_POSEDGE, 3475 }; 3476 3477 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3478 .timings = &multi_inno_mi0700s4t_6_timing, 3479 .num_timings = 1, 3480 .bpc = 8, 3481 .size = { 3482 .width = 154, 3483 .height = 86, 3484 }, 3485 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3486 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3487 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3488 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3489 .connector_type = DRM_MODE_CONNECTOR_DPI, 3490 }; 3491 3492 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3493 .pixelclock = { 32000000, 40000000, 50000000 }, 3494 .hactive = { 800, 800, 800 }, 3495 .hfront_porch = { 16, 210, 354 }, 3496 .hback_porch = { 6, 26, 45 }, 3497 .hsync_len = { 1, 20, 40 }, 3498 .vactive = { 600, 600, 600 }, 3499 .vfront_porch = { 1, 12, 77 }, 3500 .vback_porch = { 3, 13, 22 }, 3501 .vsync_len = { 1, 10, 20 }, 3502 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3503 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3504 DISPLAY_FLAGS_SYNC_POSEDGE, 3505 }; 3506 3507 static const struct panel_desc multi_inno_mi0800ft_9 = { 3508 .timings = &multi_inno_mi0800ft_9_timing, 3509 .num_timings = 1, 3510 .bpc = 8, 3511 .size = { 3512 .width = 162, 3513 .height = 122, 3514 }, 3515 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3516 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3517 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3518 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3519 .connector_type = DRM_MODE_CONNECTOR_DPI, 3520 }; 3521 3522 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3523 .pixelclock = { 68900000, 70000000, 73400000 }, 3524 .hactive = { 1280, 1280, 1280 }, 3525 .hfront_porch = { 30, 60, 71 }, 3526 .hback_porch = { 30, 60, 71 }, 3527 .hsync_len = { 10, 10, 48 }, 3528 .vactive = { 800, 800, 800 }, 3529 .vfront_porch = { 5, 10, 10 }, 3530 .vback_porch = { 5, 10, 10 }, 3531 .vsync_len = { 5, 6, 13 }, 3532 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3533 DISPLAY_FLAGS_DE_HIGH, 3534 }; 3535 3536 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3537 .timings = &multi_inno_mi1010ait_1cp_timing, 3538 .num_timings = 1, 3539 .bpc = 8, 3540 .size = { 3541 .width = 217, 3542 .height = 136, 3543 }, 3544 .delay = { 3545 .enable = 50, 3546 .disable = 50, 3547 }, 3548 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3549 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3551 }; 3552 3553 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3554 .pixelclock = { 40800000, 51200000, 67200000 }, 3555 .hactive = { 1024, 1024, 1024 }, 3556 .hfront_porch = { 30, 110, 130 }, 3557 .hback_porch = { 30, 110, 130 }, 3558 .hsync_len = { 30, 100, 116 }, 3559 .vactive = { 600, 600, 600 }, 3560 .vfront_porch = { 4, 13, 80 }, 3561 .vback_porch = { 4, 13, 80 }, 3562 .vsync_len = { 2, 9, 40 }, 3563 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3564 DISPLAY_FLAGS_DE_HIGH, 3565 }; 3566 3567 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3568 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3569 .num_timings = 1, 3570 .bpc = 6, 3571 .size = { 3572 .width = 260, 3573 .height = 162, 3574 }, 3575 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3576 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3577 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3578 }; 3579 3580 static const struct display_timing nec_nl12880bc20_05_timing = { 3581 .pixelclock = { 67000000, 71000000, 75000000 }, 3582 .hactive = { 1280, 1280, 1280 }, 3583 .hfront_porch = { 2, 30, 30 }, 3584 .hback_porch = { 6, 100, 100 }, 3585 .hsync_len = { 2, 30, 30 }, 3586 .vactive = { 800, 800, 800 }, 3587 .vfront_porch = { 5, 5, 5 }, 3588 .vback_porch = { 11, 11, 11 }, 3589 .vsync_len = { 7, 7, 7 }, 3590 }; 3591 3592 static const struct panel_desc nec_nl12880bc20_05 = { 3593 .timings = &nec_nl12880bc20_05_timing, 3594 .num_timings = 1, 3595 .bpc = 8, 3596 .size = { 3597 .width = 261, 3598 .height = 163, 3599 }, 3600 .delay = { 3601 .enable = 50, 3602 .disable = 50, 3603 }, 3604 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3605 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3606 }; 3607 3608 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3609 .clock = 10870, 3610 .hdisplay = 480, 3611 .hsync_start = 480 + 2, 3612 .hsync_end = 480 + 2 + 41, 3613 .htotal = 480 + 2 + 41 + 2, 3614 .vdisplay = 272, 3615 .vsync_start = 272 + 2, 3616 .vsync_end = 272 + 2 + 4, 3617 .vtotal = 272 + 2 + 4 + 2, 3618 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3619 }; 3620 3621 static const struct panel_desc nec_nl4827hc19_05b = { 3622 .modes = &nec_nl4827hc19_05b_mode, 3623 .num_modes = 1, 3624 .bpc = 8, 3625 .size = { 3626 .width = 95, 3627 .height = 54, 3628 }, 3629 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3630 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3631 }; 3632 3633 static const struct drm_display_mode netron_dy_e231732_mode = { 3634 .clock = 66000, 3635 .hdisplay = 1024, 3636 .hsync_start = 1024 + 160, 3637 .hsync_end = 1024 + 160 + 70, 3638 .htotal = 1024 + 160 + 70 + 90, 3639 .vdisplay = 600, 3640 .vsync_start = 600 + 127, 3641 .vsync_end = 600 + 127 + 20, 3642 .vtotal = 600 + 127 + 20 + 3, 3643 }; 3644 3645 static const struct panel_desc netron_dy_e231732 = { 3646 .modes = &netron_dy_e231732_mode, 3647 .num_modes = 1, 3648 .size = { 3649 .width = 154, 3650 .height = 87, 3651 }, 3652 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3653 }; 3654 3655 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3656 .clock = 9000, 3657 .hdisplay = 480, 3658 .hsync_start = 480 + 2, 3659 .hsync_end = 480 + 2 + 41, 3660 .htotal = 480 + 2 + 41 + 2, 3661 .vdisplay = 272, 3662 .vsync_start = 272 + 2, 3663 .vsync_end = 272 + 2 + 10, 3664 .vtotal = 272 + 2 + 10 + 2, 3665 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3666 }; 3667 3668 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3669 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3670 .num_modes = 1, 3671 .bpc = 8, 3672 .size = { 3673 .width = 95, 3674 .height = 54, 3675 }, 3676 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3677 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3678 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3679 .connector_type = DRM_MODE_CONNECTOR_DPI, 3680 }; 3681 3682 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3683 .clock = 75400, 3684 .hdisplay = 1366, 3685 .hsync_start = 1366 + 14, 3686 .hsync_end = 1366 + 14 + 56, 3687 .htotal = 1366 + 14 + 56 + 64, 3688 .vdisplay = 768, 3689 .vsync_start = 768 + 1, 3690 .vsync_end = 768 + 1 + 3, 3691 .vtotal = 768 + 1 + 3 + 22, 3692 }; 3693 3694 static const struct panel_desc nlt_nl13676bc25_03f = { 3695 .modes = &nlt_nl13676bc25_03f_mode, 3696 .num_modes = 1, 3697 .bpc = 8, 3698 .size = { 3699 .width = 363, 3700 .height = 215, 3701 }, 3702 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3703 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3704 }; 3705 3706 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3707 .pixelclock = { 130000000, 148350000, 163000000 }, 3708 .hactive = { 1920, 1920, 1920 }, 3709 .hfront_porch = { 80, 100, 100 }, 3710 .hback_porch = { 100, 120, 120 }, 3711 .hsync_len = { 50, 60, 60 }, 3712 .vactive = { 1080, 1080, 1080 }, 3713 .vfront_porch = { 12, 30, 30 }, 3714 .vback_porch = { 4, 10, 10 }, 3715 .vsync_len = { 4, 5, 5 }, 3716 }; 3717 3718 static const struct panel_desc nlt_nl192108ac18_02d = { 3719 .timings = &nlt_nl192108ac18_02d_timing, 3720 .num_timings = 1, 3721 .bpc = 8, 3722 .size = { 3723 .width = 344, 3724 .height = 194, 3725 }, 3726 .delay = { 3727 .unprepare = 500, 3728 }, 3729 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3730 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3731 }; 3732 3733 static const struct drm_display_mode nvd_9128_mode = { 3734 .clock = 29500, 3735 .hdisplay = 800, 3736 .hsync_start = 800 + 130, 3737 .hsync_end = 800 + 130 + 98, 3738 .htotal = 800 + 0 + 130 + 98, 3739 .vdisplay = 480, 3740 .vsync_start = 480 + 10, 3741 .vsync_end = 480 + 10 + 50, 3742 .vtotal = 480 + 0 + 10 + 50, 3743 }; 3744 3745 static const struct panel_desc nvd_9128 = { 3746 .modes = &nvd_9128_mode, 3747 .num_modes = 1, 3748 .bpc = 8, 3749 .size = { 3750 .width = 156, 3751 .height = 88, 3752 }, 3753 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3754 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3755 }; 3756 3757 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3758 .pixelclock = { 30000000, 30000000, 40000000 }, 3759 .hactive = { 800, 800, 800 }, 3760 .hfront_porch = { 40, 40, 40 }, 3761 .hback_porch = { 40, 40, 40 }, 3762 .hsync_len = { 1, 48, 48 }, 3763 .vactive = { 480, 480, 480 }, 3764 .vfront_porch = { 13, 13, 13 }, 3765 .vback_porch = { 29, 29, 29 }, 3766 .vsync_len = { 3, 3, 3 }, 3767 .flags = DISPLAY_FLAGS_DE_HIGH, 3768 }; 3769 3770 static const struct panel_desc okaya_rs800480t_7x0gp = { 3771 .timings = &okaya_rs800480t_7x0gp_timing, 3772 .num_timings = 1, 3773 .bpc = 6, 3774 .size = { 3775 .width = 154, 3776 .height = 87, 3777 }, 3778 .delay = { 3779 .prepare = 41, 3780 .enable = 50, 3781 .unprepare = 41, 3782 .disable = 50, 3783 }, 3784 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3785 }; 3786 3787 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3788 .clock = 9000, 3789 .hdisplay = 480, 3790 .hsync_start = 480 + 5, 3791 .hsync_end = 480 + 5 + 30, 3792 .htotal = 480 + 5 + 30 + 10, 3793 .vdisplay = 272, 3794 .vsync_start = 272 + 8, 3795 .vsync_end = 272 + 8 + 5, 3796 .vtotal = 272 + 8 + 5 + 3, 3797 }; 3798 3799 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3800 .modes = &olimex_lcd_olinuxino_43ts_mode, 3801 .num_modes = 1, 3802 .size = { 3803 .width = 95, 3804 .height = 54, 3805 }, 3806 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3807 }; 3808 3809 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3810 .clock = 33300, 3811 .hdisplay = 800, 3812 .hsync_start = 800 + 210, 3813 .hsync_end = 800 + 210 + 20, 3814 .htotal = 800 + 210 + 20 + 26, 3815 .vdisplay = 480, 3816 .vsync_start = 480 + 22, 3817 .vsync_end = 480 + 22 + 10, 3818 .vtotal = 480 + 22 + 10 + 13, 3819 }; 3820 3821 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3822 .modes = &olimex_lcd_olinuxino_5cts_mode, 3823 .num_modes = 1, 3824 .size = { 3825 .width = 154, 3826 .height = 86, 3827 }, 3828 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3829 }; 3830 3831 3832 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3833 .pixelclock = { 30000000, 30000000, 50000000 }, 3834 .hactive = { 800, 800, 800 }, 3835 .hfront_porch = { 1, 40, 255 }, 3836 .hback_porch = { 1, 40, 87 }, 3837 .hsync_len = { 1, 48, 87 }, 3838 .vactive = { 480, 480, 480 }, 3839 .vfront_porch = { 1, 13, 255 }, 3840 .vback_porch = { 1, 29, 29 }, 3841 .vsync_len = { 3, 3, 31 }, 3842 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3843 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3844 }; 3845 3846 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3847 .timings = &ontat_kd50g21_40nt_a1_timing, 3848 .num_timings = 1, 3849 .bpc = 8, 3850 .size = { 3851 .width = 108, 3852 .height = 65, 3853 }, 3854 .delay = { 3855 .prepare = 147, /* 5 VSDs */ 3856 .enable = 147, /* 5 VSDs */ 3857 .disable = 88, /* 3 VSDs */ 3858 .unprepare = 117, /* 4 VSDs */ 3859 }, 3860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3862 .connector_type = DRM_MODE_CONNECTOR_DPI, 3863 }; 3864 3865 /* 3866 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3867 * pixel clocks, but this is the timing that was being used in the Adafruit 3868 * installation instructions. 3869 */ 3870 static const struct drm_display_mode ontat_yx700wv03_mode = { 3871 .clock = 29500, 3872 .hdisplay = 800, 3873 .hsync_start = 824, 3874 .hsync_end = 896, 3875 .htotal = 992, 3876 .vdisplay = 480, 3877 .vsync_start = 483, 3878 .vsync_end = 493, 3879 .vtotal = 500, 3880 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3881 }; 3882 3883 /* 3884 * Specification at: 3885 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3886 */ 3887 static const struct panel_desc ontat_yx700wv03 = { 3888 .modes = &ontat_yx700wv03_mode, 3889 .num_modes = 1, 3890 .bpc = 8, 3891 .size = { 3892 .width = 154, 3893 .height = 83, 3894 }, 3895 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3896 }; 3897 3898 static const struct drm_display_mode ortustech_com37h3m_mode = { 3899 .clock = 22230, 3900 .hdisplay = 480, 3901 .hsync_start = 480 + 40, 3902 .hsync_end = 480 + 40 + 10, 3903 .htotal = 480 + 40 + 10 + 40, 3904 .vdisplay = 640, 3905 .vsync_start = 640 + 4, 3906 .vsync_end = 640 + 4 + 2, 3907 .vtotal = 640 + 4 + 2 + 4, 3908 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3909 }; 3910 3911 static const struct panel_desc ortustech_com37h3m = { 3912 .modes = &ortustech_com37h3m_mode, 3913 .num_modes = 1, 3914 .bpc = 8, 3915 .size = { 3916 .width = 56, /* 56.16mm */ 3917 .height = 75, /* 74.88mm */ 3918 }, 3919 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3920 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3921 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3922 }; 3923 3924 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3925 .clock = 25000, 3926 .hdisplay = 480, 3927 .hsync_start = 480 + 10, 3928 .hsync_end = 480 + 10 + 10, 3929 .htotal = 480 + 10 + 10 + 15, 3930 .vdisplay = 800, 3931 .vsync_start = 800 + 3, 3932 .vsync_end = 800 + 3 + 3, 3933 .vtotal = 800 + 3 + 3 + 3, 3934 }; 3935 3936 static const struct panel_desc ortustech_com43h4m85ulc = { 3937 .modes = &ortustech_com43h4m85ulc_mode, 3938 .num_modes = 1, 3939 .bpc = 6, 3940 .size = { 3941 .width = 56, 3942 .height = 93, 3943 }, 3944 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3945 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3946 .connector_type = DRM_MODE_CONNECTOR_DPI, 3947 }; 3948 3949 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3950 .clock = 33000, 3951 .hdisplay = 800, 3952 .hsync_start = 800 + 210, 3953 .hsync_end = 800 + 210 + 30, 3954 .htotal = 800 + 210 + 30 + 16, 3955 .vdisplay = 480, 3956 .vsync_start = 480 + 22, 3957 .vsync_end = 480 + 22 + 13, 3958 .vtotal = 480 + 22 + 13 + 10, 3959 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3960 }; 3961 3962 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3963 .modes = &osddisplays_osd070t1718_19ts_mode, 3964 .num_modes = 1, 3965 .bpc = 8, 3966 .size = { 3967 .width = 152, 3968 .height = 91, 3969 }, 3970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3971 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3972 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3973 .connector_type = DRM_MODE_CONNECTOR_DPI, 3974 }; 3975 3976 static const struct drm_display_mode pda_91_00156_a0_mode = { 3977 .clock = 33300, 3978 .hdisplay = 800, 3979 .hsync_start = 800 + 1, 3980 .hsync_end = 800 + 1 + 64, 3981 .htotal = 800 + 1 + 64 + 64, 3982 .vdisplay = 480, 3983 .vsync_start = 480 + 1, 3984 .vsync_end = 480 + 1 + 23, 3985 .vtotal = 480 + 1 + 23 + 22, 3986 }; 3987 3988 static const struct panel_desc pda_91_00156_a0 = { 3989 .modes = &pda_91_00156_a0_mode, 3990 .num_modes = 1, 3991 .size = { 3992 .width = 152, 3993 .height = 91, 3994 }, 3995 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3996 }; 3997 3998 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3999 .clock = 71150, 4000 .hdisplay = 1280, 4001 .hsync_start = 1280 + 48, 4002 .hsync_end = 1280 + 48 + 32, 4003 .htotal = 1280 + 48 + 32 + 80, 4004 .vdisplay = 800, 4005 .vsync_start = 800 + 9, 4006 .vsync_end = 800 + 9 + 8, 4007 .vtotal = 800 + 9 + 8 + 6, 4008 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4009 }; 4010 4011 static const struct panel_desc powertip_ph128800t004_zza01 = { 4012 .modes = &powertip_ph128800t004_zza01_mode, 4013 .num_modes = 1, 4014 .bpc = 8, 4015 .size = { 4016 .width = 216, 4017 .height = 135, 4018 }, 4019 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4020 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4021 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4022 }; 4023 4024 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 4025 .clock = 66500, 4026 .hdisplay = 1280, 4027 .hsync_start = 1280 + 12, 4028 .hsync_end = 1280 + 12 + 20, 4029 .htotal = 1280 + 12 + 20 + 56, 4030 .vdisplay = 800, 4031 .vsync_start = 800 + 1, 4032 .vsync_end = 800 + 1 + 3, 4033 .vtotal = 800 + 1 + 3 + 20, 4034 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4035 }; 4036 4037 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4038 .modes = &powertip_ph128800t006_zhc01_mode, 4039 .num_modes = 1, 4040 .bpc = 8, 4041 .size = { 4042 .width = 216, 4043 .height = 135, 4044 }, 4045 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4046 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4047 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4048 }; 4049 4050 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4051 .clock = 24750, 4052 .hdisplay = 800, 4053 .hsync_start = 800 + 54, 4054 .hsync_end = 800 + 54 + 2, 4055 .htotal = 800 + 54 + 2 + 44, 4056 .vdisplay = 480, 4057 .vsync_start = 480 + 49, 4058 .vsync_end = 480 + 49 + 2, 4059 .vtotal = 480 + 49 + 2 + 22, 4060 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4061 }; 4062 4063 static const struct panel_desc powertip_ph800480t013_idf02 = { 4064 .modes = &powertip_ph800480t013_idf02_mode, 4065 .num_modes = 1, 4066 .bpc = 8, 4067 .size = { 4068 .width = 152, 4069 .height = 91, 4070 }, 4071 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4072 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4073 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4074 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4075 .connector_type = DRM_MODE_CONNECTOR_DPI, 4076 }; 4077 4078 static const struct drm_display_mode powertip_ph800480t032_zhc19_mode = { 4079 .clock = 27200, 4080 .hdisplay = 800, 4081 .hsync_start = 800 + 52, 4082 .hsync_end = 800 + 52 + 2, 4083 .htotal = 800 + 52 + 2 + 44, 4084 .vdisplay = 480, 4085 .vsync_start = 480 + 7, 4086 .vsync_end = 480 + 7 + 2, 4087 .vtotal = 480 + 7 + 2 + 2, 4088 }; 4089 4090 static const struct panel_desc powertip_ph800480t032_zhc19 = { 4091 .modes = &powertip_ph800480t032_zhc19_mode, 4092 .num_modes = 1, 4093 .bpc = 8, 4094 .size = { 4095 .width = 152, 4096 .height = 91, 4097 }, 4098 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4099 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4100 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4101 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4102 .connector_type = DRM_MODE_CONNECTOR_DPI, 4103 }; 4104 4105 static const struct drm_display_mode primeview_pm070wl4_mode = { 4106 .clock = 32000, 4107 .hdisplay = 800, 4108 .hsync_start = 800 + 42, 4109 .hsync_end = 800 + 42 + 128, 4110 .htotal = 800 + 42 + 128 + 86, 4111 .vdisplay = 480, 4112 .vsync_start = 480 + 10, 4113 .vsync_end = 480 + 10 + 2, 4114 .vtotal = 480 + 10 + 2 + 33, 4115 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4116 }; 4117 4118 static const struct panel_desc primeview_pm070wl4 = { 4119 .modes = &primeview_pm070wl4_mode, 4120 .num_modes = 1, 4121 .bpc = 6, 4122 .size = { 4123 .width = 152, 4124 .height = 91, 4125 }, 4126 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4127 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4128 .connector_type = DRM_MODE_CONNECTOR_DPI, 4129 }; 4130 4131 static const struct drm_display_mode qd43003c0_40_mode = { 4132 .clock = 9000, 4133 .hdisplay = 480, 4134 .hsync_start = 480 + 8, 4135 .hsync_end = 480 + 8 + 4, 4136 .htotal = 480 + 8 + 4 + 39, 4137 .vdisplay = 272, 4138 .vsync_start = 272 + 4, 4139 .vsync_end = 272 + 4 + 10, 4140 .vtotal = 272 + 4 + 10 + 2, 4141 }; 4142 4143 static const struct panel_desc qd43003c0_40 = { 4144 .modes = &qd43003c0_40_mode, 4145 .num_modes = 1, 4146 .bpc = 8, 4147 .size = { 4148 .width = 95, 4149 .height = 53, 4150 }, 4151 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4152 }; 4153 4154 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4155 { /* 60 Hz */ 4156 .clock = 10800, 4157 .hdisplay = 480, 4158 .hsync_start = 480 + 77, 4159 .hsync_end = 480 + 77 + 41, 4160 .htotal = 480 + 77 + 41 + 2, 4161 .vdisplay = 272, 4162 .vsync_start = 272 + 16, 4163 .vsync_end = 272 + 16 + 10, 4164 .vtotal = 272 + 16 + 10 + 2, 4165 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4166 }, 4167 { /* 50 Hz */ 4168 .clock = 10800, 4169 .hdisplay = 480, 4170 .hsync_start = 480 + 17, 4171 .hsync_end = 480 + 17 + 41, 4172 .htotal = 480 + 17 + 41 + 2, 4173 .vdisplay = 272, 4174 .vsync_start = 272 + 116, 4175 .vsync_end = 272 + 116 + 10, 4176 .vtotal = 272 + 116 + 10 + 2, 4177 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4178 }, 4179 }; 4180 4181 static const struct panel_desc qishenglong_gopher2b_lcd = { 4182 .modes = qishenglong_gopher2b_lcd_modes, 4183 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4184 .bpc = 8, 4185 .size = { 4186 .width = 95, 4187 .height = 54, 4188 }, 4189 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4190 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4191 .connector_type = DRM_MODE_CONNECTOR_DPI, 4192 }; 4193 4194 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4195 .pixelclock = { 23000000, 25000000, 27000000 }, 4196 .hactive = { 800, 800, 800 }, 4197 .hback_porch = { 4, 8, 48 }, 4198 .hfront_porch = { 4, 8, 48 }, 4199 .hsync_len = { 2, 4, 8 }, 4200 .vactive = { 480, 480, 480 }, 4201 .vback_porch = { 4, 8, 12 }, 4202 .vfront_porch = { 4, 8, 12 }, 4203 .vsync_len = { 2, 4, 8 }, 4204 }; 4205 4206 static const struct panel_desc raystar_rff500f_awh_dnn = { 4207 .timings = &raystar_rff500f_awh_dnn_timing, 4208 .num_timings = 1, 4209 .bpc = 8, 4210 .size = { 4211 .width = 108, 4212 .height = 65, 4213 }, 4214 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4215 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4216 }; 4217 4218 static const struct display_timing rocktech_rk043fn48h_timing = { 4219 .pixelclock = { 6000000, 9000000, 12000000 }, 4220 .hactive = { 480, 480, 480 }, 4221 .hback_porch = { 8, 43, 43 }, 4222 .hfront_porch = { 2, 8, 10 }, 4223 .hsync_len = { 1, 1, 1 }, 4224 .vactive = { 272, 272, 272 }, 4225 .vback_porch = { 2, 12, 26 }, 4226 .vfront_porch = { 1, 4, 4 }, 4227 .vsync_len = { 1, 10, 10 }, 4228 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4229 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4230 DISPLAY_FLAGS_SYNC_POSEDGE, 4231 }; 4232 4233 static const struct panel_desc rocktech_rk043fn48h = { 4234 .timings = &rocktech_rk043fn48h_timing, 4235 .num_timings = 1, 4236 .bpc = 8, 4237 .size = { 4238 .width = 95, 4239 .height = 54, 4240 }, 4241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4242 .connector_type = DRM_MODE_CONNECTOR_DPI, 4243 }; 4244 4245 static const struct display_timing rocktech_rk070er9427_timing = { 4246 .pixelclock = { 26400000, 33300000, 46800000 }, 4247 .hactive = { 800, 800, 800 }, 4248 .hfront_porch = { 16, 210, 354 }, 4249 .hback_porch = { 46, 46, 46 }, 4250 .hsync_len = { 1, 1, 1 }, 4251 .vactive = { 480, 480, 480 }, 4252 .vfront_porch = { 7, 22, 147 }, 4253 .vback_porch = { 23, 23, 23 }, 4254 .vsync_len = { 1, 1, 1 }, 4255 .flags = DISPLAY_FLAGS_DE_HIGH, 4256 }; 4257 4258 static const struct panel_desc rocktech_rk070er9427 = { 4259 .timings = &rocktech_rk070er9427_timing, 4260 .num_timings = 1, 4261 .bpc = 6, 4262 .size = { 4263 .width = 154, 4264 .height = 86, 4265 }, 4266 .delay = { 4267 .prepare = 41, 4268 .enable = 50, 4269 .unprepare = 41, 4270 .disable = 50, 4271 }, 4272 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4273 }; 4274 4275 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4276 .clock = 71100, 4277 .hdisplay = 1280, 4278 .hsync_start = 1280 + 48, 4279 .hsync_end = 1280 + 48 + 32, 4280 .htotal = 1280 + 48 + 32 + 80, 4281 .vdisplay = 800, 4282 .vsync_start = 800 + 2, 4283 .vsync_end = 800 + 2 + 5, 4284 .vtotal = 800 + 2 + 5 + 16, 4285 }; 4286 4287 static const struct panel_desc rocktech_rk101ii01d_ct = { 4288 .modes = &rocktech_rk101ii01d_ct_mode, 4289 .bpc = 8, 4290 .num_modes = 1, 4291 .size = { 4292 .width = 217, 4293 .height = 136, 4294 }, 4295 .delay = { 4296 .prepare = 50, 4297 .disable = 50, 4298 }, 4299 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4300 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4301 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4302 }; 4303 4304 static const struct display_timing samsung_ltl101al01_timing = { 4305 .pixelclock = { 66663000, 66663000, 66663000 }, 4306 .hactive = { 1280, 1280, 1280 }, 4307 .hfront_porch = { 18, 18, 18 }, 4308 .hback_porch = { 36, 36, 36 }, 4309 .hsync_len = { 16, 16, 16 }, 4310 .vactive = { 800, 800, 800 }, 4311 .vfront_porch = { 4, 4, 4 }, 4312 .vback_porch = { 16, 16, 16 }, 4313 .vsync_len = { 3, 3, 3 }, 4314 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4315 }; 4316 4317 static const struct panel_desc samsung_ltl101al01 = { 4318 .timings = &samsung_ltl101al01_timing, 4319 .num_timings = 1, 4320 .bpc = 8, 4321 .size = { 4322 .width = 217, 4323 .height = 135, 4324 }, 4325 .delay = { 4326 .prepare = 40, 4327 .enable = 300, 4328 .disable = 200, 4329 .unprepare = 600, 4330 }, 4331 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4332 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4333 }; 4334 4335 static const struct display_timing samsung_ltl106al01_timing = { 4336 .pixelclock = { 71980000, 71980000, 71980000 }, 4337 .hactive = { 1366, 1366, 1366 }, 4338 .hfront_porch = { 56, 56, 56 }, 4339 .hback_porch = { 106, 106, 106 }, 4340 .hsync_len = { 14, 14, 14 }, 4341 .vactive = { 768, 768, 768 }, 4342 .vfront_porch = { 3, 3, 3 }, 4343 .vback_porch = { 6, 6, 6 }, 4344 .vsync_len = { 1, 1, 1 }, 4345 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4346 }; 4347 4348 static const struct panel_desc samsung_ltl106al01 = { 4349 .timings = &samsung_ltl106al01_timing, 4350 .num_timings = 1, 4351 .bpc = 8, 4352 .size = { 4353 .width = 235, 4354 .height = 132, 4355 }, 4356 .delay = { 4357 .prepare = 5, 4358 .enable = 10, 4359 .disable = 10, 4360 .unprepare = 5, 4361 }, 4362 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4363 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4364 }; 4365 4366 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4367 .clock = 54030, 4368 .hdisplay = 1024, 4369 .hsync_start = 1024 + 24, 4370 .hsync_end = 1024 + 24 + 136, 4371 .htotal = 1024 + 24 + 136 + 160, 4372 .vdisplay = 600, 4373 .vsync_start = 600 + 3, 4374 .vsync_end = 600 + 3 + 6, 4375 .vtotal = 600 + 3 + 6 + 61, 4376 }; 4377 4378 static const struct panel_desc samsung_ltn101nt05 = { 4379 .modes = &samsung_ltn101nt05_mode, 4380 .num_modes = 1, 4381 .bpc = 6, 4382 .size = { 4383 .width = 223, 4384 .height = 125, 4385 }, 4386 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4387 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4388 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4389 }; 4390 4391 static const struct display_timing satoz_sat050at40h12r2_timing = { 4392 .pixelclock = {33300000, 33300000, 50000000}, 4393 .hactive = {800, 800, 800}, 4394 .hfront_porch = {16, 210, 354}, 4395 .hback_porch = {46, 46, 46}, 4396 .hsync_len = {1, 1, 40}, 4397 .vactive = {480, 480, 480}, 4398 .vfront_porch = {7, 22, 147}, 4399 .vback_porch = {23, 23, 23}, 4400 .vsync_len = {1, 1, 20}, 4401 }; 4402 4403 static const struct panel_desc satoz_sat050at40h12r2 = { 4404 .timings = &satoz_sat050at40h12r2_timing, 4405 .num_timings = 1, 4406 .bpc = 8, 4407 .size = { 4408 .width = 108, 4409 .height = 65, 4410 }, 4411 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4412 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4413 }; 4414 4415 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4416 .clock = 33260, 4417 .hdisplay = 800, 4418 .hsync_start = 800 + 64, 4419 .hsync_end = 800 + 64 + 128, 4420 .htotal = 800 + 64 + 128 + 64, 4421 .vdisplay = 480, 4422 .vsync_start = 480 + 8, 4423 .vsync_end = 480 + 8 + 2, 4424 .vtotal = 480 + 8 + 2 + 35, 4425 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4426 }; 4427 4428 static const struct panel_desc sharp_lq070y3dg3b = { 4429 .modes = &sharp_lq070y3dg3b_mode, 4430 .num_modes = 1, 4431 .bpc = 8, 4432 .size = { 4433 .width = 152, /* 152.4mm */ 4434 .height = 91, /* 91.4mm */ 4435 }, 4436 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4437 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4438 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4439 }; 4440 4441 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4442 .clock = 5500, 4443 .hdisplay = 240, 4444 .hsync_start = 240 + 16, 4445 .hsync_end = 240 + 16 + 7, 4446 .htotal = 240 + 16 + 7 + 5, 4447 .vdisplay = 320, 4448 .vsync_start = 320 + 9, 4449 .vsync_end = 320 + 9 + 1, 4450 .vtotal = 320 + 9 + 1 + 7, 4451 }; 4452 4453 static const struct panel_desc sharp_lq035q7db03 = { 4454 .modes = &sharp_lq035q7db03_mode, 4455 .num_modes = 1, 4456 .bpc = 6, 4457 .size = { 4458 .width = 54, 4459 .height = 72, 4460 }, 4461 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4462 }; 4463 4464 static const struct display_timing sharp_lq101k1ly04_timing = { 4465 .pixelclock = { 60000000, 65000000, 80000000 }, 4466 .hactive = { 1280, 1280, 1280 }, 4467 .hfront_porch = { 20, 20, 20 }, 4468 .hback_porch = { 20, 20, 20 }, 4469 .hsync_len = { 10, 10, 10 }, 4470 .vactive = { 800, 800, 800 }, 4471 .vfront_porch = { 4, 4, 4 }, 4472 .vback_porch = { 4, 4, 4 }, 4473 .vsync_len = { 4, 4, 4 }, 4474 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4475 }; 4476 4477 static const struct panel_desc sharp_lq101k1ly04 = { 4478 .timings = &sharp_lq101k1ly04_timing, 4479 .num_timings = 1, 4480 .bpc = 8, 4481 .size = { 4482 .width = 217, 4483 .height = 136, 4484 }, 4485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4486 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4487 }; 4488 4489 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4490 { /* 50 Hz */ 4491 .clock = 3000, 4492 .hdisplay = 240, 4493 .hsync_start = 240 + 58, 4494 .hsync_end = 240 + 58 + 1, 4495 .htotal = 240 + 58 + 1 + 1, 4496 .vdisplay = 160, 4497 .vsync_start = 160 + 24, 4498 .vsync_end = 160 + 24 + 10, 4499 .vtotal = 160 + 24 + 10 + 6, 4500 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4501 }, 4502 { /* 60 Hz */ 4503 .clock = 3000, 4504 .hdisplay = 240, 4505 .hsync_start = 240 + 8, 4506 .hsync_end = 240 + 8 + 1, 4507 .htotal = 240 + 8 + 1 + 1, 4508 .vdisplay = 160, 4509 .vsync_start = 160 + 24, 4510 .vsync_end = 160 + 24 + 10, 4511 .vtotal = 160 + 24 + 10 + 6, 4512 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4513 }, 4514 }; 4515 4516 static const struct panel_desc sharp_ls020b1dd01d = { 4517 .modes = sharp_ls020b1dd01d_modes, 4518 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4519 .bpc = 6, 4520 .size = { 4521 .width = 42, 4522 .height = 28, 4523 }, 4524 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4525 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4526 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4527 | DRM_BUS_FLAG_SHARP_SIGNALS, 4528 }; 4529 4530 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4531 .clock = 33300, 4532 .hdisplay = 800, 4533 .hsync_start = 800 + 1, 4534 .hsync_end = 800 + 1 + 64, 4535 .htotal = 800 + 1 + 64 + 64, 4536 .vdisplay = 480, 4537 .vsync_start = 480 + 1, 4538 .vsync_end = 480 + 1 + 23, 4539 .vtotal = 480 + 1 + 23 + 22, 4540 }; 4541 4542 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4543 .modes = &shelly_sca07010_bfn_lnn_mode, 4544 .num_modes = 1, 4545 .size = { 4546 .width = 152, 4547 .height = 91, 4548 }, 4549 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4550 }; 4551 4552 static const struct drm_display_mode starry_kr070pe2t_mode = { 4553 .clock = 33000, 4554 .hdisplay = 800, 4555 .hsync_start = 800 + 209, 4556 .hsync_end = 800 + 209 + 1, 4557 .htotal = 800 + 209 + 1 + 45, 4558 .vdisplay = 480, 4559 .vsync_start = 480 + 22, 4560 .vsync_end = 480 + 22 + 1, 4561 .vtotal = 480 + 22 + 1 + 22, 4562 }; 4563 4564 static const struct panel_desc starry_kr070pe2t = { 4565 .modes = &starry_kr070pe2t_mode, 4566 .num_modes = 1, 4567 .bpc = 8, 4568 .size = { 4569 .width = 152, 4570 .height = 86, 4571 }, 4572 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4573 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4574 .connector_type = DRM_MODE_CONNECTOR_DPI, 4575 }; 4576 4577 static const struct display_timing startek_kd070wvfpa_mode = { 4578 .pixelclock = { 25200000, 27200000, 30500000 }, 4579 .hactive = { 800, 800, 800 }, 4580 .hfront_porch = { 19, 44, 115 }, 4581 .hback_porch = { 5, 16, 101 }, 4582 .hsync_len = { 1, 2, 100 }, 4583 .vactive = { 480, 480, 480 }, 4584 .vfront_porch = { 5, 43, 67 }, 4585 .vback_porch = { 5, 5, 67 }, 4586 .vsync_len = { 1, 2, 66 }, 4587 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4588 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4589 DISPLAY_FLAGS_SYNC_POSEDGE, 4590 }; 4591 4592 static const struct panel_desc startek_kd070wvfpa = { 4593 .timings = &startek_kd070wvfpa_mode, 4594 .num_timings = 1, 4595 .bpc = 8, 4596 .size = { 4597 .width = 152, 4598 .height = 91, 4599 }, 4600 .delay = { 4601 .prepare = 20, 4602 .enable = 200, 4603 .disable = 200, 4604 }, 4605 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4606 .connector_type = DRM_MODE_CONNECTOR_DPI, 4607 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4608 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4609 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4610 }; 4611 4612 static const struct display_timing tsd_tst043015cmhx_timing = { 4613 .pixelclock = { 5000000, 9000000, 12000000 }, 4614 .hactive = { 480, 480, 480 }, 4615 .hfront_porch = { 4, 5, 65 }, 4616 .hback_porch = { 36, 40, 255 }, 4617 .hsync_len = { 1, 1, 1 }, 4618 .vactive = { 272, 272, 272 }, 4619 .vfront_porch = { 2, 8, 97 }, 4620 .vback_porch = { 3, 8, 31 }, 4621 .vsync_len = { 1, 1, 1 }, 4622 4623 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4624 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4625 }; 4626 4627 static const struct panel_desc tsd_tst043015cmhx = { 4628 .timings = &tsd_tst043015cmhx_timing, 4629 .num_timings = 1, 4630 .bpc = 8, 4631 .size = { 4632 .width = 105, 4633 .height = 67, 4634 }, 4635 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4637 }; 4638 4639 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4640 .clock = 30000, 4641 .hdisplay = 800, 4642 .hsync_start = 800 + 39, 4643 .hsync_end = 800 + 39 + 47, 4644 .htotal = 800 + 39 + 47 + 39, 4645 .vdisplay = 480, 4646 .vsync_start = 480 + 13, 4647 .vsync_end = 480 + 13 + 2, 4648 .vtotal = 480 + 13 + 2 + 29, 4649 }; 4650 4651 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4652 .modes = &tfc_s9700rtwv43tr_01b_mode, 4653 .num_modes = 1, 4654 .bpc = 8, 4655 .size = { 4656 .width = 155, 4657 .height = 90, 4658 }, 4659 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4660 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4661 }; 4662 4663 static const struct display_timing tianma_tm070jdhg30_timing = { 4664 .pixelclock = { 62600000, 68200000, 78100000 }, 4665 .hactive = { 1280, 1280, 1280 }, 4666 .hfront_porch = { 15, 64, 159 }, 4667 .hback_porch = { 5, 5, 5 }, 4668 .hsync_len = { 1, 1, 256 }, 4669 .vactive = { 800, 800, 800 }, 4670 .vfront_porch = { 3, 40, 99 }, 4671 .vback_porch = { 2, 2, 2 }, 4672 .vsync_len = { 1, 1, 128 }, 4673 .flags = DISPLAY_FLAGS_DE_HIGH, 4674 }; 4675 4676 static const struct panel_desc tianma_tm070jdhg30 = { 4677 .timings = &tianma_tm070jdhg30_timing, 4678 .num_timings = 1, 4679 .bpc = 8, 4680 .size = { 4681 .width = 151, 4682 .height = 95, 4683 }, 4684 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4685 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4686 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4687 }; 4688 4689 static const struct panel_desc tianma_tm070jvhg33 = { 4690 .timings = &tianma_tm070jdhg30_timing, 4691 .num_timings = 1, 4692 .bpc = 8, 4693 .size = { 4694 .width = 150, 4695 .height = 94, 4696 }, 4697 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4698 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4699 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4700 }; 4701 4702 /* 4703 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4704 * front porch, not including sync pulse width. This is for both H and 4705 * V. To make the total blanking and period correct, subtract the pulse 4706 * width from the front porch. 4707 * 4708 * This works well for the Min and Typ values, but for Max values the sync 4709 * pulse width is higher than back porch + front porch, so work around that 4710 * by reducing the Max sync length value to 1 and then treating the Max 4711 * porches as in the Min and Typ cases. 4712 * 4713 * Exact datasheet values are added as a comment where they differ from the 4714 * ones implemented for the above reason. 4715 * 4716 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4717 * and total blanking time, however the resulting values are the same as 4718 * the TM070JDHG34-00. 4719 */ 4720 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4721 .pixelclock = { 68400000, 71900000, 78100000 }, 4722 .hactive = { 1280, 1280, 1280 }, 4723 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4724 .hback_porch = { 5, 5, 5 }, 4725 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4726 .vactive = { 800, 800, 800 }, 4727 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4728 .vback_porch = { 2, 2, 2 }, 4729 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4730 .flags = DISPLAY_FLAGS_DE_HIGH, 4731 }; 4732 4733 static const struct panel_desc tianma_tm070jdhg34_00 = { 4734 .timings = &tianma_tm070jdhg34_00_timing, 4735 .num_timings = 1, 4736 .bpc = 8, 4737 .size = { 4738 .width = 150, /* 149.76 */ 4739 .height = 94, /* 93.60 */ 4740 }, 4741 .delay = { 4742 .prepare = 15, /* Tp1 */ 4743 .enable = 150, /* Tp2 */ 4744 .disable = 150, /* Tp4 */ 4745 .unprepare = 120, /* Tp3 */ 4746 }, 4747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4748 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4749 }; 4750 4751 static const struct panel_desc tianma_p0700wxf1mbaa = { 4752 .timings = &tianma_tm070jdhg34_00_timing, 4753 .num_timings = 1, 4754 .bpc = 8, 4755 .size = { 4756 .width = 150, /* 149.76 */ 4757 .height = 94, /* 93.60 */ 4758 }, 4759 .delay = { 4760 .prepare = 18, /* Tr + Tp1 */ 4761 .enable = 152, /* Tp2 + Tp5 */ 4762 .disable = 152, /* Tp6 + Tp4 */ 4763 .unprepare = 120, /* Tp3 */ 4764 }, 4765 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4766 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4767 }; 4768 4769 static const struct display_timing tianma_tm070rvhg71_timing = { 4770 .pixelclock = { 27700000, 29200000, 39600000 }, 4771 .hactive = { 800, 800, 800 }, 4772 .hfront_porch = { 12, 40, 212 }, 4773 .hback_porch = { 88, 88, 88 }, 4774 .hsync_len = { 1, 1, 40 }, 4775 .vactive = { 480, 480, 480 }, 4776 .vfront_porch = { 1, 13, 88 }, 4777 .vback_porch = { 32, 32, 32 }, 4778 .vsync_len = { 1, 1, 3 }, 4779 .flags = DISPLAY_FLAGS_DE_HIGH, 4780 }; 4781 4782 static const struct panel_desc tianma_tm070rvhg71 = { 4783 .timings = &tianma_tm070rvhg71_timing, 4784 .num_timings = 1, 4785 .bpc = 8, 4786 .size = { 4787 .width = 154, 4788 .height = 86, 4789 }, 4790 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4791 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4792 }; 4793 4794 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4795 { 4796 .clock = 10000, 4797 .hdisplay = 320, 4798 .hsync_start = 320 + 50, 4799 .hsync_end = 320 + 50 + 6, 4800 .htotal = 320 + 50 + 6 + 38, 4801 .vdisplay = 240, 4802 .vsync_start = 240 + 3, 4803 .vsync_end = 240 + 3 + 1, 4804 .vtotal = 240 + 3 + 1 + 17, 4805 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4806 }, 4807 }; 4808 4809 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4810 .modes = ti_nspire_cx_lcd_mode, 4811 .num_modes = 1, 4812 .bpc = 8, 4813 .size = { 4814 .width = 65, 4815 .height = 49, 4816 }, 4817 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4818 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4819 }; 4820 4821 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4822 { 4823 .clock = 10000, 4824 .hdisplay = 320, 4825 .hsync_start = 320 + 6, 4826 .hsync_end = 320 + 6 + 6, 4827 .htotal = 320 + 6 + 6 + 6, 4828 .vdisplay = 240, 4829 .vsync_start = 240 + 0, 4830 .vsync_end = 240 + 0 + 1, 4831 .vtotal = 240 + 0 + 1 + 0, 4832 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4833 }, 4834 }; 4835 4836 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4837 .modes = ti_nspire_classic_lcd_mode, 4838 .num_modes = 1, 4839 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4840 .bpc = 8, 4841 .size = { 4842 .width = 71, 4843 .height = 53, 4844 }, 4845 /* This is the grayscale bus format */ 4846 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4847 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4848 }; 4849 4850 static const struct display_timing topland_tian_g07017_01_timing = { 4851 .pixelclock = { 44900000, 51200000, 63000000 }, 4852 .hactive = { 1024, 1024, 1024 }, 4853 .hfront_porch = { 16, 160, 216 }, 4854 .hback_porch = { 160, 160, 160 }, 4855 .hsync_len = { 1, 1, 140 }, 4856 .vactive = { 600, 600, 600 }, 4857 .vfront_porch = { 1, 12, 127 }, 4858 .vback_porch = { 23, 23, 23 }, 4859 .vsync_len = { 1, 1, 20 }, 4860 }; 4861 4862 static const struct panel_desc topland_tian_g07017_01 = { 4863 .timings = &topland_tian_g07017_01_timing, 4864 .num_timings = 1, 4865 .bpc = 8, 4866 .size = { 4867 .width = 154, 4868 .height = 86, 4869 }, 4870 .delay = { 4871 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4872 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4873 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4874 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4875 }, 4876 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4877 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4878 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4879 }; 4880 4881 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4882 .clock = 79500, 4883 .hdisplay = 1280, 4884 .hsync_start = 1280 + 192, 4885 .hsync_end = 1280 + 192 + 128, 4886 .htotal = 1280 + 192 + 128 + 64, 4887 .vdisplay = 768, 4888 .vsync_start = 768 + 20, 4889 .vsync_end = 768 + 20 + 7, 4890 .vtotal = 768 + 20 + 7 + 3, 4891 }; 4892 4893 static const struct panel_desc toshiba_lt089ac29000 = { 4894 .modes = &toshiba_lt089ac29000_mode, 4895 .num_modes = 1, 4896 .size = { 4897 .width = 194, 4898 .height = 116, 4899 }, 4900 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4901 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4902 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4903 }; 4904 4905 static const struct drm_display_mode tpk_f07a_0102_mode = { 4906 .clock = 33260, 4907 .hdisplay = 800, 4908 .hsync_start = 800 + 40, 4909 .hsync_end = 800 + 40 + 128, 4910 .htotal = 800 + 40 + 128 + 88, 4911 .vdisplay = 480, 4912 .vsync_start = 480 + 10, 4913 .vsync_end = 480 + 10 + 2, 4914 .vtotal = 480 + 10 + 2 + 33, 4915 }; 4916 4917 static const struct panel_desc tpk_f07a_0102 = { 4918 .modes = &tpk_f07a_0102_mode, 4919 .num_modes = 1, 4920 .size = { 4921 .width = 152, 4922 .height = 91, 4923 }, 4924 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4925 }; 4926 4927 static const struct drm_display_mode tpk_f10a_0102_mode = { 4928 .clock = 45000, 4929 .hdisplay = 1024, 4930 .hsync_start = 1024 + 176, 4931 .hsync_end = 1024 + 176 + 5, 4932 .htotal = 1024 + 176 + 5 + 88, 4933 .vdisplay = 600, 4934 .vsync_start = 600 + 20, 4935 .vsync_end = 600 + 20 + 5, 4936 .vtotal = 600 + 20 + 5 + 25, 4937 }; 4938 4939 static const struct panel_desc tpk_f10a_0102 = { 4940 .modes = &tpk_f10a_0102_mode, 4941 .num_modes = 1, 4942 .size = { 4943 .width = 223, 4944 .height = 125, 4945 }, 4946 }; 4947 4948 static const struct display_timing urt_umsh_8596md_timing = { 4949 .pixelclock = { 33260000, 33260000, 33260000 }, 4950 .hactive = { 800, 800, 800 }, 4951 .hfront_porch = { 41, 41, 41 }, 4952 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4953 .hsync_len = { 71, 128, 128 }, 4954 .vactive = { 480, 480, 480 }, 4955 .vfront_porch = { 10, 10, 10 }, 4956 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4957 .vsync_len = { 2, 2, 2 }, 4958 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4959 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4960 }; 4961 4962 static const struct panel_desc urt_umsh_8596md_lvds = { 4963 .timings = &urt_umsh_8596md_timing, 4964 .num_timings = 1, 4965 .bpc = 6, 4966 .size = { 4967 .width = 152, 4968 .height = 91, 4969 }, 4970 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4971 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4972 }; 4973 4974 static const struct panel_desc urt_umsh_8596md_parallel = { 4975 .timings = &urt_umsh_8596md_timing, 4976 .num_timings = 1, 4977 .bpc = 6, 4978 .size = { 4979 .width = 152, 4980 .height = 91, 4981 }, 4982 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4983 }; 4984 4985 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4986 .clock = 60000, 4987 .hdisplay = 1024, 4988 .hsync_start = 1024 + 160, 4989 .hsync_end = 1024 + 160 + 100, 4990 .htotal = 1024 + 160 + 100 + 60, 4991 .vdisplay = 600, 4992 .vsync_start = 600 + 12, 4993 .vsync_end = 600 + 12 + 10, 4994 .vtotal = 600 + 12 + 10 + 13, 4995 }; 4996 4997 static const struct panel_desc vivax_tpc9150_panel = { 4998 .modes = &vivax_tpc9150_panel_mode, 4999 .num_modes = 1, 5000 .bpc = 6, 5001 .size = { 5002 .width = 200, 5003 .height = 115, 5004 }, 5005 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5006 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5007 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5008 }; 5009 5010 static const struct drm_display_mode vl050_8048nt_c01_mode = { 5011 .clock = 33333, 5012 .hdisplay = 800, 5013 .hsync_start = 800 + 210, 5014 .hsync_end = 800 + 210 + 20, 5015 .htotal = 800 + 210 + 20 + 46, 5016 .vdisplay = 480, 5017 .vsync_start = 480 + 22, 5018 .vsync_end = 480 + 22 + 10, 5019 .vtotal = 480 + 22 + 10 + 23, 5020 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5021 }; 5022 5023 static const struct panel_desc vl050_8048nt_c01 = { 5024 .modes = &vl050_8048nt_c01_mode, 5025 .num_modes = 1, 5026 .bpc = 8, 5027 .size = { 5028 .width = 120, 5029 .height = 76, 5030 }, 5031 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5032 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5033 }; 5034 5035 static const struct drm_display_mode waveshare_133inch_mode = { 5036 .clock = 148500, 5037 .hdisplay = 1920, 5038 .hsync_start = 1920 + 88, 5039 .hsync_end = 1920 + 88 + 44, 5040 .htotal = 1920 + 88 + 44 + 148, 5041 .vdisplay = 1080, 5042 .vsync_start = 1080 + 4, 5043 .vsync_end = 1080 + 4 + 5, 5044 .vtotal = 1080 + 4 + 5 + 36, 5045 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5046 }; 5047 5048 static const struct panel_desc waveshare_133inch = { 5049 .modes = &waveshare_133inch_mode, 5050 .num_modes = 1, 5051 .bpc = 8, 5052 .size = { 5053 .width = 293, 5054 .height = 163, 5055 }, 5056 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5057 .connector_type = DRM_MODE_CONNECTOR_DPI, 5058 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5059 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5060 }; 5061 5062 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 5063 .clock = 6410, 5064 .hdisplay = 320, 5065 .hsync_start = 320 + 20, 5066 .hsync_end = 320 + 20 + 30, 5067 .htotal = 320 + 20 + 30 + 38, 5068 .vdisplay = 240, 5069 .vsync_start = 240 + 4, 5070 .vsync_end = 240 + 4 + 3, 5071 .vtotal = 240 + 4 + 3 + 15, 5072 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5073 }; 5074 5075 static const struct panel_desc winstar_wf35ltiacd = { 5076 .modes = &winstar_wf35ltiacd_mode, 5077 .num_modes = 1, 5078 .bpc = 8, 5079 .size = { 5080 .width = 70, 5081 .height = 53, 5082 }, 5083 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5084 }; 5085 5086 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5087 .clock = 51200, 5088 .hdisplay = 1024, 5089 .hsync_start = 1024 + 100, 5090 .hsync_end = 1024 + 100 + 100, 5091 .htotal = 1024 + 100 + 100 + 120, 5092 .vdisplay = 600, 5093 .vsync_start = 600 + 10, 5094 .vsync_end = 600 + 10 + 10, 5095 .vtotal = 600 + 10 + 10 + 15, 5096 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5097 }; 5098 5099 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5100 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5101 .num_modes = 1, 5102 .bpc = 8, 5103 .size = { 5104 .width = 154, 5105 .height = 90, 5106 }, 5107 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5108 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5109 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5110 }; 5111 5112 static const struct drm_display_mode mchp_ac69t88a_mode = { 5113 .clock = 25000, 5114 .hdisplay = 800, 5115 .hsync_start = 800 + 88, 5116 .hsync_end = 800 + 88 + 5, 5117 .htotal = 800 + 88 + 5 + 40, 5118 .vdisplay = 480, 5119 .vsync_start = 480 + 23, 5120 .vsync_end = 480 + 23 + 5, 5121 .vtotal = 480 + 23 + 5 + 1, 5122 }; 5123 5124 static const struct panel_desc mchp_ac69t88a = { 5125 .modes = &mchp_ac69t88a_mode, 5126 .num_modes = 1, 5127 .bpc = 8, 5128 .size = { 5129 .width = 108, 5130 .height = 65, 5131 }, 5132 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5135 }; 5136 5137 static const struct drm_display_mode arm_rtsm_mode[] = { 5138 { 5139 .clock = 65000, 5140 .hdisplay = 1024, 5141 .hsync_start = 1024 + 24, 5142 .hsync_end = 1024 + 24 + 136, 5143 .htotal = 1024 + 24 + 136 + 160, 5144 .vdisplay = 768, 5145 .vsync_start = 768 + 3, 5146 .vsync_end = 768 + 3 + 6, 5147 .vtotal = 768 + 3 + 6 + 29, 5148 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5149 }, 5150 }; 5151 5152 static const struct panel_desc arm_rtsm = { 5153 .modes = arm_rtsm_mode, 5154 .num_modes = 1, 5155 .bpc = 8, 5156 .size = { 5157 .width = 400, 5158 .height = 300, 5159 }, 5160 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5161 }; 5162 5163 static const struct of_device_id platform_of_match[] = { 5164 { 5165 .compatible = "ampire,am-1280800n3tzqw-t00h", 5166 .data = &ire_am_1280800n3tzqw_t00h, 5167 }, { 5168 .compatible = "ampire,am-480272h3tmqw-t01h", 5169 .data = &ire_am_480272h3tmqw_t01h, 5170 }, { 5171 .compatible = "ampire,am-800480l1tmqw-t00h", 5172 .data = &ire_am_800480l1tmqw_t00h, 5173 }, { 5174 .compatible = "ampire,am800480r3tmqwa1h", 5175 .data = &ire_am800480r3tmqwa1h, 5176 }, { 5177 .compatible = "ampire,am800600p5tmqw-tb8h", 5178 .data = &ire_am800600p5tmqwtb8h, 5179 }, { 5180 .compatible = "arm,rtsm-display", 5181 .data = &arm_rtsm, 5182 }, { 5183 .compatible = "armadeus,st0700-adapt", 5184 .data = &armadeus_st0700_adapt, 5185 }, { 5186 .compatible = "auo,b101aw03", 5187 .data = &auo_b101aw03, 5188 }, { 5189 .compatible = "auo,b101xtn01", 5190 .data = &auo_b101xtn01, 5191 }, { 5192 .compatible = "auo,b116xw03", 5193 .data = &auo_b116xw03, 5194 }, { 5195 .compatible = "auo,g070vvn01", 5196 .data = &auo_g070vvn01, 5197 }, { 5198 .compatible = "auo,g101evn010", 5199 .data = &auo_g101evn010, 5200 }, { 5201 .compatible = "auo,g104sn02", 5202 .data = &auo_g104sn02, 5203 }, { 5204 .compatible = "auo,g104stn01", 5205 .data = &auo_g104stn01, 5206 }, { 5207 .compatible = "auo,g121ean01", 5208 .data = &auo_g121ean01, 5209 }, { 5210 .compatible = "auo,g133han01", 5211 .data = &auo_g133han01, 5212 }, { 5213 .compatible = "auo,g156han04", 5214 .data = &auo_g156han04, 5215 }, { 5216 .compatible = "auo,g156xtn01", 5217 .data = &auo_g156xtn01, 5218 }, { 5219 .compatible = "auo,g185han01", 5220 .data = &auo_g185han01, 5221 }, { 5222 .compatible = "auo,g190ean01", 5223 .data = &auo_g190ean01, 5224 }, { 5225 .compatible = "auo,p238han01", 5226 .data = &auo_p238han01, 5227 }, { 5228 .compatible = "auo,p320hvn03", 5229 .data = &auo_p320hvn03, 5230 }, { 5231 .compatible = "auo,t215hvn01", 5232 .data = &auo_t215hvn01, 5233 }, { 5234 .compatible = "avic,tm070ddh03", 5235 .data = &avic_tm070ddh03, 5236 }, { 5237 .compatible = "bananapi,s070wv20-ct16", 5238 .data = &bananapi_s070wv20_ct16, 5239 }, { 5240 .compatible = "boe,av101hdt-a10", 5241 .data = &boe_av101hdt_a10, 5242 }, { 5243 .compatible = "boe,av123z7m-n17", 5244 .data = &boe_av123z7m_n17, 5245 }, { 5246 .compatible = "boe,bp082wx1-100", 5247 .data = &boe_bp082wx1_100, 5248 }, { 5249 .compatible = "boe,bp101wx1-100", 5250 .data = &boe_bp101wx1_100, 5251 }, { 5252 .compatible = "boe,ev121wxm-n10-1850", 5253 .data = &boe_ev121wxm_n10_1850, 5254 }, { 5255 .compatible = "boe,hv070wsa-100", 5256 .data = &boe_hv070wsa 5257 }, { 5258 .compatible = "cct,cmt430b19n00", 5259 .data = &cct_cmt430b19n00, 5260 }, { 5261 .compatible = "cdtech,s043wq26h-ct7", 5262 .data = &cdtech_s043wq26h_ct7, 5263 }, { 5264 .compatible = "cdtech,s070pws19hp-fc21", 5265 .data = &cdtech_s070pws19hp_fc21, 5266 }, { 5267 .compatible = "cdtech,s070swv29hg-dc44", 5268 .data = &cdtech_s070swv29hg_dc44, 5269 }, { 5270 .compatible = "cdtech,s070wv95-ct16", 5271 .data = &cdtech_s070wv95_ct16, 5272 }, { 5273 .compatible = "chefree,ch101olhlwh-002", 5274 .data = &chefree_ch101olhlwh_002, 5275 }, { 5276 .compatible = "chunghwa,claa070wp03xg", 5277 .data = &chunghwa_claa070wp03xg, 5278 }, { 5279 .compatible = "chunghwa,claa101wa01a", 5280 .data = &chunghwa_claa101wa01a 5281 }, { 5282 .compatible = "chunghwa,claa101wb01", 5283 .data = &chunghwa_claa101wb01 5284 }, { 5285 .compatible = "dataimage,fg040346dsswbg04", 5286 .data = &dataimage_fg040346dsswbg04, 5287 }, { 5288 .compatible = "dataimage,fg1001l0dsswmg01", 5289 .data = &dataimage_fg1001l0dsswmg01, 5290 }, { 5291 .compatible = "dataimage,scf0700c48ggu18", 5292 .data = &dataimage_scf0700c48ggu18, 5293 }, { 5294 .compatible = "dlc,dlc0700yzg-1", 5295 .data = &dlc_dlc0700yzg_1, 5296 }, { 5297 .compatible = "dlc,dlc1010gig", 5298 .data = &dlc_dlc1010gig, 5299 }, { 5300 .compatible = "edt,et035012dm6", 5301 .data = &edt_et035012dm6, 5302 }, { 5303 .compatible = "edt,etm0350g0dh6", 5304 .data = &edt_etm0350g0dh6, 5305 }, { 5306 .compatible = "edt,etm043080dh6gp", 5307 .data = &edt_etm043080dh6gp, 5308 }, { 5309 .compatible = "edt,etm0430g0dh6", 5310 .data = &edt_etm0430g0dh6, 5311 }, { 5312 .compatible = "edt,et057023udba", 5313 .data = &edt_et057023udba, 5314 }, { 5315 .compatible = "edt,et057090dhu", 5316 .data = &edt_et057090dhu, 5317 }, { 5318 .compatible = "edt,et070080dh6", 5319 .data = &edt_etm0700g0dh6, 5320 }, { 5321 .compatible = "edt,etm0700g0dh6", 5322 .data = &edt_etm0700g0dh6, 5323 }, { 5324 .compatible = "edt,etm0700g0bdh6", 5325 .data = &edt_etm0700g0bdh6, 5326 }, { 5327 .compatible = "edt,etm0700g0edh6", 5328 .data = &edt_etm0700g0bdh6, 5329 }, { 5330 .compatible = "edt,etml0700y5dha", 5331 .data = &edt_etml0700y5dha, 5332 }, { 5333 .compatible = "edt,etml1010g3dra", 5334 .data = &edt_etml1010g3dra, 5335 }, { 5336 .compatible = "edt,etmv570g2dhu", 5337 .data = &edt_etmv570g2dhu, 5338 }, { 5339 .compatible = "eink,vb3300-kca", 5340 .data = &eink_vb3300_kca, 5341 }, { 5342 .compatible = "evervision,vgg644804", 5343 .data = &evervision_vgg644804, 5344 }, { 5345 .compatible = "evervision,vgg804821", 5346 .data = &evervision_vgg804821, 5347 }, { 5348 .compatible = "foxlink,fl500wvr00-a0t", 5349 .data = &foxlink_fl500wvr00_a0t, 5350 }, { 5351 .compatible = "frida,frd350h54004", 5352 .data = &frida_frd350h54004, 5353 }, { 5354 .compatible = "giantplus,gpg482739qs5", 5355 .data = &giantplus_gpg482739qs5 5356 }, { 5357 .compatible = "giantplus,gpm940b0", 5358 .data = &giantplus_gpm940b0, 5359 }, { 5360 .compatible = "hannstar,hsd070pww1", 5361 .data = &hannstar_hsd070pww1, 5362 }, { 5363 .compatible = "hannstar,hsd100pxn1", 5364 .data = &hannstar_hsd100pxn1, 5365 }, { 5366 .compatible = "hannstar,hsd101pww2", 5367 .data = &hannstar_hsd101pww2, 5368 }, { 5369 .compatible = "hannstar,hsd156juw2", 5370 .data = &hannstar_hsd156juw2, 5371 }, { 5372 .compatible = "hit,tx23d38vm0caa", 5373 .data = &hitachi_tx23d38vm0caa 5374 }, { 5375 .compatible = "innolux,at043tn24", 5376 .data = &innolux_at043tn24, 5377 }, { 5378 .compatible = "innolux,at070tn92", 5379 .data = &innolux_at070tn92, 5380 }, { 5381 .compatible = "innolux,g070ace-l01", 5382 .data = &innolux_g070ace_l01, 5383 }, { 5384 .compatible = "innolux,g070ace-lh3", 5385 .data = &innolux_g070ace_lh3, 5386 }, { 5387 .compatible = "innolux,g070y2-l01", 5388 .data = &innolux_g070y2_l01, 5389 }, { 5390 .compatible = "innolux,g070y2-t02", 5391 .data = &innolux_g070y2_t02, 5392 }, { 5393 .compatible = "innolux,g101ice-l01", 5394 .data = &innolux_g101ice_l01 5395 }, { 5396 .compatible = "innolux,g121i1-l01", 5397 .data = &innolux_g121i1_l01 5398 }, { 5399 .compatible = "innolux,g121x1-l03", 5400 .data = &innolux_g121x1_l03, 5401 }, { 5402 .compatible = "innolux,g121xce-l01", 5403 .data = &innolux_g121xce_l01, 5404 }, { 5405 .compatible = "innolux,g150xge-l05", 5406 .data = &innolux_g150xge_l05, 5407 }, { 5408 .compatible = "innolux,g156hce-l01", 5409 .data = &innolux_g156hce_l01, 5410 }, { 5411 .compatible = "innolux,n156bge-l21", 5412 .data = &innolux_n156bge_l21, 5413 }, { 5414 .compatible = "innolux,zj070na-01p", 5415 .data = &innolux_zj070na_01p, 5416 }, { 5417 .compatible = "jutouch,jt101tm023", 5418 .data = &jutouch_jt101tm023, 5419 }, { 5420 .compatible = "koe,tx14d24vm1bpa", 5421 .data = &koe_tx14d24vm1bpa, 5422 }, { 5423 .compatible = "koe,tx26d202vm0bwa", 5424 .data = &koe_tx26d202vm0bwa, 5425 }, { 5426 .compatible = "koe,tx31d200vm0baa", 5427 .data = &koe_tx31d200vm0baa, 5428 }, { 5429 .compatible = "kyo,tcg121xglp", 5430 .data = &kyo_tcg121xglp, 5431 }, { 5432 .compatible = "lemaker,bl035-rgb-002", 5433 .data = &lemaker_bl035_rgb_002, 5434 }, { 5435 .compatible = "lg,lb070wv8", 5436 .data = &lg_lb070wv8, 5437 }, { 5438 .compatible = "lincolntech,lcd185-101ct", 5439 .data = &lincolntech_lcd185_101ct, 5440 }, { 5441 .compatible = "logicpd,type28", 5442 .data = &logicpd_type_28, 5443 }, { 5444 .compatible = "logictechno,lt161010-2nhc", 5445 .data = &logictechno_lt161010_2nh, 5446 }, { 5447 .compatible = "logictechno,lt161010-2nhr", 5448 .data = &logictechno_lt161010_2nh, 5449 }, { 5450 .compatible = "logictechno,lt170410-2whc", 5451 .data = &logictechno_lt170410_2whc, 5452 }, { 5453 .compatible = "logictechno,lttd800480070-l2rt", 5454 .data = &logictechno_lttd800480070_l2rt, 5455 }, { 5456 .compatible = "logictechno,lttd800480070-l6wh-rt", 5457 .data = &logictechno_lttd800480070_l6wh_rt, 5458 }, { 5459 .compatible = "microtips,mf-101hiebcaf0", 5460 .data = µtips_mf_101hiebcaf0_c, 5461 }, { 5462 .compatible = "microtips,mf-103hieb0ga0", 5463 .data = µtips_mf_103hieb0ga0, 5464 }, { 5465 .compatible = "mitsubishi,aa070mc01-ca1", 5466 .data = &mitsubishi_aa070mc01, 5467 }, { 5468 .compatible = "mitsubishi,aa084xe01", 5469 .data = &mitsubishi_aa084xe01, 5470 }, { 5471 .compatible = "multi-inno,mi0700a2t-30", 5472 .data = &multi_inno_mi0700a2t_30, 5473 }, { 5474 .compatible = "multi-inno,mi0700s4t-6", 5475 .data = &multi_inno_mi0700s4t_6, 5476 }, { 5477 .compatible = "multi-inno,mi0800ft-9", 5478 .data = &multi_inno_mi0800ft_9, 5479 }, { 5480 .compatible = "multi-inno,mi1010ait-1cp", 5481 .data = &multi_inno_mi1010ait_1cp, 5482 }, { 5483 .compatible = "multi-inno,mi1010z1t-1cp11", 5484 .data = &multi_inno_mi1010z1t_1cp11, 5485 }, { 5486 .compatible = "nec,nl12880bc20-05", 5487 .data = &nec_nl12880bc20_05, 5488 }, { 5489 .compatible = "nec,nl4827hc19-05b", 5490 .data = &nec_nl4827hc19_05b, 5491 }, { 5492 .compatible = "netron-dy,e231732", 5493 .data = &netron_dy_e231732, 5494 }, { 5495 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5496 .data = &newhaven_nhd_43_480272ef_atxl, 5497 }, { 5498 .compatible = "nlt,nl13676bc25-03f", 5499 .data = &nlt_nl13676bc25_03f, 5500 }, { 5501 .compatible = "nlt,nl192108ac18-02d", 5502 .data = &nlt_nl192108ac18_02d, 5503 }, { 5504 .compatible = "nvd,9128", 5505 .data = &nvd_9128, 5506 }, { 5507 .compatible = "okaya,rs800480t-7x0gp", 5508 .data = &okaya_rs800480t_7x0gp, 5509 }, { 5510 .compatible = "olimex,lcd-olinuxino-43-ts", 5511 .data = &olimex_lcd_olinuxino_43ts, 5512 }, { 5513 .compatible = "olimex,lcd-olinuxino-5-cts", 5514 .data = &olimex_lcd_olinuxino_5cts, 5515 }, { 5516 .compatible = "ontat,kd50g21-40nt-a1", 5517 .data = &ontat_kd50g21_40nt_a1, 5518 }, { 5519 .compatible = "ontat,yx700wv03", 5520 .data = &ontat_yx700wv03, 5521 }, { 5522 .compatible = "ortustech,com37h3m05dtc", 5523 .data = &ortustech_com37h3m, 5524 }, { 5525 .compatible = "ortustech,com37h3m99dtc", 5526 .data = &ortustech_com37h3m, 5527 }, { 5528 .compatible = "ortustech,com43h4m85ulc", 5529 .data = &ortustech_com43h4m85ulc, 5530 }, { 5531 .compatible = "osddisplays,osd070t1718-19ts", 5532 .data = &osddisplays_osd070t1718_19ts, 5533 }, { 5534 .compatible = "pda,91-00156-a0", 5535 .data = &pda_91_00156_a0, 5536 }, { 5537 .compatible = "powertip,ph128800t004-zza01", 5538 .data = &powertip_ph128800t004_zza01, 5539 }, { 5540 .compatible = "powertip,ph128800t006-zhc01", 5541 .data = &powertip_ph128800t006_zhc01, 5542 }, { 5543 .compatible = "powertip,ph800480t013-idf02", 5544 .data = &powertip_ph800480t013_idf02, 5545 }, { 5546 .compatible = "powertip,ph800480t032-zhc19", 5547 .data = &powertip_ph800480t032_zhc19, 5548 }, { 5549 .compatible = "primeview,pm070wl4", 5550 .data = &primeview_pm070wl4, 5551 }, { 5552 .compatible = "qiaodian,qd43003c0-40", 5553 .data = &qd43003c0_40, 5554 }, { 5555 .compatible = "qishenglong,gopher2b-lcd", 5556 .data = &qishenglong_gopher2b_lcd, 5557 }, { 5558 .compatible = "raystar,rff500f-awh-dnn", 5559 .data = &raystar_rff500f_awh_dnn, 5560 }, { 5561 .compatible = "rocktech,rk043fn48h", 5562 .data = &rocktech_rk043fn48h, 5563 }, { 5564 .compatible = "rocktech,rk070er9427", 5565 .data = &rocktech_rk070er9427, 5566 }, { 5567 .compatible = "rocktech,rk101ii01d-ct", 5568 .data = &rocktech_rk101ii01d_ct, 5569 }, { 5570 .compatible = "samsung,ltl101al01", 5571 .data = &samsung_ltl101al01, 5572 }, { 5573 .compatible = "samsung,ltl106al01", 5574 .data = &samsung_ltl106al01, 5575 }, { 5576 .compatible = "samsung,ltn101nt05", 5577 .data = &samsung_ltn101nt05, 5578 }, { 5579 .compatible = "satoz,sat050at40h12r2", 5580 .data = &satoz_sat050at40h12r2, 5581 }, { 5582 .compatible = "sharp,lq035q7db03", 5583 .data = &sharp_lq035q7db03, 5584 }, { 5585 .compatible = "sharp,lq070y3dg3b", 5586 .data = &sharp_lq070y3dg3b, 5587 }, { 5588 .compatible = "sharp,lq101k1ly04", 5589 .data = &sharp_lq101k1ly04, 5590 }, { 5591 .compatible = "sharp,ls020b1dd01d", 5592 .data = &sharp_ls020b1dd01d, 5593 }, { 5594 .compatible = "shelly,sca07010-bfn-lnn", 5595 .data = &shelly_sca07010_bfn_lnn, 5596 }, { 5597 .compatible = "starry,kr070pe2t", 5598 .data = &starry_kr070pe2t, 5599 }, { 5600 .compatible = "startek,kd070wvfpa", 5601 .data = &startek_kd070wvfpa, 5602 }, { 5603 .compatible = "team-source-display,tst043015cmhx", 5604 .data = &tsd_tst043015cmhx, 5605 }, { 5606 .compatible = "tfc,s9700rtwv43tr-01b", 5607 .data = &tfc_s9700rtwv43tr_01b, 5608 }, { 5609 .compatible = "tianma,p0700wxf1mbaa", 5610 .data = &tianma_p0700wxf1mbaa, 5611 }, { 5612 .compatible = "tianma,tm070jdhg30", 5613 .data = &tianma_tm070jdhg30, 5614 }, { 5615 .compatible = "tianma,tm070jdhg34-00", 5616 .data = &tianma_tm070jdhg34_00, 5617 }, { 5618 .compatible = "tianma,tm070jvhg33", 5619 .data = &tianma_tm070jvhg33, 5620 }, { 5621 .compatible = "tianma,tm070rvhg71", 5622 .data = &tianma_tm070rvhg71, 5623 }, { 5624 .compatible = "ti,nspire-cx-lcd-panel", 5625 .data = &ti_nspire_cx_lcd_panel, 5626 }, { 5627 .compatible = "ti,nspire-classic-lcd-panel", 5628 .data = &ti_nspire_classic_lcd_panel, 5629 }, { 5630 .compatible = "toshiba,lt089ac29000", 5631 .data = &toshiba_lt089ac29000, 5632 }, { 5633 .compatible = "topland,tian-g07017-01", 5634 .data = &topland_tian_g07017_01, 5635 }, { 5636 .compatible = "tpk,f07a-0102", 5637 .data = &tpk_f07a_0102, 5638 }, { 5639 .compatible = "tpk,f10a-0102", 5640 .data = &tpk_f10a_0102, 5641 }, { 5642 .compatible = "urt,umsh-8596md-t", 5643 .data = &urt_umsh_8596md_parallel, 5644 }, { 5645 .compatible = "urt,umsh-8596md-1t", 5646 .data = &urt_umsh_8596md_parallel, 5647 }, { 5648 .compatible = "urt,umsh-8596md-7t", 5649 .data = &urt_umsh_8596md_parallel, 5650 }, { 5651 .compatible = "urt,umsh-8596md-11t", 5652 .data = &urt_umsh_8596md_lvds, 5653 }, { 5654 .compatible = "urt,umsh-8596md-19t", 5655 .data = &urt_umsh_8596md_lvds, 5656 }, { 5657 .compatible = "urt,umsh-8596md-20t", 5658 .data = &urt_umsh_8596md_parallel, 5659 }, { 5660 .compatible = "vivax,tpc9150-panel", 5661 .data = &vivax_tpc9150_panel, 5662 }, { 5663 .compatible = "vxt,vl050-8048nt-c01", 5664 .data = &vl050_8048nt_c01, 5665 }, { 5666 .compatible = "waveshare,13.3inch-panel", 5667 .data = &waveshare_133inch, 5668 }, { 5669 .compatible = "winstar,wf35ltiacd", 5670 .data = &winstar_wf35ltiacd, 5671 }, { 5672 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5673 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5674 }, { 5675 .compatible = "microchip,ac69t88a", 5676 .data = &mchp_ac69t88a, 5677 }, { 5678 /* Must be the last entry */ 5679 .compatible = "panel-dpi", 5680 5681 /* 5682 * Explicitly NULL, the panel_desc structure will be 5683 * allocated by panel_dpi_probe(). 5684 */ 5685 .data = NULL, 5686 }, { 5687 /* sentinel */ 5688 } 5689 }; 5690 MODULE_DEVICE_TABLE(of, platform_of_match); 5691 5692 static int panel_simple_platform_probe(struct platform_device *pdev) 5693 { 5694 struct panel_simple *panel; 5695 5696 panel = panel_simple_probe(&pdev->dev); 5697 if (IS_ERR(panel)) 5698 return PTR_ERR(panel); 5699 5700 return 0; 5701 } 5702 5703 static void panel_simple_platform_remove(struct platform_device *pdev) 5704 { 5705 panel_simple_remove(&pdev->dev); 5706 } 5707 5708 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5709 { 5710 panel_simple_shutdown(&pdev->dev); 5711 } 5712 5713 static const struct dev_pm_ops panel_simple_pm_ops = { 5714 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5715 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5716 pm_runtime_force_resume) 5717 }; 5718 5719 static struct platform_driver panel_simple_platform_driver = { 5720 .driver = { 5721 .name = "panel-simple", 5722 .of_match_table = platform_of_match, 5723 .pm = &panel_simple_pm_ops, 5724 }, 5725 .probe = panel_simple_platform_probe, 5726 .remove = panel_simple_platform_remove, 5727 .shutdown = panel_simple_platform_shutdown, 5728 }; 5729 5730 static const struct drm_display_mode auo_b080uan01_mode = { 5731 .clock = 154500, 5732 .hdisplay = 1200, 5733 .hsync_start = 1200 + 62, 5734 .hsync_end = 1200 + 62 + 4, 5735 .htotal = 1200 + 62 + 4 + 62, 5736 .vdisplay = 1920, 5737 .vsync_start = 1920 + 9, 5738 .vsync_end = 1920 + 9 + 2, 5739 .vtotal = 1920 + 9 + 2 + 8, 5740 }; 5741 5742 static const struct panel_desc_dsi auo_b080uan01 = { 5743 .desc = { 5744 .modes = &auo_b080uan01_mode, 5745 .num_modes = 1, 5746 .bpc = 8, 5747 .size = { 5748 .width = 108, 5749 .height = 272, 5750 }, 5751 .connector_type = DRM_MODE_CONNECTOR_DSI, 5752 }, 5753 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5754 .format = MIPI_DSI_FMT_RGB888, 5755 .lanes = 4, 5756 }; 5757 5758 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5759 .clock = 160000, 5760 .hdisplay = 1200, 5761 .hsync_start = 1200 + 120, 5762 .hsync_end = 1200 + 120 + 20, 5763 .htotal = 1200 + 120 + 20 + 21, 5764 .vdisplay = 1920, 5765 .vsync_start = 1920 + 21, 5766 .vsync_end = 1920 + 21 + 3, 5767 .vtotal = 1920 + 21 + 3 + 18, 5768 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5769 }; 5770 5771 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5772 .desc = { 5773 .modes = &boe_tv080wum_nl0_mode, 5774 .num_modes = 1, 5775 .size = { 5776 .width = 107, 5777 .height = 172, 5778 }, 5779 .connector_type = DRM_MODE_CONNECTOR_DSI, 5780 }, 5781 .flags = MIPI_DSI_MODE_VIDEO | 5782 MIPI_DSI_MODE_VIDEO_BURST | 5783 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5784 .format = MIPI_DSI_FMT_RGB888, 5785 .lanes = 4, 5786 }; 5787 5788 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5789 .clock = 67000, 5790 .hdisplay = 720, 5791 .hsync_start = 720 + 12, 5792 .hsync_end = 720 + 12 + 4, 5793 .htotal = 720 + 12 + 4 + 112, 5794 .vdisplay = 1280, 5795 .vsync_start = 1280 + 8, 5796 .vsync_end = 1280 + 8 + 4, 5797 .vtotal = 1280 + 8 + 4 + 12, 5798 }; 5799 5800 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5801 .desc = { 5802 .modes = &lg_lh500wx1_sd03_mode, 5803 .num_modes = 1, 5804 .bpc = 8, 5805 .size = { 5806 .width = 62, 5807 .height = 110, 5808 }, 5809 .connector_type = DRM_MODE_CONNECTOR_DSI, 5810 }, 5811 .flags = MIPI_DSI_MODE_VIDEO, 5812 .format = MIPI_DSI_FMT_RGB888, 5813 .lanes = 4, 5814 }; 5815 5816 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5817 .clock = 157200, 5818 .hdisplay = 1920, 5819 .hsync_start = 1920 + 154, 5820 .hsync_end = 1920 + 154 + 16, 5821 .htotal = 1920 + 154 + 16 + 32, 5822 .vdisplay = 1200, 5823 .vsync_start = 1200 + 17, 5824 .vsync_end = 1200 + 17 + 2, 5825 .vtotal = 1200 + 17 + 2 + 16, 5826 }; 5827 5828 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5829 .desc = { 5830 .modes = &panasonic_vvx10f004b00_mode, 5831 .num_modes = 1, 5832 .bpc = 8, 5833 .size = { 5834 .width = 217, 5835 .height = 136, 5836 }, 5837 .connector_type = DRM_MODE_CONNECTOR_DSI, 5838 }, 5839 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5840 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5841 .format = MIPI_DSI_FMT_RGB888, 5842 .lanes = 4, 5843 }; 5844 5845 static const struct drm_display_mode lg_acx467akm_7_mode = { 5846 .clock = 150000, 5847 .hdisplay = 1080, 5848 .hsync_start = 1080 + 2, 5849 .hsync_end = 1080 + 2 + 2, 5850 .htotal = 1080 + 2 + 2 + 2, 5851 .vdisplay = 1920, 5852 .vsync_start = 1920 + 2, 5853 .vsync_end = 1920 + 2 + 2, 5854 .vtotal = 1920 + 2 + 2 + 2, 5855 }; 5856 5857 static const struct panel_desc_dsi lg_acx467akm_7 = { 5858 .desc = { 5859 .modes = &lg_acx467akm_7_mode, 5860 .num_modes = 1, 5861 .bpc = 8, 5862 .size = { 5863 .width = 62, 5864 .height = 110, 5865 }, 5866 .connector_type = DRM_MODE_CONNECTOR_DSI, 5867 }, 5868 .flags = 0, 5869 .format = MIPI_DSI_FMT_RGB888, 5870 .lanes = 4, 5871 }; 5872 5873 static const struct drm_display_mode osd101t2045_53ts_mode = { 5874 .clock = 154500, 5875 .hdisplay = 1920, 5876 .hsync_start = 1920 + 112, 5877 .hsync_end = 1920 + 112 + 16, 5878 .htotal = 1920 + 112 + 16 + 32, 5879 .vdisplay = 1200, 5880 .vsync_start = 1200 + 16, 5881 .vsync_end = 1200 + 16 + 2, 5882 .vtotal = 1200 + 16 + 2 + 16, 5883 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5884 }; 5885 5886 static const struct panel_desc_dsi osd101t2045_53ts = { 5887 .desc = { 5888 .modes = &osd101t2045_53ts_mode, 5889 .num_modes = 1, 5890 .bpc = 8, 5891 .size = { 5892 .width = 217, 5893 .height = 136, 5894 }, 5895 .connector_type = DRM_MODE_CONNECTOR_DSI, 5896 }, 5897 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5898 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5899 MIPI_DSI_MODE_NO_EOT_PACKET, 5900 .format = MIPI_DSI_FMT_RGB888, 5901 .lanes = 4, 5902 }; 5903 5904 static const struct of_device_id dsi_of_match[] = { 5905 { 5906 .compatible = "auo,b080uan01", 5907 .data = &auo_b080uan01 5908 }, { 5909 .compatible = "boe,tv080wum-nl0", 5910 .data = &boe_tv080wum_nl0 5911 }, { 5912 .compatible = "lg,lh500wx1-sd03", 5913 .data = &lg_lh500wx1_sd03 5914 }, { 5915 .compatible = "panasonic,vvx10f004b00", 5916 .data = &panasonic_vvx10f004b00 5917 }, { 5918 .compatible = "lg,acx467akm-7", 5919 .data = &lg_acx467akm_7 5920 }, { 5921 .compatible = "osddisplays,osd101t2045-53ts", 5922 .data = &osd101t2045_53ts 5923 }, { 5924 /* sentinel */ 5925 } 5926 }; 5927 MODULE_DEVICE_TABLE(of, dsi_of_match); 5928 5929 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5930 { 5931 const struct panel_desc_dsi *desc; 5932 struct panel_simple *panel; 5933 int err; 5934 5935 panel = panel_simple_probe(&dsi->dev); 5936 if (IS_ERR(panel)) 5937 return PTR_ERR(panel); 5938 5939 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5940 dsi->mode_flags = desc->flags; 5941 dsi->format = desc->format; 5942 dsi->lanes = desc->lanes; 5943 5944 err = mipi_dsi_attach(dsi); 5945 if (err) { 5946 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5947 5948 drm_panel_remove(&panel->base); 5949 } 5950 5951 return err; 5952 } 5953 5954 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5955 { 5956 int err; 5957 5958 err = mipi_dsi_detach(dsi); 5959 if (err < 0) 5960 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5961 5962 panel_simple_remove(&dsi->dev); 5963 } 5964 5965 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5966 { 5967 panel_simple_shutdown(&dsi->dev); 5968 } 5969 5970 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5971 .driver = { 5972 .name = "panel-simple-dsi", 5973 .of_match_table = dsi_of_match, 5974 .pm = &panel_simple_pm_ops, 5975 }, 5976 .probe = panel_simple_dsi_probe, 5977 .remove = panel_simple_dsi_remove, 5978 .shutdown = panel_simple_dsi_shutdown, 5979 }; 5980 5981 static int __init panel_simple_init(void) 5982 { 5983 int err; 5984 5985 err = platform_driver_register(&panel_simple_platform_driver); 5986 if (err < 0) 5987 return err; 5988 5989 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5990 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5991 if (err < 0) 5992 goto err_did_platform_register; 5993 } 5994 5995 return 0; 5996 5997 err_did_platform_register: 5998 platform_driver_unregister(&panel_simple_platform_driver); 5999 6000 return err; 6001 } 6002 module_init(panel_simple_init); 6003 6004 static void __exit panel_simple_exit(void) 6005 { 6006 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6007 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 6008 6009 platform_driver_unregister(&panel_simple_platform_driver); 6010 } 6011 module_exit(panel_simple_exit); 6012 6013 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 6014 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 6015 MODULE_LICENSE("GPL and additional rights"); 6016