1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 bool enabled; 142 143 bool prepared; 144 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 const struct drm_edid *drm_edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 drm_edid_free(p->drm_edid); 313 p->drm_edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->drm_edid) 403 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 404 405 drm_edid_connector_update(connector, p->drm_edid); 406 407 num += drm_edid_connector_add_modes(connector); 408 409 pm_runtime_mark_last_busy(panel->dev); 410 pm_runtime_put_autosuspend(panel->dev); 411 } 412 413 /* add hard-coded panel modes */ 414 num += panel_simple_get_non_edid_modes(p, connector); 415 416 /* 417 * TODO: Remove once all drm drivers call 418 * drm_connector_set_orientation_from_panel() 419 */ 420 drm_connector_set_panel_orientation(connector, p->orientation); 421 422 return num; 423 } 424 425 static int panel_simple_get_timings(struct drm_panel *panel, 426 unsigned int num_timings, 427 struct display_timing *timings) 428 { 429 struct panel_simple *p = to_panel_simple(panel); 430 unsigned int i; 431 432 if (p->desc->num_timings < num_timings) 433 num_timings = p->desc->num_timings; 434 435 if (timings) 436 for (i = 0; i < num_timings; i++) 437 timings[i] = p->desc->timings[i]; 438 439 return p->desc->num_timings; 440 } 441 442 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 443 { 444 struct panel_simple *p = to_panel_simple(panel); 445 446 return p->orientation; 447 } 448 449 static const struct drm_panel_funcs panel_simple_funcs = { 450 .disable = panel_simple_disable, 451 .unprepare = panel_simple_unprepare, 452 .prepare = panel_simple_prepare, 453 .enable = panel_simple_enable, 454 .get_modes = panel_simple_get_modes, 455 .get_orientation = panel_simple_get_orientation, 456 .get_timings = panel_simple_get_timings, 457 }; 458 459 static struct panel_desc panel_dpi; 460 461 static int panel_dpi_probe(struct device *dev, 462 struct panel_simple *panel) 463 { 464 struct display_timing *timing; 465 const struct device_node *np; 466 struct panel_desc *desc; 467 unsigned int bus_flags; 468 struct videomode vm; 469 int ret; 470 471 np = dev->of_node; 472 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 473 if (!desc) 474 return -ENOMEM; 475 476 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 477 if (!timing) 478 return -ENOMEM; 479 480 ret = of_get_display_timing(np, "panel-timing", timing); 481 if (ret < 0) { 482 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 483 np); 484 return ret; 485 } 486 487 desc->timings = timing; 488 desc->num_timings = 1; 489 490 of_property_read_u32(np, "width-mm", &desc->size.width); 491 of_property_read_u32(np, "height-mm", &desc->size.height); 492 493 /* Extract bus_flags from display_timing */ 494 bus_flags = 0; 495 vm.flags = timing->flags; 496 drm_bus_flags_from_videomode(&vm, &bus_flags); 497 desc->bus_flags = bus_flags; 498 499 /* We do not know the connector for the DT node, so guess it */ 500 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 501 502 panel->desc = desc; 503 504 return 0; 505 } 506 507 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 508 (to_check->field.typ >= bounds->field.min && \ 509 to_check->field.typ <= bounds->field.max) 510 static void panel_simple_parse_panel_timing_node(struct device *dev, 511 struct panel_simple *panel, 512 const struct display_timing *ot) 513 { 514 const struct panel_desc *desc = panel->desc; 515 struct videomode vm; 516 unsigned int i; 517 518 if (WARN_ON(desc->num_modes)) { 519 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 520 return; 521 } 522 if (WARN_ON(!desc->num_timings)) { 523 dev_err(dev, "Reject override mode: no timings specified\n"); 524 return; 525 } 526 527 for (i = 0; i < panel->desc->num_timings; i++) { 528 const struct display_timing *dt = &panel->desc->timings[i]; 529 530 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 538 continue; 539 540 if (ot->flags != dt->flags) 541 continue; 542 543 videomode_from_timing(ot, &vm); 544 drm_display_mode_from_videomode(&vm, &panel->override_mode); 545 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 546 DRM_MODE_TYPE_PREFERRED; 547 break; 548 } 549 550 if (WARN_ON(!panel->override_mode.type)) 551 dev_err(dev, "Reject override mode: No display_timing found\n"); 552 } 553 554 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 555 struct panel_simple *panel) 556 { 557 int ret, bpc; 558 559 ret = drm_of_lvds_get_data_mapping(dev->of_node); 560 if (ret < 0) { 561 if (ret == -EINVAL) 562 dev_warn(dev, "Ignore invalid data-mapping property\n"); 563 564 /* 565 * Ignore non-existing or malformatted property, fallback to 566 * default data-mapping, and return 0. 567 */ 568 return 0; 569 } 570 571 switch (ret) { 572 default: 573 WARN_ON(1); 574 fallthrough; 575 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 576 fallthrough; 577 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 578 bpc = 8; 579 break; 580 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 581 bpc = 6; 582 } 583 584 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 585 struct panel_desc *override_desc; 586 587 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 588 if (!override_desc) 589 return -ENOMEM; 590 591 override_desc->bus_format = ret; 592 override_desc->bpc = bpc; 593 panel->desc = override_desc; 594 } 595 596 return 0; 597 } 598 599 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 600 { 601 struct panel_simple *panel; 602 struct display_timing dt; 603 struct device_node *ddc; 604 int connector_type; 605 u32 bus_flags; 606 int err; 607 608 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 609 if (!panel) 610 return -ENOMEM; 611 612 panel->enabled = false; 613 panel->desc = desc; 614 615 panel->supply = devm_regulator_get(dev, "power"); 616 if (IS_ERR(panel->supply)) 617 return PTR_ERR(panel->supply); 618 619 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 620 GPIOD_OUT_LOW); 621 if (IS_ERR(panel->enable_gpio)) 622 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 623 "failed to request GPIO\n"); 624 625 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 626 if (err) { 627 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 628 return err; 629 } 630 631 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 632 if (ddc) { 633 panel->ddc = of_find_i2c_adapter_by_node(ddc); 634 of_node_put(ddc); 635 636 if (!panel->ddc) 637 return -EPROBE_DEFER; 638 } 639 640 if (desc == &panel_dpi) { 641 /* Handle the generic panel-dpi binding */ 642 err = panel_dpi_probe(dev, panel); 643 if (err) 644 goto free_ddc; 645 desc = panel->desc; 646 } else { 647 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 648 panel_simple_parse_panel_timing_node(dev, panel, &dt); 649 } 650 651 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 652 /* Optional data-mapping property for overriding bus format */ 653 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 654 if (err) 655 goto free_ddc; 656 } 657 658 connector_type = desc->connector_type; 659 /* Catch common mistakes for panels. */ 660 switch (connector_type) { 661 case 0: 662 dev_warn(dev, "Specify missing connector_type\n"); 663 connector_type = DRM_MODE_CONNECTOR_DPI; 664 break; 665 case DRM_MODE_CONNECTOR_LVDS: 666 WARN_ON(desc->bus_flags & 667 ~(DRM_BUS_FLAG_DE_LOW | 668 DRM_BUS_FLAG_DE_HIGH | 669 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 670 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 671 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 673 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 674 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 675 desc->bpc != 6); 676 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 677 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 678 desc->bpc != 8); 679 break; 680 case DRM_MODE_CONNECTOR_eDP: 681 dev_warn(dev, "eDP panels moved to panel-edp\n"); 682 err = -EINVAL; 683 goto free_ddc; 684 case DRM_MODE_CONNECTOR_DSI: 685 if (desc->bpc != 6 && desc->bpc != 8) 686 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 687 break; 688 case DRM_MODE_CONNECTOR_DPI: 689 bus_flags = DRM_BUS_FLAG_DE_LOW | 690 DRM_BUS_FLAG_DE_HIGH | 691 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 692 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 693 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 694 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 695 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 696 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 697 if (desc->bus_flags & ~bus_flags) 698 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 699 if (!(desc->bus_flags & bus_flags)) 700 dev_warn(dev, "Specify missing bus_flags\n"); 701 if (desc->bus_format == 0) 702 dev_warn(dev, "Specify missing bus_format\n"); 703 if (desc->bpc != 6 && desc->bpc != 8) 704 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 705 break; 706 default: 707 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 708 connector_type = DRM_MODE_CONNECTOR_DPI; 709 break; 710 } 711 712 dev_set_drvdata(dev, panel); 713 714 /* 715 * We use runtime PM for prepare / unprepare since those power the panel 716 * on and off and those can be very slow operations. This is important 717 * to optimize powering the panel on briefly to read the EDID before 718 * fully enabling the panel. 719 */ 720 pm_runtime_enable(dev); 721 pm_runtime_set_autosuspend_delay(dev, 1000); 722 pm_runtime_use_autosuspend(dev); 723 724 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 725 726 err = drm_panel_of_backlight(&panel->base); 727 if (err) { 728 dev_err_probe(dev, err, "Could not find backlight\n"); 729 goto disable_pm_runtime; 730 } 731 732 drm_panel_add(&panel->base); 733 734 return 0; 735 736 disable_pm_runtime: 737 pm_runtime_dont_use_autosuspend(dev); 738 pm_runtime_disable(dev); 739 free_ddc: 740 if (panel->ddc) 741 put_device(&panel->ddc->dev); 742 743 return err; 744 } 745 746 static void panel_simple_remove(struct device *dev) 747 { 748 struct panel_simple *panel = dev_get_drvdata(dev); 749 750 drm_panel_remove(&panel->base); 751 drm_panel_disable(&panel->base); 752 drm_panel_unprepare(&panel->base); 753 754 pm_runtime_dont_use_autosuspend(dev); 755 pm_runtime_disable(dev); 756 if (panel->ddc) 757 put_device(&panel->ddc->dev); 758 } 759 760 static void panel_simple_shutdown(struct device *dev) 761 { 762 struct panel_simple *panel = dev_get_drvdata(dev); 763 764 drm_panel_disable(&panel->base); 765 drm_panel_unprepare(&panel->base); 766 } 767 768 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 769 .clock = 71100, 770 .hdisplay = 1280, 771 .hsync_start = 1280 + 40, 772 .hsync_end = 1280 + 40 + 80, 773 .htotal = 1280 + 40 + 80 + 40, 774 .vdisplay = 800, 775 .vsync_start = 800 + 3, 776 .vsync_end = 800 + 3 + 10, 777 .vtotal = 800 + 3 + 10 + 10, 778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 779 }; 780 781 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 782 .modes = &ire_am_1280800n3tzqw_t00h_mode, 783 .num_modes = 1, 784 .bpc = 8, 785 .size = { 786 .width = 217, 787 .height = 136, 788 }, 789 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 790 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 791 .connector_type = DRM_MODE_CONNECTOR_LVDS, 792 }; 793 794 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 795 .clock = 9000, 796 .hdisplay = 480, 797 .hsync_start = 480 + 2, 798 .hsync_end = 480 + 2 + 41, 799 .htotal = 480 + 2 + 41 + 2, 800 .vdisplay = 272, 801 .vsync_start = 272 + 2, 802 .vsync_end = 272 + 2 + 10, 803 .vtotal = 272 + 2 + 10 + 2, 804 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 805 }; 806 807 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 808 .modes = &ire_am_480272h3tmqw_t01h_mode, 809 .num_modes = 1, 810 .bpc = 8, 811 .size = { 812 .width = 99, 813 .height = 58, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 816 }; 817 818 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 819 .clock = 33333, 820 .hdisplay = 800, 821 .hsync_start = 800 + 0, 822 .hsync_end = 800 + 0 + 255, 823 .htotal = 800 + 0 + 255 + 0, 824 .vdisplay = 480, 825 .vsync_start = 480 + 2, 826 .vsync_end = 480 + 2 + 45, 827 .vtotal = 480 + 2 + 45 + 0, 828 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 829 }; 830 831 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 832 .pixelclock = { 29930000, 33260000, 36590000 }, 833 .hactive = { 800, 800, 800 }, 834 .hfront_porch = { 1, 40, 168 }, 835 .hback_porch = { 88, 88, 88 }, 836 .hsync_len = { 1, 128, 128 }, 837 .vactive = { 480, 480, 480 }, 838 .vfront_porch = { 1, 35, 37 }, 839 .vback_porch = { 8, 8, 8 }, 840 .vsync_len = { 1, 2, 2 }, 841 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 842 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 843 DISPLAY_FLAGS_SYNC_POSEDGE, 844 }; 845 846 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 847 .timings = &ire_am_800480l1tmqw_t00h_timing, 848 .num_timings = 1, 849 .bpc = 8, 850 .size = { 851 .width = 111, 852 .height = 67, 853 }, 854 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 855 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 856 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 857 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 858 .connector_type = DRM_MODE_CONNECTOR_DPI, 859 }; 860 861 static const struct panel_desc ampire_am800480r3tmqwa1h = { 862 .modes = &ire_am800480r3tmqwa1h_mode, 863 .num_modes = 1, 864 .bpc = 6, 865 .size = { 866 .width = 152, 867 .height = 91, 868 }, 869 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 870 }; 871 872 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 873 .pixelclock = { 34500000, 39600000, 50400000 }, 874 .hactive = { 800, 800, 800 }, 875 .hfront_porch = { 12, 112, 312 }, 876 .hback_porch = { 87, 87, 48 }, 877 .hsync_len = { 1, 1, 40 }, 878 .vactive = { 600, 600, 600 }, 879 .vfront_porch = { 1, 21, 61 }, 880 .vback_porch = { 38, 38, 19 }, 881 .vsync_len = { 1, 1, 20 }, 882 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 883 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 884 DISPLAY_FLAGS_SYNC_POSEDGE, 885 }; 886 887 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 888 .timings = &ire_am800600p5tmqw_tb8h_timing, 889 .num_timings = 1, 890 .bpc = 6, 891 .size = { 892 .width = 162, 893 .height = 122, 894 }, 895 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 896 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 897 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 898 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 899 .connector_type = DRM_MODE_CONNECTOR_DPI, 900 }; 901 902 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 903 .pixelclock = { 26400000, 33300000, 46800000 }, 904 .hactive = { 800, 800, 800 }, 905 .hfront_porch = { 16, 210, 354 }, 906 .hback_porch = { 45, 36, 6 }, 907 .hsync_len = { 1, 10, 40 }, 908 .vactive = { 480, 480, 480 }, 909 .vfront_porch = { 7, 22, 147 }, 910 .vback_porch = { 22, 13, 3 }, 911 .vsync_len = { 1, 10, 20 }, 912 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 913 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 914 }; 915 916 static const struct panel_desc armadeus_st0700_adapt = { 917 .timings = &santek_st0700i5y_rbslw_f_timing, 918 .num_timings = 1, 919 .bpc = 6, 920 .size = { 921 .width = 154, 922 .height = 86, 923 }, 924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 926 }; 927 928 static const struct drm_display_mode auo_b101aw03_mode = { 929 .clock = 51450, 930 .hdisplay = 1024, 931 .hsync_start = 1024 + 156, 932 .hsync_end = 1024 + 156 + 8, 933 .htotal = 1024 + 156 + 8 + 156, 934 .vdisplay = 600, 935 .vsync_start = 600 + 16, 936 .vsync_end = 600 + 16 + 6, 937 .vtotal = 600 + 16 + 6 + 16, 938 }; 939 940 static const struct panel_desc auo_b101aw03 = { 941 .modes = &auo_b101aw03_mode, 942 .num_modes = 1, 943 .bpc = 6, 944 .size = { 945 .width = 223, 946 .height = 125, 947 }, 948 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 949 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 950 .connector_type = DRM_MODE_CONNECTOR_LVDS, 951 }; 952 953 static const struct drm_display_mode auo_b101xtn01_mode = { 954 .clock = 72000, 955 .hdisplay = 1366, 956 .hsync_start = 1366 + 20, 957 .hsync_end = 1366 + 20 + 70, 958 .htotal = 1366 + 20 + 70, 959 .vdisplay = 768, 960 .vsync_start = 768 + 14, 961 .vsync_end = 768 + 14 + 42, 962 .vtotal = 768 + 14 + 42, 963 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 964 }; 965 966 static const struct panel_desc auo_b101xtn01 = { 967 .modes = &auo_b101xtn01_mode, 968 .num_modes = 1, 969 .bpc = 6, 970 .size = { 971 .width = 223, 972 .height = 125, 973 }, 974 }; 975 976 static const struct drm_display_mode auo_b116xw03_mode = { 977 .clock = 70589, 978 .hdisplay = 1366, 979 .hsync_start = 1366 + 40, 980 .hsync_end = 1366 + 40 + 40, 981 .htotal = 1366 + 40 + 40 + 32, 982 .vdisplay = 768, 983 .vsync_start = 768 + 10, 984 .vsync_end = 768 + 10 + 12, 985 .vtotal = 768 + 10 + 12 + 6, 986 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 987 }; 988 989 static const struct panel_desc auo_b116xw03 = { 990 .modes = &auo_b116xw03_mode, 991 .num_modes = 1, 992 .bpc = 6, 993 .size = { 994 .width = 256, 995 .height = 144, 996 }, 997 .delay = { 998 .prepare = 1, 999 .enable = 200, 1000 .disable = 200, 1001 .unprepare = 500, 1002 }, 1003 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1004 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1005 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1006 }; 1007 1008 static const struct display_timing auo_g070vvn01_timings = { 1009 .pixelclock = { 33300000, 34209000, 45000000 }, 1010 .hactive = { 800, 800, 800 }, 1011 .hfront_porch = { 20, 40, 200 }, 1012 .hback_porch = { 87, 40, 1 }, 1013 .hsync_len = { 1, 48, 87 }, 1014 .vactive = { 480, 480, 480 }, 1015 .vfront_porch = { 5, 13, 200 }, 1016 .vback_porch = { 31, 31, 29 }, 1017 .vsync_len = { 1, 1, 3 }, 1018 }; 1019 1020 static const struct panel_desc auo_g070vvn01 = { 1021 .timings = &auo_g070vvn01_timings, 1022 .num_timings = 1, 1023 .bpc = 8, 1024 .size = { 1025 .width = 152, 1026 .height = 91, 1027 }, 1028 .delay = { 1029 .prepare = 200, 1030 .enable = 50, 1031 .disable = 50, 1032 .unprepare = 1000, 1033 }, 1034 }; 1035 1036 static const struct drm_display_mode auo_g101evn010_mode = { 1037 .clock = 68930, 1038 .hdisplay = 1280, 1039 .hsync_start = 1280 + 82, 1040 .hsync_end = 1280 + 82 + 2, 1041 .htotal = 1280 + 82 + 2 + 84, 1042 .vdisplay = 800, 1043 .vsync_start = 800 + 8, 1044 .vsync_end = 800 + 8 + 2, 1045 .vtotal = 800 + 8 + 2 + 6, 1046 }; 1047 1048 static const struct panel_desc auo_g101evn010 = { 1049 .modes = &auo_g101evn010_mode, 1050 .num_modes = 1, 1051 .bpc = 6, 1052 .size = { 1053 .width = 216, 1054 .height = 135, 1055 }, 1056 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1057 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1058 }; 1059 1060 static const struct drm_display_mode auo_g104sn02_mode = { 1061 .clock = 40000, 1062 .hdisplay = 800, 1063 .hsync_start = 800 + 40, 1064 .hsync_end = 800 + 40 + 216, 1065 .htotal = 800 + 40 + 216 + 128, 1066 .vdisplay = 600, 1067 .vsync_start = 600 + 10, 1068 .vsync_end = 600 + 10 + 35, 1069 .vtotal = 600 + 10 + 35 + 2, 1070 }; 1071 1072 static const struct panel_desc auo_g104sn02 = { 1073 .modes = &auo_g104sn02_mode, 1074 .num_modes = 1, 1075 .bpc = 8, 1076 .size = { 1077 .width = 211, 1078 .height = 158, 1079 }, 1080 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1081 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1082 }; 1083 1084 static const struct display_timing auo_g121ean01_timing = { 1085 .pixelclock = { 60000000, 74400000, 90000000 }, 1086 .hactive = { 1280, 1280, 1280 }, 1087 .hfront_porch = { 20, 50, 100 }, 1088 .hback_porch = { 20, 50, 100 }, 1089 .hsync_len = { 30, 100, 200 }, 1090 .vactive = { 800, 800, 800 }, 1091 .vfront_porch = { 2, 10, 25 }, 1092 .vback_porch = { 2, 10, 25 }, 1093 .vsync_len = { 4, 18, 50 }, 1094 }; 1095 1096 static const struct panel_desc auo_g121ean01 = { 1097 .timings = &auo_g121ean01_timing, 1098 .num_timings = 1, 1099 .bpc = 8, 1100 .size = { 1101 .width = 261, 1102 .height = 163, 1103 }, 1104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1106 }; 1107 1108 static const struct display_timing auo_g133han01_timings = { 1109 .pixelclock = { 134000000, 141200000, 149000000 }, 1110 .hactive = { 1920, 1920, 1920 }, 1111 .hfront_porch = { 39, 58, 77 }, 1112 .hback_porch = { 59, 88, 117 }, 1113 .hsync_len = { 28, 42, 56 }, 1114 .vactive = { 1080, 1080, 1080 }, 1115 .vfront_porch = { 3, 8, 11 }, 1116 .vback_porch = { 5, 14, 19 }, 1117 .vsync_len = { 4, 14, 19 }, 1118 }; 1119 1120 static const struct panel_desc auo_g133han01 = { 1121 .timings = &auo_g133han01_timings, 1122 .num_timings = 1, 1123 .bpc = 8, 1124 .size = { 1125 .width = 293, 1126 .height = 165, 1127 }, 1128 .delay = { 1129 .prepare = 200, 1130 .enable = 50, 1131 .disable = 50, 1132 .unprepare = 1000, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136 }; 1137 1138 static const struct display_timing auo_g156han04_timings = { 1139 .pixelclock = { 137000000, 141000000, 146000000 }, 1140 .hactive = { 1920, 1920, 1920 }, 1141 .hfront_porch = { 60, 60, 60 }, 1142 .hback_porch = { 90, 92, 111 }, 1143 .hsync_len = { 32, 32, 32 }, 1144 .vactive = { 1080, 1080, 1080 }, 1145 .vfront_porch = { 12, 12, 12 }, 1146 .vback_porch = { 24, 36, 56 }, 1147 .vsync_len = { 8, 8, 8 }, 1148 }; 1149 1150 static const struct panel_desc auo_g156han04 = { 1151 .timings = &auo_g156han04_timings, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 344, 1156 .height = 194, 1157 }, 1158 .delay = { 1159 .prepare = 50, /* T2 */ 1160 .enable = 200, /* T3 */ 1161 .disable = 110, /* T10 */ 1162 .unprepare = 1000, /* T13 */ 1163 }, 1164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1165 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1166 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1167 }; 1168 1169 static const struct drm_display_mode auo_g156xtn01_mode = { 1170 .clock = 76000, 1171 .hdisplay = 1366, 1172 .hsync_start = 1366 + 33, 1173 .hsync_end = 1366 + 33 + 67, 1174 .htotal = 1560, 1175 .vdisplay = 768, 1176 .vsync_start = 768 + 4, 1177 .vsync_end = 768 + 4 + 4, 1178 .vtotal = 806, 1179 }; 1180 1181 static const struct panel_desc auo_g156xtn01 = { 1182 .modes = &auo_g156xtn01_mode, 1183 .num_modes = 1, 1184 .bpc = 8, 1185 .size = { 1186 .width = 344, 1187 .height = 194, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1191 }; 1192 1193 static const struct display_timing auo_g185han01_timings = { 1194 .pixelclock = { 120000000, 144000000, 175000000 }, 1195 .hactive = { 1920, 1920, 1920 }, 1196 .hfront_porch = { 36, 120, 148 }, 1197 .hback_porch = { 24, 88, 108 }, 1198 .hsync_len = { 20, 48, 64 }, 1199 .vactive = { 1080, 1080, 1080 }, 1200 .vfront_porch = { 6, 10, 40 }, 1201 .vback_porch = { 2, 5, 20 }, 1202 .vsync_len = { 2, 5, 20 }, 1203 }; 1204 1205 static const struct panel_desc auo_g185han01 = { 1206 .timings = &auo_g185han01_timings, 1207 .num_timings = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 409, 1211 .height = 230, 1212 }, 1213 .delay = { 1214 .prepare = 50, 1215 .enable = 200, 1216 .disable = 110, 1217 .unprepare = 1000, 1218 }, 1219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1221 }; 1222 1223 static const struct display_timing auo_g190ean01_timings = { 1224 .pixelclock = { 90000000, 108000000, 135000000 }, 1225 .hactive = { 1280, 1280, 1280 }, 1226 .hfront_porch = { 126, 184, 1266 }, 1227 .hback_porch = { 84, 122, 844 }, 1228 .hsync_len = { 70, 102, 704 }, 1229 .vactive = { 1024, 1024, 1024 }, 1230 .vfront_porch = { 4, 26, 76 }, 1231 .vback_porch = { 2, 8, 25 }, 1232 .vsync_len = { 2, 8, 25 }, 1233 }; 1234 1235 static const struct panel_desc auo_g190ean01 = { 1236 .timings = &auo_g190ean01_timings, 1237 .num_timings = 1, 1238 .bpc = 8, 1239 .size = { 1240 .width = 376, 1241 .height = 301, 1242 }, 1243 .delay = { 1244 .prepare = 50, 1245 .enable = 200, 1246 .disable = 110, 1247 .unprepare = 1000, 1248 }, 1249 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1250 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1251 }; 1252 1253 static const struct display_timing auo_p320hvn03_timings = { 1254 .pixelclock = { 106000000, 148500000, 164000000 }, 1255 .hactive = { 1920, 1920, 1920 }, 1256 .hfront_porch = { 25, 50, 130 }, 1257 .hback_porch = { 25, 50, 130 }, 1258 .hsync_len = { 20, 40, 105 }, 1259 .vactive = { 1080, 1080, 1080 }, 1260 .vfront_porch = { 8, 17, 150 }, 1261 .vback_porch = { 8, 17, 150 }, 1262 .vsync_len = { 4, 11, 100 }, 1263 }; 1264 1265 static const struct panel_desc auo_p320hvn03 = { 1266 .timings = &auo_p320hvn03_timings, 1267 .num_timings = 1, 1268 .bpc = 8, 1269 .size = { 1270 .width = 698, 1271 .height = 393, 1272 }, 1273 .delay = { 1274 .prepare = 1, 1275 .enable = 450, 1276 .unprepare = 500, 1277 }, 1278 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1279 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1280 }; 1281 1282 static const struct drm_display_mode auo_t215hvn01_mode = { 1283 .clock = 148800, 1284 .hdisplay = 1920, 1285 .hsync_start = 1920 + 88, 1286 .hsync_end = 1920 + 88 + 44, 1287 .htotal = 1920 + 88 + 44 + 148, 1288 .vdisplay = 1080, 1289 .vsync_start = 1080 + 4, 1290 .vsync_end = 1080 + 4 + 5, 1291 .vtotal = 1080 + 4 + 5 + 36, 1292 }; 1293 1294 static const struct panel_desc auo_t215hvn01 = { 1295 .modes = &auo_t215hvn01_mode, 1296 .num_modes = 1, 1297 .bpc = 8, 1298 .size = { 1299 .width = 430, 1300 .height = 270, 1301 }, 1302 .delay = { 1303 .disable = 5, 1304 .unprepare = 1000, 1305 }, 1306 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1307 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1308 }; 1309 1310 static const struct drm_display_mode avic_tm070ddh03_mode = { 1311 .clock = 51200, 1312 .hdisplay = 1024, 1313 .hsync_start = 1024 + 160, 1314 .hsync_end = 1024 + 160 + 4, 1315 .htotal = 1024 + 160 + 4 + 156, 1316 .vdisplay = 600, 1317 .vsync_start = 600 + 17, 1318 .vsync_end = 600 + 17 + 1, 1319 .vtotal = 600 + 17 + 1 + 17, 1320 }; 1321 1322 static const struct panel_desc avic_tm070ddh03 = { 1323 .modes = &avic_tm070ddh03_mode, 1324 .num_modes = 1, 1325 .bpc = 8, 1326 .size = { 1327 .width = 154, 1328 .height = 90, 1329 }, 1330 .delay = { 1331 .prepare = 20, 1332 .enable = 200, 1333 .disable = 200, 1334 }, 1335 }; 1336 1337 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1338 .clock = 30000, 1339 .hdisplay = 800, 1340 .hsync_start = 800 + 40, 1341 .hsync_end = 800 + 40 + 48, 1342 .htotal = 800 + 40 + 48 + 40, 1343 .vdisplay = 480, 1344 .vsync_start = 480 + 13, 1345 .vsync_end = 480 + 13 + 3, 1346 .vtotal = 480 + 13 + 3 + 29, 1347 }; 1348 1349 static const struct panel_desc bananapi_s070wv20_ct16 = { 1350 .modes = &bananapi_s070wv20_ct16_mode, 1351 .num_modes = 1, 1352 .bpc = 6, 1353 .size = { 1354 .width = 154, 1355 .height = 86, 1356 }, 1357 }; 1358 1359 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1360 .clock = 78945, 1361 .hdisplay = 1280, 1362 .hsync_start = 1280 + 0, 1363 .hsync_end = 1280 + 0 + 2, 1364 .htotal = 1280 + 62 + 0 + 2, 1365 .vdisplay = 800, 1366 .vsync_start = 800 + 8, 1367 .vsync_end = 800 + 8 + 2, 1368 .vtotal = 800 + 6 + 8 + 2, 1369 }; 1370 1371 static const struct panel_desc boe_bp082wx1_100 = { 1372 .modes = &boe_bp101wx1_100_mode, 1373 .num_modes = 1, 1374 .bpc = 8, 1375 .size = { 1376 .width = 177, 1377 .height = 110, 1378 }, 1379 .delay = { 1380 .enable = 50, 1381 .disable = 50, 1382 }, 1383 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1384 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1386 }; 1387 1388 static const struct panel_desc boe_bp101wx1_100 = { 1389 .modes = &boe_bp101wx1_100_mode, 1390 .num_modes = 1, 1391 .bpc = 8, 1392 .size = { 1393 .width = 217, 1394 .height = 136, 1395 }, 1396 .delay = { 1397 .enable = 50, 1398 .disable = 50, 1399 }, 1400 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1401 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1402 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1403 }; 1404 1405 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1406 .pixelclock = { 69922000, 71000000, 72293000 }, 1407 .hactive = { 1280, 1280, 1280 }, 1408 .hfront_porch = { 48, 48, 48 }, 1409 .hback_porch = { 80, 80, 80 }, 1410 .hsync_len = { 32, 32, 32 }, 1411 .vactive = { 800, 800, 800 }, 1412 .vfront_porch = { 3, 3, 3 }, 1413 .vback_porch = { 14, 14, 14 }, 1414 .vsync_len = { 6, 6, 6 }, 1415 }; 1416 1417 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1418 .timings = &boe_ev121wxm_n10_1850_timing, 1419 .num_timings = 1, 1420 .bpc = 8, 1421 .size = { 1422 .width = 261, 1423 .height = 163, 1424 }, 1425 .delay = { 1426 .prepare = 9, 1427 .enable = 300, 1428 .unprepare = 300, 1429 .disable = 560, 1430 }, 1431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1432 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1433 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1434 }; 1435 1436 static const struct drm_display_mode boe_hv070wsa_mode = { 1437 .clock = 42105, 1438 .hdisplay = 1024, 1439 .hsync_start = 1024 + 30, 1440 .hsync_end = 1024 + 30 + 30, 1441 .htotal = 1024 + 30 + 30 + 30, 1442 .vdisplay = 600, 1443 .vsync_start = 600 + 10, 1444 .vsync_end = 600 + 10 + 10, 1445 .vtotal = 600 + 10 + 10 + 10, 1446 }; 1447 1448 static const struct panel_desc boe_hv070wsa = { 1449 .modes = &boe_hv070wsa_mode, 1450 .num_modes = 1, 1451 .bpc = 8, 1452 .size = { 1453 .width = 154, 1454 .height = 90, 1455 }, 1456 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1457 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1458 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1459 }; 1460 1461 static const struct display_timing cct_cmt430b19n00_timing = { 1462 .pixelclock = { 8000000, 9000000, 12000000 }, 1463 .hactive = { 480, 480, 480 }, 1464 .hfront_porch = { 2, 8, 75 }, 1465 .hback_porch = { 3, 43, 43 }, 1466 .hsync_len = { 2, 4, 75 }, 1467 .vactive = { 272, 272, 272 }, 1468 .vfront_porch = { 2, 8, 37 }, 1469 .vback_porch = { 2, 12, 12 }, 1470 .vsync_len = { 2, 4, 37 }, 1471 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1472 }; 1473 1474 static const struct panel_desc cct_cmt430b19n00 = { 1475 .timings = &cct_cmt430b19n00_timing, 1476 .num_timings = 1, 1477 .bpc = 8, 1478 .size = { 1479 .width = 95, 1480 .height = 53, 1481 }, 1482 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1483 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1484 .connector_type = DRM_MODE_CONNECTOR_DPI, 1485 }; 1486 1487 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1488 .clock = 9000, 1489 .hdisplay = 480, 1490 .hsync_start = 480 + 5, 1491 .hsync_end = 480 + 5 + 5, 1492 .htotal = 480 + 5 + 5 + 40, 1493 .vdisplay = 272, 1494 .vsync_start = 272 + 8, 1495 .vsync_end = 272 + 8 + 8, 1496 .vtotal = 272 + 8 + 8 + 8, 1497 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1498 }; 1499 1500 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1501 .modes = &cdtech_s043wq26h_ct7_mode, 1502 .num_modes = 1, 1503 .bpc = 8, 1504 .size = { 1505 .width = 95, 1506 .height = 54, 1507 }, 1508 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1509 }; 1510 1511 /* S070PWS19HP-FC21 2017/04/22 */ 1512 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1513 .clock = 51200, 1514 .hdisplay = 1024, 1515 .hsync_start = 1024 + 160, 1516 .hsync_end = 1024 + 160 + 20, 1517 .htotal = 1024 + 160 + 20 + 140, 1518 .vdisplay = 600, 1519 .vsync_start = 600 + 12, 1520 .vsync_end = 600 + 12 + 3, 1521 .vtotal = 600 + 12 + 3 + 20, 1522 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1523 }; 1524 1525 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1526 .modes = &cdtech_s070pws19hp_fc21_mode, 1527 .num_modes = 1, 1528 .bpc = 6, 1529 .size = { 1530 .width = 154, 1531 .height = 86, 1532 }, 1533 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1534 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1535 .connector_type = DRM_MODE_CONNECTOR_DPI, 1536 }; 1537 1538 /* S070SWV29HG-DC44 2017/09/21 */ 1539 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1540 .clock = 33300, 1541 .hdisplay = 800, 1542 .hsync_start = 800 + 210, 1543 .hsync_end = 800 + 210 + 2, 1544 .htotal = 800 + 210 + 2 + 44, 1545 .vdisplay = 480, 1546 .vsync_start = 480 + 22, 1547 .vsync_end = 480 + 22 + 2, 1548 .vtotal = 480 + 22 + 2 + 21, 1549 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1550 }; 1551 1552 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1553 .modes = &cdtech_s070swv29hg_dc44_mode, 1554 .num_modes = 1, 1555 .bpc = 6, 1556 .size = { 1557 .width = 154, 1558 .height = 86, 1559 }, 1560 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1562 .connector_type = DRM_MODE_CONNECTOR_DPI, 1563 }; 1564 1565 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1566 .clock = 35000, 1567 .hdisplay = 800, 1568 .hsync_start = 800 + 40, 1569 .hsync_end = 800 + 40 + 40, 1570 .htotal = 800 + 40 + 40 + 48, 1571 .vdisplay = 480, 1572 .vsync_start = 480 + 29, 1573 .vsync_end = 480 + 29 + 13, 1574 .vtotal = 480 + 29 + 13 + 3, 1575 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1576 }; 1577 1578 static const struct panel_desc cdtech_s070wv95_ct16 = { 1579 .modes = &cdtech_s070wv95_ct16_mode, 1580 .num_modes = 1, 1581 .bpc = 8, 1582 .size = { 1583 .width = 154, 1584 .height = 85, 1585 }, 1586 }; 1587 1588 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1589 .pixelclock = { 68900000, 71100000, 73400000 }, 1590 .hactive = { 1280, 1280, 1280 }, 1591 .hfront_porch = { 65, 80, 95 }, 1592 .hback_porch = { 64, 79, 94 }, 1593 .hsync_len = { 1, 1, 1 }, 1594 .vactive = { 800, 800, 800 }, 1595 .vfront_porch = { 7, 11, 14 }, 1596 .vback_porch = { 7, 11, 14 }, 1597 .vsync_len = { 1, 1, 1 }, 1598 .flags = DISPLAY_FLAGS_DE_HIGH, 1599 }; 1600 1601 static const struct panel_desc chefree_ch101olhlwh_002 = { 1602 .timings = &chefree_ch101olhlwh_002_timing, 1603 .num_timings = 1, 1604 .bpc = 8, 1605 .size = { 1606 .width = 217, 1607 .height = 135, 1608 }, 1609 .delay = { 1610 .enable = 200, 1611 .disable = 200, 1612 }, 1613 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1614 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1615 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1616 }; 1617 1618 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1619 .clock = 66770, 1620 .hdisplay = 800, 1621 .hsync_start = 800 + 49, 1622 .hsync_end = 800 + 49 + 33, 1623 .htotal = 800 + 49 + 33 + 17, 1624 .vdisplay = 1280, 1625 .vsync_start = 1280 + 1, 1626 .vsync_end = 1280 + 1 + 7, 1627 .vtotal = 1280 + 1 + 7 + 15, 1628 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1629 }; 1630 1631 static const struct panel_desc chunghwa_claa070wp03xg = { 1632 .modes = &chunghwa_claa070wp03xg_mode, 1633 .num_modes = 1, 1634 .bpc = 6, 1635 .size = { 1636 .width = 94, 1637 .height = 150, 1638 }, 1639 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1640 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1641 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1642 }; 1643 1644 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1645 .clock = 72070, 1646 .hdisplay = 1366, 1647 .hsync_start = 1366 + 58, 1648 .hsync_end = 1366 + 58 + 58, 1649 .htotal = 1366 + 58 + 58 + 58, 1650 .vdisplay = 768, 1651 .vsync_start = 768 + 4, 1652 .vsync_end = 768 + 4 + 4, 1653 .vtotal = 768 + 4 + 4 + 4, 1654 }; 1655 1656 static const struct panel_desc chunghwa_claa101wa01a = { 1657 .modes = &chunghwa_claa101wa01a_mode, 1658 .num_modes = 1, 1659 .bpc = 6, 1660 .size = { 1661 .width = 220, 1662 .height = 120, 1663 }, 1664 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1665 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1666 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1667 }; 1668 1669 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1670 .clock = 69300, 1671 .hdisplay = 1366, 1672 .hsync_start = 1366 + 48, 1673 .hsync_end = 1366 + 48 + 32, 1674 .htotal = 1366 + 48 + 32 + 20, 1675 .vdisplay = 768, 1676 .vsync_start = 768 + 16, 1677 .vsync_end = 768 + 16 + 8, 1678 .vtotal = 768 + 16 + 8 + 16, 1679 }; 1680 1681 static const struct panel_desc chunghwa_claa101wb01 = { 1682 .modes = &chunghwa_claa101wb01_mode, 1683 .num_modes = 1, 1684 .bpc = 6, 1685 .size = { 1686 .width = 223, 1687 .height = 125, 1688 }, 1689 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1690 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1691 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1692 }; 1693 1694 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1695 .pixelclock = { 5000000, 9000000, 12000000 }, 1696 .hactive = { 480, 480, 480 }, 1697 .hfront_porch = { 12, 12, 12 }, 1698 .hback_porch = { 12, 12, 12 }, 1699 .hsync_len = { 21, 21, 21 }, 1700 .vactive = { 272, 272, 272 }, 1701 .vfront_porch = { 4, 4, 4 }, 1702 .vback_porch = { 4, 4, 4 }, 1703 .vsync_len = { 8, 8, 8 }, 1704 }; 1705 1706 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1707 .timings = &dataimage_fg040346dsswbg04_timing, 1708 .num_timings = 1, 1709 .bpc = 8, 1710 .size = { 1711 .width = 95, 1712 .height = 54, 1713 }, 1714 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1715 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1716 .connector_type = DRM_MODE_CONNECTOR_DPI, 1717 }; 1718 1719 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1720 .pixelclock = { 68900000, 71110000, 73400000 }, 1721 .hactive = { 1280, 1280, 1280 }, 1722 .vactive = { 800, 800, 800 }, 1723 .hback_porch = { 100, 100, 100 }, 1724 .hfront_porch = { 100, 100, 100 }, 1725 .vback_porch = { 5, 5, 5 }, 1726 .vfront_porch = { 5, 5, 5 }, 1727 .hsync_len = { 24, 24, 24 }, 1728 .vsync_len = { 3, 3, 3 }, 1729 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1730 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1731 }; 1732 1733 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1734 .timings = &dataimage_fg1001l0dsswmg01_timing, 1735 .num_timings = 1, 1736 .bpc = 8, 1737 .size = { 1738 .width = 217, 1739 .height = 136, 1740 }, 1741 }; 1742 1743 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1744 .clock = 33260, 1745 .hdisplay = 800, 1746 .hsync_start = 800 + 40, 1747 .hsync_end = 800 + 40 + 128, 1748 .htotal = 800 + 40 + 128 + 88, 1749 .vdisplay = 480, 1750 .vsync_start = 480 + 10, 1751 .vsync_end = 480 + 10 + 2, 1752 .vtotal = 480 + 10 + 2 + 33, 1753 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1754 }; 1755 1756 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1757 .modes = &dataimage_scf0700c48ggu18_mode, 1758 .num_modes = 1, 1759 .bpc = 8, 1760 .size = { 1761 .width = 152, 1762 .height = 91, 1763 }, 1764 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1765 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1766 }; 1767 1768 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1769 .pixelclock = { 45000000, 51200000, 57000000 }, 1770 .hactive = { 1024, 1024, 1024 }, 1771 .hfront_porch = { 100, 106, 113 }, 1772 .hback_porch = { 100, 106, 113 }, 1773 .hsync_len = { 100, 108, 114 }, 1774 .vactive = { 600, 600, 600 }, 1775 .vfront_porch = { 8, 11, 15 }, 1776 .vback_porch = { 8, 11, 15 }, 1777 .vsync_len = { 9, 13, 15 }, 1778 .flags = DISPLAY_FLAGS_DE_HIGH, 1779 }; 1780 1781 static const struct panel_desc dlc_dlc0700yzg_1 = { 1782 .timings = &dlc_dlc0700yzg_1_timing, 1783 .num_timings = 1, 1784 .bpc = 6, 1785 .size = { 1786 .width = 154, 1787 .height = 86, 1788 }, 1789 .delay = { 1790 .prepare = 30, 1791 .enable = 200, 1792 .disable = 200, 1793 }, 1794 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1795 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1796 }; 1797 1798 static const struct display_timing dlc_dlc1010gig_timing = { 1799 .pixelclock = { 68900000, 71100000, 73400000 }, 1800 .hactive = { 1280, 1280, 1280 }, 1801 .hfront_porch = { 43, 53, 63 }, 1802 .hback_porch = { 43, 53, 63 }, 1803 .hsync_len = { 44, 54, 64 }, 1804 .vactive = { 800, 800, 800 }, 1805 .vfront_porch = { 5, 8, 11 }, 1806 .vback_porch = { 5, 8, 11 }, 1807 .vsync_len = { 5, 7, 11 }, 1808 .flags = DISPLAY_FLAGS_DE_HIGH, 1809 }; 1810 1811 static const struct panel_desc dlc_dlc1010gig = { 1812 .timings = &dlc_dlc1010gig_timing, 1813 .num_timings = 1, 1814 .bpc = 8, 1815 .size = { 1816 .width = 216, 1817 .height = 135, 1818 }, 1819 .delay = { 1820 .prepare = 60, 1821 .enable = 150, 1822 .disable = 100, 1823 .unprepare = 60, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1826 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1827 }; 1828 1829 static const struct drm_display_mode edt_et035012dm6_mode = { 1830 .clock = 6500, 1831 .hdisplay = 320, 1832 .hsync_start = 320 + 20, 1833 .hsync_end = 320 + 20 + 30, 1834 .htotal = 320 + 20 + 68, 1835 .vdisplay = 240, 1836 .vsync_start = 240 + 4, 1837 .vsync_end = 240 + 4 + 4, 1838 .vtotal = 240 + 4 + 4 + 14, 1839 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1840 }; 1841 1842 static const struct panel_desc edt_et035012dm6 = { 1843 .modes = &edt_et035012dm6_mode, 1844 .num_modes = 1, 1845 .bpc = 8, 1846 .size = { 1847 .width = 70, 1848 .height = 52, 1849 }, 1850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1851 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1852 }; 1853 1854 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1855 .clock = 6520, 1856 .hdisplay = 320, 1857 .hsync_start = 320 + 20, 1858 .hsync_end = 320 + 20 + 68, 1859 .htotal = 320 + 20 + 68, 1860 .vdisplay = 240, 1861 .vsync_start = 240 + 4, 1862 .vsync_end = 240 + 4 + 18, 1863 .vtotal = 240 + 4 + 18, 1864 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1865 }; 1866 1867 static const struct panel_desc edt_etm0350g0dh6 = { 1868 .modes = &edt_etm0350g0dh6_mode, 1869 .num_modes = 1, 1870 .bpc = 6, 1871 .size = { 1872 .width = 70, 1873 .height = 53, 1874 }, 1875 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1876 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1877 .connector_type = DRM_MODE_CONNECTOR_DPI, 1878 }; 1879 1880 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1881 .clock = 10870, 1882 .hdisplay = 480, 1883 .hsync_start = 480 + 8, 1884 .hsync_end = 480 + 8 + 4, 1885 .htotal = 480 + 8 + 4 + 41, 1886 1887 /* 1888 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1889 * fb_align 1890 */ 1891 1892 .vdisplay = 288, 1893 .vsync_start = 288 + 2, 1894 .vsync_end = 288 + 2 + 4, 1895 .vtotal = 288 + 2 + 4 + 10, 1896 }; 1897 1898 static const struct panel_desc edt_etm043080dh6gp = { 1899 .modes = &edt_etm043080dh6gp_mode, 1900 .num_modes = 1, 1901 .bpc = 8, 1902 .size = { 1903 .width = 100, 1904 .height = 65, 1905 }, 1906 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1907 .connector_type = DRM_MODE_CONNECTOR_DPI, 1908 }; 1909 1910 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1911 .clock = 9000, 1912 .hdisplay = 480, 1913 .hsync_start = 480 + 2, 1914 .hsync_end = 480 + 2 + 41, 1915 .htotal = 480 + 2 + 41 + 2, 1916 .vdisplay = 272, 1917 .vsync_start = 272 + 2, 1918 .vsync_end = 272 + 2 + 10, 1919 .vtotal = 272 + 2 + 10 + 2, 1920 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1921 }; 1922 1923 static const struct panel_desc edt_etm0430g0dh6 = { 1924 .modes = &edt_etm0430g0dh6_mode, 1925 .num_modes = 1, 1926 .bpc = 6, 1927 .size = { 1928 .width = 95, 1929 .height = 54, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1932 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1933 .connector_type = DRM_MODE_CONNECTOR_DPI, 1934 }; 1935 1936 static const struct drm_display_mode edt_et057090dhu_mode = { 1937 .clock = 25175, 1938 .hdisplay = 640, 1939 .hsync_start = 640 + 16, 1940 .hsync_end = 640 + 16 + 30, 1941 .htotal = 640 + 16 + 30 + 114, 1942 .vdisplay = 480, 1943 .vsync_start = 480 + 10, 1944 .vsync_end = 480 + 10 + 3, 1945 .vtotal = 480 + 10 + 3 + 32, 1946 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1947 }; 1948 1949 static const struct panel_desc edt_et057090dhu = { 1950 .modes = &edt_et057090dhu_mode, 1951 .num_modes = 1, 1952 .bpc = 6, 1953 .size = { 1954 .width = 115, 1955 .height = 86, 1956 }, 1957 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1958 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1959 .connector_type = DRM_MODE_CONNECTOR_DPI, 1960 }; 1961 1962 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1963 .clock = 33260, 1964 .hdisplay = 800, 1965 .hsync_start = 800 + 40, 1966 .hsync_end = 800 + 40 + 128, 1967 .htotal = 800 + 40 + 128 + 88, 1968 .vdisplay = 480, 1969 .vsync_start = 480 + 10, 1970 .vsync_end = 480 + 10 + 2, 1971 .vtotal = 480 + 10 + 2 + 33, 1972 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1973 }; 1974 1975 static const struct panel_desc edt_etm0700g0dh6 = { 1976 .modes = &edt_etm0700g0dh6_mode, 1977 .num_modes = 1, 1978 .bpc = 6, 1979 .size = { 1980 .width = 152, 1981 .height = 91, 1982 }, 1983 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1984 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1985 .connector_type = DRM_MODE_CONNECTOR_DPI, 1986 }; 1987 1988 static const struct panel_desc edt_etm0700g0bdh6 = { 1989 .modes = &edt_etm0700g0dh6_mode, 1990 .num_modes = 1, 1991 .bpc = 6, 1992 .size = { 1993 .width = 152, 1994 .height = 91, 1995 }, 1996 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1997 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1998 .connector_type = DRM_MODE_CONNECTOR_DPI, 1999 }; 2000 2001 static const struct display_timing edt_etml0700y5dha_timing = { 2002 .pixelclock = { 40800000, 51200000, 67200000 }, 2003 .hactive = { 1024, 1024, 1024 }, 2004 .hfront_porch = { 30, 106, 125 }, 2005 .hback_porch = { 30, 106, 125 }, 2006 .hsync_len = { 30, 108, 126 }, 2007 .vactive = { 600, 600, 600 }, 2008 .vfront_porch = { 3, 12, 67}, 2009 .vback_porch = { 3, 12, 67 }, 2010 .vsync_len = { 4, 11, 66 }, 2011 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2012 DISPLAY_FLAGS_DE_HIGH, 2013 }; 2014 2015 static const struct panel_desc edt_etml0700y5dha = { 2016 .timings = &edt_etml0700y5dha_timing, 2017 .num_timings = 1, 2018 .bpc = 8, 2019 .size = { 2020 .width = 155, 2021 .height = 86, 2022 }, 2023 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2024 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2025 }; 2026 2027 static const struct display_timing edt_etml1010g3dra_timing = { 2028 .pixelclock = { 66300000, 72400000, 78900000 }, 2029 .hactive = { 1280, 1280, 1280 }, 2030 .hfront_porch = { 12, 72, 132 }, 2031 .hback_porch = { 86, 86, 86 }, 2032 .hsync_len = { 2, 2, 2 }, 2033 .vactive = { 800, 800, 800 }, 2034 .vfront_porch = { 1, 15, 49 }, 2035 .vback_porch = { 21, 21, 21 }, 2036 .vsync_len = { 2, 2, 2 }, 2037 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2038 DISPLAY_FLAGS_DE_HIGH, 2039 }; 2040 2041 static const struct panel_desc edt_etml1010g3dra = { 2042 .timings = &edt_etml1010g3dra_timing, 2043 .num_timings = 1, 2044 .bpc = 8, 2045 .size = { 2046 .width = 216, 2047 .height = 135, 2048 }, 2049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2050 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2052 }; 2053 2054 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2055 .clock = 25175, 2056 .hdisplay = 640, 2057 .hsync_start = 640, 2058 .hsync_end = 640 + 16, 2059 .htotal = 640 + 16 + 30 + 114, 2060 .vdisplay = 480, 2061 .vsync_start = 480 + 10, 2062 .vsync_end = 480 + 10 + 3, 2063 .vtotal = 480 + 10 + 3 + 35, 2064 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2065 }; 2066 2067 static const struct panel_desc edt_etmv570g2dhu = { 2068 .modes = &edt_etmv570g2dhu_mode, 2069 .num_modes = 1, 2070 .bpc = 6, 2071 .size = { 2072 .width = 115, 2073 .height = 86, 2074 }, 2075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2076 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2077 .connector_type = DRM_MODE_CONNECTOR_DPI, 2078 }; 2079 2080 static const struct display_timing eink_vb3300_kca_timing = { 2081 .pixelclock = { 40000000, 40000000, 40000000 }, 2082 .hactive = { 334, 334, 334 }, 2083 .hfront_porch = { 1, 1, 1 }, 2084 .hback_porch = { 1, 1, 1 }, 2085 .hsync_len = { 1, 1, 1 }, 2086 .vactive = { 1405, 1405, 1405 }, 2087 .vfront_porch = { 1, 1, 1 }, 2088 .vback_porch = { 1, 1, 1 }, 2089 .vsync_len = { 1, 1, 1 }, 2090 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2091 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2092 }; 2093 2094 static const struct panel_desc eink_vb3300_kca = { 2095 .timings = &eink_vb3300_kca_timing, 2096 .num_timings = 1, 2097 .bpc = 6, 2098 .size = { 2099 .width = 157, 2100 .height = 209, 2101 }, 2102 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2103 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2104 .connector_type = DRM_MODE_CONNECTOR_DPI, 2105 }; 2106 2107 static const struct display_timing evervision_vgg644804_timing = { 2108 .pixelclock = { 25175000, 25175000, 25175000 }, 2109 .hactive = { 640, 640, 640 }, 2110 .hfront_porch = { 16, 16, 16 }, 2111 .hback_porch = { 82, 114, 170 }, 2112 .hsync_len = { 5, 30, 30 }, 2113 .vactive = { 480, 480, 480 }, 2114 .vfront_porch = { 10, 10, 10 }, 2115 .vback_porch = { 30, 32, 34 }, 2116 .vsync_len = { 1, 3, 5 }, 2117 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2118 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2119 DISPLAY_FLAGS_SYNC_POSEDGE, 2120 }; 2121 2122 static const struct panel_desc evervision_vgg644804 = { 2123 .timings = &evervision_vgg644804_timing, 2124 .num_timings = 1, 2125 .bpc = 8, 2126 .size = { 2127 .width = 115, 2128 .height = 86, 2129 }, 2130 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2131 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2132 }; 2133 2134 static const struct display_timing evervision_vgg804821_timing = { 2135 .pixelclock = { 27600000, 33300000, 50000000 }, 2136 .hactive = { 800, 800, 800 }, 2137 .hfront_porch = { 40, 66, 70 }, 2138 .hback_porch = { 40, 67, 70 }, 2139 .hsync_len = { 40, 67, 70 }, 2140 .vactive = { 480, 480, 480 }, 2141 .vfront_porch = { 6, 10, 10 }, 2142 .vback_porch = { 7, 11, 11 }, 2143 .vsync_len = { 7, 11, 11 }, 2144 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2145 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2146 DISPLAY_FLAGS_SYNC_NEGEDGE, 2147 }; 2148 2149 static const struct panel_desc evervision_vgg804821 = { 2150 .timings = &evervision_vgg804821_timing, 2151 .num_timings = 1, 2152 .bpc = 8, 2153 .size = { 2154 .width = 108, 2155 .height = 64, 2156 }, 2157 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2158 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2159 }; 2160 2161 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2162 .clock = 32260, 2163 .hdisplay = 800, 2164 .hsync_start = 800 + 168, 2165 .hsync_end = 800 + 168 + 64, 2166 .htotal = 800 + 168 + 64 + 88, 2167 .vdisplay = 480, 2168 .vsync_start = 480 + 37, 2169 .vsync_end = 480 + 37 + 2, 2170 .vtotal = 480 + 37 + 2 + 8, 2171 }; 2172 2173 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2174 .modes = &foxlink_fl500wvr00_a0t_mode, 2175 .num_modes = 1, 2176 .bpc = 8, 2177 .size = { 2178 .width = 108, 2179 .height = 65, 2180 }, 2181 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2182 }; 2183 2184 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2185 { /* 60 Hz */ 2186 .clock = 6000, 2187 .hdisplay = 320, 2188 .hsync_start = 320 + 44, 2189 .hsync_end = 320 + 44 + 16, 2190 .htotal = 320 + 44 + 16 + 20, 2191 .vdisplay = 240, 2192 .vsync_start = 240 + 2, 2193 .vsync_end = 240 + 2 + 6, 2194 .vtotal = 240 + 2 + 6 + 2, 2195 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2196 }, 2197 { /* 50 Hz */ 2198 .clock = 5400, 2199 .hdisplay = 320, 2200 .hsync_start = 320 + 56, 2201 .hsync_end = 320 + 56 + 16, 2202 .htotal = 320 + 56 + 16 + 40, 2203 .vdisplay = 240, 2204 .vsync_start = 240 + 2, 2205 .vsync_end = 240 + 2 + 6, 2206 .vtotal = 240 + 2 + 6 + 2, 2207 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2208 }, 2209 }; 2210 2211 static const struct panel_desc frida_frd350h54004 = { 2212 .modes = frida_frd350h54004_modes, 2213 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2214 .bpc = 8, 2215 .size = { 2216 .width = 77, 2217 .height = 64, 2218 }, 2219 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2220 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2221 .connector_type = DRM_MODE_CONNECTOR_DPI, 2222 }; 2223 2224 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2225 .clock = 67185, 2226 .hdisplay = 800, 2227 .hsync_start = 800 + 20, 2228 .hsync_end = 800 + 20 + 24, 2229 .htotal = 800 + 20 + 24 + 20, 2230 .vdisplay = 1280, 2231 .vsync_start = 1280 + 4, 2232 .vsync_end = 1280 + 4 + 8, 2233 .vtotal = 1280 + 4 + 8 + 4, 2234 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2235 }; 2236 2237 static const struct panel_desc friendlyarm_hd702e = { 2238 .modes = &friendlyarm_hd702e_mode, 2239 .num_modes = 1, 2240 .size = { 2241 .width = 94, 2242 .height = 151, 2243 }, 2244 }; 2245 2246 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2247 .clock = 9000, 2248 .hdisplay = 480, 2249 .hsync_start = 480 + 5, 2250 .hsync_end = 480 + 5 + 1, 2251 .htotal = 480 + 5 + 1 + 40, 2252 .vdisplay = 272, 2253 .vsync_start = 272 + 8, 2254 .vsync_end = 272 + 8 + 1, 2255 .vtotal = 272 + 8 + 1 + 8, 2256 }; 2257 2258 static const struct panel_desc giantplus_gpg482739qs5 = { 2259 .modes = &giantplus_gpg482739qs5_mode, 2260 .num_modes = 1, 2261 .bpc = 8, 2262 .size = { 2263 .width = 95, 2264 .height = 54, 2265 }, 2266 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2267 }; 2268 2269 static const struct display_timing giantplus_gpm940b0_timing = { 2270 .pixelclock = { 13500000, 27000000, 27500000 }, 2271 .hactive = { 320, 320, 320 }, 2272 .hfront_porch = { 14, 686, 718 }, 2273 .hback_porch = { 50, 70, 255 }, 2274 .hsync_len = { 1, 1, 1 }, 2275 .vactive = { 240, 240, 240 }, 2276 .vfront_porch = { 1, 1, 179 }, 2277 .vback_porch = { 1, 21, 31 }, 2278 .vsync_len = { 1, 1, 6 }, 2279 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2280 }; 2281 2282 static const struct panel_desc giantplus_gpm940b0 = { 2283 .timings = &giantplus_gpm940b0_timing, 2284 .num_timings = 1, 2285 .bpc = 8, 2286 .size = { 2287 .width = 60, 2288 .height = 45, 2289 }, 2290 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2291 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2292 }; 2293 2294 static const struct display_timing hannstar_hsd070pww1_timing = { 2295 .pixelclock = { 64300000, 71100000, 82000000 }, 2296 .hactive = { 1280, 1280, 1280 }, 2297 .hfront_porch = { 1, 1, 10 }, 2298 .hback_porch = { 1, 1, 10 }, 2299 /* 2300 * According to the data sheet, the minimum horizontal blanking interval 2301 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2302 * minimum working horizontal blanking interval to be 60 clocks. 2303 */ 2304 .hsync_len = { 58, 158, 661 }, 2305 .vactive = { 800, 800, 800 }, 2306 .vfront_porch = { 1, 1, 10 }, 2307 .vback_porch = { 1, 1, 10 }, 2308 .vsync_len = { 1, 21, 203 }, 2309 .flags = DISPLAY_FLAGS_DE_HIGH, 2310 }; 2311 2312 static const struct panel_desc hannstar_hsd070pww1 = { 2313 .timings = &hannstar_hsd070pww1_timing, 2314 .num_timings = 1, 2315 .bpc = 6, 2316 .size = { 2317 .width = 151, 2318 .height = 94, 2319 }, 2320 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2321 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2322 }; 2323 2324 static const struct display_timing hannstar_hsd100pxn1_timing = { 2325 .pixelclock = { 55000000, 65000000, 75000000 }, 2326 .hactive = { 1024, 1024, 1024 }, 2327 .hfront_porch = { 40, 40, 40 }, 2328 .hback_porch = { 220, 220, 220 }, 2329 .hsync_len = { 20, 60, 100 }, 2330 .vactive = { 768, 768, 768 }, 2331 .vfront_porch = { 7, 7, 7 }, 2332 .vback_porch = { 21, 21, 21 }, 2333 .vsync_len = { 10, 10, 10 }, 2334 .flags = DISPLAY_FLAGS_DE_HIGH, 2335 }; 2336 2337 static const struct panel_desc hannstar_hsd100pxn1 = { 2338 .timings = &hannstar_hsd100pxn1_timing, 2339 .num_timings = 1, 2340 .bpc = 6, 2341 .size = { 2342 .width = 203, 2343 .height = 152, 2344 }, 2345 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2346 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2347 }; 2348 2349 static const struct display_timing hannstar_hsd101pww2_timing = { 2350 .pixelclock = { 64300000, 71100000, 82000000 }, 2351 .hactive = { 1280, 1280, 1280 }, 2352 .hfront_porch = { 1, 1, 10 }, 2353 .hback_porch = { 1, 1, 10 }, 2354 .hsync_len = { 58, 158, 661 }, 2355 .vactive = { 800, 800, 800 }, 2356 .vfront_porch = { 1, 1, 10 }, 2357 .vback_porch = { 1, 1, 10 }, 2358 .vsync_len = { 1, 21, 203 }, 2359 .flags = DISPLAY_FLAGS_DE_HIGH, 2360 }; 2361 2362 static const struct panel_desc hannstar_hsd101pww2 = { 2363 .timings = &hannstar_hsd101pww2_timing, 2364 .num_timings = 1, 2365 .bpc = 8, 2366 .size = { 2367 .width = 217, 2368 .height = 136, 2369 }, 2370 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2371 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2372 }; 2373 2374 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2375 .clock = 33333, 2376 .hdisplay = 800, 2377 .hsync_start = 800 + 85, 2378 .hsync_end = 800 + 85 + 86, 2379 .htotal = 800 + 85 + 86 + 85, 2380 .vdisplay = 480, 2381 .vsync_start = 480 + 16, 2382 .vsync_end = 480 + 16 + 13, 2383 .vtotal = 480 + 16 + 13 + 16, 2384 }; 2385 2386 static const struct panel_desc hitachi_tx23d38vm0caa = { 2387 .modes = &hitachi_tx23d38vm0caa_mode, 2388 .num_modes = 1, 2389 .bpc = 6, 2390 .size = { 2391 .width = 195, 2392 .height = 117, 2393 }, 2394 .delay = { 2395 .enable = 160, 2396 .disable = 160, 2397 }, 2398 }; 2399 2400 static const struct drm_display_mode innolux_at043tn24_mode = { 2401 .clock = 9000, 2402 .hdisplay = 480, 2403 .hsync_start = 480 + 2, 2404 .hsync_end = 480 + 2 + 41, 2405 .htotal = 480 + 2 + 41 + 2, 2406 .vdisplay = 272, 2407 .vsync_start = 272 + 2, 2408 .vsync_end = 272 + 2 + 10, 2409 .vtotal = 272 + 2 + 10 + 2, 2410 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2411 }; 2412 2413 static const struct panel_desc innolux_at043tn24 = { 2414 .modes = &innolux_at043tn24_mode, 2415 .num_modes = 1, 2416 .bpc = 8, 2417 .size = { 2418 .width = 95, 2419 .height = 54, 2420 }, 2421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2422 .connector_type = DRM_MODE_CONNECTOR_DPI, 2423 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2424 }; 2425 2426 static const struct drm_display_mode innolux_at070tn92_mode = { 2427 .clock = 33333, 2428 .hdisplay = 800, 2429 .hsync_start = 800 + 210, 2430 .hsync_end = 800 + 210 + 20, 2431 .htotal = 800 + 210 + 20 + 46, 2432 .vdisplay = 480, 2433 .vsync_start = 480 + 22, 2434 .vsync_end = 480 + 22 + 10, 2435 .vtotal = 480 + 22 + 23 + 10, 2436 }; 2437 2438 static const struct panel_desc innolux_at070tn92 = { 2439 .modes = &innolux_at070tn92_mode, 2440 .num_modes = 1, 2441 .size = { 2442 .width = 154, 2443 .height = 86, 2444 }, 2445 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2446 }; 2447 2448 static const struct display_timing innolux_g070ace_l01_timing = { 2449 .pixelclock = { 25200000, 35000000, 35700000 }, 2450 .hactive = { 800, 800, 800 }, 2451 .hfront_porch = { 30, 32, 87 }, 2452 .hback_porch = { 30, 32, 87 }, 2453 .hsync_len = { 1, 1, 1 }, 2454 .vactive = { 480, 480, 480 }, 2455 .vfront_porch = { 3, 3, 3 }, 2456 .vback_porch = { 13, 13, 13 }, 2457 .vsync_len = { 1, 1, 4 }, 2458 .flags = DISPLAY_FLAGS_DE_HIGH, 2459 }; 2460 2461 static const struct panel_desc innolux_g070ace_l01 = { 2462 .timings = &innolux_g070ace_l01_timing, 2463 .num_timings = 1, 2464 .bpc = 8, 2465 .size = { 2466 .width = 152, 2467 .height = 91, 2468 }, 2469 .delay = { 2470 .prepare = 10, 2471 .enable = 50, 2472 .disable = 50, 2473 .unprepare = 500, 2474 }, 2475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2476 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2477 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2478 }; 2479 2480 static const struct display_timing innolux_g070y2_l01_timing = { 2481 .pixelclock = { 28000000, 29500000, 32000000 }, 2482 .hactive = { 800, 800, 800 }, 2483 .hfront_porch = { 61, 91, 141 }, 2484 .hback_porch = { 60, 90, 140 }, 2485 .hsync_len = { 12, 12, 12 }, 2486 .vactive = { 480, 480, 480 }, 2487 .vfront_porch = { 4, 9, 30 }, 2488 .vback_porch = { 4, 8, 28 }, 2489 .vsync_len = { 2, 2, 2 }, 2490 .flags = DISPLAY_FLAGS_DE_HIGH, 2491 }; 2492 2493 static const struct panel_desc innolux_g070y2_l01 = { 2494 .timings = &innolux_g070y2_l01_timing, 2495 .num_timings = 1, 2496 .bpc = 8, 2497 .size = { 2498 .width = 152, 2499 .height = 91, 2500 }, 2501 .delay = { 2502 .prepare = 10, 2503 .enable = 100, 2504 .disable = 100, 2505 .unprepare = 800, 2506 }, 2507 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2508 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2510 }; 2511 2512 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2513 .clock = 33333, 2514 .hdisplay = 800, 2515 .hsync_start = 800 + 210, 2516 .hsync_end = 800 + 210 + 20, 2517 .htotal = 800 + 210 + 20 + 46, 2518 .vdisplay = 480, 2519 .vsync_start = 480 + 22, 2520 .vsync_end = 480 + 22 + 10, 2521 .vtotal = 480 + 22 + 23 + 10, 2522 }; 2523 2524 static const struct panel_desc innolux_g070y2_t02 = { 2525 .modes = &innolux_g070y2_t02_mode, 2526 .num_modes = 1, 2527 .bpc = 8, 2528 .size = { 2529 .width = 152, 2530 .height = 92, 2531 }, 2532 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2533 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2534 .connector_type = DRM_MODE_CONNECTOR_DPI, 2535 }; 2536 2537 static const struct display_timing innolux_g101ice_l01_timing = { 2538 .pixelclock = { 60400000, 71100000, 74700000 }, 2539 .hactive = { 1280, 1280, 1280 }, 2540 .hfront_porch = { 30, 60, 70 }, 2541 .hback_porch = { 30, 60, 70 }, 2542 .hsync_len = { 22, 40, 60 }, 2543 .vactive = { 800, 800, 800 }, 2544 .vfront_porch = { 3, 8, 14 }, 2545 .vback_porch = { 3, 8, 14 }, 2546 .vsync_len = { 4, 7, 12 }, 2547 .flags = DISPLAY_FLAGS_DE_HIGH, 2548 }; 2549 2550 static const struct panel_desc innolux_g101ice_l01 = { 2551 .timings = &innolux_g101ice_l01_timing, 2552 .num_timings = 1, 2553 .bpc = 8, 2554 .size = { 2555 .width = 217, 2556 .height = 135, 2557 }, 2558 .delay = { 2559 .enable = 200, 2560 .disable = 200, 2561 }, 2562 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2563 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2564 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2565 }; 2566 2567 static const struct display_timing innolux_g121i1_l01_timing = { 2568 .pixelclock = { 67450000, 71000000, 74550000 }, 2569 .hactive = { 1280, 1280, 1280 }, 2570 .hfront_porch = { 40, 80, 160 }, 2571 .hback_porch = { 39, 79, 159 }, 2572 .hsync_len = { 1, 1, 1 }, 2573 .vactive = { 800, 800, 800 }, 2574 .vfront_porch = { 5, 11, 100 }, 2575 .vback_porch = { 4, 11, 99 }, 2576 .vsync_len = { 1, 1, 1 }, 2577 }; 2578 2579 static const struct panel_desc innolux_g121i1_l01 = { 2580 .timings = &innolux_g121i1_l01_timing, 2581 .num_timings = 1, 2582 .bpc = 6, 2583 .size = { 2584 .width = 261, 2585 .height = 163, 2586 }, 2587 .delay = { 2588 .enable = 200, 2589 .disable = 20, 2590 }, 2591 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2592 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2593 }; 2594 2595 static const struct display_timing innolux_g121x1_l03_timings = { 2596 .pixelclock = { 57500000, 64900000, 74400000 }, 2597 .hactive = { 1024, 1024, 1024 }, 2598 .hfront_porch = { 90, 140, 190 }, 2599 .hback_porch = { 90, 140, 190 }, 2600 .hsync_len = { 36, 40, 60 }, 2601 .vactive = { 768, 768, 768 }, 2602 .vfront_porch = { 2, 15, 30 }, 2603 .vback_porch = { 2, 15, 30 }, 2604 .vsync_len = { 2, 8, 20 }, 2605 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2606 }; 2607 2608 static const struct panel_desc innolux_g121x1_l03 = { 2609 .timings = &innolux_g121x1_l03_timings, 2610 .num_timings = 1, 2611 .bpc = 6, 2612 .size = { 2613 .width = 246, 2614 .height = 185, 2615 }, 2616 .delay = { 2617 .enable = 200, 2618 .unprepare = 200, 2619 .disable = 400, 2620 }, 2621 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2622 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2623 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2624 }; 2625 2626 static const struct panel_desc innolux_g121xce_l01 = { 2627 .timings = &innolux_g121x1_l03_timings, 2628 .num_timings = 1, 2629 .bpc = 8, 2630 .size = { 2631 .width = 246, 2632 .height = 185, 2633 }, 2634 .delay = { 2635 .enable = 200, 2636 .unprepare = 200, 2637 .disable = 400, 2638 }, 2639 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2640 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2641 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2642 }; 2643 2644 static const struct display_timing innolux_g156hce_l01_timings = { 2645 .pixelclock = { 120000000, 141860000, 150000000 }, 2646 .hactive = { 1920, 1920, 1920 }, 2647 .hfront_porch = { 80, 90, 100 }, 2648 .hback_porch = { 80, 90, 100 }, 2649 .hsync_len = { 20, 30, 30 }, 2650 .vactive = { 1080, 1080, 1080 }, 2651 .vfront_porch = { 3, 10, 20 }, 2652 .vback_porch = { 3, 10, 20 }, 2653 .vsync_len = { 4, 10, 10 }, 2654 }; 2655 2656 static const struct panel_desc innolux_g156hce_l01 = { 2657 .timings = &innolux_g156hce_l01_timings, 2658 .num_timings = 1, 2659 .bpc = 8, 2660 .size = { 2661 .width = 344, 2662 .height = 194, 2663 }, 2664 .delay = { 2665 .prepare = 1, /* T1+T2 */ 2666 .enable = 450, /* T5 */ 2667 .disable = 200, /* T6 */ 2668 .unprepare = 10, /* T3+T7 */ 2669 }, 2670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2671 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2672 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2673 }; 2674 2675 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2676 .clock = 69300, 2677 .hdisplay = 1366, 2678 .hsync_start = 1366 + 16, 2679 .hsync_end = 1366 + 16 + 34, 2680 .htotal = 1366 + 16 + 34 + 50, 2681 .vdisplay = 768, 2682 .vsync_start = 768 + 2, 2683 .vsync_end = 768 + 2 + 6, 2684 .vtotal = 768 + 2 + 6 + 12, 2685 }; 2686 2687 static const struct panel_desc innolux_n156bge_l21 = { 2688 .modes = &innolux_n156bge_l21_mode, 2689 .num_modes = 1, 2690 .bpc = 6, 2691 .size = { 2692 .width = 344, 2693 .height = 193, 2694 }, 2695 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2696 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2697 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2698 }; 2699 2700 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2701 .clock = 51501, 2702 .hdisplay = 1024, 2703 .hsync_start = 1024 + 128, 2704 .hsync_end = 1024 + 128 + 64, 2705 .htotal = 1024 + 128 + 64 + 128, 2706 .vdisplay = 600, 2707 .vsync_start = 600 + 16, 2708 .vsync_end = 600 + 16 + 4, 2709 .vtotal = 600 + 16 + 4 + 16, 2710 }; 2711 2712 static const struct panel_desc innolux_zj070na_01p = { 2713 .modes = &innolux_zj070na_01p_mode, 2714 .num_modes = 1, 2715 .bpc = 6, 2716 .size = { 2717 .width = 154, 2718 .height = 90, 2719 }, 2720 }; 2721 2722 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2723 .pixelclock = { 5580000, 5850000, 6200000 }, 2724 .hactive = { 320, 320, 320 }, 2725 .hfront_porch = { 30, 30, 30 }, 2726 .hback_porch = { 30, 30, 30 }, 2727 .hsync_len = { 1, 5, 17 }, 2728 .vactive = { 240, 240, 240 }, 2729 .vfront_porch = { 6, 6, 6 }, 2730 .vback_porch = { 5, 5, 5 }, 2731 .vsync_len = { 1, 2, 11 }, 2732 .flags = DISPLAY_FLAGS_DE_HIGH, 2733 }; 2734 2735 static const struct panel_desc koe_tx14d24vm1bpa = { 2736 .timings = &koe_tx14d24vm1bpa_timing, 2737 .num_timings = 1, 2738 .bpc = 6, 2739 .size = { 2740 .width = 115, 2741 .height = 86, 2742 }, 2743 }; 2744 2745 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2746 .pixelclock = { 151820000, 156720000, 159780000 }, 2747 .hactive = { 1920, 1920, 1920 }, 2748 .hfront_porch = { 105, 130, 142 }, 2749 .hback_porch = { 45, 70, 82 }, 2750 .hsync_len = { 30, 30, 30 }, 2751 .vactive = { 1200, 1200, 1200}, 2752 .vfront_porch = { 3, 5, 10 }, 2753 .vback_porch = { 2, 5, 10 }, 2754 .vsync_len = { 5, 5, 5 }, 2755 }; 2756 2757 static const struct panel_desc koe_tx26d202vm0bwa = { 2758 .timings = &koe_tx26d202vm0bwa_timing, 2759 .num_timings = 1, 2760 .bpc = 8, 2761 .size = { 2762 .width = 217, 2763 .height = 136, 2764 }, 2765 .delay = { 2766 .prepare = 1000, 2767 .enable = 1000, 2768 .unprepare = 1000, 2769 .disable = 1000, 2770 }, 2771 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2772 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2773 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2774 }; 2775 2776 static const struct display_timing koe_tx31d200vm0baa_timing = { 2777 .pixelclock = { 39600000, 43200000, 48000000 }, 2778 .hactive = { 1280, 1280, 1280 }, 2779 .hfront_porch = { 16, 36, 56 }, 2780 .hback_porch = { 16, 36, 56 }, 2781 .hsync_len = { 8, 8, 8 }, 2782 .vactive = { 480, 480, 480 }, 2783 .vfront_porch = { 6, 21, 33 }, 2784 .vback_porch = { 6, 21, 33 }, 2785 .vsync_len = { 8, 8, 8 }, 2786 .flags = DISPLAY_FLAGS_DE_HIGH, 2787 }; 2788 2789 static const struct panel_desc koe_tx31d200vm0baa = { 2790 .timings = &koe_tx31d200vm0baa_timing, 2791 .num_timings = 1, 2792 .bpc = 6, 2793 .size = { 2794 .width = 292, 2795 .height = 109, 2796 }, 2797 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2798 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2799 }; 2800 2801 static const struct display_timing kyo_tcg121xglp_timing = { 2802 .pixelclock = { 52000000, 65000000, 71000000 }, 2803 .hactive = { 1024, 1024, 1024 }, 2804 .hfront_porch = { 2, 2, 2 }, 2805 .hback_porch = { 2, 2, 2 }, 2806 .hsync_len = { 86, 124, 244 }, 2807 .vactive = { 768, 768, 768 }, 2808 .vfront_porch = { 2, 2, 2 }, 2809 .vback_porch = { 2, 2, 2 }, 2810 .vsync_len = { 6, 34, 73 }, 2811 .flags = DISPLAY_FLAGS_DE_HIGH, 2812 }; 2813 2814 static const struct panel_desc kyo_tcg121xglp = { 2815 .timings = &kyo_tcg121xglp_timing, 2816 .num_timings = 1, 2817 .bpc = 8, 2818 .size = { 2819 .width = 246, 2820 .height = 184, 2821 }, 2822 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2823 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2824 }; 2825 2826 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2827 .clock = 7000, 2828 .hdisplay = 320, 2829 .hsync_start = 320 + 20, 2830 .hsync_end = 320 + 20 + 30, 2831 .htotal = 320 + 20 + 30 + 38, 2832 .vdisplay = 240, 2833 .vsync_start = 240 + 4, 2834 .vsync_end = 240 + 4 + 3, 2835 .vtotal = 240 + 4 + 3 + 15, 2836 }; 2837 2838 static const struct panel_desc lemaker_bl035_rgb_002 = { 2839 .modes = &lemaker_bl035_rgb_002_mode, 2840 .num_modes = 1, 2841 .size = { 2842 .width = 70, 2843 .height = 52, 2844 }, 2845 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2846 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2847 }; 2848 2849 static const struct display_timing lg_lb070wv8_timing = { 2850 .pixelclock = { 31950000, 33260000, 34600000 }, 2851 .hactive = { 800, 800, 800 }, 2852 .hfront_porch = { 88, 88, 88 }, 2853 .hback_porch = { 88, 88, 88 }, 2854 .hsync_len = { 80, 80, 80 }, 2855 .vactive = { 480, 480, 480 }, 2856 .vfront_porch = { 10, 10, 10 }, 2857 .vback_porch = { 10, 10, 10 }, 2858 .vsync_len = { 25, 25, 25 }, 2859 }; 2860 2861 static const struct panel_desc lg_lb070wv8 = { 2862 .timings = &lg_lb070wv8_timing, 2863 .num_timings = 1, 2864 .bpc = 8, 2865 .size = { 2866 .width = 151, 2867 .height = 91, 2868 }, 2869 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2870 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2871 }; 2872 2873 static const struct display_timing logictechno_lt161010_2nh_timing = { 2874 .pixelclock = { 26400000, 33300000, 46800000 }, 2875 .hactive = { 800, 800, 800 }, 2876 .hfront_porch = { 16, 210, 354 }, 2877 .hback_porch = { 46, 46, 46 }, 2878 .hsync_len = { 1, 20, 40 }, 2879 .vactive = { 480, 480, 480 }, 2880 .vfront_porch = { 7, 22, 147 }, 2881 .vback_porch = { 23, 23, 23 }, 2882 .vsync_len = { 1, 10, 20 }, 2883 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2884 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2885 DISPLAY_FLAGS_SYNC_POSEDGE, 2886 }; 2887 2888 static const struct panel_desc logictechno_lt161010_2nh = { 2889 .timings = &logictechno_lt161010_2nh_timing, 2890 .num_timings = 1, 2891 .bpc = 6, 2892 .size = { 2893 .width = 154, 2894 .height = 86, 2895 }, 2896 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2897 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2898 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2899 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2900 .connector_type = DRM_MODE_CONNECTOR_DPI, 2901 }; 2902 2903 static const struct display_timing logictechno_lt170410_2whc_timing = { 2904 .pixelclock = { 68900000, 71100000, 73400000 }, 2905 .hactive = { 1280, 1280, 1280 }, 2906 .hfront_porch = { 23, 60, 71 }, 2907 .hback_porch = { 23, 60, 71 }, 2908 .hsync_len = { 15, 40, 47 }, 2909 .vactive = { 800, 800, 800 }, 2910 .vfront_porch = { 5, 7, 10 }, 2911 .vback_porch = { 5, 7, 10 }, 2912 .vsync_len = { 6, 9, 12 }, 2913 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2914 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2915 DISPLAY_FLAGS_SYNC_POSEDGE, 2916 }; 2917 2918 static const struct panel_desc logictechno_lt170410_2whc = { 2919 .timings = &logictechno_lt170410_2whc_timing, 2920 .num_timings = 1, 2921 .bpc = 8, 2922 .size = { 2923 .width = 217, 2924 .height = 136, 2925 }, 2926 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2927 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2928 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2929 }; 2930 2931 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2932 .clock = 33000, 2933 .hdisplay = 800, 2934 .hsync_start = 800 + 112, 2935 .hsync_end = 800 + 112 + 3, 2936 .htotal = 800 + 112 + 3 + 85, 2937 .vdisplay = 480, 2938 .vsync_start = 480 + 38, 2939 .vsync_end = 480 + 38 + 3, 2940 .vtotal = 480 + 38 + 3 + 29, 2941 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2942 }; 2943 2944 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2945 .modes = &logictechno_lttd800480070_l2rt_mode, 2946 .num_modes = 1, 2947 .bpc = 8, 2948 .size = { 2949 .width = 154, 2950 .height = 86, 2951 }, 2952 .delay = { 2953 .prepare = 45, 2954 .enable = 100, 2955 .disable = 100, 2956 .unprepare = 45 2957 }, 2958 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2959 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2960 .connector_type = DRM_MODE_CONNECTOR_DPI, 2961 }; 2962 2963 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2964 .clock = 33000, 2965 .hdisplay = 800, 2966 .hsync_start = 800 + 154, 2967 .hsync_end = 800 + 154 + 3, 2968 .htotal = 800 + 154 + 3 + 43, 2969 .vdisplay = 480, 2970 .vsync_start = 480 + 47, 2971 .vsync_end = 480 + 47 + 3, 2972 .vtotal = 480 + 47 + 3 + 20, 2973 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2974 }; 2975 2976 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2977 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2978 .num_modes = 1, 2979 .bpc = 8, 2980 .size = { 2981 .width = 154, 2982 .height = 86, 2983 }, 2984 .delay = { 2985 .prepare = 45, 2986 .enable = 100, 2987 .disable = 100, 2988 .unprepare = 45 2989 }, 2990 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2991 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2992 .connector_type = DRM_MODE_CONNECTOR_DPI, 2993 }; 2994 2995 static const struct drm_display_mode logicpd_type_28_mode = { 2996 .clock = 9107, 2997 .hdisplay = 480, 2998 .hsync_start = 480 + 3, 2999 .hsync_end = 480 + 3 + 42, 3000 .htotal = 480 + 3 + 42 + 2, 3001 3002 .vdisplay = 272, 3003 .vsync_start = 272 + 2, 3004 .vsync_end = 272 + 2 + 11, 3005 .vtotal = 272 + 2 + 11 + 3, 3006 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3007 }; 3008 3009 static const struct panel_desc logicpd_type_28 = { 3010 .modes = &logicpd_type_28_mode, 3011 .num_modes = 1, 3012 .bpc = 8, 3013 .size = { 3014 .width = 105, 3015 .height = 67, 3016 }, 3017 .delay = { 3018 .prepare = 200, 3019 .enable = 200, 3020 .unprepare = 200, 3021 .disable = 200, 3022 }, 3023 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3024 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3025 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3026 .connector_type = DRM_MODE_CONNECTOR_DPI, 3027 }; 3028 3029 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3030 .clock = 30400, 3031 .hdisplay = 800, 3032 .hsync_start = 800 + 0, 3033 .hsync_end = 800 + 1, 3034 .htotal = 800 + 0 + 1 + 160, 3035 .vdisplay = 480, 3036 .vsync_start = 480 + 0, 3037 .vsync_end = 480 + 48 + 1, 3038 .vtotal = 480 + 48 + 1 + 0, 3039 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3040 }; 3041 3042 static const struct panel_desc mitsubishi_aa070mc01 = { 3043 .modes = &mitsubishi_aa070mc01_mode, 3044 .num_modes = 1, 3045 .bpc = 8, 3046 .size = { 3047 .width = 152, 3048 .height = 91, 3049 }, 3050 3051 .delay = { 3052 .enable = 200, 3053 .unprepare = 200, 3054 .disable = 400, 3055 }, 3056 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3057 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3058 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3059 }; 3060 3061 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3062 .clock = 56234, 3063 .hdisplay = 1024, 3064 .hsync_start = 1024 + 24, 3065 .hsync_end = 1024 + 24 + 63, 3066 .htotal = 1024 + 24 + 63 + 1, 3067 .vdisplay = 768, 3068 .vsync_start = 768 + 3, 3069 .vsync_end = 768 + 3 + 6, 3070 .vtotal = 768 + 3 + 6 + 1, 3071 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3072 }; 3073 3074 static const struct panel_desc mitsubishi_aa084xe01 = { 3075 .modes = &mitsubishi_aa084xe01_mode, 3076 .num_modes = 1, 3077 .bpc = 8, 3078 .size = { 3079 .width = 1024, 3080 .height = 768, 3081 }, 3082 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3083 .connector_type = DRM_MODE_CONNECTOR_DPI, 3084 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3085 }; 3086 3087 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3088 .pixelclock = { 29000000, 33000000, 38000000 }, 3089 .hactive = { 800, 800, 800 }, 3090 .hfront_porch = { 180, 210, 240 }, 3091 .hback_porch = { 16, 16, 16 }, 3092 .hsync_len = { 30, 30, 30 }, 3093 .vactive = { 480, 480, 480 }, 3094 .vfront_porch = { 12, 22, 32 }, 3095 .vback_porch = { 10, 10, 10 }, 3096 .vsync_len = { 13, 13, 13 }, 3097 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3098 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3099 DISPLAY_FLAGS_SYNC_POSEDGE, 3100 }; 3101 3102 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3103 .timings = &multi_inno_mi0700s4t_6_timing, 3104 .num_timings = 1, 3105 .bpc = 8, 3106 .size = { 3107 .width = 154, 3108 .height = 86, 3109 }, 3110 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3111 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3112 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3113 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3114 .connector_type = DRM_MODE_CONNECTOR_DPI, 3115 }; 3116 3117 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3118 .pixelclock = { 32000000, 40000000, 50000000 }, 3119 .hactive = { 800, 800, 800 }, 3120 .hfront_porch = { 16, 210, 354 }, 3121 .hback_porch = { 6, 26, 45 }, 3122 .hsync_len = { 1, 20, 40 }, 3123 .vactive = { 600, 600, 600 }, 3124 .vfront_porch = { 1, 12, 77 }, 3125 .vback_porch = { 3, 13, 22 }, 3126 .vsync_len = { 1, 10, 20 }, 3127 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3128 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3129 DISPLAY_FLAGS_SYNC_POSEDGE, 3130 }; 3131 3132 static const struct panel_desc multi_inno_mi0800ft_9 = { 3133 .timings = &multi_inno_mi0800ft_9_timing, 3134 .num_timings = 1, 3135 .bpc = 8, 3136 .size = { 3137 .width = 162, 3138 .height = 122, 3139 }, 3140 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3141 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3142 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3143 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3144 .connector_type = DRM_MODE_CONNECTOR_DPI, 3145 }; 3146 3147 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3148 .pixelclock = { 68900000, 70000000, 73400000 }, 3149 .hactive = { 1280, 1280, 1280 }, 3150 .hfront_porch = { 30, 60, 71 }, 3151 .hback_porch = { 30, 60, 71 }, 3152 .hsync_len = { 10, 10, 48 }, 3153 .vactive = { 800, 800, 800 }, 3154 .vfront_porch = { 5, 10, 10 }, 3155 .vback_porch = { 5, 10, 10 }, 3156 .vsync_len = { 5, 6, 13 }, 3157 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3158 DISPLAY_FLAGS_DE_HIGH, 3159 }; 3160 3161 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3162 .timings = &multi_inno_mi1010ait_1cp_timing, 3163 .num_timings = 1, 3164 .bpc = 8, 3165 .size = { 3166 .width = 217, 3167 .height = 136, 3168 }, 3169 .delay = { 3170 .enable = 50, 3171 .disable = 50, 3172 }, 3173 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3174 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3175 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3176 }; 3177 3178 static const struct display_timing nec_nl12880bc20_05_timing = { 3179 .pixelclock = { 67000000, 71000000, 75000000 }, 3180 .hactive = { 1280, 1280, 1280 }, 3181 .hfront_porch = { 2, 30, 30 }, 3182 .hback_porch = { 6, 100, 100 }, 3183 .hsync_len = { 2, 30, 30 }, 3184 .vactive = { 800, 800, 800 }, 3185 .vfront_porch = { 5, 5, 5 }, 3186 .vback_porch = { 11, 11, 11 }, 3187 .vsync_len = { 7, 7, 7 }, 3188 }; 3189 3190 static const struct panel_desc nec_nl12880bc20_05 = { 3191 .timings = &nec_nl12880bc20_05_timing, 3192 .num_timings = 1, 3193 .bpc = 8, 3194 .size = { 3195 .width = 261, 3196 .height = 163, 3197 }, 3198 .delay = { 3199 .enable = 50, 3200 .disable = 50, 3201 }, 3202 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3203 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3204 }; 3205 3206 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3207 .clock = 10870, 3208 .hdisplay = 480, 3209 .hsync_start = 480 + 2, 3210 .hsync_end = 480 + 2 + 41, 3211 .htotal = 480 + 2 + 41 + 2, 3212 .vdisplay = 272, 3213 .vsync_start = 272 + 2, 3214 .vsync_end = 272 + 2 + 4, 3215 .vtotal = 272 + 2 + 4 + 2, 3216 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3217 }; 3218 3219 static const struct panel_desc nec_nl4827hc19_05b = { 3220 .modes = &nec_nl4827hc19_05b_mode, 3221 .num_modes = 1, 3222 .bpc = 8, 3223 .size = { 3224 .width = 95, 3225 .height = 54, 3226 }, 3227 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3228 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3229 }; 3230 3231 static const struct drm_display_mode netron_dy_e231732_mode = { 3232 .clock = 66000, 3233 .hdisplay = 1024, 3234 .hsync_start = 1024 + 160, 3235 .hsync_end = 1024 + 160 + 70, 3236 .htotal = 1024 + 160 + 70 + 90, 3237 .vdisplay = 600, 3238 .vsync_start = 600 + 127, 3239 .vsync_end = 600 + 127 + 20, 3240 .vtotal = 600 + 127 + 20 + 3, 3241 }; 3242 3243 static const struct panel_desc netron_dy_e231732 = { 3244 .modes = &netron_dy_e231732_mode, 3245 .num_modes = 1, 3246 .size = { 3247 .width = 154, 3248 .height = 87, 3249 }, 3250 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3251 }; 3252 3253 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3254 .clock = 9000, 3255 .hdisplay = 480, 3256 .hsync_start = 480 + 2, 3257 .hsync_end = 480 + 2 + 41, 3258 .htotal = 480 + 2 + 41 + 2, 3259 .vdisplay = 272, 3260 .vsync_start = 272 + 2, 3261 .vsync_end = 272 + 2 + 10, 3262 .vtotal = 272 + 2 + 10 + 2, 3263 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3264 }; 3265 3266 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3267 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3268 .num_modes = 1, 3269 .bpc = 8, 3270 .size = { 3271 .width = 95, 3272 .height = 54, 3273 }, 3274 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3275 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3276 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3277 .connector_type = DRM_MODE_CONNECTOR_DPI, 3278 }; 3279 3280 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3281 .pixelclock = { 130000000, 148350000, 163000000 }, 3282 .hactive = { 1920, 1920, 1920 }, 3283 .hfront_porch = { 80, 100, 100 }, 3284 .hback_porch = { 100, 120, 120 }, 3285 .hsync_len = { 50, 60, 60 }, 3286 .vactive = { 1080, 1080, 1080 }, 3287 .vfront_porch = { 12, 30, 30 }, 3288 .vback_porch = { 4, 10, 10 }, 3289 .vsync_len = { 4, 5, 5 }, 3290 }; 3291 3292 static const struct panel_desc nlt_nl192108ac18_02d = { 3293 .timings = &nlt_nl192108ac18_02d_timing, 3294 .num_timings = 1, 3295 .bpc = 8, 3296 .size = { 3297 .width = 344, 3298 .height = 194, 3299 }, 3300 .delay = { 3301 .unprepare = 500, 3302 }, 3303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3304 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3305 }; 3306 3307 static const struct drm_display_mode nvd_9128_mode = { 3308 .clock = 29500, 3309 .hdisplay = 800, 3310 .hsync_start = 800 + 130, 3311 .hsync_end = 800 + 130 + 98, 3312 .htotal = 800 + 0 + 130 + 98, 3313 .vdisplay = 480, 3314 .vsync_start = 480 + 10, 3315 .vsync_end = 480 + 10 + 50, 3316 .vtotal = 480 + 0 + 10 + 50, 3317 }; 3318 3319 static const struct panel_desc nvd_9128 = { 3320 .modes = &nvd_9128_mode, 3321 .num_modes = 1, 3322 .bpc = 8, 3323 .size = { 3324 .width = 156, 3325 .height = 88, 3326 }, 3327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3329 }; 3330 3331 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3332 .pixelclock = { 30000000, 30000000, 40000000 }, 3333 .hactive = { 800, 800, 800 }, 3334 .hfront_porch = { 40, 40, 40 }, 3335 .hback_porch = { 40, 40, 40 }, 3336 .hsync_len = { 1, 48, 48 }, 3337 .vactive = { 480, 480, 480 }, 3338 .vfront_porch = { 13, 13, 13 }, 3339 .vback_porch = { 29, 29, 29 }, 3340 .vsync_len = { 3, 3, 3 }, 3341 .flags = DISPLAY_FLAGS_DE_HIGH, 3342 }; 3343 3344 static const struct panel_desc okaya_rs800480t_7x0gp = { 3345 .timings = &okaya_rs800480t_7x0gp_timing, 3346 .num_timings = 1, 3347 .bpc = 6, 3348 .size = { 3349 .width = 154, 3350 .height = 87, 3351 }, 3352 .delay = { 3353 .prepare = 41, 3354 .enable = 50, 3355 .unprepare = 41, 3356 .disable = 50, 3357 }, 3358 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3359 }; 3360 3361 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3362 .clock = 9000, 3363 .hdisplay = 480, 3364 .hsync_start = 480 + 5, 3365 .hsync_end = 480 + 5 + 30, 3366 .htotal = 480 + 5 + 30 + 10, 3367 .vdisplay = 272, 3368 .vsync_start = 272 + 8, 3369 .vsync_end = 272 + 8 + 5, 3370 .vtotal = 272 + 8 + 5 + 3, 3371 }; 3372 3373 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3374 .modes = &olimex_lcd_olinuxino_43ts_mode, 3375 .num_modes = 1, 3376 .size = { 3377 .width = 95, 3378 .height = 54, 3379 }, 3380 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3381 }; 3382 3383 /* 3384 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3385 * pixel clocks, but this is the timing that was being used in the Adafruit 3386 * installation instructions. 3387 */ 3388 static const struct drm_display_mode ontat_yx700wv03_mode = { 3389 .clock = 29500, 3390 .hdisplay = 800, 3391 .hsync_start = 824, 3392 .hsync_end = 896, 3393 .htotal = 992, 3394 .vdisplay = 480, 3395 .vsync_start = 483, 3396 .vsync_end = 493, 3397 .vtotal = 500, 3398 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3399 }; 3400 3401 /* 3402 * Specification at: 3403 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3404 */ 3405 static const struct panel_desc ontat_yx700wv03 = { 3406 .modes = &ontat_yx700wv03_mode, 3407 .num_modes = 1, 3408 .bpc = 8, 3409 .size = { 3410 .width = 154, 3411 .height = 83, 3412 }, 3413 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3414 }; 3415 3416 static const struct drm_display_mode ortustech_com37h3m_mode = { 3417 .clock = 22230, 3418 .hdisplay = 480, 3419 .hsync_start = 480 + 40, 3420 .hsync_end = 480 + 40 + 10, 3421 .htotal = 480 + 40 + 10 + 40, 3422 .vdisplay = 640, 3423 .vsync_start = 640 + 4, 3424 .vsync_end = 640 + 4 + 2, 3425 .vtotal = 640 + 4 + 2 + 4, 3426 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3427 }; 3428 3429 static const struct panel_desc ortustech_com37h3m = { 3430 .modes = &ortustech_com37h3m_mode, 3431 .num_modes = 1, 3432 .bpc = 8, 3433 .size = { 3434 .width = 56, /* 56.16mm */ 3435 .height = 75, /* 74.88mm */ 3436 }, 3437 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3438 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3439 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3440 }; 3441 3442 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3443 .clock = 25000, 3444 .hdisplay = 480, 3445 .hsync_start = 480 + 10, 3446 .hsync_end = 480 + 10 + 10, 3447 .htotal = 480 + 10 + 10 + 15, 3448 .vdisplay = 800, 3449 .vsync_start = 800 + 3, 3450 .vsync_end = 800 + 3 + 3, 3451 .vtotal = 800 + 3 + 3 + 3, 3452 }; 3453 3454 static const struct panel_desc ortustech_com43h4m85ulc = { 3455 .modes = &ortustech_com43h4m85ulc_mode, 3456 .num_modes = 1, 3457 .bpc = 6, 3458 .size = { 3459 .width = 56, 3460 .height = 93, 3461 }, 3462 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3463 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3464 .connector_type = DRM_MODE_CONNECTOR_DPI, 3465 }; 3466 3467 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3468 .clock = 33000, 3469 .hdisplay = 800, 3470 .hsync_start = 800 + 210, 3471 .hsync_end = 800 + 210 + 30, 3472 .htotal = 800 + 210 + 30 + 16, 3473 .vdisplay = 480, 3474 .vsync_start = 480 + 22, 3475 .vsync_end = 480 + 22 + 13, 3476 .vtotal = 480 + 22 + 13 + 10, 3477 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3478 }; 3479 3480 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3481 .modes = &osddisplays_osd070t1718_19ts_mode, 3482 .num_modes = 1, 3483 .bpc = 8, 3484 .size = { 3485 .width = 152, 3486 .height = 91, 3487 }, 3488 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3489 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3490 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3491 .connector_type = DRM_MODE_CONNECTOR_DPI, 3492 }; 3493 3494 static const struct drm_display_mode pda_91_00156_a0_mode = { 3495 .clock = 33300, 3496 .hdisplay = 800, 3497 .hsync_start = 800 + 1, 3498 .hsync_end = 800 + 1 + 64, 3499 .htotal = 800 + 1 + 64 + 64, 3500 .vdisplay = 480, 3501 .vsync_start = 480 + 1, 3502 .vsync_end = 480 + 1 + 23, 3503 .vtotal = 480 + 1 + 23 + 22, 3504 }; 3505 3506 static const struct panel_desc pda_91_00156_a0 = { 3507 .modes = &pda_91_00156_a0_mode, 3508 .num_modes = 1, 3509 .size = { 3510 .width = 152, 3511 .height = 91, 3512 }, 3513 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3514 }; 3515 3516 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3517 .clock = 66500, 3518 .hdisplay = 1280, 3519 .hsync_start = 1280 + 12, 3520 .hsync_end = 1280 + 12 + 20, 3521 .htotal = 1280 + 12 + 20 + 56, 3522 .vdisplay = 800, 3523 .vsync_start = 800 + 1, 3524 .vsync_end = 800 + 1 + 3, 3525 .vtotal = 800 + 1 + 3 + 20, 3526 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3527 }; 3528 3529 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3530 .modes = &powertip_ph128800t006_zhc01_mode, 3531 .num_modes = 1, 3532 .bpc = 8, 3533 .size = { 3534 .width = 216, 3535 .height = 135, 3536 }, 3537 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3538 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3539 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3540 }; 3541 3542 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3543 .clock = 24750, 3544 .hdisplay = 800, 3545 .hsync_start = 800 + 54, 3546 .hsync_end = 800 + 54 + 2, 3547 .htotal = 800 + 54 + 2 + 44, 3548 .vdisplay = 480, 3549 .vsync_start = 480 + 49, 3550 .vsync_end = 480 + 49 + 2, 3551 .vtotal = 480 + 49 + 2 + 22, 3552 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3553 }; 3554 3555 static const struct panel_desc powertip_ph800480t013_idf02 = { 3556 .modes = &powertip_ph800480t013_idf02_mode, 3557 .num_modes = 1, 3558 .bpc = 8, 3559 .size = { 3560 .width = 152, 3561 .height = 91, 3562 }, 3563 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3564 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3565 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3566 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3567 .connector_type = DRM_MODE_CONNECTOR_DPI, 3568 }; 3569 3570 static const struct drm_display_mode qd43003c0_40_mode = { 3571 .clock = 9000, 3572 .hdisplay = 480, 3573 .hsync_start = 480 + 8, 3574 .hsync_end = 480 + 8 + 4, 3575 .htotal = 480 + 8 + 4 + 39, 3576 .vdisplay = 272, 3577 .vsync_start = 272 + 4, 3578 .vsync_end = 272 + 4 + 10, 3579 .vtotal = 272 + 4 + 10 + 2, 3580 }; 3581 3582 static const struct panel_desc qd43003c0_40 = { 3583 .modes = &qd43003c0_40_mode, 3584 .num_modes = 1, 3585 .bpc = 8, 3586 .size = { 3587 .width = 95, 3588 .height = 53, 3589 }, 3590 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3591 }; 3592 3593 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3594 { /* 60 Hz */ 3595 .clock = 10800, 3596 .hdisplay = 480, 3597 .hsync_start = 480 + 77, 3598 .hsync_end = 480 + 77 + 41, 3599 .htotal = 480 + 77 + 41 + 2, 3600 .vdisplay = 272, 3601 .vsync_start = 272 + 16, 3602 .vsync_end = 272 + 16 + 10, 3603 .vtotal = 272 + 16 + 10 + 2, 3604 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3605 }, 3606 { /* 50 Hz */ 3607 .clock = 10800, 3608 .hdisplay = 480, 3609 .hsync_start = 480 + 17, 3610 .hsync_end = 480 + 17 + 41, 3611 .htotal = 480 + 17 + 41 + 2, 3612 .vdisplay = 272, 3613 .vsync_start = 272 + 116, 3614 .vsync_end = 272 + 116 + 10, 3615 .vtotal = 272 + 116 + 10 + 2, 3616 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3617 }, 3618 }; 3619 3620 static const struct panel_desc qishenglong_gopher2b_lcd = { 3621 .modes = qishenglong_gopher2b_lcd_modes, 3622 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3623 .bpc = 8, 3624 .size = { 3625 .width = 95, 3626 .height = 54, 3627 }, 3628 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3629 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3630 .connector_type = DRM_MODE_CONNECTOR_DPI, 3631 }; 3632 3633 static const struct display_timing rocktech_rk043fn48h_timing = { 3634 .pixelclock = { 6000000, 9000000, 12000000 }, 3635 .hactive = { 480, 480, 480 }, 3636 .hback_porch = { 8, 43, 43 }, 3637 .hfront_porch = { 2, 8, 10 }, 3638 .hsync_len = { 1, 1, 1 }, 3639 .vactive = { 272, 272, 272 }, 3640 .vback_porch = { 2, 12, 26 }, 3641 .vfront_porch = { 1, 4, 4 }, 3642 .vsync_len = { 1, 10, 10 }, 3643 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3644 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3645 DISPLAY_FLAGS_SYNC_POSEDGE, 3646 }; 3647 3648 static const struct panel_desc rocktech_rk043fn48h = { 3649 .timings = &rocktech_rk043fn48h_timing, 3650 .num_timings = 1, 3651 .bpc = 8, 3652 .size = { 3653 .width = 95, 3654 .height = 54, 3655 }, 3656 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3657 .connector_type = DRM_MODE_CONNECTOR_DPI, 3658 }; 3659 3660 static const struct display_timing rocktech_rk070er9427_timing = { 3661 .pixelclock = { 26400000, 33300000, 46800000 }, 3662 .hactive = { 800, 800, 800 }, 3663 .hfront_porch = { 16, 210, 354 }, 3664 .hback_porch = { 46, 46, 46 }, 3665 .hsync_len = { 1, 1, 1 }, 3666 .vactive = { 480, 480, 480 }, 3667 .vfront_porch = { 7, 22, 147 }, 3668 .vback_porch = { 23, 23, 23 }, 3669 .vsync_len = { 1, 1, 1 }, 3670 .flags = DISPLAY_FLAGS_DE_HIGH, 3671 }; 3672 3673 static const struct panel_desc rocktech_rk070er9427 = { 3674 .timings = &rocktech_rk070er9427_timing, 3675 .num_timings = 1, 3676 .bpc = 6, 3677 .size = { 3678 .width = 154, 3679 .height = 86, 3680 }, 3681 .delay = { 3682 .prepare = 41, 3683 .enable = 50, 3684 .unprepare = 41, 3685 .disable = 50, 3686 }, 3687 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3688 }; 3689 3690 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3691 .clock = 71100, 3692 .hdisplay = 1280, 3693 .hsync_start = 1280 + 48, 3694 .hsync_end = 1280 + 48 + 32, 3695 .htotal = 1280 + 48 + 32 + 80, 3696 .vdisplay = 800, 3697 .vsync_start = 800 + 2, 3698 .vsync_end = 800 + 2 + 5, 3699 .vtotal = 800 + 2 + 5 + 16, 3700 }; 3701 3702 static const struct panel_desc rocktech_rk101ii01d_ct = { 3703 .modes = &rocktech_rk101ii01d_ct_mode, 3704 .bpc = 8, 3705 .num_modes = 1, 3706 .size = { 3707 .width = 217, 3708 .height = 136, 3709 }, 3710 .delay = { 3711 .prepare = 50, 3712 .disable = 50, 3713 }, 3714 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3715 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3716 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3717 }; 3718 3719 static const struct display_timing samsung_ltl101al01_timing = { 3720 .pixelclock = { 66663000, 66663000, 66663000 }, 3721 .hactive = { 1280, 1280, 1280 }, 3722 .hfront_porch = { 18, 18, 18 }, 3723 .hback_porch = { 36, 36, 36 }, 3724 .hsync_len = { 16, 16, 16 }, 3725 .vactive = { 800, 800, 800 }, 3726 .vfront_porch = { 4, 4, 4 }, 3727 .vback_porch = { 16, 16, 16 }, 3728 .vsync_len = { 3, 3, 3 }, 3729 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3730 }; 3731 3732 static const struct panel_desc samsung_ltl101al01 = { 3733 .timings = &samsung_ltl101al01_timing, 3734 .num_timings = 1, 3735 .bpc = 8, 3736 .size = { 3737 .width = 217, 3738 .height = 135, 3739 }, 3740 .delay = { 3741 .prepare = 40, 3742 .enable = 300, 3743 .disable = 200, 3744 .unprepare = 600, 3745 }, 3746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3747 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3748 }; 3749 3750 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3751 .clock = 54030, 3752 .hdisplay = 1024, 3753 .hsync_start = 1024 + 24, 3754 .hsync_end = 1024 + 24 + 136, 3755 .htotal = 1024 + 24 + 136 + 160, 3756 .vdisplay = 600, 3757 .vsync_start = 600 + 3, 3758 .vsync_end = 600 + 3 + 6, 3759 .vtotal = 600 + 3 + 6 + 61, 3760 }; 3761 3762 static const struct panel_desc samsung_ltn101nt05 = { 3763 .modes = &samsung_ltn101nt05_mode, 3764 .num_modes = 1, 3765 .bpc = 6, 3766 .size = { 3767 .width = 223, 3768 .height = 125, 3769 }, 3770 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3771 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3772 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3773 }; 3774 3775 static const struct display_timing satoz_sat050at40h12r2_timing = { 3776 .pixelclock = {33300000, 33300000, 50000000}, 3777 .hactive = {800, 800, 800}, 3778 .hfront_porch = {16, 210, 354}, 3779 .hback_porch = {46, 46, 46}, 3780 .hsync_len = {1, 1, 40}, 3781 .vactive = {480, 480, 480}, 3782 .vfront_porch = {7, 22, 147}, 3783 .vback_porch = {23, 23, 23}, 3784 .vsync_len = {1, 1, 20}, 3785 }; 3786 3787 static const struct panel_desc satoz_sat050at40h12r2 = { 3788 .timings = &satoz_sat050at40h12r2_timing, 3789 .num_timings = 1, 3790 .bpc = 8, 3791 .size = { 3792 .width = 108, 3793 .height = 65, 3794 }, 3795 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3796 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3797 }; 3798 3799 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3800 .clock = 33260, 3801 .hdisplay = 800, 3802 .hsync_start = 800 + 64, 3803 .hsync_end = 800 + 64 + 128, 3804 .htotal = 800 + 64 + 128 + 64, 3805 .vdisplay = 480, 3806 .vsync_start = 480 + 8, 3807 .vsync_end = 480 + 8 + 2, 3808 .vtotal = 480 + 8 + 2 + 35, 3809 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3810 }; 3811 3812 static const struct panel_desc sharp_lq070y3dg3b = { 3813 .modes = &sharp_lq070y3dg3b_mode, 3814 .num_modes = 1, 3815 .bpc = 8, 3816 .size = { 3817 .width = 152, /* 152.4mm */ 3818 .height = 91, /* 91.4mm */ 3819 }, 3820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3821 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3822 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3823 }; 3824 3825 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3826 .clock = 5500, 3827 .hdisplay = 240, 3828 .hsync_start = 240 + 16, 3829 .hsync_end = 240 + 16 + 7, 3830 .htotal = 240 + 16 + 7 + 5, 3831 .vdisplay = 320, 3832 .vsync_start = 320 + 9, 3833 .vsync_end = 320 + 9 + 1, 3834 .vtotal = 320 + 9 + 1 + 7, 3835 }; 3836 3837 static const struct panel_desc sharp_lq035q7db03 = { 3838 .modes = &sharp_lq035q7db03_mode, 3839 .num_modes = 1, 3840 .bpc = 6, 3841 .size = { 3842 .width = 54, 3843 .height = 72, 3844 }, 3845 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3846 }; 3847 3848 static const struct display_timing sharp_lq101k1ly04_timing = { 3849 .pixelclock = { 60000000, 65000000, 80000000 }, 3850 .hactive = { 1280, 1280, 1280 }, 3851 .hfront_porch = { 20, 20, 20 }, 3852 .hback_porch = { 20, 20, 20 }, 3853 .hsync_len = { 10, 10, 10 }, 3854 .vactive = { 800, 800, 800 }, 3855 .vfront_porch = { 4, 4, 4 }, 3856 .vback_porch = { 4, 4, 4 }, 3857 .vsync_len = { 4, 4, 4 }, 3858 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3859 }; 3860 3861 static const struct panel_desc sharp_lq101k1ly04 = { 3862 .timings = &sharp_lq101k1ly04_timing, 3863 .num_timings = 1, 3864 .bpc = 8, 3865 .size = { 3866 .width = 217, 3867 .height = 136, 3868 }, 3869 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3870 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3871 }; 3872 3873 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3874 { /* 50 Hz */ 3875 .clock = 3000, 3876 .hdisplay = 240, 3877 .hsync_start = 240 + 58, 3878 .hsync_end = 240 + 58 + 1, 3879 .htotal = 240 + 58 + 1 + 1, 3880 .vdisplay = 160, 3881 .vsync_start = 160 + 24, 3882 .vsync_end = 160 + 24 + 10, 3883 .vtotal = 160 + 24 + 10 + 6, 3884 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3885 }, 3886 { /* 60 Hz */ 3887 .clock = 3000, 3888 .hdisplay = 240, 3889 .hsync_start = 240 + 8, 3890 .hsync_end = 240 + 8 + 1, 3891 .htotal = 240 + 8 + 1 + 1, 3892 .vdisplay = 160, 3893 .vsync_start = 160 + 24, 3894 .vsync_end = 160 + 24 + 10, 3895 .vtotal = 160 + 24 + 10 + 6, 3896 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3897 }, 3898 }; 3899 3900 static const struct panel_desc sharp_ls020b1dd01d = { 3901 .modes = sharp_ls020b1dd01d_modes, 3902 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3903 .bpc = 6, 3904 .size = { 3905 .width = 42, 3906 .height = 28, 3907 }, 3908 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3909 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3910 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3911 | DRM_BUS_FLAG_SHARP_SIGNALS, 3912 }; 3913 3914 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3915 .clock = 33300, 3916 .hdisplay = 800, 3917 .hsync_start = 800 + 1, 3918 .hsync_end = 800 + 1 + 64, 3919 .htotal = 800 + 1 + 64 + 64, 3920 .vdisplay = 480, 3921 .vsync_start = 480 + 1, 3922 .vsync_end = 480 + 1 + 23, 3923 .vtotal = 480 + 1 + 23 + 22, 3924 }; 3925 3926 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3927 .modes = &shelly_sca07010_bfn_lnn_mode, 3928 .num_modes = 1, 3929 .size = { 3930 .width = 152, 3931 .height = 91, 3932 }, 3933 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3934 }; 3935 3936 static const struct drm_display_mode starry_kr070pe2t_mode = { 3937 .clock = 33000, 3938 .hdisplay = 800, 3939 .hsync_start = 800 + 209, 3940 .hsync_end = 800 + 209 + 1, 3941 .htotal = 800 + 209 + 1 + 45, 3942 .vdisplay = 480, 3943 .vsync_start = 480 + 22, 3944 .vsync_end = 480 + 22 + 1, 3945 .vtotal = 480 + 22 + 1 + 22, 3946 }; 3947 3948 static const struct panel_desc starry_kr070pe2t = { 3949 .modes = &starry_kr070pe2t_mode, 3950 .num_modes = 1, 3951 .bpc = 8, 3952 .size = { 3953 .width = 152, 3954 .height = 86, 3955 }, 3956 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3957 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3958 .connector_type = DRM_MODE_CONNECTOR_DPI, 3959 }; 3960 3961 static const struct display_timing startek_kd070wvfpa_mode = { 3962 .pixelclock = { 25200000, 27200000, 30500000 }, 3963 .hactive = { 800, 800, 800 }, 3964 .hfront_porch = { 19, 44, 115 }, 3965 .hback_porch = { 5, 16, 101 }, 3966 .hsync_len = { 1, 2, 100 }, 3967 .vactive = { 480, 480, 480 }, 3968 .vfront_porch = { 5, 43, 67 }, 3969 .vback_porch = { 5, 5, 67 }, 3970 .vsync_len = { 1, 2, 66 }, 3971 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3972 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3973 DISPLAY_FLAGS_SYNC_POSEDGE, 3974 }; 3975 3976 static const struct panel_desc startek_kd070wvfpa = { 3977 .timings = &startek_kd070wvfpa_mode, 3978 .num_timings = 1, 3979 .bpc = 8, 3980 .size = { 3981 .width = 152, 3982 .height = 91, 3983 }, 3984 .delay = { 3985 .prepare = 20, 3986 .enable = 200, 3987 .disable = 200, 3988 }, 3989 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3990 .connector_type = DRM_MODE_CONNECTOR_DPI, 3991 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3992 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3993 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3994 }; 3995 3996 static const struct display_timing tsd_tst043015cmhx_timing = { 3997 .pixelclock = { 5000000, 9000000, 12000000 }, 3998 .hactive = { 480, 480, 480 }, 3999 .hfront_porch = { 4, 5, 65 }, 4000 .hback_porch = { 36, 40, 255 }, 4001 .hsync_len = { 1, 1, 1 }, 4002 .vactive = { 272, 272, 272 }, 4003 .vfront_porch = { 2, 8, 97 }, 4004 .vback_porch = { 3, 8, 31 }, 4005 .vsync_len = { 1, 1, 1 }, 4006 4007 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4008 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4009 }; 4010 4011 static const struct panel_desc tsd_tst043015cmhx = { 4012 .timings = &tsd_tst043015cmhx_timing, 4013 .num_timings = 1, 4014 .bpc = 8, 4015 .size = { 4016 .width = 105, 4017 .height = 67, 4018 }, 4019 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4020 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4021 }; 4022 4023 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4024 .clock = 30000, 4025 .hdisplay = 800, 4026 .hsync_start = 800 + 39, 4027 .hsync_end = 800 + 39 + 47, 4028 .htotal = 800 + 39 + 47 + 39, 4029 .vdisplay = 480, 4030 .vsync_start = 480 + 13, 4031 .vsync_end = 480 + 13 + 2, 4032 .vtotal = 480 + 13 + 2 + 29, 4033 }; 4034 4035 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4036 .modes = &tfc_s9700rtwv43tr_01b_mode, 4037 .num_modes = 1, 4038 .bpc = 8, 4039 .size = { 4040 .width = 155, 4041 .height = 90, 4042 }, 4043 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4044 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4045 }; 4046 4047 static const struct display_timing tianma_tm070jdhg30_timing = { 4048 .pixelclock = { 62600000, 68200000, 78100000 }, 4049 .hactive = { 1280, 1280, 1280 }, 4050 .hfront_porch = { 15, 64, 159 }, 4051 .hback_porch = { 5, 5, 5 }, 4052 .hsync_len = { 1, 1, 256 }, 4053 .vactive = { 800, 800, 800 }, 4054 .vfront_porch = { 3, 40, 99 }, 4055 .vback_porch = { 2, 2, 2 }, 4056 .vsync_len = { 1, 1, 128 }, 4057 .flags = DISPLAY_FLAGS_DE_HIGH, 4058 }; 4059 4060 static const struct panel_desc tianma_tm070jdhg30 = { 4061 .timings = &tianma_tm070jdhg30_timing, 4062 .num_timings = 1, 4063 .bpc = 8, 4064 .size = { 4065 .width = 151, 4066 .height = 95, 4067 }, 4068 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4069 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4070 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4071 }; 4072 4073 static const struct panel_desc tianma_tm070jvhg33 = { 4074 .timings = &tianma_tm070jdhg30_timing, 4075 .num_timings = 1, 4076 .bpc = 8, 4077 .size = { 4078 .width = 150, 4079 .height = 94, 4080 }, 4081 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4082 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4083 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4084 }; 4085 4086 static const struct display_timing tianma_tm070rvhg71_timing = { 4087 .pixelclock = { 27700000, 29200000, 39600000 }, 4088 .hactive = { 800, 800, 800 }, 4089 .hfront_porch = { 12, 40, 212 }, 4090 .hback_porch = { 88, 88, 88 }, 4091 .hsync_len = { 1, 1, 40 }, 4092 .vactive = { 480, 480, 480 }, 4093 .vfront_porch = { 1, 13, 88 }, 4094 .vback_porch = { 32, 32, 32 }, 4095 .vsync_len = { 1, 1, 3 }, 4096 .flags = DISPLAY_FLAGS_DE_HIGH, 4097 }; 4098 4099 static const struct panel_desc tianma_tm070rvhg71 = { 4100 .timings = &tianma_tm070rvhg71_timing, 4101 .num_timings = 1, 4102 .bpc = 8, 4103 .size = { 4104 .width = 154, 4105 .height = 86, 4106 }, 4107 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4108 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4109 }; 4110 4111 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4112 { 4113 .clock = 10000, 4114 .hdisplay = 320, 4115 .hsync_start = 320 + 50, 4116 .hsync_end = 320 + 50 + 6, 4117 .htotal = 320 + 50 + 6 + 38, 4118 .vdisplay = 240, 4119 .vsync_start = 240 + 3, 4120 .vsync_end = 240 + 3 + 1, 4121 .vtotal = 240 + 3 + 1 + 17, 4122 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4123 }, 4124 }; 4125 4126 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4127 .modes = ti_nspire_cx_lcd_mode, 4128 .num_modes = 1, 4129 .bpc = 8, 4130 .size = { 4131 .width = 65, 4132 .height = 49, 4133 }, 4134 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4135 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4136 }; 4137 4138 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4139 { 4140 .clock = 10000, 4141 .hdisplay = 320, 4142 .hsync_start = 320 + 6, 4143 .hsync_end = 320 + 6 + 6, 4144 .htotal = 320 + 6 + 6 + 6, 4145 .vdisplay = 240, 4146 .vsync_start = 240 + 0, 4147 .vsync_end = 240 + 0 + 1, 4148 .vtotal = 240 + 0 + 1 + 0, 4149 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4150 }, 4151 }; 4152 4153 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4154 .modes = ti_nspire_classic_lcd_mode, 4155 .num_modes = 1, 4156 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4157 .bpc = 8, 4158 .size = { 4159 .width = 71, 4160 .height = 53, 4161 }, 4162 /* This is the grayscale bus format */ 4163 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4164 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4165 }; 4166 4167 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4168 .clock = 79500, 4169 .hdisplay = 1280, 4170 .hsync_start = 1280 + 192, 4171 .hsync_end = 1280 + 192 + 128, 4172 .htotal = 1280 + 192 + 128 + 64, 4173 .vdisplay = 768, 4174 .vsync_start = 768 + 20, 4175 .vsync_end = 768 + 20 + 7, 4176 .vtotal = 768 + 20 + 7 + 3, 4177 }; 4178 4179 static const struct panel_desc toshiba_lt089ac29000 = { 4180 .modes = &toshiba_lt089ac29000_mode, 4181 .num_modes = 1, 4182 .size = { 4183 .width = 194, 4184 .height = 116, 4185 }, 4186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4187 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4189 }; 4190 4191 static const struct drm_display_mode tpk_f07a_0102_mode = { 4192 .clock = 33260, 4193 .hdisplay = 800, 4194 .hsync_start = 800 + 40, 4195 .hsync_end = 800 + 40 + 128, 4196 .htotal = 800 + 40 + 128 + 88, 4197 .vdisplay = 480, 4198 .vsync_start = 480 + 10, 4199 .vsync_end = 480 + 10 + 2, 4200 .vtotal = 480 + 10 + 2 + 33, 4201 }; 4202 4203 static const struct panel_desc tpk_f07a_0102 = { 4204 .modes = &tpk_f07a_0102_mode, 4205 .num_modes = 1, 4206 .size = { 4207 .width = 152, 4208 .height = 91, 4209 }, 4210 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4211 }; 4212 4213 static const struct drm_display_mode tpk_f10a_0102_mode = { 4214 .clock = 45000, 4215 .hdisplay = 1024, 4216 .hsync_start = 1024 + 176, 4217 .hsync_end = 1024 + 176 + 5, 4218 .htotal = 1024 + 176 + 5 + 88, 4219 .vdisplay = 600, 4220 .vsync_start = 600 + 20, 4221 .vsync_end = 600 + 20 + 5, 4222 .vtotal = 600 + 20 + 5 + 25, 4223 }; 4224 4225 static const struct panel_desc tpk_f10a_0102 = { 4226 .modes = &tpk_f10a_0102_mode, 4227 .num_modes = 1, 4228 .size = { 4229 .width = 223, 4230 .height = 125, 4231 }, 4232 }; 4233 4234 static const struct display_timing urt_umsh_8596md_timing = { 4235 .pixelclock = { 33260000, 33260000, 33260000 }, 4236 .hactive = { 800, 800, 800 }, 4237 .hfront_porch = { 41, 41, 41 }, 4238 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4239 .hsync_len = { 71, 128, 128 }, 4240 .vactive = { 480, 480, 480 }, 4241 .vfront_porch = { 10, 10, 10 }, 4242 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4243 .vsync_len = { 2, 2, 2 }, 4244 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4245 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4246 }; 4247 4248 static const struct panel_desc urt_umsh_8596md_lvds = { 4249 .timings = &urt_umsh_8596md_timing, 4250 .num_timings = 1, 4251 .bpc = 6, 4252 .size = { 4253 .width = 152, 4254 .height = 91, 4255 }, 4256 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4257 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4258 }; 4259 4260 static const struct panel_desc urt_umsh_8596md_parallel = { 4261 .timings = &urt_umsh_8596md_timing, 4262 .num_timings = 1, 4263 .bpc = 6, 4264 .size = { 4265 .width = 152, 4266 .height = 91, 4267 }, 4268 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4269 }; 4270 4271 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4272 .clock = 60000, 4273 .hdisplay = 1024, 4274 .hsync_start = 1024 + 160, 4275 .hsync_end = 1024 + 160 + 100, 4276 .htotal = 1024 + 160 + 100 + 60, 4277 .vdisplay = 600, 4278 .vsync_start = 600 + 12, 4279 .vsync_end = 600 + 12 + 10, 4280 .vtotal = 600 + 12 + 10 + 13, 4281 }; 4282 4283 static const struct panel_desc vivax_tpc9150_panel = { 4284 .modes = &vivax_tpc9150_panel_mode, 4285 .num_modes = 1, 4286 .bpc = 6, 4287 .size = { 4288 .width = 200, 4289 .height = 115, 4290 }, 4291 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4292 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4293 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4294 }; 4295 4296 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4297 .clock = 33333, 4298 .hdisplay = 800, 4299 .hsync_start = 800 + 210, 4300 .hsync_end = 800 + 210 + 20, 4301 .htotal = 800 + 210 + 20 + 46, 4302 .vdisplay = 480, 4303 .vsync_start = 480 + 22, 4304 .vsync_end = 480 + 22 + 10, 4305 .vtotal = 480 + 22 + 10 + 23, 4306 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4307 }; 4308 4309 static const struct panel_desc vl050_8048nt_c01 = { 4310 .modes = &vl050_8048nt_c01_mode, 4311 .num_modes = 1, 4312 .bpc = 8, 4313 .size = { 4314 .width = 120, 4315 .height = 76, 4316 }, 4317 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4318 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4319 }; 4320 4321 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4322 .clock = 6410, 4323 .hdisplay = 320, 4324 .hsync_start = 320 + 20, 4325 .hsync_end = 320 + 20 + 30, 4326 .htotal = 320 + 20 + 30 + 38, 4327 .vdisplay = 240, 4328 .vsync_start = 240 + 4, 4329 .vsync_end = 240 + 4 + 3, 4330 .vtotal = 240 + 4 + 3 + 15, 4331 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4332 }; 4333 4334 static const struct panel_desc winstar_wf35ltiacd = { 4335 .modes = &winstar_wf35ltiacd_mode, 4336 .num_modes = 1, 4337 .bpc = 8, 4338 .size = { 4339 .width = 70, 4340 .height = 53, 4341 }, 4342 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4343 }; 4344 4345 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4346 .clock = 51200, 4347 .hdisplay = 1024, 4348 .hsync_start = 1024 + 100, 4349 .hsync_end = 1024 + 100 + 100, 4350 .htotal = 1024 + 100 + 100 + 120, 4351 .vdisplay = 600, 4352 .vsync_start = 600 + 10, 4353 .vsync_end = 600 + 10 + 10, 4354 .vtotal = 600 + 10 + 10 + 15, 4355 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4356 }; 4357 4358 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4359 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4360 .num_modes = 1, 4361 .bpc = 8, 4362 .size = { 4363 .width = 154, 4364 .height = 90, 4365 }, 4366 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4367 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4368 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4369 }; 4370 4371 static const struct drm_display_mode arm_rtsm_mode[] = { 4372 { 4373 .clock = 65000, 4374 .hdisplay = 1024, 4375 .hsync_start = 1024 + 24, 4376 .hsync_end = 1024 + 24 + 136, 4377 .htotal = 1024 + 24 + 136 + 160, 4378 .vdisplay = 768, 4379 .vsync_start = 768 + 3, 4380 .vsync_end = 768 + 3 + 6, 4381 .vtotal = 768 + 3 + 6 + 29, 4382 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4383 }, 4384 }; 4385 4386 static const struct panel_desc arm_rtsm = { 4387 .modes = arm_rtsm_mode, 4388 .num_modes = 1, 4389 .bpc = 8, 4390 .size = { 4391 .width = 400, 4392 .height = 300, 4393 }, 4394 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4395 }; 4396 4397 static const struct of_device_id platform_of_match[] = { 4398 { 4399 .compatible = "ampire,am-1280800n3tzqw-t00h", 4400 .data = &ire_am_1280800n3tzqw_t00h, 4401 }, { 4402 .compatible = "ampire,am-480272h3tmqw-t01h", 4403 .data = &ire_am_480272h3tmqw_t01h, 4404 }, { 4405 .compatible = "ampire,am-800480l1tmqw-t00h", 4406 .data = &ire_am_800480l1tmqw_t00h, 4407 }, { 4408 .compatible = "ampire,am800480r3tmqwa1h", 4409 .data = &ire_am800480r3tmqwa1h, 4410 }, { 4411 .compatible = "ampire,am800600p5tmqw-tb8h", 4412 .data = &ire_am800600p5tmqwtb8h, 4413 }, { 4414 .compatible = "arm,rtsm-display", 4415 .data = &arm_rtsm, 4416 }, { 4417 .compatible = "armadeus,st0700-adapt", 4418 .data = &armadeus_st0700_adapt, 4419 }, { 4420 .compatible = "auo,b101aw03", 4421 .data = &auo_b101aw03, 4422 }, { 4423 .compatible = "auo,b101xtn01", 4424 .data = &auo_b101xtn01, 4425 }, { 4426 .compatible = "auo,b116xw03", 4427 .data = &auo_b116xw03, 4428 }, { 4429 .compatible = "auo,g070vvn01", 4430 .data = &auo_g070vvn01, 4431 }, { 4432 .compatible = "auo,g101evn010", 4433 .data = &auo_g101evn010, 4434 }, { 4435 .compatible = "auo,g104sn02", 4436 .data = &auo_g104sn02, 4437 }, { 4438 .compatible = "auo,g121ean01", 4439 .data = &auo_g121ean01, 4440 }, { 4441 .compatible = "auo,g133han01", 4442 .data = &auo_g133han01, 4443 }, { 4444 .compatible = "auo,g156han04", 4445 .data = &auo_g156han04, 4446 }, { 4447 .compatible = "auo,g156xtn01", 4448 .data = &auo_g156xtn01, 4449 }, { 4450 .compatible = "auo,g185han01", 4451 .data = &auo_g185han01, 4452 }, { 4453 .compatible = "auo,g190ean01", 4454 .data = &auo_g190ean01, 4455 }, { 4456 .compatible = "auo,p320hvn03", 4457 .data = &auo_p320hvn03, 4458 }, { 4459 .compatible = "auo,t215hvn01", 4460 .data = &auo_t215hvn01, 4461 }, { 4462 .compatible = "avic,tm070ddh03", 4463 .data = &avic_tm070ddh03, 4464 }, { 4465 .compatible = "bananapi,s070wv20-ct16", 4466 .data = &bananapi_s070wv20_ct16, 4467 }, { 4468 .compatible = "boe,bp082wx1-100", 4469 .data = &boe_bp082wx1_100, 4470 }, { 4471 .compatible = "boe,bp101wx1-100", 4472 .data = &boe_bp101wx1_100, 4473 }, { 4474 .compatible = "boe,ev121wxm-n10-1850", 4475 .data = &boe_ev121wxm_n10_1850, 4476 }, { 4477 .compatible = "boe,hv070wsa-100", 4478 .data = &boe_hv070wsa 4479 }, { 4480 .compatible = "cct,cmt430b19n00", 4481 .data = &cct_cmt430b19n00, 4482 }, { 4483 .compatible = "cdtech,s043wq26h-ct7", 4484 .data = &cdtech_s043wq26h_ct7, 4485 }, { 4486 .compatible = "cdtech,s070pws19hp-fc21", 4487 .data = &cdtech_s070pws19hp_fc21, 4488 }, { 4489 .compatible = "cdtech,s070swv29hg-dc44", 4490 .data = &cdtech_s070swv29hg_dc44, 4491 }, { 4492 .compatible = "cdtech,s070wv95-ct16", 4493 .data = &cdtech_s070wv95_ct16, 4494 }, { 4495 .compatible = "chefree,ch101olhlwh-002", 4496 .data = &chefree_ch101olhlwh_002, 4497 }, { 4498 .compatible = "chunghwa,claa070wp03xg", 4499 .data = &chunghwa_claa070wp03xg, 4500 }, { 4501 .compatible = "chunghwa,claa101wa01a", 4502 .data = &chunghwa_claa101wa01a 4503 }, { 4504 .compatible = "chunghwa,claa101wb01", 4505 .data = &chunghwa_claa101wb01 4506 }, { 4507 .compatible = "dataimage,fg040346dsswbg04", 4508 .data = &dataimage_fg040346dsswbg04, 4509 }, { 4510 .compatible = "dataimage,fg1001l0dsswmg01", 4511 .data = &dataimage_fg1001l0dsswmg01, 4512 }, { 4513 .compatible = "dataimage,scf0700c48ggu18", 4514 .data = &dataimage_scf0700c48ggu18, 4515 }, { 4516 .compatible = "dlc,dlc0700yzg-1", 4517 .data = &dlc_dlc0700yzg_1, 4518 }, { 4519 .compatible = "dlc,dlc1010gig", 4520 .data = &dlc_dlc1010gig, 4521 }, { 4522 .compatible = "edt,et035012dm6", 4523 .data = &edt_et035012dm6, 4524 }, { 4525 .compatible = "edt,etm0350g0dh6", 4526 .data = &edt_etm0350g0dh6, 4527 }, { 4528 .compatible = "edt,etm043080dh6gp", 4529 .data = &edt_etm043080dh6gp, 4530 }, { 4531 .compatible = "edt,etm0430g0dh6", 4532 .data = &edt_etm0430g0dh6, 4533 }, { 4534 .compatible = "edt,et057090dhu", 4535 .data = &edt_et057090dhu, 4536 }, { 4537 .compatible = "edt,et070080dh6", 4538 .data = &edt_etm0700g0dh6, 4539 }, { 4540 .compatible = "edt,etm0700g0dh6", 4541 .data = &edt_etm0700g0dh6, 4542 }, { 4543 .compatible = "edt,etm0700g0bdh6", 4544 .data = &edt_etm0700g0bdh6, 4545 }, { 4546 .compatible = "edt,etm0700g0edh6", 4547 .data = &edt_etm0700g0bdh6, 4548 }, { 4549 .compatible = "edt,etml0700y5dha", 4550 .data = &edt_etml0700y5dha, 4551 }, { 4552 .compatible = "edt,etml1010g3dra", 4553 .data = &edt_etml1010g3dra, 4554 }, { 4555 .compatible = "edt,etmv570g2dhu", 4556 .data = &edt_etmv570g2dhu, 4557 }, { 4558 .compatible = "eink,vb3300-kca", 4559 .data = &eink_vb3300_kca, 4560 }, { 4561 .compatible = "evervision,vgg644804", 4562 .data = &evervision_vgg644804, 4563 }, { 4564 .compatible = "evervision,vgg804821", 4565 .data = &evervision_vgg804821, 4566 }, { 4567 .compatible = "foxlink,fl500wvr00-a0t", 4568 .data = &foxlink_fl500wvr00_a0t, 4569 }, { 4570 .compatible = "frida,frd350h54004", 4571 .data = &frida_frd350h54004, 4572 }, { 4573 .compatible = "friendlyarm,hd702e", 4574 .data = &friendlyarm_hd702e, 4575 }, { 4576 .compatible = "giantplus,gpg482739qs5", 4577 .data = &giantplus_gpg482739qs5 4578 }, { 4579 .compatible = "giantplus,gpm940b0", 4580 .data = &giantplus_gpm940b0, 4581 }, { 4582 .compatible = "hannstar,hsd070pww1", 4583 .data = &hannstar_hsd070pww1, 4584 }, { 4585 .compatible = "hannstar,hsd100pxn1", 4586 .data = &hannstar_hsd100pxn1, 4587 }, { 4588 .compatible = "hannstar,hsd101pww2", 4589 .data = &hannstar_hsd101pww2, 4590 }, { 4591 .compatible = "hit,tx23d38vm0caa", 4592 .data = &hitachi_tx23d38vm0caa 4593 }, { 4594 .compatible = "innolux,at043tn24", 4595 .data = &innolux_at043tn24, 4596 }, { 4597 .compatible = "innolux,at070tn92", 4598 .data = &innolux_at070tn92, 4599 }, { 4600 .compatible = "innolux,g070ace-l01", 4601 .data = &innolux_g070ace_l01, 4602 }, { 4603 .compatible = "innolux,g070y2-l01", 4604 .data = &innolux_g070y2_l01, 4605 }, { 4606 .compatible = "innolux,g070y2-t02", 4607 .data = &innolux_g070y2_t02, 4608 }, { 4609 .compatible = "innolux,g101ice-l01", 4610 .data = &innolux_g101ice_l01 4611 }, { 4612 .compatible = "innolux,g121i1-l01", 4613 .data = &innolux_g121i1_l01 4614 }, { 4615 .compatible = "innolux,g121x1-l03", 4616 .data = &innolux_g121x1_l03, 4617 }, { 4618 .compatible = "innolux,g121xce-l01", 4619 .data = &innolux_g121xce_l01, 4620 }, { 4621 .compatible = "innolux,g156hce-l01", 4622 .data = &innolux_g156hce_l01, 4623 }, { 4624 .compatible = "innolux,n156bge-l21", 4625 .data = &innolux_n156bge_l21, 4626 }, { 4627 .compatible = "innolux,zj070na-01p", 4628 .data = &innolux_zj070na_01p, 4629 }, { 4630 .compatible = "koe,tx14d24vm1bpa", 4631 .data = &koe_tx14d24vm1bpa, 4632 }, { 4633 .compatible = "koe,tx26d202vm0bwa", 4634 .data = &koe_tx26d202vm0bwa, 4635 }, { 4636 .compatible = "koe,tx31d200vm0baa", 4637 .data = &koe_tx31d200vm0baa, 4638 }, { 4639 .compatible = "kyo,tcg121xglp", 4640 .data = &kyo_tcg121xglp, 4641 }, { 4642 .compatible = "lemaker,bl035-rgb-002", 4643 .data = &lemaker_bl035_rgb_002, 4644 }, { 4645 .compatible = "lg,lb070wv8", 4646 .data = &lg_lb070wv8, 4647 }, { 4648 .compatible = "logicpd,type28", 4649 .data = &logicpd_type_28, 4650 }, { 4651 .compatible = "logictechno,lt161010-2nhc", 4652 .data = &logictechno_lt161010_2nh, 4653 }, { 4654 .compatible = "logictechno,lt161010-2nhr", 4655 .data = &logictechno_lt161010_2nh, 4656 }, { 4657 .compatible = "logictechno,lt170410-2whc", 4658 .data = &logictechno_lt170410_2whc, 4659 }, { 4660 .compatible = "logictechno,lttd800480070-l2rt", 4661 .data = &logictechno_lttd800480070_l2rt, 4662 }, { 4663 .compatible = "logictechno,lttd800480070-l6wh-rt", 4664 .data = &logictechno_lttd800480070_l6wh_rt, 4665 }, { 4666 .compatible = "mitsubishi,aa070mc01-ca1", 4667 .data = &mitsubishi_aa070mc01, 4668 }, { 4669 .compatible = "mitsubishi,aa084xe01", 4670 .data = &mitsubishi_aa084xe01, 4671 }, { 4672 .compatible = "multi-inno,mi0700s4t-6", 4673 .data = &multi_inno_mi0700s4t_6, 4674 }, { 4675 .compatible = "multi-inno,mi0800ft-9", 4676 .data = &multi_inno_mi0800ft_9, 4677 }, { 4678 .compatible = "multi-inno,mi1010ait-1cp", 4679 .data = &multi_inno_mi1010ait_1cp, 4680 }, { 4681 .compatible = "nec,nl12880bc20-05", 4682 .data = &nec_nl12880bc20_05, 4683 }, { 4684 .compatible = "nec,nl4827hc19-05b", 4685 .data = &nec_nl4827hc19_05b, 4686 }, { 4687 .compatible = "netron-dy,e231732", 4688 .data = &netron_dy_e231732, 4689 }, { 4690 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4691 .data = &newhaven_nhd_43_480272ef_atxl, 4692 }, { 4693 .compatible = "nlt,nl192108ac18-02d", 4694 .data = &nlt_nl192108ac18_02d, 4695 }, { 4696 .compatible = "nvd,9128", 4697 .data = &nvd_9128, 4698 }, { 4699 .compatible = "okaya,rs800480t-7x0gp", 4700 .data = &okaya_rs800480t_7x0gp, 4701 }, { 4702 .compatible = "olimex,lcd-olinuxino-43-ts", 4703 .data = &olimex_lcd_olinuxino_43ts, 4704 }, { 4705 .compatible = "ontat,yx700wv03", 4706 .data = &ontat_yx700wv03, 4707 }, { 4708 .compatible = "ortustech,com37h3m05dtc", 4709 .data = &ortustech_com37h3m, 4710 }, { 4711 .compatible = "ortustech,com37h3m99dtc", 4712 .data = &ortustech_com37h3m, 4713 }, { 4714 .compatible = "ortustech,com43h4m85ulc", 4715 .data = &ortustech_com43h4m85ulc, 4716 }, { 4717 .compatible = "osddisplays,osd070t1718-19ts", 4718 .data = &osddisplays_osd070t1718_19ts, 4719 }, { 4720 .compatible = "pda,91-00156-a0", 4721 .data = &pda_91_00156_a0, 4722 }, { 4723 .compatible = "powertip,ph128800t006-zhc01", 4724 .data = &powertip_ph128800t006_zhc01, 4725 }, { 4726 .compatible = "powertip,ph800480t013-idf02", 4727 .data = &powertip_ph800480t013_idf02, 4728 }, { 4729 .compatible = "qiaodian,qd43003c0-40", 4730 .data = &qd43003c0_40, 4731 }, { 4732 .compatible = "qishenglong,gopher2b-lcd", 4733 .data = &qishenglong_gopher2b_lcd, 4734 }, { 4735 .compatible = "rocktech,rk043fn48h", 4736 .data = &rocktech_rk043fn48h, 4737 }, { 4738 .compatible = "rocktech,rk070er9427", 4739 .data = &rocktech_rk070er9427, 4740 }, { 4741 .compatible = "rocktech,rk101ii01d-ct", 4742 .data = &rocktech_rk101ii01d_ct, 4743 }, { 4744 .compatible = "samsung,ltl101al01", 4745 .data = &samsung_ltl101al01, 4746 }, { 4747 .compatible = "samsung,ltn101nt05", 4748 .data = &samsung_ltn101nt05, 4749 }, { 4750 .compatible = "satoz,sat050at40h12r2", 4751 .data = &satoz_sat050at40h12r2, 4752 }, { 4753 .compatible = "sharp,lq035q7db03", 4754 .data = &sharp_lq035q7db03, 4755 }, { 4756 .compatible = "sharp,lq070y3dg3b", 4757 .data = &sharp_lq070y3dg3b, 4758 }, { 4759 .compatible = "sharp,lq101k1ly04", 4760 .data = &sharp_lq101k1ly04, 4761 }, { 4762 .compatible = "sharp,ls020b1dd01d", 4763 .data = &sharp_ls020b1dd01d, 4764 }, { 4765 .compatible = "shelly,sca07010-bfn-lnn", 4766 .data = &shelly_sca07010_bfn_lnn, 4767 }, { 4768 .compatible = "starry,kr070pe2t", 4769 .data = &starry_kr070pe2t, 4770 }, { 4771 .compatible = "startek,kd070wvfpa", 4772 .data = &startek_kd070wvfpa, 4773 }, { 4774 .compatible = "team-source-display,tst043015cmhx", 4775 .data = &tsd_tst043015cmhx, 4776 }, { 4777 .compatible = "tfc,s9700rtwv43tr-01b", 4778 .data = &tfc_s9700rtwv43tr_01b, 4779 }, { 4780 .compatible = "tianma,tm070jdhg30", 4781 .data = &tianma_tm070jdhg30, 4782 }, { 4783 .compatible = "tianma,tm070jvhg33", 4784 .data = &tianma_tm070jvhg33, 4785 }, { 4786 .compatible = "tianma,tm070rvhg71", 4787 .data = &tianma_tm070rvhg71, 4788 }, { 4789 .compatible = "ti,nspire-cx-lcd-panel", 4790 .data = &ti_nspire_cx_lcd_panel, 4791 }, { 4792 .compatible = "ti,nspire-classic-lcd-panel", 4793 .data = &ti_nspire_classic_lcd_panel, 4794 }, { 4795 .compatible = "toshiba,lt089ac29000", 4796 .data = &toshiba_lt089ac29000, 4797 }, { 4798 .compatible = "tpk,f07a-0102", 4799 .data = &tpk_f07a_0102, 4800 }, { 4801 .compatible = "tpk,f10a-0102", 4802 .data = &tpk_f10a_0102, 4803 }, { 4804 .compatible = "urt,umsh-8596md-t", 4805 .data = &urt_umsh_8596md_parallel, 4806 }, { 4807 .compatible = "urt,umsh-8596md-1t", 4808 .data = &urt_umsh_8596md_parallel, 4809 }, { 4810 .compatible = "urt,umsh-8596md-7t", 4811 .data = &urt_umsh_8596md_parallel, 4812 }, { 4813 .compatible = "urt,umsh-8596md-11t", 4814 .data = &urt_umsh_8596md_lvds, 4815 }, { 4816 .compatible = "urt,umsh-8596md-19t", 4817 .data = &urt_umsh_8596md_lvds, 4818 }, { 4819 .compatible = "urt,umsh-8596md-20t", 4820 .data = &urt_umsh_8596md_parallel, 4821 }, { 4822 .compatible = "vivax,tpc9150-panel", 4823 .data = &vivax_tpc9150_panel, 4824 }, { 4825 .compatible = "vxt,vl050-8048nt-c01", 4826 .data = &vl050_8048nt_c01, 4827 }, { 4828 .compatible = "winstar,wf35ltiacd", 4829 .data = &winstar_wf35ltiacd, 4830 }, { 4831 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4832 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4833 }, { 4834 /* Must be the last entry */ 4835 .compatible = "panel-dpi", 4836 .data = &panel_dpi, 4837 }, { 4838 /* sentinel */ 4839 } 4840 }; 4841 MODULE_DEVICE_TABLE(of, platform_of_match); 4842 4843 static int panel_simple_platform_probe(struct platform_device *pdev) 4844 { 4845 const struct panel_desc *desc; 4846 4847 desc = of_device_get_match_data(&pdev->dev); 4848 if (!desc) 4849 return -ENODEV; 4850 4851 return panel_simple_probe(&pdev->dev, desc); 4852 } 4853 4854 static void panel_simple_platform_remove(struct platform_device *pdev) 4855 { 4856 panel_simple_remove(&pdev->dev); 4857 } 4858 4859 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4860 { 4861 panel_simple_shutdown(&pdev->dev); 4862 } 4863 4864 static const struct dev_pm_ops panel_simple_pm_ops = { 4865 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4866 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4867 pm_runtime_force_resume) 4868 }; 4869 4870 static struct platform_driver panel_simple_platform_driver = { 4871 .driver = { 4872 .name = "panel-simple", 4873 .of_match_table = platform_of_match, 4874 .pm = &panel_simple_pm_ops, 4875 }, 4876 .probe = panel_simple_platform_probe, 4877 .remove_new = panel_simple_platform_remove, 4878 .shutdown = panel_simple_platform_shutdown, 4879 }; 4880 4881 struct panel_desc_dsi { 4882 struct panel_desc desc; 4883 4884 unsigned long flags; 4885 enum mipi_dsi_pixel_format format; 4886 unsigned int lanes; 4887 }; 4888 4889 static const struct drm_display_mode auo_b080uan01_mode = { 4890 .clock = 154500, 4891 .hdisplay = 1200, 4892 .hsync_start = 1200 + 62, 4893 .hsync_end = 1200 + 62 + 4, 4894 .htotal = 1200 + 62 + 4 + 62, 4895 .vdisplay = 1920, 4896 .vsync_start = 1920 + 9, 4897 .vsync_end = 1920 + 9 + 2, 4898 .vtotal = 1920 + 9 + 2 + 8, 4899 }; 4900 4901 static const struct panel_desc_dsi auo_b080uan01 = { 4902 .desc = { 4903 .modes = &auo_b080uan01_mode, 4904 .num_modes = 1, 4905 .bpc = 8, 4906 .size = { 4907 .width = 108, 4908 .height = 272, 4909 }, 4910 .connector_type = DRM_MODE_CONNECTOR_DSI, 4911 }, 4912 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4913 .format = MIPI_DSI_FMT_RGB888, 4914 .lanes = 4, 4915 }; 4916 4917 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4918 .clock = 160000, 4919 .hdisplay = 1200, 4920 .hsync_start = 1200 + 120, 4921 .hsync_end = 1200 + 120 + 20, 4922 .htotal = 1200 + 120 + 20 + 21, 4923 .vdisplay = 1920, 4924 .vsync_start = 1920 + 21, 4925 .vsync_end = 1920 + 21 + 3, 4926 .vtotal = 1920 + 21 + 3 + 18, 4927 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4928 }; 4929 4930 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4931 .desc = { 4932 .modes = &boe_tv080wum_nl0_mode, 4933 .num_modes = 1, 4934 .size = { 4935 .width = 107, 4936 .height = 172, 4937 }, 4938 .connector_type = DRM_MODE_CONNECTOR_DSI, 4939 }, 4940 .flags = MIPI_DSI_MODE_VIDEO | 4941 MIPI_DSI_MODE_VIDEO_BURST | 4942 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4943 .format = MIPI_DSI_FMT_RGB888, 4944 .lanes = 4, 4945 }; 4946 4947 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4948 .clock = 71000, 4949 .hdisplay = 800, 4950 .hsync_start = 800 + 32, 4951 .hsync_end = 800 + 32 + 1, 4952 .htotal = 800 + 32 + 1 + 57, 4953 .vdisplay = 1280, 4954 .vsync_start = 1280 + 28, 4955 .vsync_end = 1280 + 28 + 1, 4956 .vtotal = 1280 + 28 + 1 + 14, 4957 }; 4958 4959 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4960 .desc = { 4961 .modes = &lg_ld070wx3_sl01_mode, 4962 .num_modes = 1, 4963 .bpc = 8, 4964 .size = { 4965 .width = 94, 4966 .height = 151, 4967 }, 4968 .connector_type = DRM_MODE_CONNECTOR_DSI, 4969 }, 4970 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4971 .format = MIPI_DSI_FMT_RGB888, 4972 .lanes = 4, 4973 }; 4974 4975 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4976 .clock = 67000, 4977 .hdisplay = 720, 4978 .hsync_start = 720 + 12, 4979 .hsync_end = 720 + 12 + 4, 4980 .htotal = 720 + 12 + 4 + 112, 4981 .vdisplay = 1280, 4982 .vsync_start = 1280 + 8, 4983 .vsync_end = 1280 + 8 + 4, 4984 .vtotal = 1280 + 8 + 4 + 12, 4985 }; 4986 4987 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4988 .desc = { 4989 .modes = &lg_lh500wx1_sd03_mode, 4990 .num_modes = 1, 4991 .bpc = 8, 4992 .size = { 4993 .width = 62, 4994 .height = 110, 4995 }, 4996 .connector_type = DRM_MODE_CONNECTOR_DSI, 4997 }, 4998 .flags = MIPI_DSI_MODE_VIDEO, 4999 .format = MIPI_DSI_FMT_RGB888, 5000 .lanes = 4, 5001 }; 5002 5003 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5004 .clock = 157200, 5005 .hdisplay = 1920, 5006 .hsync_start = 1920 + 154, 5007 .hsync_end = 1920 + 154 + 16, 5008 .htotal = 1920 + 154 + 16 + 32, 5009 .vdisplay = 1200, 5010 .vsync_start = 1200 + 17, 5011 .vsync_end = 1200 + 17 + 2, 5012 .vtotal = 1200 + 17 + 2 + 16, 5013 }; 5014 5015 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5016 .desc = { 5017 .modes = &panasonic_vvx10f004b00_mode, 5018 .num_modes = 1, 5019 .bpc = 8, 5020 .size = { 5021 .width = 217, 5022 .height = 136, 5023 }, 5024 .connector_type = DRM_MODE_CONNECTOR_DSI, 5025 }, 5026 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5027 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5028 .format = MIPI_DSI_FMT_RGB888, 5029 .lanes = 4, 5030 }; 5031 5032 static const struct drm_display_mode lg_acx467akm_7_mode = { 5033 .clock = 150000, 5034 .hdisplay = 1080, 5035 .hsync_start = 1080 + 2, 5036 .hsync_end = 1080 + 2 + 2, 5037 .htotal = 1080 + 2 + 2 + 2, 5038 .vdisplay = 1920, 5039 .vsync_start = 1920 + 2, 5040 .vsync_end = 1920 + 2 + 2, 5041 .vtotal = 1920 + 2 + 2 + 2, 5042 }; 5043 5044 static const struct panel_desc_dsi lg_acx467akm_7 = { 5045 .desc = { 5046 .modes = &lg_acx467akm_7_mode, 5047 .num_modes = 1, 5048 .bpc = 8, 5049 .size = { 5050 .width = 62, 5051 .height = 110, 5052 }, 5053 .connector_type = DRM_MODE_CONNECTOR_DSI, 5054 }, 5055 .flags = 0, 5056 .format = MIPI_DSI_FMT_RGB888, 5057 .lanes = 4, 5058 }; 5059 5060 static const struct drm_display_mode osd101t2045_53ts_mode = { 5061 .clock = 154500, 5062 .hdisplay = 1920, 5063 .hsync_start = 1920 + 112, 5064 .hsync_end = 1920 + 112 + 16, 5065 .htotal = 1920 + 112 + 16 + 32, 5066 .vdisplay = 1200, 5067 .vsync_start = 1200 + 16, 5068 .vsync_end = 1200 + 16 + 2, 5069 .vtotal = 1200 + 16 + 2 + 16, 5070 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5071 }; 5072 5073 static const struct panel_desc_dsi osd101t2045_53ts = { 5074 .desc = { 5075 .modes = &osd101t2045_53ts_mode, 5076 .num_modes = 1, 5077 .bpc = 8, 5078 .size = { 5079 .width = 217, 5080 .height = 136, 5081 }, 5082 .connector_type = DRM_MODE_CONNECTOR_DSI, 5083 }, 5084 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5085 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5086 MIPI_DSI_MODE_NO_EOT_PACKET, 5087 .format = MIPI_DSI_FMT_RGB888, 5088 .lanes = 4, 5089 }; 5090 5091 static const struct of_device_id dsi_of_match[] = { 5092 { 5093 .compatible = "auo,b080uan01", 5094 .data = &auo_b080uan01 5095 }, { 5096 .compatible = "boe,tv080wum-nl0", 5097 .data = &boe_tv080wum_nl0 5098 }, { 5099 .compatible = "lg,ld070wx3-sl01", 5100 .data = &lg_ld070wx3_sl01 5101 }, { 5102 .compatible = "lg,lh500wx1-sd03", 5103 .data = &lg_lh500wx1_sd03 5104 }, { 5105 .compatible = "panasonic,vvx10f004b00", 5106 .data = &panasonic_vvx10f004b00 5107 }, { 5108 .compatible = "lg,acx467akm-7", 5109 .data = &lg_acx467akm_7 5110 }, { 5111 .compatible = "osddisplays,osd101t2045-53ts", 5112 .data = &osd101t2045_53ts 5113 }, { 5114 /* sentinel */ 5115 } 5116 }; 5117 MODULE_DEVICE_TABLE(of, dsi_of_match); 5118 5119 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5120 { 5121 const struct panel_desc_dsi *desc; 5122 int err; 5123 5124 desc = of_device_get_match_data(&dsi->dev); 5125 if (!desc) 5126 return -ENODEV; 5127 5128 err = panel_simple_probe(&dsi->dev, &desc->desc); 5129 if (err < 0) 5130 return err; 5131 5132 dsi->mode_flags = desc->flags; 5133 dsi->format = desc->format; 5134 dsi->lanes = desc->lanes; 5135 5136 err = mipi_dsi_attach(dsi); 5137 if (err) { 5138 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5139 5140 drm_panel_remove(&panel->base); 5141 } 5142 5143 return err; 5144 } 5145 5146 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5147 { 5148 int err; 5149 5150 err = mipi_dsi_detach(dsi); 5151 if (err < 0) 5152 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5153 5154 panel_simple_remove(&dsi->dev); 5155 } 5156 5157 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5158 { 5159 panel_simple_shutdown(&dsi->dev); 5160 } 5161 5162 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5163 .driver = { 5164 .name = "panel-simple-dsi", 5165 .of_match_table = dsi_of_match, 5166 .pm = &panel_simple_pm_ops, 5167 }, 5168 .probe = panel_simple_dsi_probe, 5169 .remove = panel_simple_dsi_remove, 5170 .shutdown = panel_simple_dsi_shutdown, 5171 }; 5172 5173 static int __init panel_simple_init(void) 5174 { 5175 int err; 5176 5177 err = platform_driver_register(&panel_simple_platform_driver); 5178 if (err < 0) 5179 return err; 5180 5181 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5182 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5183 if (err < 0) 5184 goto err_did_platform_register; 5185 } 5186 5187 return 0; 5188 5189 err_did_platform_register: 5190 platform_driver_unregister(&panel_simple_platform_driver); 5191 5192 return err; 5193 } 5194 module_init(panel_simple_init); 5195 5196 static void __exit panel_simple_exit(void) 5197 { 5198 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5199 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5200 5201 platform_driver_unregister(&panel_simple_platform_driver); 5202 } 5203 module_exit(panel_simple_exit); 5204 5205 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5206 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5207 MODULE_LICENSE("GPL and additional rights"); 5208