1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/module.h> 12 #include <linux/regulator/consumer.h> 13 14 #include <video/mipi_display.h> 15 16 #include <drm/drm_mipi_dsi.h> 17 #include <drm/drm_modes.h> 18 #include <drm/drm_panel.h> 19 20 /*** Manufacturer Command Set ***/ 21 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */ 22 #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */ 23 #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */ 24 #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */ 25 #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */ 26 #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */ 27 28 /* CMD2 P0 commands (Display Options and Power) */ 29 #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */ 30 #define MCS_SGOPCTR 0x16 /* Source Bias Current */ 31 #define MCS_SDCTR 0x1A /* Source Output Delay Time */ 32 #define MCS_INVCTR 0x1B /* Inversion Type */ 33 #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */ 34 #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */ 35 #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */ 36 #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */ 37 #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */ 38 #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */ 39 #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */ 40 #define MCS_SETVGN 0x52 /* VG M/S N Control */ 41 #define MCS_SETVGP 0x54 /* VG M/S P Control */ 42 #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */ 43 44 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */ 45 #define GOA_VSTV1 0x00 46 #define GOA_VSTV2 0x07 47 #define GOA_VCLK1 0x0E 48 #define GOA_VCLK2 0x17 49 #define GOA_VCLK_OPT1 0x20 50 #define GOA_BICLK1 0x2A 51 #define GOA_BICLK2 0x37 52 #define GOA_BICLK3 0x44 53 #define GOA_BICLK4 0x4F 54 #define GOA_BICLK_OPT1 0x5B 55 #define GOA_BICLK_OPT2 0x60 56 #define MCS_GOA_GPO1 0x6D 57 #define MCS_GOA_GPO2 0x71 58 #define MCS_GOA_EQ 0x74 59 #define MCS_GOA_CLK_GALLON 0x7C 60 #define MCS_GOA_FS_SEL0 0x7E 61 #define MCS_GOA_FS_SEL1 0x87 62 #define MCS_GOA_FS_SEL2 0x91 63 #define MCS_GOA_FS_SEL3 0x9B 64 #define MCS_GOA_BS_SEL0 0xAC 65 #define MCS_GOA_BS_SEL1 0xB5 66 #define MCS_GOA_BS_SEL2 0xBF 67 #define MCS_GOA_BS_SEL3 0xC9 68 #define MCS_GOA_BS_SEL4 0xD3 69 70 /* CMD2 P3 commands (Gamma) */ 71 #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */ 72 #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */ 73 74 struct rm68200 { 75 struct device *dev; 76 struct drm_panel panel; 77 struct gpio_desc *reset_gpio; 78 struct regulator *supply; 79 }; 80 81 static const struct drm_display_mode default_mode = { 82 .clock = 54000, 83 .hdisplay = 720, 84 .hsync_start = 720 + 48, 85 .hsync_end = 720 + 48 + 9, 86 .htotal = 720 + 48 + 9 + 48, 87 .vdisplay = 1280, 88 .vsync_start = 1280 + 12, 89 .vsync_end = 1280 + 12 + 5, 90 .vtotal = 1280 + 12 + 5 + 12, 91 .flags = 0, 92 .width_mm = 68, 93 .height_mm = 122, 94 }; 95 96 static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel) 97 { 98 return container_of(panel, struct rm68200, panel); 99 } 100 101 static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data, 102 size_t len) 103 { 104 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 105 int err; 106 107 err = mipi_dsi_dcs_write_buffer(dsi, data, len); 108 if (err < 0) 109 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err); 110 } 111 112 static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value) 113 { 114 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 115 int err; 116 117 err = mipi_dsi_dcs_write(dsi, cmd, &value, 1); 118 if (err < 0) 119 dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err); 120 } 121 122 #define dcs_write_seq(ctx, seq...) \ 123 ({ \ 124 static const u8 d[] = { seq }; \ 125 \ 126 rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ 127 }) 128 129 /* 130 * This panel is not able to auto-increment all cmd addresses so for some of 131 * them, we need to send them one by one... 132 */ 133 #define dcs_write_cmd_seq(ctx, cmd, seq...) \ 134 ({ \ 135 static const u8 d[] = { seq }; \ 136 unsigned int i; \ 137 \ 138 for (i = 0; i < ARRAY_SIZE(d) ; i++) \ 139 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \ 140 }) 141 142 static void rm68200_init_sequence(struct rm68200 *ctx) 143 { 144 /* Enter CMD2 with page 0 */ 145 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0); 146 dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00); 147 dcs_write_seq(ctx, MCS_BT2CTR, 0xE5); 148 dcs_write_seq(ctx, MCS_SETAVDD, 0x0A); 149 dcs_write_seq(ctx, MCS_SETAVEE, 0x0A); 150 dcs_write_seq(ctx, MCS_SGOPCTR, 0x52); 151 dcs_write_seq(ctx, MCS_BT3CTR, 0x53); 152 dcs_write_seq(ctx, MCS_BT4CTR, 0x5A); 153 dcs_write_seq(ctx, MCS_INVCTR, 0x00); 154 dcs_write_seq(ctx, MCS_STBCTR, 0x0A); 155 dcs_write_seq(ctx, MCS_SDCTR, 0x06); 156 dcs_write_seq(ctx, MCS_VCMCTR, 0x56); 157 dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00); 158 dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00); 159 dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */ 160 161 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2); 162 dcs_write_seq(ctx, GOA_VSTV1, 0x05); 163 dcs_write_seq(ctx, 0x02, 0x0B); 164 dcs_write_seq(ctx, 0x03, 0x0F); 165 dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50); 166 dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00, 167 0x50); 168 dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D, 169 0x00, 0x85, 0x08); 170 dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D, 171 0x00, 0x85, 0x08); 172 dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 173 0x00, 0x00, 0x00, 0x00); 174 dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08); 175 dcs_write_seq(ctx, 0x2D, 0x01); 176 dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D, 177 0x00); 178 dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00); 179 dcs_write_seq(ctx, 0x3D, 0x40); 180 dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00); 181 dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 182 0x00, 0x00, 0x00, 0x00, 0x00); 183 dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 184 0x00, 0x00); 185 dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00); 186 dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00); 187 dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 189 dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00); 190 dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00); 191 dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 192 0x00, 0x00); 193 dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00); 194 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10, 195 0x16, 0x12, 0x08, 0x3F); 196 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C, 197 0x0A, 0x0E, 0x3F, 0x3F, 0x00); 198 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F, 199 0x05, 0x01, 0x3F, 0x3F, 0x0F); 200 dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F, 201 0x3F); 202 dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15); 203 dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F); 204 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13, 205 0x15, 0x11, 0x0F, 0x3F); 206 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B, 207 0x0D, 0x09, 0x3F, 0x3F, 0x07); 208 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F, 209 0x02, 0x06, 0x3F, 0x3F, 0x08); 210 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F, 211 0x3F, 0x3F, 0x0E, 0x10, 0x14); 212 dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F); 213 dcs_write_seq(ctx, 0xDC, 0x02); 214 dcs_write_seq(ctx, 0xDE, 0x12); 215 216 dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */ 217 dcs_write_seq(ctx, 0x01, 0x75); 218 219 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3); 220 dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06, 221 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, 222 0x12, 0x0C, 0x00); 223 dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06, 224 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F, 225 0x12, 0x0C, 0x00); 226 227 /* Exit CMD2 */ 228 dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS); 229 } 230 231 static int rm68200_unprepare(struct drm_panel *panel) 232 { 233 struct rm68200 *ctx = panel_to_rm68200(panel); 234 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 235 int ret; 236 237 ret = mipi_dsi_dcs_set_display_off(dsi); 238 if (ret) 239 dev_warn(panel->dev, "failed to set display off: %d\n", ret); 240 241 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 242 if (ret) 243 dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret); 244 245 msleep(120); 246 247 if (ctx->reset_gpio) { 248 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 249 msleep(20); 250 } 251 252 regulator_disable(ctx->supply); 253 254 return 0; 255 } 256 257 static int rm68200_prepare(struct drm_panel *panel) 258 { 259 struct rm68200 *ctx = panel_to_rm68200(panel); 260 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 261 int ret; 262 263 ret = regulator_enable(ctx->supply); 264 if (ret < 0) { 265 dev_err(ctx->dev, "failed to enable supply: %d\n", ret); 266 return ret; 267 } 268 269 if (ctx->reset_gpio) { 270 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 271 msleep(20); 272 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 273 msleep(100); 274 } 275 276 rm68200_init_sequence(ctx); 277 278 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 279 if (ret) 280 return ret; 281 282 msleep(125); 283 284 ret = mipi_dsi_dcs_set_display_on(dsi); 285 if (ret) 286 return ret; 287 288 msleep(20); 289 290 return 0; 291 } 292 293 static int rm68200_get_modes(struct drm_panel *panel, 294 struct drm_connector *connector) 295 { 296 struct drm_display_mode *mode; 297 298 mode = drm_mode_duplicate(connector->dev, &default_mode); 299 if (!mode) { 300 dev_err(panel->dev, "failed to add mode %ux%u@%u\n", 301 default_mode.hdisplay, default_mode.vdisplay, 302 drm_mode_vrefresh(&default_mode)); 303 return -ENOMEM; 304 } 305 306 drm_mode_set_name(mode); 307 308 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 309 drm_mode_probed_add(connector, mode); 310 311 connector->display_info.width_mm = mode->width_mm; 312 connector->display_info.height_mm = mode->height_mm; 313 314 return 1; 315 } 316 317 static const struct drm_panel_funcs rm68200_drm_funcs = { 318 .unprepare = rm68200_unprepare, 319 .prepare = rm68200_prepare, 320 .get_modes = rm68200_get_modes, 321 }; 322 323 static int rm68200_probe(struct mipi_dsi_device *dsi) 324 { 325 struct device *dev = &dsi->dev; 326 struct rm68200 *ctx; 327 int ret; 328 329 ctx = devm_drm_panel_alloc(dev, struct rm68200, panel, 330 &rm68200_drm_funcs, 331 DRM_MODE_CONNECTOR_DSI); 332 if (IS_ERR(ctx)) 333 return PTR_ERR(ctx); 334 335 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 336 if (IS_ERR(ctx->reset_gpio)) { 337 ret = PTR_ERR(ctx->reset_gpio); 338 dev_err(dev, "cannot get reset GPIO: %d\n", ret); 339 return ret; 340 } 341 342 ctx->supply = devm_regulator_get(dev, "power"); 343 if (IS_ERR(ctx->supply)) { 344 ret = PTR_ERR(ctx->supply); 345 if (ret != -EPROBE_DEFER) 346 dev_err(dev, "cannot get regulator: %d\n", ret); 347 return ret; 348 } 349 350 mipi_dsi_set_drvdata(dsi, ctx); 351 352 ctx->dev = dev; 353 354 dsi->lanes = 2; 355 dsi->format = MIPI_DSI_FMT_RGB888; 356 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 357 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; 358 359 ret = drm_panel_of_backlight(&ctx->panel); 360 if (ret) 361 return ret; 362 363 drm_panel_add(&ctx->panel); 364 365 ret = mipi_dsi_attach(dsi); 366 if (ret < 0) { 367 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret); 368 drm_panel_remove(&ctx->panel); 369 return ret; 370 } 371 372 return 0; 373 } 374 375 static void rm68200_remove(struct mipi_dsi_device *dsi) 376 { 377 struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi); 378 379 mipi_dsi_detach(dsi); 380 drm_panel_remove(&ctx->panel); 381 } 382 383 static const struct of_device_id raydium_rm68200_of_match[] = { 384 { .compatible = "raydium,rm68200" }, 385 { } 386 }; 387 MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match); 388 389 static struct mipi_dsi_driver raydium_rm68200_driver = { 390 .probe = rm68200_probe, 391 .remove = rm68200_remove, 392 .driver = { 393 .name = "panel-raydium-rm68200", 394 .of_match_table = raydium_rm68200_of_match, 395 }, 396 }; 397 module_mipi_dsi_driver(raydium_rm68200_driver); 398 399 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 400 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 401 MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel"); 402 MODULE_LICENSE("GPL v2"); 403