1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/backlight.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/module.h> 13 #include <linux/regulator/consumer.h> 14 15 #include <video/mipi_display.h> 16 17 #include <drm/drm_mipi_dsi.h> 18 #include <drm/drm_modes.h> 19 #include <drm/drm_panel.h> 20 21 #define OTM8009A_BACKLIGHT_DEFAULT 240 22 #define OTM8009A_BACKLIGHT_MAX 255 23 24 /* Manufacturer Command Set */ 25 #define MCS_ADRSFT 0x0000 /* Address Shift Function */ 26 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */ 27 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */ 28 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */ 29 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */ 30 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */ 31 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */ 32 #define MCS_NO_DOC1 0xC48A /* Command not documented */ 33 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */ 34 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */ 35 #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */ 36 #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */ 37 #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */ 38 #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */ 39 #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */ 40 #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */ 41 #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */ 42 #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */ 43 #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */ 44 #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */ 45 #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */ 46 #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */ 47 #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */ 48 #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */ 49 #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */ 50 #define MCS_GOAVST 0xCE80 /* GOA VST Setting */ 51 #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */ 52 #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */ 53 #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */ 54 #define MCS_NO_DOC2 0xCFD0 /* Command not documented */ 55 #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */ 56 #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */ 57 #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */ 58 #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */ 59 #define MCS_NO_DOC3 0xF5B6 /* Command not documented */ 60 #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */ 61 #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */ 62 63 #define OTM8009A_HDISPLAY 480 64 #define OTM8009A_VDISPLAY 800 65 66 struct otm8009a { 67 struct device *dev; 68 struct drm_panel panel; 69 struct backlight_device *bl_dev; 70 struct gpio_desc *reset_gpio; 71 struct regulator *supply; 72 bool prepared; 73 bool enabled; 74 }; 75 76 static const struct drm_display_mode modes[] = { 77 { /* 50 Hz, preferred */ 78 .clock = 29700, 79 .hdisplay = 480, 80 .hsync_start = 480 + 98, 81 .hsync_end = 480 + 98 + 32, 82 .htotal = 480 + 98 + 32 + 98, 83 .vdisplay = 800, 84 .vsync_start = 800 + 15, 85 .vsync_end = 800 + 15 + 10, 86 .vtotal = 800 + 15 + 10 + 14, 87 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 88 .width_mm = 52, 89 .height_mm = 86, 90 }, 91 { /* 60 Hz */ 92 .clock = 33000, 93 .hdisplay = 480, 94 .hsync_start = 480 + 70, 95 .hsync_end = 480 + 70 + 32, 96 .htotal = 480 + 70 + 32 + 72, 97 .vdisplay = 800, 98 .vsync_start = 800 + 15, 99 .vsync_end = 800 + 15 + 10, 100 .vtotal = 800 + 15 + 10 + 16, 101 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 102 .width_mm = 52, 103 .height_mm = 86, 104 }, 105 }; 106 107 static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel) 108 { 109 return container_of(panel, struct otm8009a, panel); 110 } 111 112 static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data, 113 size_t len) 114 { 115 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 116 117 if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0) 118 dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n"); 119 } 120 121 #define dcs_write_seq(ctx, seq...) \ 122 ({ \ 123 static const u8 d[] = { seq }; \ 124 otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \ 125 }) 126 127 #define dcs_write_cmd_at(ctx, cmd, seq...) \ 128 ({ \ 129 dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \ 130 dcs_write_seq(ctx, (cmd) >> 8, seq); \ 131 }) 132 133 static int otm8009a_init_sequence(struct otm8009a *ctx) 134 { 135 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 136 int ret; 137 138 /* Enter CMD2 */ 139 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); 140 141 /* Enter Orise Command2 */ 142 dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09); 143 144 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30); 145 mdelay(10); 146 147 dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40); 148 mdelay(10); 149 150 dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9); 151 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34); 152 dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50); 153 dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E); 154 dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */ 155 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01); 156 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34); 157 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33); 158 dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79); 159 dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B); 160 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83); 161 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83); 162 dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E); 163 dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01); 164 165 dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); 166 dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, 167 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); 168 dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, 169 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); 170 dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, 171 0x01, 0x02, 0x00, 0x00); 172 173 dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00); 174 175 dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 176 dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 177 0, 0, 0, 0, 0); 178 dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 179 0, 0, 0, 0, 0); 180 dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 181 dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, 182 0, 0, 0, 0, 0); 183 dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 184 4, 0, 0, 0, 0); 185 dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 186 dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 187 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); 188 189 dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, 190 0x00, 0x00, 0x00, 0x00); 191 dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 192 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); 193 dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 195 dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, 196 0x00, 0x00, 0x00, 0x00); 197 dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 198 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); 199 dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 201 202 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66); 203 204 dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06); 205 206 dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 207 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 208 0x01); 209 dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 210 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 211 0x01); 212 213 /* Exit CMD2 */ 214 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); 215 216 ret = mipi_dsi_dcs_nop(dsi); 217 if (ret) 218 return ret; 219 220 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 221 if (ret) 222 return ret; 223 224 /* Wait for sleep out exit */ 225 mdelay(120); 226 227 /* Default portrait 480x800 rgb24 */ 228 dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); 229 230 ret = mipi_dsi_dcs_set_column_address(dsi, 0, OTM8009A_HDISPLAY - 1); 231 if (ret) 232 return ret; 233 234 ret = mipi_dsi_dcs_set_page_address(dsi, 0, OTM8009A_VDISPLAY - 1); 235 if (ret) 236 return ret; 237 238 /* See otm8009a driver documentation for pixel format descriptions */ 239 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT | 240 MIPI_DCS_PIXEL_FMT_24BIT << 4); 241 if (ret) 242 return ret; 243 244 /* Disable CABC feature */ 245 dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); 246 247 ret = mipi_dsi_dcs_set_display_on(dsi); 248 if (ret) 249 return ret; 250 251 ret = mipi_dsi_dcs_nop(dsi); 252 if (ret) 253 return ret; 254 255 /* Send Command GRAM memory write (no parameters) */ 256 dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START); 257 258 /* Wait a short while to let the panel be ready before the 1st frame */ 259 mdelay(10); 260 261 return 0; 262 } 263 264 static int otm8009a_disable(struct drm_panel *panel) 265 { 266 struct otm8009a *ctx = panel_to_otm8009a(panel); 267 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 268 int ret; 269 270 if (!ctx->enabled) 271 return 0; /* This is not an issue so we return 0 here */ 272 273 backlight_disable(ctx->bl_dev); 274 275 ret = mipi_dsi_dcs_set_display_off(dsi); 276 if (ret) 277 return ret; 278 279 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 280 if (ret) 281 return ret; 282 283 msleep(120); 284 285 ctx->enabled = false; 286 287 return 0; 288 } 289 290 static int otm8009a_unprepare(struct drm_panel *panel) 291 { 292 struct otm8009a *ctx = panel_to_otm8009a(panel); 293 294 if (!ctx->prepared) 295 return 0; 296 297 if (ctx->reset_gpio) { 298 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 299 msleep(20); 300 } 301 302 regulator_disable(ctx->supply); 303 304 ctx->prepared = false; 305 306 return 0; 307 } 308 309 static int otm8009a_prepare(struct drm_panel *panel) 310 { 311 struct otm8009a *ctx = panel_to_otm8009a(panel); 312 int ret; 313 314 if (ctx->prepared) 315 return 0; 316 317 ret = regulator_enable(ctx->supply); 318 if (ret < 0) { 319 dev_err(panel->dev, "failed to enable supply: %d\n", ret); 320 return ret; 321 } 322 323 if (ctx->reset_gpio) { 324 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 325 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 326 msleep(20); 327 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 328 msleep(100); 329 } 330 331 ret = otm8009a_init_sequence(ctx); 332 if (ret) 333 return ret; 334 335 ctx->prepared = true; 336 337 return 0; 338 } 339 340 static int otm8009a_enable(struct drm_panel *panel) 341 { 342 struct otm8009a *ctx = panel_to_otm8009a(panel); 343 344 if (ctx->enabled) 345 return 0; 346 347 backlight_enable(ctx->bl_dev); 348 349 ctx->enabled = true; 350 351 return 0; 352 } 353 354 static int otm8009a_get_modes(struct drm_panel *panel, 355 struct drm_connector *connector) 356 { 357 struct drm_display_mode *mode; 358 unsigned int num_modes = ARRAY_SIZE(modes); 359 unsigned int i; 360 361 for (i = 0; i < num_modes; i++) { 362 mode = drm_mode_duplicate(connector->dev, &modes[i]); 363 if (!mode) { 364 dev_err(panel->dev, "failed to add mode %ux%u@%u\n", 365 modes[i].hdisplay, 366 modes[i].vdisplay, 367 drm_mode_vrefresh(&modes[i])); 368 return -ENOMEM; 369 } 370 371 mode->type = DRM_MODE_TYPE_DRIVER; 372 373 /* Setting first mode as preferred */ 374 if (!i) 375 mode->type |= DRM_MODE_TYPE_PREFERRED; 376 377 drm_mode_set_name(mode); 378 drm_mode_probed_add(connector, mode); 379 } 380 381 connector->display_info.width_mm = mode->width_mm; 382 connector->display_info.height_mm = mode->height_mm; 383 384 return num_modes; 385 } 386 387 static const struct drm_panel_funcs otm8009a_drm_funcs = { 388 .disable = otm8009a_disable, 389 .unprepare = otm8009a_unprepare, 390 .prepare = otm8009a_prepare, 391 .enable = otm8009a_enable, 392 .get_modes = otm8009a_get_modes, 393 }; 394 395 /* 396 * DSI-BASED BACKLIGHT 397 */ 398 399 static int otm8009a_backlight_update_status(struct backlight_device *bd) 400 { 401 struct otm8009a *ctx = bl_get_data(bd); 402 u8 data[2]; 403 404 if (!ctx->prepared) { 405 dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n"); 406 return -ENXIO; 407 } 408 409 if (bd->props.power <= FB_BLANK_NORMAL) { 410 /* Power on the backlight with the requested brightness 411 * Note We can not use mipi_dsi_dcs_set_display_brightness() 412 * as otm8009a driver support only 8-bit brightness (1 param). 413 */ 414 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS; 415 data[1] = bd->props.brightness; 416 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data)); 417 418 /* set Brightness Control & Backlight on */ 419 data[1] = 0x24; 420 421 } else { 422 /* Power off the backlight: set Brightness Control & Bl off */ 423 data[1] = 0; 424 } 425 426 /* Update Brightness Control & Backlight */ 427 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY; 428 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data)); 429 430 return 0; 431 } 432 433 static const struct backlight_ops otm8009a_backlight_ops = { 434 .update_status = otm8009a_backlight_update_status, 435 }; 436 437 static int otm8009a_probe(struct mipi_dsi_device *dsi) 438 { 439 struct device *dev = &dsi->dev; 440 struct otm8009a *ctx; 441 int ret; 442 443 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 444 if (!ctx) 445 return -ENOMEM; 446 447 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 448 if (IS_ERR(ctx->reset_gpio)) { 449 dev_err(dev, "cannot get reset-gpio\n"); 450 return PTR_ERR(ctx->reset_gpio); 451 } 452 453 ctx->supply = devm_regulator_get(dev, "power"); 454 if (IS_ERR(ctx->supply)) { 455 ret = PTR_ERR(ctx->supply); 456 if (ret != -EPROBE_DEFER) 457 dev_err(dev, "failed to request regulator: %d\n", ret); 458 return ret; 459 } 460 461 mipi_dsi_set_drvdata(dsi, ctx); 462 463 ctx->dev = dev; 464 465 dsi->lanes = 2; 466 dsi->format = MIPI_DSI_FMT_RGB888; 467 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 468 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; 469 470 drm_panel_init(&ctx->panel, dev, &otm8009a_drm_funcs, 471 DRM_MODE_CONNECTOR_DSI); 472 473 ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev), 474 dev, ctx, 475 &otm8009a_backlight_ops, 476 NULL); 477 if (IS_ERR(ctx->bl_dev)) { 478 ret = PTR_ERR(ctx->bl_dev); 479 dev_err(dev, "failed to register backlight: %d\n", ret); 480 return ret; 481 } 482 483 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX; 484 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT; 485 ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; 486 ctx->bl_dev->props.type = BACKLIGHT_RAW; 487 488 drm_panel_add(&ctx->panel); 489 490 ret = mipi_dsi_attach(dsi); 491 if (ret < 0) { 492 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n"); 493 drm_panel_remove(&ctx->panel); 494 return ret; 495 } 496 497 return 0; 498 } 499 500 static void otm8009a_remove(struct mipi_dsi_device *dsi) 501 { 502 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi); 503 504 mipi_dsi_detach(dsi); 505 drm_panel_remove(&ctx->panel); 506 } 507 508 static const struct of_device_id orisetech_otm8009a_of_match[] = { 509 { .compatible = "orisetech,otm8009a" }, 510 { } 511 }; 512 MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match); 513 514 static struct mipi_dsi_driver orisetech_otm8009a_driver = { 515 .probe = otm8009a_probe, 516 .remove = otm8009a_remove, 517 .driver = { 518 .name = "panel-orisetech-otm8009a", 519 .of_match_table = orisetech_otm8009a_of_match, 520 }, 521 }; 522 module_mipi_dsi_driver(orisetech_otm8009a_driver); 523 524 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 525 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 526 MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel"); 527 MODULE_LICENSE("GPL v2"); 528