1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/backlight.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <video/mipi_display.h> 17 18 #include <drm/drm_mipi_dsi.h> 19 #include <drm/drm_modes.h> 20 #include <drm/drm_panel.h> 21 22 #define OTM8009A_BACKLIGHT_DEFAULT 240 23 #define OTM8009A_BACKLIGHT_MAX 255 24 25 /* Manufacturer Command Set */ 26 #define MCS_ADRSFT 0x0000 /* Address Shift Function */ 27 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */ 28 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */ 29 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */ 30 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */ 31 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */ 32 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */ 33 #define MCS_NO_DOC1 0xC48A /* Command not documented */ 34 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */ 35 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */ 36 #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */ 37 #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */ 38 #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */ 39 #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */ 40 #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */ 41 #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */ 42 #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */ 43 #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */ 44 #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */ 45 #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */ 46 #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */ 47 #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */ 48 #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */ 49 #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */ 50 #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */ 51 #define MCS_GOAVST 0xCE80 /* GOA VST Setting */ 52 #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */ 53 #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */ 54 #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */ 55 #define MCS_NO_DOC2 0xCFD0 /* Command not documented */ 56 #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */ 57 #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */ 58 #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */ 59 #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */ 60 #define MCS_NO_DOC3 0xF5B6 /* Command not documented */ 61 #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */ 62 #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */ 63 64 #define OTM8009A_HDISPLAY 480 65 #define OTM8009A_VDISPLAY 800 66 67 struct otm8009a { 68 struct device *dev; 69 struct drm_panel panel; 70 struct backlight_device *bl_dev; 71 struct gpio_desc *reset_gpio; 72 struct regulator *supply; 73 bool prepared; 74 }; 75 76 static const struct drm_display_mode modes[] = { 77 { /* 50 Hz, preferred */ 78 .clock = 29700, 79 .hdisplay = 480, 80 .hsync_start = 480 + 98, 81 .hsync_end = 480 + 98 + 32, 82 .htotal = 480 + 98 + 32 + 98, 83 .vdisplay = 800, 84 .vsync_start = 800 + 15, 85 .vsync_end = 800 + 15 + 10, 86 .vtotal = 800 + 15 + 10 + 14, 87 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 88 .width_mm = 52, 89 .height_mm = 86, 90 }, 91 { /* 60 Hz */ 92 .clock = 33000, 93 .hdisplay = 480, 94 .hsync_start = 480 + 70, 95 .hsync_end = 480 + 70 + 32, 96 .htotal = 480 + 70 + 32 + 72, 97 .vdisplay = 800, 98 .vsync_start = 800 + 15, 99 .vsync_end = 800 + 15 + 10, 100 .vtotal = 800 + 15 + 10 + 16, 101 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 102 .width_mm = 52, 103 .height_mm = 86, 104 }, 105 }; 106 107 static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel) 108 { 109 return container_of(panel, struct otm8009a, panel); 110 } 111 112 #define dcs_write_cmd_at(ctx, cmd, seq...) \ 113 ({ \ 114 mipi_dsi_dcs_write_seq_multi(ctx, MCS_ADRSFT, (cmd) & 0xFF); \ 115 mipi_dsi_dcs_write_seq_multi(ctx, (cmd) >> 8, seq); \ 116 }) 117 118 static int otm8009a_init_sequence(struct otm8009a *ctx) 119 { 120 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 121 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 122 123 /* Enter CMD2 */ 124 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01); 125 126 /* Enter Orise Command2 */ 127 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA2, 0x80, 0x09); 128 129 dcs_write_cmd_at(&dsi_ctx, MCS_SD_PCH_CTRL, 0x30); 130 mipi_dsi_msleep(&dsi_ctx, 10); 131 132 dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC1, 0x40); 133 mipi_dsi_msleep(&dsi_ctx, 10); 134 135 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL4 + 1, 0xA9); 136 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 1, 0x34); 137 dcs_write_cmd_at(&dsi_ctx, MCS_P_DRV_M, 0x50); 138 dcs_write_cmd_at(&dsi_ctx, MCS_VCOMDC, 0x4E); 139 dcs_write_cmd_at(&dsi_ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */ 140 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 2, 0x01); 141 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 5, 0x34); 142 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL2 + 4, 0x33); 143 dcs_write_cmd_at(&dsi_ctx, MCS_GVDDSET, 0x79, 0x79); 144 dcs_write_cmd_at(&dsi_ctx, MCS_SD_CTRL + 1, 0x1B); 145 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL1 + 2, 0x83); 146 dcs_write_cmd_at(&dsi_ctx, MCS_SD_PCH_CTRL + 1, 0x83); 147 dcs_write_cmd_at(&dsi_ctx, MCS_RGB_VID_SET, 0x0E); 148 dcs_write_cmd_at(&dsi_ctx, MCS_PANSET, 0x00, 0x01); 149 150 dcs_write_cmd_at(&dsi_ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00); 151 dcs_write_cmd_at(&dsi_ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00, 152 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00); 153 dcs_write_cmd_at(&dsi_ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00, 154 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00); 155 dcs_write_cmd_at(&dsi_ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, 156 0x01, 0x02, 0x00, 0x00); 157 158 dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC2, 0x00); 159 160 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 161 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 162 0, 0, 0, 0, 0); 163 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 164 0, 0, 0, 0, 0); 165 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 166 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0, 167 0, 0, 0, 0, 0); 168 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 169 4, 0, 0, 0, 0); 170 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); 171 dcs_write_cmd_at(&dsi_ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 172 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); 173 174 dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25, 175 0x00, 0x00, 0x00, 0x00); 176 dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 177 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02); 178 dcs_write_cmd_at(&dsi_ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 180 dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26, 181 0x00, 0x00, 0x00, 0x00); 182 dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 183 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01); 184 dcs_write_cmd_at(&dsi_ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 186 187 dcs_write_cmd_at(&dsi_ctx, MCS_PWR_CTRL1 + 1, 0x66); 188 189 dcs_write_cmd_at(&dsi_ctx, MCS_NO_DOC3, 0x06); 190 191 dcs_write_cmd_at(&dsi_ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 192 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 193 0x01); 194 dcs_write_cmd_at(&dsi_ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10, 195 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A, 196 0x01); 197 198 /* Exit CMD2 */ 199 dcs_write_cmd_at(&dsi_ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF); 200 201 mipi_dsi_dcs_nop_multi(&dsi_ctx); 202 203 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 204 mipi_dsi_msleep(&dsi_ctx, 120); 205 206 /* Default portrait 480x800 rgb24 */ 207 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); 208 209 mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0, OTM8009A_HDISPLAY - 1); 210 211 mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0, OTM8009A_VDISPLAY - 1); 212 213 /* See otm8009a driver documentation for pixel format descriptions */ 214 mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, MIPI_DCS_PIXEL_FMT_24BIT | 215 MIPI_DCS_PIXEL_FMT_24BIT << 4); 216 217 /* Disable CABC feature */ 218 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); 219 220 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 221 222 mipi_dsi_dcs_nop_multi(&dsi_ctx); 223 224 /* Send Command GRAM memory write (no parameters) */ 225 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_MEMORY_START); 226 227 /* Wait a short while to let the panel be ready before the 1st frame */ 228 mipi_dsi_msleep(&dsi_ctx, 10); 229 230 return dsi_ctx.accum_err; 231 } 232 233 static int otm8009a_disable(struct drm_panel *panel) 234 { 235 struct otm8009a *ctx = panel_to_otm8009a(panel); 236 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 237 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 238 239 backlight_disable(ctx->bl_dev); 240 241 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 242 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 243 mipi_dsi_msleep(&dsi_ctx, 120); 244 245 return dsi_ctx.accum_err; 246 } 247 248 static int otm8009a_unprepare(struct drm_panel *panel) 249 { 250 struct otm8009a *ctx = panel_to_otm8009a(panel); 251 252 if (ctx->reset_gpio) { 253 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 254 msleep(20); 255 } 256 257 regulator_disable(ctx->supply); 258 259 ctx->prepared = false; 260 261 return 0; 262 } 263 264 static int otm8009a_prepare(struct drm_panel *panel) 265 { 266 struct otm8009a *ctx = panel_to_otm8009a(panel); 267 int ret; 268 269 ret = regulator_enable(ctx->supply); 270 if (ret < 0) { 271 dev_err(panel->dev, "failed to enable supply: %d\n", ret); 272 return ret; 273 } 274 275 if (ctx->reset_gpio) { 276 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 277 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 278 msleep(20); 279 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 280 msleep(100); 281 } 282 283 ret = otm8009a_init_sequence(ctx); 284 if (ret) 285 return ret; 286 287 ctx->prepared = true; 288 289 return 0; 290 } 291 292 static int otm8009a_enable(struct drm_panel *panel) 293 { 294 struct otm8009a *ctx = panel_to_otm8009a(panel); 295 296 backlight_enable(ctx->bl_dev); 297 298 return 0; 299 } 300 301 static int otm8009a_get_modes(struct drm_panel *panel, 302 struct drm_connector *connector) 303 { 304 struct drm_display_mode *mode; 305 unsigned int num_modes = ARRAY_SIZE(modes); 306 unsigned int i; 307 308 for (i = 0; i < num_modes; i++) { 309 mode = drm_mode_duplicate(connector->dev, &modes[i]); 310 if (!mode) { 311 dev_err(panel->dev, "failed to add mode %ux%u@%u\n", 312 modes[i].hdisplay, 313 modes[i].vdisplay, 314 drm_mode_vrefresh(&modes[i])); 315 return -ENOMEM; 316 } 317 318 mode->type = DRM_MODE_TYPE_DRIVER; 319 320 /* Setting first mode as preferred */ 321 if (!i) 322 mode->type |= DRM_MODE_TYPE_PREFERRED; 323 324 drm_mode_set_name(mode); 325 drm_mode_probed_add(connector, mode); 326 } 327 328 connector->display_info.width_mm = mode->width_mm; 329 connector->display_info.height_mm = mode->height_mm; 330 331 return num_modes; 332 } 333 334 static const struct drm_panel_funcs otm8009a_drm_funcs = { 335 .disable = otm8009a_disable, 336 .unprepare = otm8009a_unprepare, 337 .prepare = otm8009a_prepare, 338 .enable = otm8009a_enable, 339 .get_modes = otm8009a_get_modes, 340 }; 341 342 /* 343 * DSI-BASED BACKLIGHT 344 */ 345 346 static int otm8009a_backlight_update_status(struct backlight_device *bd) 347 { 348 struct otm8009a *ctx = bl_get_data(bd); 349 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 350 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 351 u8 data[2]; 352 353 if (!ctx->prepared) { 354 dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n"); 355 return -ENXIO; 356 } 357 358 if (bd->props.power <= BACKLIGHT_POWER_REDUCED) { 359 /* Power on the backlight with the requested brightness 360 * Note We can not use mipi_dsi_dcs_set_display_brightness() 361 * as otm8009a driver support only 8-bit brightness (1 param). 362 */ 363 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS; 364 data[1] = bd->props.brightness; 365 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, data, ARRAY_SIZE(data)); 366 367 /* set Brightness Control & Backlight on */ 368 data[1] = 0x24; 369 370 } else { 371 /* Power off the backlight: set Brightness Control & Bl off */ 372 data[1] = 0; 373 } 374 375 /* Update Brightness Control & Backlight */ 376 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY; 377 mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, data, ARRAY_SIZE(data)); 378 379 return dsi_ctx.accum_err; 380 } 381 382 static const struct backlight_ops otm8009a_backlight_ops = { 383 .update_status = otm8009a_backlight_update_status, 384 }; 385 386 static int otm8009a_probe(struct mipi_dsi_device *dsi) 387 { 388 struct device *dev = &dsi->dev; 389 struct otm8009a *ctx; 390 int ret; 391 392 ctx = devm_drm_panel_alloc(dev, struct otm8009a, panel, 393 &otm8009a_drm_funcs, 394 DRM_MODE_CONNECTOR_DSI); 395 if (IS_ERR(ctx)) 396 return PTR_ERR(ctx); 397 398 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 399 if (IS_ERR(ctx->reset_gpio)) { 400 dev_err(dev, "cannot get reset-gpio\n"); 401 return PTR_ERR(ctx->reset_gpio); 402 } 403 404 ctx->supply = devm_regulator_get(dev, "power"); 405 if (IS_ERR(ctx->supply)) { 406 ret = PTR_ERR(ctx->supply); 407 if (ret != -EPROBE_DEFER) 408 dev_err(dev, "failed to request regulator: %d\n", ret); 409 return ret; 410 } 411 412 mipi_dsi_set_drvdata(dsi, ctx); 413 414 ctx->dev = dev; 415 416 dsi->lanes = 2; 417 dsi->format = MIPI_DSI_FMT_RGB888; 418 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 419 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; 420 421 ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev), 422 dev, ctx, 423 &otm8009a_backlight_ops, 424 NULL); 425 if (IS_ERR(ctx->bl_dev)) { 426 ret = PTR_ERR(ctx->bl_dev); 427 dev_err(dev, "failed to register backlight: %d\n", ret); 428 return ret; 429 } 430 431 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX; 432 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT; 433 ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF; 434 ctx->bl_dev->props.type = BACKLIGHT_RAW; 435 436 drm_panel_add(&ctx->panel); 437 438 ret = mipi_dsi_attach(dsi); 439 if (ret < 0) { 440 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n"); 441 drm_panel_remove(&ctx->panel); 442 return ret; 443 } 444 445 return 0; 446 } 447 448 static void otm8009a_remove(struct mipi_dsi_device *dsi) 449 { 450 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi); 451 452 mipi_dsi_detach(dsi); 453 drm_panel_remove(&ctx->panel); 454 } 455 456 static const struct of_device_id orisetech_otm8009a_of_match[] = { 457 { .compatible = "orisetech,otm8009a" }, 458 { } 459 }; 460 MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match); 461 462 static struct mipi_dsi_driver orisetech_otm8009a_driver = { 463 .probe = otm8009a_probe, 464 .remove = otm8009a_remove, 465 .driver = { 466 .name = "panel-orisetech-otm8009a", 467 .of_match_table = orisetech_otm8009a_of_match, 468 }, 469 }; 470 module_mipi_dsi_driver(orisetech_otm8009a_driver); 471 472 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 473 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 474 MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel"); 475 MODULE_LICENSE("GPL v2"); 476