1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 4 #include <linux/delay.h> 5 #include <linux/gpio/consumer.h> 6 #include <linux/module.h> 7 #include <linux/of.h> 8 #include <linux/regulator/consumer.h> 9 10 #include <drm/drm_mipi_dsi.h> 11 #include <drm/drm_modes.h> 12 #include <drm/drm_panel.h> 13 14 #include <video/mipi_display.h> 15 16 static const char * const regulator_names[] = { 17 "vddi", 18 "avdd", 19 "avee", 20 }; 21 22 static const unsigned long regulator_enable_loads[] = { 23 62000, 24 100000, 25 100000, 26 }; 27 28 struct panel_desc { 29 const struct drm_display_mode *display_mode; 30 u32 width_mm; 31 u32 height_mm; 32 unsigned long mode_flags; 33 enum mipi_dsi_pixel_format format; 34 unsigned int lanes; 35 const char *panel_name; 36 void (*init_sequence)(struct mipi_dsi_multi_context *ctx); 37 }; 38 39 struct nt36672e_panel { 40 struct drm_panel panel; 41 struct mipi_dsi_device *dsi; 42 struct gpio_desc *reset_gpio; 43 struct regulator_bulk_data supplies[3]; 44 const struct panel_desc *desc; 45 }; 46 47 static inline struct nt36672e_panel *to_nt36672e_panel(struct drm_panel *panel) 48 { 49 return container_of(panel, struct nt36672e_panel, panel); 50 } 51 52 static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) 53 { 54 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); 55 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 56 mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00); 57 mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); 58 mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x89, 0x28, 0x00, 0x08, 0x00, 0xaa, 0x02, 59 0x0e, 0x00, 0x2b, 0x00, 0x07, 0x0d, 0xb7, 0x0c, 0xb7); 60 61 mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x1b, 0xa0); 62 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); 63 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 64 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x66); 65 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x40); 66 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x38); 67 mipi_dsi_dcs_write_seq_multi(ctx, 0x2f, 0x83); 68 mipi_dsi_dcs_write_seq_multi(ctx, 0x69, 0x91); 69 mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0xd1); 70 mipi_dsi_dcs_write_seq_multi(ctx, 0x96, 0xd1); 71 mipi_dsi_dcs_write_seq_multi(ctx, 0xf2, 0x64); 72 mipi_dsi_dcs_write_seq_multi(ctx, 0xf3, 0x54); 73 mipi_dsi_dcs_write_seq_multi(ctx, 0xf4, 0x64); 74 mipi_dsi_dcs_write_seq_multi(ctx, 0xf5, 0x54); 75 mipi_dsi_dcs_write_seq_multi(ctx, 0xf6, 0x64); 76 mipi_dsi_dcs_write_seq_multi(ctx, 0xf7, 0x54); 77 mipi_dsi_dcs_write_seq_multi(ctx, 0xf8, 0x64); 78 mipi_dsi_dcs_write_seq_multi(ctx, 0xf9, 0x54); 79 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x24); 80 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 81 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0f); 82 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x0c); 83 mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x1d); 84 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x2f); 85 mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x2e); 86 mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x2d); 87 mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x2c); 88 mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0x17); 89 mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x13); 90 mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x15); 91 mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x14); 92 mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x16); 93 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x18); 94 mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x01); 95 mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x1d); 96 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x2f); 97 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x2e); 98 mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x2d); 99 mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x2c); 100 mipi_dsi_dcs_write_seq_multi(ctx, 0x29, 0x17); 101 mipi_dsi_dcs_write_seq_multi(ctx, 0x2a, 0x13); 102 mipi_dsi_dcs_write_seq_multi(ctx, 0x2b, 0x15); 103 mipi_dsi_dcs_write_seq_multi(ctx, 0x2f, 0x14); 104 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x16); 105 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x18); 106 mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x04); 107 mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0x10); 108 mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x1f); 109 mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0x1f); 110 mipi_dsi_dcs_write_seq_multi(ctx, 0x4d, 0x14); 111 mipi_dsi_dcs_write_seq_multi(ctx, 0x4e, 0x36); 112 mipi_dsi_dcs_write_seq_multi(ctx, 0x4f, 0x36); 113 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x36); 114 mipi_dsi_dcs_write_seq_multi(ctx, 0x71, 0x30); 115 mipi_dsi_dcs_write_seq_multi(ctx, 0x79, 0x11); 116 mipi_dsi_dcs_write_seq_multi(ctx, 0x7a, 0x82); 117 mipi_dsi_dcs_write_seq_multi(ctx, 0x7b, 0x8f); 118 mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x04); 119 mipi_dsi_dcs_write_seq_multi(ctx, 0x80, 0x04); 120 mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x04); 121 mipi_dsi_dcs_write_seq_multi(ctx, 0x82, 0x13); 122 mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x31); 123 mipi_dsi_dcs_write_seq_multi(ctx, 0x85, 0x00); 124 mipi_dsi_dcs_write_seq_multi(ctx, 0x86, 0x00); 125 mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x00); 126 mipi_dsi_dcs_write_seq_multi(ctx, 0x90, 0x13); 127 mipi_dsi_dcs_write_seq_multi(ctx, 0x92, 0x31); 128 mipi_dsi_dcs_write_seq_multi(ctx, 0x93, 0x00); 129 mipi_dsi_dcs_write_seq_multi(ctx, 0x94, 0x00); 130 mipi_dsi_dcs_write_seq_multi(ctx, 0x95, 0x00); 131 mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0xf4); 132 mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x01); 133 mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x0f); 134 mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x0f); 135 mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x02); 136 mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x04); 137 mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x04); 138 mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0xc0); 139 mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x00); 140 mipi_dsi_dcs_write_seq_multi(ctx, 0xd9, 0x80); 141 mipi_dsi_dcs_write_seq_multi(ctx, 0xe9, 0x02); 142 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x25); 143 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 144 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x22); 145 mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0xe4); 146 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x40); 147 mipi_dsi_dcs_write_seq_multi(ctx, 0x66, 0xd8); 148 mipi_dsi_dcs_write_seq_multi(ctx, 0x68, 0x50); 149 mipi_dsi_dcs_write_seq_multi(ctx, 0x69, 0x10); 150 mipi_dsi_dcs_write_seq_multi(ctx, 0x6b, 0x00); 151 mipi_dsi_dcs_write_seq_multi(ctx, 0x6d, 0x0d); 152 mipi_dsi_dcs_write_seq_multi(ctx, 0x6e, 0x48); 153 mipi_dsi_dcs_write_seq_multi(ctx, 0x72, 0x41); 154 mipi_dsi_dcs_write_seq_multi(ctx, 0x73, 0x4a); 155 mipi_dsi_dcs_write_seq_multi(ctx, 0x74, 0xd0); 156 mipi_dsi_dcs_write_seq_multi(ctx, 0x77, 0x62); 157 mipi_dsi_dcs_write_seq_multi(ctx, 0x79, 0x7e); 158 mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x03); 159 mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x15); 160 mipi_dsi_dcs_write_seq_multi(ctx, 0x7f, 0x00); 161 mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x4d); 162 mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x80); 163 mipi_dsi_dcs_write_seq_multi(ctx, 0xd6, 0x80); 164 mipi_dsi_dcs_write_seq_multi(ctx, 0xd7, 0x80); 165 mipi_dsi_dcs_write_seq_multi(ctx, 0xef, 0x20); 166 mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x84); 167 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x26); 168 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 169 mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x0f); 170 mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x01); 171 mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x03); 172 mipi_dsi_dcs_write_seq_multi(ctx, 0x85, 0x01); 173 mipi_dsi_dcs_write_seq_multi(ctx, 0x86, 0x03); 174 mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x01); 175 mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x05); 176 mipi_dsi_dcs_write_seq_multi(ctx, 0x8a, 0x1a); 177 mipi_dsi_dcs_write_seq_multi(ctx, 0x8b, 0x11); 178 mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x24); 179 mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x42); 180 mipi_dsi_dcs_write_seq_multi(ctx, 0x8f, 0x11); 181 mipi_dsi_dcs_write_seq_multi(ctx, 0x90, 0x11); 182 mipi_dsi_dcs_write_seq_multi(ctx, 0x91, 0x11); 183 mipi_dsi_dcs_write_seq_multi(ctx, 0x9a, 0x80); 184 mipi_dsi_dcs_write_seq_multi(ctx, 0x9b, 0x04); 185 mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0x00); 186 mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x00); 187 mipi_dsi_dcs_write_seq_multi(ctx, 0x9e, 0x00); 188 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x27); 189 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 190 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x68); 191 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x81); 192 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x6a); 193 mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x81); 194 mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x94); 195 mipi_dsi_dcs_write_seq_multi(ctx, 0x6e, 0x00); 196 mipi_dsi_dcs_write_seq_multi(ctx, 0x6f, 0x00); 197 mipi_dsi_dcs_write_seq_multi(ctx, 0x70, 0x00); 198 mipi_dsi_dcs_write_seq_multi(ctx, 0x71, 0x00); 199 mipi_dsi_dcs_write_seq_multi(ctx, 0x72, 0x00); 200 mipi_dsi_dcs_write_seq_multi(ctx, 0x75, 0x00); 201 mipi_dsi_dcs_write_seq_multi(ctx, 0x76, 0x00); 202 mipi_dsi_dcs_write_seq_multi(ctx, 0x77, 0x00); 203 mipi_dsi_dcs_write_seq_multi(ctx, 0x7d, 0x09); 204 mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x67); 205 mipi_dsi_dcs_write_seq_multi(ctx, 0x80, 0x23); 206 mipi_dsi_dcs_write_seq_multi(ctx, 0x82, 0x09); 207 mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x67); 208 mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x01); 209 mipi_dsi_dcs_write_seq_multi(ctx, 0x89, 0x10); 210 mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x10); 211 mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x23); 212 mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x01); 213 mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x40); 214 mipi_dsi_dcs_write_seq_multi(ctx, 0xe5, 0x02); 215 mipi_dsi_dcs_write_seq_multi(ctx, 0xe6, 0xd3); 216 mipi_dsi_dcs_write_seq_multi(ctx, 0xeb, 0x03); 217 mipi_dsi_dcs_write_seq_multi(ctx, 0xec, 0x28); 218 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2a); 219 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 220 mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x91); 221 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x20); 222 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x50); 223 mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x70); 224 mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x04); 225 mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x40); 226 mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x01); 227 mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xe0); 228 mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x0f); 229 mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0xa4); 230 mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x0f); 231 mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x78); 232 mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x23); 233 mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x36); 234 mipi_dsi_dcs_write_seq_multi(ctx, 0x1e, 0x3e); 235 mipi_dsi_dcs_write_seq_multi(ctx, 0x1f, 0x3e); 236 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x3e); 237 mipi_dsi_dcs_write_seq_multi(ctx, 0x28, 0xfd); 238 mipi_dsi_dcs_write_seq_multi(ctx, 0x29, 0x12); 239 mipi_dsi_dcs_write_seq_multi(ctx, 0x2a, 0xe1); 240 mipi_dsi_dcs_write_seq_multi(ctx, 0x2d, 0x0a); 241 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x49); 242 mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0x96); 243 mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xff); 244 mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0x40); 245 mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xde); 246 mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0xf9); 247 mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x45); 248 mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0xd9); 249 mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x49); 250 mipi_dsi_dcs_write_seq_multi(ctx, 0x4a, 0xf0); 251 mipi_dsi_dcs_write_seq_multi(ctx, 0x7a, 0x09); 252 mipi_dsi_dcs_write_seq_multi(ctx, 0x7b, 0x40); 253 mipi_dsi_dcs_write_seq_multi(ctx, 0x7f, 0xf0); 254 mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x0f); 255 mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0xa4); 256 mipi_dsi_dcs_write_seq_multi(ctx, 0x87, 0x0f); 257 mipi_dsi_dcs_write_seq_multi(ctx, 0x88, 0x78); 258 mipi_dsi_dcs_write_seq_multi(ctx, 0x89, 0x23); 259 mipi_dsi_dcs_write_seq_multi(ctx, 0x8b, 0x36); 260 mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x7d); 261 mipi_dsi_dcs_write_seq_multi(ctx, 0x8d, 0x7d); 262 mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x7d); 263 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); 264 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 265 mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00, 266 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); 267 mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01, 268 0x7a, 0x01, 0xa9, 0x01, 0xf2, 0x02, 0x2d, 0x02, 0x2e); 269 mipi_dsi_dcs_write_seq_multi(ctx, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0xca, 0x03, 270 0x00, 0x03, 0x1e, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); 271 mipi_dsi_dcs_write_seq_multi(ctx, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 272 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 273 mipi_dsi_dcs_write_seq_multi(ctx, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00, 274 0x71, 0x00, 0x90, 0x00, 0xa7, 0x00, 0xbf, 0x00, 0xd1); 275 mipi_dsi_dcs_write_seq_multi(ctx, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x43, 0x01, 276 0x83, 0x01, 0xb2, 0x01, 0xfa, 0x02, 0x34, 0x02, 0x36); 277 mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0xd0, 0x03, 278 0x03, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5b, 0x03, 0x6b); 279 mipi_dsi_dcs_write_seq_multi(ctx, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0xac, 0x03, 280 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 281 mipi_dsi_dcs_write_seq_multi(ctx, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00, 282 0x72, 0x00, 0x92, 0x00, 0xa8, 0x00, 0xbf, 0x00, 0xd1); 283 mipi_dsi_dcs_write_seq_multi(ctx, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x42, 0x01, 284 0x81, 0x01, 0xaf, 0x01, 0xf5, 0x02, 0x2f, 0x02, 0x31); 285 mipi_dsi_dcs_write_seq_multi(ctx, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xcd, 0x03, 286 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); 287 mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 288 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 289 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x21); 290 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 291 mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00, 292 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); 293 mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01, 294 0x7a, 0x01, 0xa9, 0x01, 0xf2, 0x02, 0x2d, 0x02, 0x2e); 295 mipi_dsi_dcs_write_seq_multi(ctx, 0xb2, 0x02, 0x64, 0x02, 0xa3, 0x02, 0xca, 0x03, 296 0x00, 0x03, 0x1e, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); 297 mipi_dsi_dcs_write_seq_multi(ctx, 0xb3, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 298 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 299 mipi_dsi_dcs_write_seq_multi(ctx, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00, 300 0x71, 0x00, 0x90, 0x00, 0xa7, 0x00, 0xbf, 0x00, 0xd1); 301 mipi_dsi_dcs_write_seq_multi(ctx, 0xb5, 0x00, 0xe2, 0x01, 0x1a, 0x01, 0x43, 0x01, 302 0x83, 0x01, 0xb2, 0x01, 0xfa, 0x02, 0x34, 0x02, 0x36); 303 mipi_dsi_dcs_write_seq_multi(ctx, 0xb6, 0x02, 0x6b, 0x02, 0xa8, 0x02, 0xd0, 0x03, 304 0x03, 0x03, 0x21, 0x03, 0x4d, 0x03, 0x5b, 0x03, 0x6b); 305 mipi_dsi_dcs_write_seq_multi(ctx, 0xb7, 0x03, 0x7e, 0x03, 0x94, 0x03, 0xac, 0x03, 306 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 307 mipi_dsi_dcs_write_seq_multi(ctx, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x51, 0x00, 308 0x72, 0x00, 0x92, 0x00, 0xa8, 0x00, 0xbf, 0x00, 0xd1); 309 mipi_dsi_dcs_write_seq_multi(ctx, 0xb9, 0x00, 0xe2, 0x01, 0x18, 0x01, 0x42, 0x01, 310 0x81, 0x01, 0xaf, 0x01, 0xf5, 0x02, 0x2f, 0x02, 0x31); 311 mipi_dsi_dcs_write_seq_multi(ctx, 0xba, 0x02, 0x68, 0x02, 0xa6, 0x02, 0xcd, 0x03, 312 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); 313 mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 314 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); 315 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2c); 316 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 317 mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x1f); 318 mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x1f); 319 mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x03); 320 mipi_dsi_dcs_write_seq_multi(ctx, 0x6a, 0x14); 321 mipi_dsi_dcs_write_seq_multi(ctx, 0x6b, 0x36); 322 mipi_dsi_dcs_write_seq_multi(ctx, 0x6c, 0x36); 323 mipi_dsi_dcs_write_seq_multi(ctx, 0x6d, 0x36); 324 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x04); 325 mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x04); 326 mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x04); 327 mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x0f); 328 mipi_dsi_dcs_write_seq_multi(ctx, 0x58, 0x0f); 329 mipi_dsi_dcs_write_seq_multi(ctx, 0x59, 0x0f); 330 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xf0); 331 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 332 mipi_dsi_dcs_write_seq_multi(ctx, 0x5a, 0x00); 333 334 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); 335 mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); 336 mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0xff); 337 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x24); 338 mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x01); 339 } 340 341 static int nt36672e_power_on(struct nt36672e_panel *ctx) 342 { 343 struct mipi_dsi_device *dsi = ctx->dsi; 344 int ret; 345 346 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 347 if (ret < 0) { 348 dev_err(&dsi->dev, "regulator bulk enable failed: %d\n", ret); 349 return ret; 350 } 351 352 /* 353 * Reset sequence of nt36672e panel requires the panel to be out of reset 354 * for 10ms, followed by being held in reset for 10ms and then out again. 355 */ 356 gpiod_set_value(ctx->reset_gpio, 1); 357 usleep_range(10000, 20000); 358 gpiod_set_value(ctx->reset_gpio, 0); 359 usleep_range(10000, 20000); 360 gpiod_set_value(ctx->reset_gpio, 1); 361 usleep_range(10000, 20000); 362 363 return 0; 364 } 365 366 static int nt36672e_power_off(struct nt36672e_panel *ctx) 367 { 368 struct mipi_dsi_device *dsi = ctx->dsi; 369 int ret = 0; 370 371 gpiod_set_value(ctx->reset_gpio, 0); 372 373 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 374 if (ret) 375 dev_err(&dsi->dev, "regulator bulk disable failed: %d\n", ret); 376 377 return ret; 378 } 379 380 static int nt36672e_on(struct nt36672e_panel *nt36672e) 381 { 382 struct mipi_dsi_multi_context ctx = { .dsi = nt36672e->dsi }; 383 const struct panel_desc *desc = nt36672e->desc; 384 385 nt36672e->dsi->mode_flags |= MIPI_DSI_MODE_LPM; 386 387 if (desc->init_sequence) 388 desc->init_sequence(&ctx); 389 390 mipi_dsi_dcs_exit_sleep_mode_multi(&ctx); 391 mipi_dsi_msleep(&ctx, 120); 392 393 mipi_dsi_dcs_set_display_on_multi(&ctx); 394 395 mipi_dsi_msleep(&ctx, 100); 396 397 return ctx.accum_err; 398 } 399 400 static int nt36672e_off(struct nt36672e_panel *panel) 401 { 402 struct mipi_dsi_multi_context ctx = { .dsi = panel->dsi }; 403 404 panel->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 405 406 mipi_dsi_dcs_set_display_off_multi(&ctx); 407 mipi_dsi_msleep(&ctx, 20); 408 409 mipi_dsi_dcs_enter_sleep_mode_multi(&ctx); 410 mipi_dsi_msleep(&ctx, 60); 411 412 return ctx.accum_err; 413 } 414 415 static int nt36672e_panel_prepare(struct drm_panel *panel) 416 { 417 struct nt36672e_panel *ctx = to_nt36672e_panel(panel); 418 struct mipi_dsi_device *dsi = ctx->dsi; 419 int ret; 420 421 ret = nt36672e_power_on(ctx); 422 if (ret < 0) 423 return ret; 424 425 ret = nt36672e_on(ctx); 426 if (ret < 0) { 427 if (nt36672e_power_off(ctx)) 428 dev_err(&dsi->dev, "power off failed\n"); 429 return ret; 430 } 431 432 return 0; 433 } 434 435 static int nt36672e_panel_unprepare(struct drm_panel *panel) 436 { 437 struct nt36672e_panel *ctx = to_nt36672e_panel(panel); 438 struct mipi_dsi_device *dsi = ctx->dsi; 439 int ret; 440 441 nt36672e_off(ctx); 442 443 ret = nt36672e_power_off(ctx); 444 if (ret < 0) 445 dev_err(&dsi->dev, "power off failed: %d\n", ret); 446 447 return 0; 448 } 449 450 static const struct drm_display_mode nt36672e_1080x2408_60hz = { 451 .name = "1080x2408", 452 .clock = 181690, 453 .hdisplay = 1080, 454 .hsync_start = 1080 + 76, 455 .hsync_end = 1080 + 76 + 12, 456 .htotal = 1080 + 76 + 12 + 56, 457 .vdisplay = 2408, 458 .vsync_start = 2408 + 46, 459 .vsync_end = 2408 + 46 + 10, 460 .vtotal = 2408 + 46 + 10 + 10, 461 .flags = 0, 462 }; 463 464 static const struct panel_desc nt36672e_panel_desc = { 465 .display_mode = &nt36672e_1080x2408_60hz, 466 .width_mm = 74, 467 .height_mm = 131, 468 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS, 469 .format = MIPI_DSI_FMT_RGB888, 470 .lanes = 4, 471 .panel_name = "nt36672e fhd plus panel", 472 .init_sequence = nt36672e_1080x2408_60hz_init, 473 }; 474 475 static int nt36672e_panel_get_modes(struct drm_panel *panel, struct drm_connector *connector) 476 { 477 struct nt36672e_panel *ctx = to_nt36672e_panel(panel); 478 struct drm_display_mode *mode; 479 480 mode = drm_mode_duplicate(connector->dev, ctx->desc->display_mode); 481 if (!mode) 482 return -ENOMEM; 483 484 drm_mode_set_name(mode); 485 486 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 487 connector->display_info.width_mm = ctx->desc->width_mm; 488 connector->display_info.height_mm = ctx->desc->height_mm; 489 drm_mode_probed_add(connector, mode); 490 491 return 1; 492 } 493 494 static const struct drm_panel_funcs nt36672e_drm_funcs = { 495 .prepare = nt36672e_panel_prepare, 496 .unprepare = nt36672e_panel_unprepare, 497 .get_modes = nt36672e_panel_get_modes, 498 }; 499 500 static int nt36672e_panel_probe(struct mipi_dsi_device *dsi) 501 { 502 struct device *dev = &dsi->dev; 503 struct nt36672e_panel *ctx; 504 int i, ret = 0; 505 506 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 507 if (!ctx) 508 return -ENOMEM; 509 510 ctx->desc = of_device_get_match_data(dev); 511 if (!ctx->desc) { 512 dev_err(dev, "missing device configuration\n"); 513 return -ENODEV; 514 } 515 516 for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) { 517 ctx->supplies[i].supply = regulator_names[i]; 518 ctx->supplies[i].init_load_uA = regulator_enable_loads[i]; 519 } 520 521 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), 522 ctx->supplies); 523 if (ret < 0) 524 return ret; 525 526 ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 527 if (IS_ERR(ctx->reset_gpio)) 528 return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset-gpios\n"); 529 530 ctx->dsi = dsi; 531 mipi_dsi_set_drvdata(dsi, ctx); 532 533 dsi->lanes = ctx->desc->lanes; 534 dsi->format = ctx->desc->format; 535 dsi->mode_flags = ctx->desc->mode_flags; 536 537 drm_panel_init(&ctx->panel, dev, &nt36672e_drm_funcs, DRM_MODE_CONNECTOR_DSI); 538 539 ret = drm_panel_of_backlight(&ctx->panel); 540 if (ret) 541 return dev_err_probe(dev, ret, "Failed to get backlight\n"); 542 543 ctx->panel.prepare_prev_first = true; 544 545 drm_panel_add(&ctx->panel); 546 547 ret = mipi_dsi_attach(dsi); 548 if (ret < 0) { 549 dev_err(dev, "Failed to attach to DSI host: %d\n", ret); 550 goto err_dsi_attach; 551 } 552 553 return 0; 554 555 err_dsi_attach: 556 drm_panel_remove(&ctx->panel); 557 return ret; 558 } 559 560 static void nt36672e_panel_remove(struct mipi_dsi_device *dsi) 561 { 562 struct nt36672e_panel *ctx = mipi_dsi_get_drvdata(dsi); 563 564 mipi_dsi_detach(ctx->dsi); 565 drm_panel_remove(&ctx->panel); 566 } 567 568 static const struct of_device_id nt36672e_of_match[] = { 569 { 570 .compatible = "novatek,nt36672e", 571 .data = &nt36672e_panel_desc, 572 }, 573 { } 574 }; 575 MODULE_DEVICE_TABLE(of, nt36672e_of_match); 576 577 static struct mipi_dsi_driver nt36672e_panel_driver = { 578 .driver = { 579 .name = "panel-novatek-nt36672e", 580 .of_match_table = nt36672e_of_match, 581 }, 582 .probe = nt36672e_panel_probe, 583 .remove = nt36672e_panel_remove, 584 }; 585 module_mipi_dsi_driver(nt36672e_panel_driver); 586 587 MODULE_AUTHOR("Ritesh Kumar <quic_riteshk@quicinc.com>"); 588 MODULE_DESCRIPTION("Novatek NT36672E DSI Panel Driver"); 589 MODULE_LICENSE("GPL"); 590