1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2019 Radxa Limited 4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. 5 * 6 * Author: 7 * - Jagan Teki <jagan@amarulasolutions.com> 8 * - Stephen Chen <stephen@radxa.com> 9 */ 10 11 #include <drm/drm_mipi_dsi.h> 12 #include <drm/drm_modes.h> 13 #include <drm/drm_panel.h> 14 #include <drm/drm_print.h> 15 16 #include <linux/gpio/consumer.h> 17 #include <linux/delay.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/regulator/consumer.h> 21 22 struct jadard; 23 24 struct jadard_panel_desc { 25 const struct drm_display_mode mode; 26 unsigned int lanes; 27 enum mipi_dsi_pixel_format format; 28 int (*init)(struct jadard *jadard); 29 u32 num_init_cmds; 30 bool lp11_before_reset; 31 bool reset_before_power_off_vcioo; 32 unsigned int vcioo_to_lp11_delay_ms; 33 unsigned int lp11_to_reset_delay_ms; 34 unsigned int exit_sleep_to_display_on_delay_ms; 35 unsigned int display_on_delay_ms; 36 unsigned int backlight_off_to_display_off_delay_ms; 37 unsigned int display_off_to_enter_sleep_delay_ms; 38 unsigned int enter_sleep_to_reset_down_delay_ms; 39 }; 40 41 struct jadard { 42 struct drm_panel panel; 43 struct mipi_dsi_device *dsi; 44 const struct jadard_panel_desc *desc; 45 enum drm_panel_orientation orientation; 46 struct regulator *vdd; 47 struct regulator *vccio; 48 struct gpio_desc *reset; 49 }; 50 51 static inline struct jadard *panel_to_jadard(struct drm_panel *panel) 52 { 53 return container_of(panel, struct jadard, panel); 54 } 55 56 static int jadard_enable(struct drm_panel *panel) 57 { 58 struct jadard *jadard = panel_to_jadard(panel); 59 struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 60 61 msleep(120); 62 63 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 64 65 if (jadard->desc->exit_sleep_to_display_on_delay_ms) 66 mipi_dsi_msleep(&dsi_ctx, jadard->desc->exit_sleep_to_display_on_delay_ms); 67 68 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 69 70 if (jadard->desc->display_on_delay_ms) 71 mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_on_delay_ms); 72 73 return dsi_ctx.accum_err; 74 } 75 76 static int jadard_disable(struct drm_panel *panel) 77 { 78 struct jadard *jadard = panel_to_jadard(panel); 79 struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 80 81 if (jadard->desc->backlight_off_to_display_off_delay_ms) 82 mipi_dsi_msleep(&dsi_ctx, jadard->desc->backlight_off_to_display_off_delay_ms); 83 84 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 85 86 if (jadard->desc->display_off_to_enter_sleep_delay_ms) 87 mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_off_to_enter_sleep_delay_ms); 88 89 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 90 91 if (jadard->desc->enter_sleep_to_reset_down_delay_ms) 92 mipi_dsi_msleep(&dsi_ctx, jadard->desc->enter_sleep_to_reset_down_delay_ms); 93 94 return dsi_ctx.accum_err; 95 } 96 97 static int jadard_prepare(struct drm_panel *panel) 98 { 99 struct jadard *jadard = panel_to_jadard(panel); 100 int ret; 101 102 ret = regulator_enable(jadard->vccio); 103 if (ret) 104 return ret; 105 106 ret = regulator_enable(jadard->vdd); 107 if (ret) 108 return ret; 109 110 if (jadard->desc->vcioo_to_lp11_delay_ms) 111 msleep(jadard->desc->vcioo_to_lp11_delay_ms); 112 113 if (jadard->desc->lp11_before_reset) { 114 ret = mipi_dsi_dcs_nop(jadard->dsi); 115 if (ret) 116 return ret; 117 } 118 119 if (jadard->desc->lp11_to_reset_delay_ms) 120 msleep(jadard->desc->lp11_to_reset_delay_ms); 121 122 gpiod_set_value(jadard->reset, 1); 123 msleep(5); 124 125 gpiod_set_value(jadard->reset, 0); 126 msleep(10); 127 128 gpiod_set_value(jadard->reset, 1); 129 msleep(130); 130 131 ret = jadard->desc->init(jadard); 132 if (ret) 133 return ret; 134 135 return 0; 136 } 137 138 static int jadard_unprepare(struct drm_panel *panel) 139 { 140 struct jadard *jadard = panel_to_jadard(panel); 141 142 gpiod_set_value(jadard->reset, 1); 143 msleep(120); 144 145 if (jadard->desc->reset_before_power_off_vcioo) { 146 gpiod_set_value(jadard->reset, 0); 147 148 usleep_range(1000, 2000); 149 } 150 151 regulator_disable(jadard->vdd); 152 regulator_disable(jadard->vccio); 153 154 return 0; 155 } 156 157 static int jadard_get_modes(struct drm_panel *panel, 158 struct drm_connector *connector) 159 { 160 struct jadard *jadard = panel_to_jadard(panel); 161 const struct drm_display_mode *desc_mode = &jadard->desc->mode; 162 struct drm_display_mode *mode; 163 164 mode = drm_mode_duplicate(connector->dev, desc_mode); 165 if (!mode) { 166 DRM_DEV_ERROR(&jadard->dsi->dev, "failed to add mode %ux%ux@%u\n", 167 desc_mode->hdisplay, desc_mode->vdisplay, 168 drm_mode_vrefresh(desc_mode)); 169 return -ENOMEM; 170 } 171 172 drm_mode_set_name(mode); 173 drm_mode_probed_add(connector, mode); 174 175 connector->display_info.width_mm = mode->width_mm; 176 connector->display_info.height_mm = mode->height_mm; 177 178 return 1; 179 } 180 181 static enum drm_panel_orientation jadard_panel_get_orientation(struct drm_panel *panel) 182 { 183 struct jadard *jadard = panel_to_jadard(panel); 184 185 return jadard->orientation; 186 } 187 188 static const struct drm_panel_funcs jadard_funcs = { 189 .disable = jadard_disable, 190 .unprepare = jadard_unprepare, 191 .prepare = jadard_prepare, 192 .enable = jadard_enable, 193 .get_modes = jadard_get_modes, 194 .get_orientation = jadard_panel_get_orientation, 195 }; 196 197 static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) 198 { 199 struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 200 201 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 202 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); 203 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); 204 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); 205 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); 206 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); 207 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); 208 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); 209 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); 210 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65); 211 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); 212 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); 213 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7); 214 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); 215 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); 216 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7); 217 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); 218 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE); 219 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); 220 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); 221 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); 222 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); 223 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01); 224 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70); 225 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); 226 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); 227 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF); 228 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); 229 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); 230 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E); 231 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F); 232 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); 233 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04); 234 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); 235 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); 236 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9); 237 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A); 238 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); 239 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37); 240 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19); 241 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78); 242 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63); 243 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54); 244 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49); 245 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45); 246 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38); 247 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D); 248 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28); 249 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43); 250 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41); 251 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); 252 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62); 253 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50); 254 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57); 255 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49); 256 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44); 257 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37); 258 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23); 259 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10); 260 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78); 261 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63); 262 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54); 263 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49); 264 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45); 265 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38); 266 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D); 267 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28); 268 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43); 269 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41); 270 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); 271 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62); 272 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50); 273 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57); 274 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49); 275 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44); 276 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); 277 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); 278 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); 279 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); 280 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); 281 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); 282 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); 283 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45); 284 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B); 285 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B); 286 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49); 287 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49); 288 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41); 289 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F); 290 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F); 291 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F); 292 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F); 293 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F); 294 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F); 295 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F); 296 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F); 297 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57); 298 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77); 299 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35); 300 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F); 301 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); 302 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46); 303 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46); 304 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44); 305 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44); 306 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A); 307 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A); 308 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48); 309 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48); 310 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40); 311 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F); 312 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F); 313 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F); 314 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F); 315 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F); 316 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F); 317 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F); 318 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F); 319 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57); 320 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77); 321 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35); 322 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F); 323 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); 324 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); 325 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00); 326 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00); 327 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10); 328 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06); 329 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40); 330 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01); 331 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); 332 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30); 333 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01); 334 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02); 335 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03); 336 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B); 337 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); 338 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C); 339 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); 340 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09); 341 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03); 342 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56); 343 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); 344 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); 345 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04); 346 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04); 347 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); 348 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00); 349 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00); 350 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06); 351 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B); 352 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00); 353 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8); 354 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); 355 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5); 356 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E); 357 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12); 358 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03); 359 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00); 360 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00); 361 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03); 362 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B); 363 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); 364 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); 365 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); 366 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); 367 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A); 368 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); 369 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 370 371 return dsi_ctx.accum_err; 372 }; 373 374 static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = { 375 .mode = { 376 .clock = 70000, 377 378 .hdisplay = 800, 379 .hsync_start = 800 + 40, 380 .hsync_end = 800 + 40 + 18, 381 .htotal = 800 + 40 + 18 + 20, 382 383 .vdisplay = 1280, 384 .vsync_start = 1280 + 20, 385 .vsync_end = 1280 + 20 + 4, 386 .vtotal = 1280 + 20 + 4 + 20, 387 388 .width_mm = 127, 389 .height_mm = 199, 390 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 391 }, 392 .lanes = 4, 393 .format = MIPI_DSI_FMT_RGB888, 394 .init = radxa_display_8hd_ad002_init_cmds, 395 }; 396 397 static int cz101b4001_init_cmds(struct jadard *jadard) 398 { 399 struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 400 401 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 402 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); 403 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); 404 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); 405 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); 406 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); 407 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); 408 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B); 409 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); 410 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); 411 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xAF); 412 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); 413 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00); 414 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xAF); 415 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00); 416 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26); 417 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09); 418 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04); 419 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00); 420 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01); 421 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x78); 422 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF); 423 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF); 424 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x7F); 425 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); 426 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0); 427 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81); 428 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14); 429 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23); 430 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28); 431 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); 432 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69); 433 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A); 434 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x2A); 435 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x17); 436 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x7F); 437 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x6B); 438 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x5C); 439 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4F); 440 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4D); 441 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3F); 442 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42); 443 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2B); 444 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44); 445 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43); 446 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43); 447 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63); 448 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52); 449 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x5A); 450 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x4F); 451 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x4E); 452 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x20); 453 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x0F); 454 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x00); 455 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7F); 456 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6B); 457 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5C); 458 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4F); 459 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4D); 460 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3F); 461 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42); 462 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2B); 463 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44); 464 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43); 465 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43); 466 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x63); 467 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x52); 468 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x5A); 469 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x4F); 470 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x4E); 471 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); 472 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); 473 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); 474 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); 475 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); 476 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); 477 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); 478 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); 479 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1E); 480 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1E); 481 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1F); 482 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1F); 483 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1F); 484 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17); 485 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x17); 486 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x37); 487 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x37); 488 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x47); 489 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x47); 490 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x45); 491 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45); 492 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4B); 493 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4B); 494 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49); 495 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49); 496 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F); 497 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01); 498 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01); 499 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00); 500 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00); 501 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x1E); 502 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x1E); 503 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x1F); 504 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x1F); 505 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x1F); 506 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x17); 507 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17); 508 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37); 509 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37); 510 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46); 511 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46); 512 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44); 513 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44); 514 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4A); 515 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4A); 516 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48); 517 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x48); 518 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F); 519 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2C, 0x01); 520 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2D, 0x01); 521 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2E, 0x00); 522 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2F, 0x00); 523 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1F); 524 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1F); 525 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1E); 526 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1E); 527 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1F); 528 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17); 529 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17); 530 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37); 531 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37); 532 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); 533 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x08); 534 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x0A); 535 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x0A); 536 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0x04); 537 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0x04); 538 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0x06); 539 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); 540 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1F); 541 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02); 542 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02); 543 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); 544 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); 545 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1F); 546 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1F); 547 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1E); 548 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1E); 549 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4A, 0x1F); 550 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x17); 551 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4C, 0x17); 552 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4D, 0x37); 553 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4E, 0x37); 554 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4F, 0x09); 555 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09); 556 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0B); 557 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0B); 558 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05); 559 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05); 560 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07); 561 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07); 562 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1F); 563 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); 564 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x30); 565 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x16); 566 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x34); 567 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x05); 568 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02); 569 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00); 570 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6A); 571 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73); 572 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1D); 573 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08); 574 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x6A); 575 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08); 576 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00); 577 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x00); 578 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x00); 579 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88); 580 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xFF); 581 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xDD); 582 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3F); 583 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15); 584 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17); 585 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14); 586 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82); 587 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); 588 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); 589 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); 590 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); 591 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); 592 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); 593 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02); 594 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C); 595 596 return dsi_ctx.accum_err; 597 }; 598 599 static const struct jadard_panel_desc cz101b4001_desc = { 600 .mode = { 601 .clock = 70000, 602 603 .hdisplay = 800, 604 .hsync_start = 800 + 40, 605 .hsync_end = 800 + 40 + 18, 606 .htotal = 800 + 40 + 18 + 20, 607 608 .vdisplay = 1280, 609 .vsync_start = 1280 + 20, 610 .vsync_end = 1280 + 20 + 4, 611 .vtotal = 1280 + 20 + 4 + 20, 612 613 .width_mm = 62, 614 .height_mm = 110, 615 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 616 }, 617 .lanes = 4, 618 .format = MIPI_DSI_FMT_RGB888, 619 .init = cz101b4001_init_cmds, 620 }; 621 622 static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) 623 { 624 struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; 625 626 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); 627 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); 628 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); 629 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); 630 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); 631 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); 632 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); 633 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); 634 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xc7); 635 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01); 636 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); 637 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xc7); 638 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01); 639 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe); 640 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); 641 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28); 642 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); 643 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); 644 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12); 645 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e); 646 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); 647 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); 648 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f); 649 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); 650 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); 651 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e); 652 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b); 653 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); 654 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a); 655 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); 656 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e); 657 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a); 658 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15); 659 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f); 660 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x61); 661 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x50); 662 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x43); 663 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3f); 664 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x32); 665 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x35); 666 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x1f); 667 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x38); 668 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x36); 669 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x36); 670 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x54); 671 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x42); 672 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x48); 673 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x39); 674 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x34); 675 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x26); 676 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x14); 677 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02); 678 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f); 679 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x61); 680 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x50); 681 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x43); 682 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3f); 683 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x32); 684 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x35); 685 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x1f); 686 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x38); 687 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x36); 688 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x36); 689 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x54); 690 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x42); 691 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x48); 692 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x39); 693 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x34); 694 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x26); 695 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x14); 696 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02); 697 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); 698 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52); 699 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f); 700 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f); 701 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50); 702 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77); 703 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57); 704 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f); 705 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e); 706 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c); 707 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f); 708 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a); 709 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48); 710 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x5f); 711 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46); 712 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44); 713 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40); 714 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f); 715 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x5f); 716 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f); 717 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f); 718 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f); 719 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f); 720 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53); 721 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f); 722 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5f); 723 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51); 724 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77); 725 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57); 726 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f); 727 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f); 728 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d); 729 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f); 730 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b); 731 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49); 732 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x5f); 733 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47); 734 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45); 735 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41); 736 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f); 737 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x5f); 738 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f); 739 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f); 740 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f); 741 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f); 742 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13); 743 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f); 744 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f); 745 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01); 746 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x17); 747 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17); 748 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1f); 749 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d); 750 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f); 751 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x1f); 752 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05); 753 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07); 754 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x1f); 755 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09); 756 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b); 757 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11); 758 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x1f); 759 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x1f); 760 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f); 761 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f); 762 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f); 763 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f); 764 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12); 765 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f); 766 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f); 767 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); 768 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x17); 769 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17); 770 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1f); 771 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c); 772 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e); 773 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x1f); 774 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04); 775 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06); 776 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x1f); 777 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08); 778 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a); 779 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10); 780 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x1f); 781 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x1f); 782 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f); 783 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f); 784 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f); 785 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f); 786 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); 787 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); 788 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06); 789 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40); 790 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00); 791 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00); 792 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40); 793 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03); 794 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04); 795 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c); 796 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c); 797 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75); 798 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08); 799 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4); 800 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08); 801 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c); 802 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c); 803 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c); 804 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); 805 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00); 806 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); 807 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb); 808 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); 809 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05); 810 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a); 811 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); 812 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); 813 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); 814 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); 815 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); 816 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); 817 818 return dsi_ctx.accum_err; 819 }; 820 821 static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = { 822 .mode = { 823 .clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000, 824 825 .hdisplay = 800, 826 .hsync_start = 800 + 24, 827 .hsync_end = 800 + 24 + 24, 828 .htotal = 800 + 24 + 24 + 24, 829 830 .vdisplay = 1280, 831 .vsync_start = 1280 + 30, 832 .vsync_end = 1280 + 30 + 4, 833 .vtotal = 1280 + 30 + 4 + 8, 834 835 .width_mm = 135, 836 .height_mm = 216, 837 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 838 }, 839 .lanes = 4, 840 .format = MIPI_DSI_FMT_RGB888, 841 .init = kingdisplay_kd101ne3_init_cmds, 842 .lp11_before_reset = true, 843 .reset_before_power_off_vcioo = true, 844 .vcioo_to_lp11_delay_ms = 5, 845 .lp11_to_reset_delay_ms = 10, 846 .exit_sleep_to_display_on_delay_ms = 120, 847 .display_on_delay_ms = 20, 848 .backlight_off_to_display_off_delay_ms = 100, 849 .display_off_to_enter_sleep_delay_ms = 50, 850 .enter_sleep_to_reset_down_delay_ms = 100, 851 }; 852 853 static int jadard_dsi_probe(struct mipi_dsi_device *dsi) 854 { 855 struct device *dev = &dsi->dev; 856 const struct jadard_panel_desc *desc; 857 struct jadard *jadard; 858 int ret; 859 860 jadard = devm_kzalloc(&dsi->dev, sizeof(*jadard), GFP_KERNEL); 861 if (!jadard) 862 return -ENOMEM; 863 864 desc = of_device_get_match_data(dev); 865 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 866 MIPI_DSI_MODE_NO_EOT_PACKET; 867 dsi->format = desc->format; 868 dsi->lanes = desc->lanes; 869 870 jadard->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 871 if (IS_ERR(jadard->reset)) { 872 DRM_DEV_ERROR(&dsi->dev, "failed to get our reset GPIO\n"); 873 return PTR_ERR(jadard->reset); 874 } 875 876 jadard->vdd = devm_regulator_get(dev, "vdd"); 877 if (IS_ERR(jadard->vdd)) { 878 DRM_DEV_ERROR(&dsi->dev, "failed to get vdd regulator\n"); 879 return PTR_ERR(jadard->vdd); 880 } 881 882 jadard->vccio = devm_regulator_get(dev, "vccio"); 883 if (IS_ERR(jadard->vccio)) { 884 DRM_DEV_ERROR(&dsi->dev, "failed to get vccio regulator\n"); 885 return PTR_ERR(jadard->vccio); 886 } 887 888 drm_panel_init(&jadard->panel, dev, &jadard_funcs, 889 DRM_MODE_CONNECTOR_DSI); 890 891 ret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation); 892 if (ret < 0) 893 return dev_err_probe(dev, ret, "failed to get orientation\n"); 894 895 ret = drm_panel_of_backlight(&jadard->panel); 896 if (ret) 897 return ret; 898 899 drm_panel_add(&jadard->panel); 900 901 mipi_dsi_set_drvdata(dsi, jadard); 902 jadard->dsi = dsi; 903 jadard->desc = desc; 904 905 ret = mipi_dsi_attach(dsi); 906 if (ret < 0) 907 drm_panel_remove(&jadard->panel); 908 909 return ret; 910 } 911 912 static void jadard_dsi_remove(struct mipi_dsi_device *dsi) 913 { 914 struct jadard *jadard = mipi_dsi_get_drvdata(dsi); 915 916 mipi_dsi_detach(dsi); 917 drm_panel_remove(&jadard->panel); 918 } 919 920 static const struct of_device_id jadard_of_match[] = { 921 { 922 .compatible = "chongzhou,cz101b4001", 923 .data = &cz101b4001_desc 924 }, 925 { 926 .compatible = "kingdisplay,kd101ne3-40ti", 927 .data = &kingdisplay_kd101ne3_40ti_desc 928 }, 929 { 930 .compatible = "radxa,display-10hd-ad001", 931 .data = &cz101b4001_desc 932 }, 933 { 934 .compatible = "radxa,display-8hd-ad002", 935 .data = &radxa_display_8hd_ad002_desc 936 }, 937 { /* sentinel */ } 938 }; 939 MODULE_DEVICE_TABLE(of, jadard_of_match); 940 941 static struct mipi_dsi_driver jadard_driver = { 942 .probe = jadard_dsi_probe, 943 .remove = jadard_dsi_remove, 944 .driver = { 945 .name = "jadard-jd9365da", 946 .of_match_table = jadard_of_match, 947 }, 948 }; 949 module_mipi_dsi_driver(jadard_driver); 950 951 MODULE_AUTHOR("Jagan Teki <jagan@edgeble.ai>"); 952 MODULE_AUTHOR("Stephen Chen <stephen@radxa.com>"); 953 MODULE_DESCRIPTION("Jadard JD9365DA-H3 WXGA DSI panel"); 954 MODULE_LICENSE("GPL"); 955