1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for panels based on Himax HX83102 controller, such as: 4 * 5 * - Starry 10.51" WUXGA MIPI-DSI panel 6 * 7 * Based on drivers/gpu/drm/panel/panel-himax-hx8394.c 8 */ 9 10 #include <linux/backlight.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/regulator/consumer.h> 16 17 #include <drm/drm_connector.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_panel.h> 21 22 #include <video/mipi_display.h> 23 24 /* Manufacturer specific DSI commands */ 25 #define HX83102_SETPOWER 0xb1 26 #define HX83102_SETDISP 0xb2 27 #define HX83102_SETCYC 0xb4 28 #define HX83102_UNKNOWN_B6 0xb6 29 #define HX83102_UNKNOWN_B8 0xb8 30 #define HX83102_SETEXTC 0xb9 31 #define HX83102_SETMIPI 0xba 32 #define HX83102_SETVDC 0xbc 33 #define HX83102_SETBANK 0xbd 34 #define HX83102_UNKNOWN_BE 0xbe 35 #define HX83102_SETPTBA 0xbf 36 #define HX83102_SETSTBA 0xc0 37 #define HX83102_SETTCON 0xc7 38 #define HX83102_SETRAMDMY 0xc8 39 #define HX83102_SETPWM 0xc9 40 #define HX83102_SETCLOCK 0xcb 41 #define HX83102_SETPANEL 0xcc 42 #define HX83102_SETCASCADE 0xd0 43 #define HX83102_SETPCTRL 0xd1 44 #define HX83102_UNKNOWN_D2 0xd2 45 #define HX83102_SETGIP0 0xd3 46 #define HX83102_SETGIP1 0xd5 47 #define HX83102_SETGIP2 0xd6 48 #define HX83102_SETGIP3 0xd8 49 #define HX83102_UNKNOWN_D9 0xd9 50 #define HX83102_SETGMA 0xe0 51 #define HX83102_UNKNOWN_E1 0xe1 52 #define HX83102_SETTP1 0xe7 53 #define HX83102_SETSPCCMD 0xe9 54 55 struct hx83102 { 56 struct drm_panel base; 57 struct mipi_dsi_device *dsi; 58 59 const struct hx83102_panel_desc *desc; 60 61 enum drm_panel_orientation orientation; 62 struct regulator *pp1800; 63 struct regulator *avee; 64 struct regulator *avdd; 65 struct gpio_desc *enable_gpio; 66 }; 67 68 struct hx83102_panel_desc { 69 const struct drm_display_mode *modes; 70 71 /** 72 * @width_mm: width of the panel's active display area 73 * @height_mm: height of the panel's active display area 74 */ 75 struct { 76 unsigned int width_mm; 77 unsigned int height_mm; 78 } size; 79 80 bool has_backlight; 81 82 int (*init)(struct hx83102 *ctx); 83 }; 84 85 static inline struct hx83102 *panel_to_hx83102(struct drm_panel *panel) 86 { 87 return container_of(panel, struct hx83102, base); 88 } 89 90 static void hx83102_enable_extended_cmds(struct mipi_dsi_multi_context *dsi_ctx, bool enable) 91 { 92 if (enable) 93 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x21, 0x55, 0x00); 94 else 95 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x00, 0x00, 0x00); 96 } 97 98 static int starry_himax83102_j02_init(struct hx83102 *ctx) 99 { 100 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 101 102 hx83102_enable_extended_cmds(&dsi_ctx, true); 103 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb5, 0xb5, 0x31, 0xf1, 104 0x31, 0xd7, 0x2f, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 105 0x65, 0x00, 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x74, 106 0x33); 107 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 108 0x12, 0x72, 0x3c, 0xa3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xf5); 109 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x76, 0x76, 0x76, 0x76, 0x76, 110 0x76, 0x63, 0x5c, 0x63, 0x5c, 0x01, 0x9e); 111 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 112 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 113 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 114 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 115 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 116 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4); 117 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x36, 0x36, 0x22, 0x11, 0x22, 118 0xa0, 0x61, 0x08, 0xf5, 0x03); 119 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 120 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 121 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 122 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 123 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 124 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 125 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 126 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x33); 127 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); 128 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 129 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 130 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 131 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0c, 132 0xff); 133 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x1f, 0x11, 0x1f); 134 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 135 0x08, 0x00, 0x08, 0x37, 0x47, 0x34, 0x3b, 0x12, 0x12, 0x03, 0x03, 136 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 137 0x17, 0x94, 0x07, 0x94, 0x00, 0x00); 138 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 139 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1a, 0x1a, 0x1b, 140 0x1b, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 141 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 142 0x18, 0x18, 0x18, 0x18, 0x18); 143 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 144 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1a, 0x1a, 0x1b, 145 0x1b, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, 146 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 147 0x18, 0x18, 0x18, 0x18, 0x18); 148 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 149 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 150 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 151 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0); 152 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x09, 0x14, 0x1e, 0x26, 0x48, 153 0x61, 0x67, 0x6c, 0x67, 0x7d, 0x7f, 0x80, 0x8b, 0x87, 0x8f, 0x98, 154 0xab, 0xab, 0x55, 0x5c, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1e, 0x26, 155 0x48, 0x61, 0x67, 0x6c, 0x67, 0x7d, 0x7f, 0x80, 0x8b, 0x87, 0x8f, 156 0x98, 0xab, 0xab, 0x55, 0x5c, 0x68, 0x73); 157 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x0e, 0x10, 0x10, 0x21, 0x2b, 0x9a, 158 0x02, 0x54, 0x9a, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 159 0x02, 0x02, 0x10); 160 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 161 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0xbf, 0x11); 162 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 163 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x3c, 0xfa); 164 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 165 0x00, 0x00, 0x80, 0x0c, 0x01); 166 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x28, 0x01, 0x7e, 0x0f, 167 0x7e, 0x10, 0xa0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40); 168 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 169 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xbf, 0xfe, 0xaa, 0xa0, 170 0xff, 0xff, 0xbf, 0xfe, 0xaa, 0xa0); 171 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x04, 0xfe, 0x04, 0xfe, 0x04, 172 0x03, 0x03, 0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 173 0x9e, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00); 174 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 175 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 176 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 177 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 178 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00, 179 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xfc, 0x00, 180 0x00, 0x00, 0x3f, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa8, 181 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00); 182 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 183 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 184 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 185 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 186 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 187 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 188 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 189 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 190 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 191 192 return dsi_ctx.accum_err; 193 }; 194 195 static int boe_nv110wum_init(struct hx83102 *ctx) 196 { 197 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 198 199 msleep(60); 200 201 hx83102_enable_extended_cmds(&dsi_ctx, true); 202 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xaf, 0xaf, 0x2b, 0xeb, 0x42, 203 0xe1, 0x4d, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 0x65, 0x00, 204 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x9a, 0x33); 205 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x12, 206 0x71, 0x3c, 0xa3, 0x11, 0x00, 0x00, 0x00, 0x88, 0xf5, 0x22, 0x8f); 207 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x49, 0x49, 0x32, 0x32, 0x14, 0x32, 208 0x84, 0x6e, 0x84, 0x6e, 0x01, 0x9c); 209 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 210 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 211 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 212 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 213 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 214 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x84); 215 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x36, 0x36, 0x22, 0x00, 0x00, 0xa0, 216 0x61, 0x08, 0xf5, 0x03); 217 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 218 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 219 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 220 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 221 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 222 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 223 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x30, 0xd4, 0x01); 224 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x34); 225 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 226 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 227 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 228 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 229 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0c, 0xff); 230 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x1f, 0x11, 0x1f, 0x11); 231 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x04, 232 0x08, 0x04, 0x08, 0x37, 0x37, 0x64, 0x4b, 0x11, 0x11, 0x03, 0x03, 0x32, 233 0x10, 0x0e, 0x00, 0x0e, 0x32, 0x10, 0x0a, 0x00, 0x0a, 0x32, 0x17, 0x98, 234 0x07, 0x98, 0x00, 0x00); 235 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x1e, 0x1e, 236 0x1e, 0x1e, 0x1f, 0x1f, 0x1f, 0x1f, 0x24, 0x24, 0x24, 0x24, 0x07, 0x06, 237 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 238 0x01, 0x00, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 239 0x18, 0x18); 240 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaf, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 241 0xaf, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); 242 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x05, 0x0d, 0x14, 0x1b, 0x2c, 243 0x44, 0x49, 0x51, 0x4c, 0x67, 0x6c, 0x71, 0x80, 0x7d, 0x84, 0x8d, 0xa0, 244 0xa0, 0x4f, 0x58, 0x64, 0x73, 0x00, 0x05, 0x0d, 0x14, 0x1b, 0x2c, 0x44, 245 0x49, 0x51, 0x4c, 0x67, 0x6c, 0x71, 0x80, 0x7d, 0x84, 0x8d, 0xa0, 0xa0, 246 0x4f, 0x58, 0x64, 0x73); 247 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x1a, 0x26, 0x9e, 248 0x00, 0x53, 0x9b, 0x14, 0x14); 249 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 250 0x07, 0x80, 0x02, 0x58, 0x00, 0x14, 0x02, 0x58, 0x02, 0x58, 0x02, 0x00, 251 0x02, 0x2c, 0x00, 0x20, 0x02, 0x02, 0x00, 0x08, 0x00, 0x0c, 0x05, 0x0e, 252 0x04, 0x94, 0x18, 0x00, 0x10, 0xf0, 0x03, 0x0c, 0x20, 0x00, 0x06, 0x0b, 253 0x0b, 0x33, 0x0e); 254 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 255 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 256 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0); 257 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0xbf, 0x11); 258 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 259 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x96); 260 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc9); 261 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x84); 262 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 263 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd1); 264 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0xf6, 0x2b, 0x34, 0x2b, 0x74, 0x3b, 265 0x74, 0x6b, 0x74); 266 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 267 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x2b, 0x01, 0x7e, 0x0f, 268 0x7e, 0x10, 0xa0, 0x00, 0x00); 269 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 270 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x02, 0x00, 0xbb, 0x11); 271 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xaf, 0xff, 0xff, 0xfa, 0xa0, 272 0xff, 0xaf, 0xff, 0xff, 0xfa, 0xa0); 273 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 274 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x65, 275 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00); 276 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 277 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00, 278 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00, 279 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00); 280 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 281 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 282 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 283 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00); 284 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 285 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 286 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 287 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 288 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 289 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 290 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 291 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 292 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 293 hx83102_enable_extended_cmds(&dsi_ctx, false); 294 295 mipi_dsi_msleep(&dsi_ctx, 50); 296 297 return dsi_ctx.accum_err; 298 }; 299 300 static int csot_pna957qt1_1_init(struct hx83102 *ctx) 301 { 302 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 303 304 msleep(60); 305 306 hx83102_enable_extended_cmds(&dsi_ctx, true); 307 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 308 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd2); 309 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 310 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb3, 0xb3, 0x31, 0xf1, 0x33, 311 0xe0, 0x54, 0x36, 0x36, 0x3a, 0x3a, 0x32, 0x8b, 0x11, 0xe5, 312 0x98); 313 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd9); 314 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x8b, 0x33); 315 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 316 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x2c, 317 0x80, 0x3c, 0x9f, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); 318 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x41, 0x41, 0x41, 0x41, 0x64, 0x64, 319 0x40, 0x84, 0x64, 0x84, 0x01, 0x9d, 0x01, 0x02, 0x01, 0x00, 320 0x00); 321 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 322 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 323 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4, 0x80, 0x9c, 0x36, 0x00, 324 0x0d, 0x04); 325 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32, 0x22, 0x11, 0x22, 0xa0, 326 0x31, 0x08, 0xf5, 0x03); 327 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 328 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 329 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 330 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 331 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 332 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 333 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 334 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 335 0x36); 336 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 337 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2c, 338 0xff); 339 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, 340 0x08, 0x04, 0x08, 0x37, 0x07, 0x44, 0x37, 0x2b, 0x2b, 0x03, 341 0x03, 0x32, 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, 342 0x29, 0x32, 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); 343 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 344 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 345 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 346 0x18, 0x18, 0x25, 0x24, 0x25, 0x24, 0x1f, 0x1f, 0x1f, 0x1f, 347 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x20, 0x20, 0x20); 348 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 349 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 350 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x0a, 0x0e, 0x1a, 0x21, 0x28, 0x46, 351 0x5c, 0x61, 0x63, 0x5e, 0x78, 0x7d, 0x80, 0x8e, 0x89, 0x90, 352 0x98, 0xaa, 0xa8, 0x52, 0x59, 0x60, 0x6f, 0x06, 0x0a, 0x16, 353 0x1d, 0x24, 0x46, 0x5c, 0x61, 0x6b, 0x66, 0x7c, 0x7d, 0x80, 354 0x8e, 0x89, 0x90, 0x98, 0xaa, 0xa8, 0x52, 0x59, 0x60, 0x6f); 355 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xe0, 0x10, 0x10, 0x0d, 0x1e, 0x9d, 356 0x02, 0x52, 0x9d, 0x14, 0x14); 357 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 358 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 359 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 360 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 361 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 362 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 363 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x64); 364 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 365 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00); 366 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 367 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 368 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x05, 0x15, 0x55, 0x45, 369 0x55, 0x50, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); 370 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x24, 0x01, 0x7e, 0x0f, 371 0x7c, 0x10, 0xa0, 0x00, 0x00); 372 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 373 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7b); 374 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0, 375 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0); 376 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 377 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 378 0x20, 0x9d, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 379 0x01, 0x00); 380 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 381 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x66, 0x81); 382 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 383 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 384 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 385 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 386 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x0f, 0x2a, 0xaa, 0x8a, 387 0xaa, 0xf0, 0x0f, 0x2a, 0xaa, 0x8a, 0xaa, 0xf0, 0x0a, 0x2a, 388 0xaa, 0x8a, 0xaa, 0xa0, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 389 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 390 hx83102_enable_extended_cmds(&dsi_ctx, false); 391 392 mipi_dsi_msleep(&dsi_ctx, 60); 393 394 return dsi_ctx.accum_err; 395 }; 396 397 static int ivo_t109nw41_init(struct hx83102 *ctx) 398 { 399 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 400 401 msleep(60); 402 403 hx83102_enable_extended_cmds(&dsi_ctx, true); 404 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xed, 0xed, 0x27, 0xe7, 0x52, 405 0xf5, 0x39, 0x36, 0x36, 0x36, 0x36, 0x32, 0x8b, 0x11, 0x65, 0x00, 0x88, 406 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0xd6, 0x33); 407 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x12, 408 0x71, 0x3c, 0xa3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01); 409 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x35, 0x35, 0x43, 0x43, 0x35, 0x35, 410 0x30, 0x7a, 0x30, 0x7a, 0x01, 0x9d); 411 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 412 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 413 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 414 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 415 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 416 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4); 417 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x34, 0x34, 0x22, 0x11, 0x22, 0xa0, 418 0x31, 0x08, 0xf5, 0x03); 419 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 420 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 421 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 422 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd3); 423 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x22); 424 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 425 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 426 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 427 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 428 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 429 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x34); 430 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 431 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 432 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 433 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 434 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2c, 435 0xff); 436 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x08, 437 0x08, 0x08, 0x08, 0x37, 0x07, 0x64, 0x7c, 0x11, 0x11, 0x03, 0x03, 0x32, 438 0x10, 0x0e, 0x00, 0x0e, 0x32, 0x17, 0x97, 0x07, 0x97, 0x32, 0x00, 0x02, 439 0x00, 0x02, 0x00, 0x00); 440 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x25, 0x24, 0x25, 0x24, 0x18, 0x18, 441 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 442 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x1e, 0x1e, 0x1e, 0x1e, 0x1f, 0x1f, 443 0x1f, 0x1f, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 444 0x18, 0x18); 445 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 446 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 447 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 448 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 449 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x07, 0x10, 0x17, 0x1c, 0x33, 450 0x48, 0x50, 0x57, 0x50, 0x68, 0x6e, 0x71, 0x7f, 0x81, 0x8a, 0x8e, 0x9b, 451 0x9c, 0x4d, 0x56, 0x5d, 0x73, 0x00, 0x07, 0x10, 0x17, 0x1c, 0x33, 0x48, 452 0x50, 0x57, 0x50, 0x68, 0x6e, 0x71, 0x7f, 0x81, 0x8a, 0x8e, 0x9b, 0x9c, 453 0x4d, 0x56, 0x5d, 0x73); 454 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x1a, 0x26, 0x9e, 455 0x00, 0x4f, 0xa0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0a, 0x02, 456 0x02, 0x00, 0x33, 0x02, 0x04, 0x18, 0x01); 457 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 458 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 459 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 460 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x04, 0x00, 0x00); 461 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 462 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 463 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 464 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 465 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x2b, 0x01, 0x7e, 0x0f, 466 0x7e, 0x10, 0xa0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); 467 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 468 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2); 469 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x79); 470 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 471 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0); 472 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 473 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x6e, 474 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 475 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 476 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 477 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 478 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 479 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 480 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 481 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 482 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 483 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 484 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00); 485 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 486 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff); 487 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 488 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 489 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 490 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 491 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 492 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 493 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 494 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 495 hx83102_enable_extended_cmds(&dsi_ctx, false); 496 497 mipi_dsi_msleep(&dsi_ctx, 60); 498 499 return dsi_ctx.accum_err; 500 }; 501 502 static int kingdisplay_kd110n11_51ie_init(struct hx83102 *ctx) 503 { 504 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 505 506 msleep(50); 507 508 hx83102_enable_extended_cmds(&dsi_ctx, true); 509 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 510 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd1); 511 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 512 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb3, 0xb3, 0x31, 0xf1, 513 0x33, 0xe0, 0x54, 0x36, 0x36, 0x3a, 0x3a, 0x32, 0x8b, 514 0x11, 0xe5, 0x98); 515 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd9); 516 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x8b, 0x33); 517 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 518 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x2c, 519 0x80, 0x3c, 0x9f, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); 520 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 521 0x40, 0x84, 0x64, 0x84, 0x01, 0x9d, 0x01, 0x02, 0x01, 0x00, 522 0x00); 523 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 524 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 525 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4, 0x80, 0x9c, 0x36, 0x00, 526 0x0d, 0x04); 527 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32, 0x22, 0x11, 0x22, 0xa0, 528 0x31, 0x08, 0xf5, 0x03); 529 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 530 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 531 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 532 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 533 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 534 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 535 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 536 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 537 0x0f, 0x36); 538 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 539 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 540 0x04, 0x2c, 0xff); 541 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, 542 0x08, 0x04, 0x08, 0x37, 0x07, 0x44, 0x37, 0x2b, 0x2b, 0x03, 543 0x03, 0x32, 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, 544 0x29, 0x32, 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); 545 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 546 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 547 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 548 0x18, 0x18, 0x25, 0x24, 0x25, 0x24, 0x1f, 0x1f, 0x1f, 0x1f, 549 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x20, 0x20, 0x20); 550 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 551 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 552 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xe0, 0x10, 0x10, 0x0d, 0x1e, 0x9d, 553 0x02, 0x52, 0x9d, 0x14, 0x14); 554 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 555 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 556 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 557 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 558 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 559 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 560 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x64); 561 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 562 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00); 563 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 564 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 565 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x05, 0x15, 0x55, 0x45, 566 0x55, 0x50, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); 567 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x24, 0x01, 0x7e, 0x0f, 568 0x7c, 0x10, 0xa0, 0x00, 0x00); 569 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 570 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7b); 571 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0, 572 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0); 573 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 574 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 575 0x20, 0x9d, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 576 0x01, 0x00); 577 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 578 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x66, 0x81); 579 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 580 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 581 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 582 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 583 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x0f, 0x2a, 0xaa, 0x8a, 584 0xaa, 0xf0, 0x0f, 0x2a, 0xaa, 0x8a, 0xaa, 0xf0, 0x0a, 0x2a, 585 0xaa, 0x8a, 0xaa, 0xa0, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 586 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 587 hx83102_enable_extended_cmds(&dsi_ctx, false); 588 589 return dsi_ctx.accum_err; 590 } 591 592 static int starry_2082109qfh040022_50e_init(struct hx83102 *ctx) 593 { 594 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 595 596 msleep(50); 597 598 hx83102_enable_extended_cmds(&dsi_ctx, true); 599 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 600 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd1); 601 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 602 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb5, 0xb5, 0x31, 0xf1, 0x33, 603 0xc3, 0x57, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 0x65, 604 0x00, 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x3c, 0x33); 605 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x22, 606 0x70, 0x3c, 0xa1, 0x22, 0x00, 0x00, 0x00, 0x88, 0xf4); 607 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x14, 0x16, 0x14, 0x50, 0x14, 0x50, 608 0x0d, 0x6a, 0x0d, 0x6a, 0x01, 0x9e); 609 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x34, 0x34, 0x03); 610 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B8, 0x40); 611 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 612 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 613 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 614 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 615 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 616 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4); 617 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x38, 0x38, 0x22, 0x11, 0x33, 0xa0, 618 0x61, 0x08, 0xf5, 0x03); 619 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 620 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 621 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 622 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 623 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 624 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 625 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x30, 0xd4, 0x01); 626 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 627 0x16); 628 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 629 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 630 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 631 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 632 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, 633 0x2c, 0xff); 634 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 635 0x00, 0x00, 0x00, 0x3b, 0x03, 0x73, 0x3b, 0x21, 0x21, 0x03, 636 0x03, 0x98, 0x10, 0x1d, 0x00, 0x1d, 0x32, 0x17, 0xa1, 0x07, 637 0xa1, 0x43, 0x17, 0xa6, 0x07, 0xa6, 0x00, 0x00); 638 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 639 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x2a, 0x2b, 0x1f, 0x1f, 640 0x1e, 0x1e, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 641 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 642 0x0a, 0x0b, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18); 643 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x02, 0xaa, 0xea, 0xaa, 0xaa, 0x00, 644 0x02, 0xaa, 0xea, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 646 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 647 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x2a, 0x32, 0x9f, 648 0x01, 0x5a, 0x91, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 649 0x05, 0x02, 0x02, 0x10, 0x33, 0x02, 0x04, 0x18, 0x01); 650 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 651 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 652 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 653 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x3d); 654 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 655 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0c, 656 0xa1); 657 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 658 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x03, 0xff, 0xff, 0xff, 0xff, 0x00, 659 0x03, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 660 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 661 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 662 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x2d, 0x01, 0x7f, 0x0f, 663 0x7c, 0x10, 0xa0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); 664 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 665 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2); 666 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x02, 0x00, 0x00, 0x10, 0x58); 667 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x0a, 0x0a, 0x05, 0x03, 0x0a, 668 0x0a, 0x01, 0x03, 0x01, 0x01, 0x05, 0x0e); 669 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 670 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x03, 0x1f, 0xe0, 0x11, 0x70); 671 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 672 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xab, 0xff, 0xff, 0xff, 0xff, 0xa0, 673 0xab, 0xff, 0xff, 0xff, 0xff, 0xa0); 674 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 675 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x81, 0x02, 0x40, 0x00, 676 0x20, 0x9e, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 677 0x00, 0x00); 678 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 679 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 680 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 681 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 682 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xab, 0xea, 0xaa, 0xaa, 0xa0, 683 0xaa, 0xab, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xbf, 0xff, 0xff, 684 0xfe, 0xa0, 0xaa, 0xbf, 0xff, 0xff, 0xfe, 0xa0, 0xaa, 0xaa, 685 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); 686 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00); 687 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 688 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 689 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 690 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 691 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 692 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 693 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 694 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 695 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 696 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 697 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 698 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 699 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 700 hx83102_enable_extended_cmds(&dsi_ctx, false); 701 702 mipi_dsi_msleep(&dsi_ctx, 110); 703 704 return dsi_ctx.accum_err; 705 } 706 707 static int holitech_htf065h045_init(struct hx83102 *ctx) 708 { 709 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 710 711 msleep(50); 712 713 hx83102_enable_extended_cmds(&dsi_ctx, true); 714 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x22, 0x44, 0x27, 0x27, 0x32, 715 0x52, 0x57, 0x39, 0x08, 0x08, 0x08); 716 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x00, 0x06, 0x40, 0x00, 717 0x0e, 0xae, 0x38, 0x00, 0x00, 0x00, 0x00, 0xf4, 0xa0); 718 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x01, 0x58, 0x01, 0x58, 0x01, 719 0x58, 0x03, 0x58, 0x03, 0xff, 0x01, 0x20, 0x00, 0xff); 720 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); 721 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x00, 0x00, 0x00, 722 0x10, 0x00, 0x17, 0x00, 0x63, 0x37, 0x0e, 0x0e, 0x00, 0x00, 723 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x16, 0x4e, 0x06, 0x4e); 724 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x04, 0x0c, 0xb2, 0x01); 725 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x24, 0x25, 0x18, 0x18, 0x19, 726 0x19, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 727 0x18, 0x18, 0x18, 0x06, 0x07, 0x04, 0x05, 0x18, 0x18, 0x18, 728 0x18, 0x02, 0x03, 0x00, 0x01, 0x20, 0x21, 0x18, 0x18, 0x18, 729 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); 730 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 0x00, 0x09, 0x16, 0x1f, 0x28, 731 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, 0x91, 0xa0, 0x9e, 732 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, 0x7f, 0x00, 0x09, 733 0x16, 0x1f, 0x28, 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, 734 0x91, 0xa0, 0x9e, 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, 735 0x7f); 736 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xff, 0x14, 0x00, 0x00); 737 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 738 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x01); 739 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 740 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xff, 741 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0); 742 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 743 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 744 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 745 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); 746 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 747 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x70, 0x23, 0xa8, 0x93, 0xb2, 748 0xc0, 0xc0, 0x01, 0x10, 0x00, 0x00, 0x00, 0x0d, 0x3d, 0x82, 749 0x77, 0x04, 0x01, 0x04); 750 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 751 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x01); 752 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 753 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x00, 0x53, 0x00, 0x02, 0x59); 754 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x00, 0x04, 0x9e, 0xf6, 755 0x00, 0x5d); 756 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 757 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x42, 0x00, 0x33, 0x00, 0x33, 758 0x88, 0xb3, 0x00); 759 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 760 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x20, 0x01); 761 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 762 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x7f, 0x03, 0xf5); 763 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 764 765 return dsi_ctx.accum_err; 766 } 767 768 static const struct drm_display_mode starry_mode = { 769 .clock = 162680, 770 .hdisplay = 1200, 771 .hsync_start = 1200 + 60, 772 .hsync_end = 1200 + 60 + 20, 773 .htotal = 1200 + 60 + 20 + 40, 774 .vdisplay = 1920, 775 .vsync_start = 1920 + 116, 776 .vsync_end = 1920 + 116 + 8, 777 .vtotal = 1920 + 116 + 8 + 12, 778 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 779 }; 780 781 static const struct hx83102_panel_desc starry_desc = { 782 .modes = &starry_mode, 783 .size = { 784 .width_mm = 141, 785 .height_mm = 226, 786 }, 787 .init = starry_himax83102_j02_init, 788 }; 789 790 static const struct drm_display_mode boe_tv110wum_default_mode = { 791 .clock = 167700, 792 .hdisplay = 1200, 793 .hsync_start = 1200 + 75, 794 .hsync_end = 1200 + 75 + 20, 795 .htotal = 1200 + 75 + 20 + 65, 796 .vdisplay = 1920, 797 .vsync_start = 1920 + 115, 798 .vsync_end = 1920 + 115 + 8, 799 .vtotal = 1920 + 115 + 8 + 12, 800 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 801 }; 802 803 static const struct hx83102_panel_desc boe_nv110wum_desc = { 804 .modes = &boe_tv110wum_default_mode, 805 .size = { 806 .width_mm = 147, 807 .height_mm = 235, 808 }, 809 .init = boe_nv110wum_init, 810 }; 811 812 static const struct drm_display_mode csot_pna957qt1_1_default_mode = { 813 .clock = 177958, 814 .hdisplay = 1200, 815 .hsync_start = 1200 + 124, 816 .hsync_end = 1200 + 124 + 80, 817 .htotal = 1200 + 124 + 80 + 40, 818 .vdisplay = 1920, 819 .vsync_start = 1920 + 88, 820 .vsync_end = 1920 + 88 + 8, 821 .vtotal = 1920 + 88 + 8 + 38, 822 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 823 }; 824 825 static const struct hx83102_panel_desc csot_pna957qt1_1_desc = { 826 .modes = &csot_pna957qt1_1_default_mode, 827 .size = { 828 .width_mm = 147, 829 .height_mm = 235, 830 }, 831 .init = csot_pna957qt1_1_init, 832 }; 833 834 static const struct drm_display_mode ivo_t109nw41_default_mode = { 835 .clock = 167700, 836 .hdisplay = 1200, 837 .hsync_start = 1200 + 75, 838 .hsync_end = 1200 + 75 + 20, 839 .htotal = 1200 + 75 + 20 + 65, 840 .vdisplay = 1920, 841 .vsync_start = 1920 + 115, 842 .vsync_end = 1920 + 115 + 8, 843 .vtotal = 1920 + 115 + 8 + 12, 844 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 845 }; 846 847 static const struct hx83102_panel_desc ivo_t109nw41_desc = { 848 .modes = &ivo_t109nw41_default_mode, 849 .size = { 850 .width_mm = 147, 851 .height_mm = 235, 852 }, 853 .init = ivo_t109nw41_init, 854 }; 855 856 static const struct drm_display_mode kingdisplay_kd110n11_51ie_default_mode = { 857 .clock = 182750, 858 .hdisplay = 1200, 859 .hsync_start = 1200 + 124, 860 .hsync_end = 1200 + 124 + 80, 861 .htotal = 1200 + 124 + 80 + 80, 862 .vdisplay = 1920, 863 .vsync_start = 1920 + 88, 864 .vsync_end = 1920 + 88 + 8, 865 .vtotal = 1920 + 88 + 8 + 38, 866 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 867 }; 868 869 static const struct hx83102_panel_desc kingdisplay_kd110n11_51ie_desc = { 870 .modes = &kingdisplay_kd110n11_51ie_default_mode, 871 .size = { 872 .width_mm = 147, 873 .height_mm = 235, 874 }, 875 .init = kingdisplay_kd110n11_51ie_init, 876 }; 877 878 static const struct drm_display_mode starry_2082109qfh040022_50e_default_mode = { 879 .clock = 192050, 880 .hdisplay = 1200, 881 .hsync_start = 1200 + 160, 882 .hsync_end = 1200 + 160 + 66, 883 .htotal = 1200 + 160 + 66 + 120, 884 .vdisplay = 1920, 885 .vsync_start = 1920 + 115, 886 .vsync_end = 1920 + 115 + 8, 887 .vtotal = 1920 + 115 + 8 + 28, 888 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 889 }; 890 891 static const struct hx83102_panel_desc starry_2082109qfh040022_50e_desc = { 892 .modes = &starry_2082109qfh040022_50e_default_mode, 893 .size = { 894 .width_mm = 147, 895 .height_mm = 235, 896 }, 897 .init = starry_2082109qfh040022_50e_init, 898 }; 899 900 static const struct drm_display_mode holitech_htf065h045_default_mode = { 901 .clock = 90720, 902 .hdisplay = 720, 903 .hsync_start = 720 + 40, 904 .hsync_end = 720 + 40 + 40, 905 .htotal = 720 + 40 + 40 + 40, 906 .vdisplay = 1600, 907 .vsync_start = 1600 + 186, 908 .vsync_end = 1600 + 186 + 2, 909 .vtotal = 1600 + 186 + 2 + 12, 910 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 911 }; 912 913 static const struct hx83102_panel_desc holitech_htf065h045_desc = { 914 .modes = &holitech_htf065h045_default_mode, 915 .size = { 916 .width_mm = 68, 917 .height_mm = 151, 918 }, 919 .has_backlight = true, 920 .init = holitech_htf065h045_init, 921 }; 922 923 static int hx83102_enable(struct drm_panel *panel) 924 { 925 msleep(130); 926 return 0; 927 } 928 929 static int hx83102_disable(struct drm_panel *panel) 930 { 931 struct hx83102 *ctx = panel_to_hx83102(panel); 932 struct mipi_dsi_device *dsi = ctx->dsi; 933 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 934 935 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 936 937 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 938 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 939 940 mipi_dsi_msleep(&dsi_ctx, 150); 941 942 return dsi_ctx.accum_err; 943 } 944 945 static int hx83102_unprepare(struct drm_panel *panel) 946 { 947 struct hx83102 *ctx = panel_to_hx83102(panel); 948 949 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 950 usleep_range(1000, 2000); 951 regulator_disable(ctx->avee); 952 regulator_disable(ctx->avdd); 953 usleep_range(5000, 7000); 954 regulator_disable(ctx->pp1800); 955 956 return 0; 957 } 958 959 static int hx83102_prepare(struct drm_panel *panel) 960 { 961 struct hx83102 *ctx = panel_to_hx83102(panel); 962 struct mipi_dsi_device *dsi = ctx->dsi; 963 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 964 965 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 966 usleep_range(1000, 1500); 967 968 dsi_ctx.accum_err = regulator_enable(ctx->pp1800); 969 if (dsi_ctx.accum_err) 970 return dsi_ctx.accum_err; 971 972 usleep_range(3000, 5000); 973 974 dsi_ctx.accum_err = regulator_enable(ctx->avdd); 975 if (dsi_ctx.accum_err) 976 goto poweroff1v8; 977 dsi_ctx.accum_err = regulator_enable(ctx->avee); 978 if (dsi_ctx.accum_err) 979 goto poweroffavdd; 980 981 usleep_range(10000, 11000); 982 983 mipi_dsi_dcs_nop_multi(&dsi_ctx); 984 if (dsi_ctx.accum_err) 985 goto poweroff; 986 987 usleep_range(1000, 2000); 988 989 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 990 usleep_range(1000, 2000); 991 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 992 usleep_range(1000, 2000); 993 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 994 usleep_range(6000, 10000); 995 996 dsi_ctx.accum_err = ctx->desc->init(ctx); 997 998 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 999 mipi_dsi_msleep(&dsi_ctx, 120); 1000 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 1001 if (dsi_ctx.accum_err) 1002 goto poweroff; 1003 1004 return 0; 1005 1006 poweroff: 1007 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 1008 regulator_disable(ctx->avee); 1009 poweroffavdd: 1010 regulator_disable(ctx->avdd); 1011 poweroff1v8: 1012 usleep_range(5000, 7000); 1013 regulator_disable(ctx->pp1800); 1014 1015 return dsi_ctx.accum_err; 1016 } 1017 1018 static int hx83102_get_modes(struct drm_panel *panel, 1019 struct drm_connector *connector) 1020 { 1021 struct hx83102 *ctx = panel_to_hx83102(panel); 1022 const struct drm_display_mode *m = ctx->desc->modes; 1023 struct drm_display_mode *mode; 1024 1025 mode = drm_mode_duplicate(connector->dev, m); 1026 if (!mode) 1027 return -ENOMEM; 1028 1029 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 1030 drm_mode_set_name(mode); 1031 drm_mode_probed_add(connector, mode); 1032 1033 connector->display_info.width_mm = ctx->desc->size.width_mm; 1034 connector->display_info.height_mm = ctx->desc->size.height_mm; 1035 connector->display_info.bpc = 8; 1036 1037 return 1; 1038 } 1039 1040 static enum drm_panel_orientation hx83102_get_orientation(struct drm_panel *panel) 1041 { 1042 struct hx83102 *ctx = panel_to_hx83102(panel); 1043 1044 return ctx->orientation; 1045 } 1046 1047 static const struct drm_panel_funcs hx83102_drm_funcs = { 1048 .disable = hx83102_disable, 1049 .unprepare = hx83102_unprepare, 1050 .prepare = hx83102_prepare, 1051 .enable = hx83102_enable, 1052 .get_modes = hx83102_get_modes, 1053 .get_orientation = hx83102_get_orientation, 1054 }; 1055 1056 static int hx83102_bl_update_status(struct backlight_device *bl) 1057 { 1058 struct mipi_dsi_device *dsi = bl_get_data(bl); 1059 u16 brightness = backlight_get_brightness(bl); 1060 int ret; 1061 1062 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 1063 1064 ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness); 1065 if (ret < 0) 1066 return ret; 1067 1068 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 1069 1070 return 0; 1071 } 1072 1073 static int hx83102_bl_get_brightness(struct backlight_device *bl) 1074 { 1075 struct mipi_dsi_device *dsi = bl_get_data(bl); 1076 u16 brightness; 1077 int ret; 1078 1079 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 1080 1081 ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness); 1082 if (ret < 0) 1083 return ret; 1084 1085 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 1086 1087 return brightness; 1088 } 1089 1090 static const struct backlight_ops hx83102_bl_ops = { 1091 .update_status = hx83102_bl_update_status, 1092 .get_brightness = hx83102_bl_get_brightness, 1093 }; 1094 1095 static struct backlight_device * 1096 hx83102_create_dcs_backlight(struct mipi_dsi_device *dsi) 1097 { 1098 struct device *dev = &dsi->dev; 1099 const struct backlight_properties props = { 1100 .type = BACKLIGHT_RAW, 1101 .brightness = 4095, 1102 .max_brightness = 4095, 1103 }; 1104 1105 return devm_backlight_device_register(dev, dev_name(dev), dev, dsi, 1106 &hx83102_bl_ops, &props); 1107 } 1108 1109 static int hx83102_panel_add(struct hx83102 *ctx) 1110 { 1111 struct device *dev = &ctx->dsi->dev; 1112 int err; 1113 1114 ctx->avdd = devm_regulator_get(dev, "avdd"); 1115 if (IS_ERR(ctx->avdd)) 1116 return PTR_ERR(ctx->avdd); 1117 1118 ctx->avee = devm_regulator_get(dev, "avee"); 1119 if (IS_ERR(ctx->avee)) 1120 return PTR_ERR(ctx->avee); 1121 1122 ctx->pp1800 = devm_regulator_get(dev, "pp1800"); 1123 if (IS_ERR(ctx->pp1800)) 1124 return PTR_ERR(ctx->pp1800); 1125 1126 ctx->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 1127 if (IS_ERR(ctx->enable_gpio)) 1128 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "Cannot get enable GPIO\n"); 1129 1130 ctx->base.prepare_prev_first = true; 1131 1132 err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation); 1133 if (err < 0) 1134 return dev_err_probe(dev, err, "failed to get orientation\n"); 1135 1136 err = drm_panel_of_backlight(&ctx->base); 1137 if (err) 1138 return err; 1139 1140 /* Use DSI-based backlight as fallback if available */ 1141 if (ctx->desc->has_backlight && !ctx->base.backlight) { 1142 ctx->base.backlight = hx83102_create_dcs_backlight(ctx->dsi); 1143 if (IS_ERR(ctx->base.backlight)) 1144 return dev_err_probe(dev, PTR_ERR(ctx->base.backlight), 1145 "Failed to create backlight\n"); 1146 } 1147 1148 ctx->base.funcs = &hx83102_drm_funcs; 1149 ctx->base.dev = &ctx->dsi->dev; 1150 1151 drm_panel_add(&ctx->base); 1152 1153 return 0; 1154 } 1155 1156 static int hx83102_probe(struct mipi_dsi_device *dsi) 1157 { 1158 struct hx83102 *ctx; 1159 int ret; 1160 const struct hx83102_panel_desc *desc; 1161 1162 ctx = devm_drm_panel_alloc(&dsi->dev, __typeof(*ctx), base, 1163 &hx83102_drm_funcs, DRM_MODE_CONNECTOR_DSI); 1164 1165 if (IS_ERR(ctx)) 1166 return PTR_ERR(ctx); 1167 1168 desc = of_device_get_match_data(&dsi->dev); 1169 dsi->lanes = 4; 1170 dsi->format = MIPI_DSI_FMT_RGB888; 1171 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1172 MIPI_DSI_MODE_LPM; 1173 ctx->desc = desc; 1174 ctx->dsi = dsi; 1175 ret = hx83102_panel_add(ctx); 1176 if (ret < 0) 1177 return ret; 1178 1179 mipi_dsi_set_drvdata(dsi, ctx); 1180 1181 ret = mipi_dsi_attach(dsi); 1182 if (ret) 1183 drm_panel_remove(&ctx->base); 1184 1185 return ret; 1186 } 1187 1188 static void hx83102_remove(struct mipi_dsi_device *dsi) 1189 { 1190 struct hx83102 *ctx = mipi_dsi_get_drvdata(dsi); 1191 int ret; 1192 1193 ret = mipi_dsi_detach(dsi); 1194 if (ret < 0) 1195 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret); 1196 1197 if (ctx->base.dev) 1198 drm_panel_remove(&ctx->base); 1199 } 1200 1201 static const struct of_device_id hx83102_of_match[] = { 1202 { .compatible = "boe,nv110wum-l60", 1203 .data = &boe_nv110wum_desc 1204 }, 1205 { .compatible = "csot,pna957qt1-1", 1206 .data = &csot_pna957qt1_1_desc 1207 }, 1208 { .compatible = "ivo,t109nw41", 1209 .data = &ivo_t109nw41_desc 1210 }, 1211 { .compatible = "kingdisplay,kd110n11-51ie", 1212 .data = &kingdisplay_kd110n11_51ie_desc 1213 }, 1214 { .compatible = "starry,2082109qfh040022-50e", 1215 .data = &starry_2082109qfh040022_50e_desc 1216 }, 1217 { .compatible = "starry,himax83102-j02", 1218 .data = &starry_desc 1219 }, 1220 { .compatible = "holitech,htf065h045", 1221 .data = &holitech_htf065h045_desc 1222 }, 1223 { /* sentinel */ } 1224 }; 1225 MODULE_DEVICE_TABLE(of, hx83102_of_match); 1226 1227 static struct mipi_dsi_driver hx83102_driver = { 1228 .probe = hx83102_probe, 1229 .remove = hx83102_remove, 1230 .driver = { 1231 .name = "panel-himax-hx83102", 1232 .of_match_table = hx83102_of_match, 1233 }, 1234 }; 1235 module_mipi_dsi_driver(hx83102_driver); 1236 1237 MODULE_AUTHOR("Cong Yang <yangcong5@huaqin.corp-partner.google.com>"); 1238 MODULE_DESCRIPTION("DRM driver for Himax HX83102 based MIPI DSI panels"); 1239 MODULE_LICENSE("GPL"); 1240