1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019-2020 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6 #include <linux/gpio/consumer.h> 7 #include <linux/delay.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/regulator/consumer.h> 11 12 #include <drm/drm_mipi_dsi.h> 13 #include <drm/drm_modes.h> 14 #include <drm/drm_panel.h> 15 16 #define K101_IM2BA02_INIT_CMD_LEN 2 17 18 static const char * const regulator_names[] = { 19 "dvdd", 20 "avdd", 21 "cvdd" 22 }; 23 24 struct k101_im2ba02 { 25 struct drm_panel panel; 26 struct mipi_dsi_device *dsi; 27 28 struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)]; 29 struct gpio_desc *reset; 30 }; 31 32 static inline struct k101_im2ba02 *panel_to_k101_im2ba02(struct drm_panel *panel) 33 { 34 return container_of(panel, struct k101_im2ba02, panel); 35 } 36 37 struct k101_im2ba02_init_cmd { 38 u8 data[K101_IM2BA02_INIT_CMD_LEN]; 39 }; 40 41 static const struct k101_im2ba02_init_cmd k101_im2ba02_init_cmds[] = { 42 /* Switch to page 0 */ 43 { .data = { 0xE0, 0x00 } }, 44 45 /* Seems to be some password */ 46 { .data = { 0xE1, 0x93} }, 47 { .data = { 0xE2, 0x65 } }, 48 { .data = { 0xE3, 0xF8 } }, 49 50 /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */ 51 { .data = { 0x80, 0x03 } }, 52 53 /* Sequence control */ 54 { .data = { 0x70, 0x02 } }, 55 { .data = { 0x71, 0x23 } }, 56 { .data = { 0x72, 0x06 } }, 57 58 /* Switch to page 1 */ 59 { .data = { 0xE0, 0x01 } }, 60 61 /* Set VCOM */ 62 { .data = { 0x00, 0x00 } }, 63 { .data = { 0x01, 0x66 } }, 64 /* Set VCOM_Reverse */ 65 { .data = { 0x03, 0x00 } }, 66 { .data = { 0x04, 0x25 } }, 67 68 /* Set Gamma Power, VG[MS][PN] */ 69 { .data = { 0x17, 0x00 } }, 70 { .data = { 0x18, 0x6D } }, 71 { .data = { 0x19, 0x00 } }, 72 { .data = { 0x1A, 0x00 } }, 73 { .data = { 0x1B, 0xBF } }, /* VGMN = -4.5V */ 74 { .data = { 0x1C, 0x00 } }, 75 76 /* Set Gate Power */ 77 { .data = { 0x1F, 0x3E } }, /* VGH_R = 15V */ 78 { .data = { 0x20, 0x28 } }, /* VGL_R = -11V */ 79 { .data = { 0x21, 0x28 } }, /* VGL_R2 = -11V */ 80 { .data = { 0x22, 0x0E } }, /* PA[6:4] = 0, PA[0] = 0 */ 81 82 /* Set Panel */ 83 { .data = { 0x37, 0x09 } }, /* SS = 1, BGR = 1 */ 84 85 /* Set RGBCYC */ 86 { .data = { 0x38, 0x04 } }, /* JDT = 100 column inversion */ 87 { .data = { 0x39, 0x08 } }, /* RGB_N_EQ1 */ 88 { .data = { 0x3A, 0x12 } }, /* RGB_N_EQ2 */ 89 { .data = { 0x3C, 0x78 } }, /* set EQ3 for TE_H */ 90 { .data = { 0x3D, 0xFF } }, /* set CHGEN_ON */ 91 { .data = { 0x3E, 0xFF } }, /* set CHGEN_OFF */ 92 { .data = { 0x3F, 0x7F } }, /* set CHGEN_OFF2 */ 93 94 /* Set TCON parameter */ 95 { .data = { 0x40, 0x06 } }, /* RSO = 800 points */ 96 { .data = { 0x41, 0xA0 } }, /* LN = 1280 lines */ 97 98 /* Set power voltage */ 99 { .data = { 0x55, 0x0F } }, /* DCDCM */ 100 { .data = { 0x56, 0x01 } }, 101 { .data = { 0x57, 0x69 } }, 102 { .data = { 0x58, 0x0A } }, 103 { .data = { 0x59, 0x0A } }, 104 { .data = { 0x5A, 0x45 } }, 105 { .data = { 0x5B, 0x15 } }, 106 107 /* Set gamma */ 108 { .data = { 0x5D, 0x7C } }, 109 { .data = { 0x5E, 0x65 } }, 110 { .data = { 0x5F, 0x55 } }, 111 { .data = { 0x60, 0x49 } }, 112 { .data = { 0x61, 0x44 } }, 113 { .data = { 0x62, 0x35 } }, 114 { .data = { 0x63, 0x3A } }, 115 { .data = { 0x64, 0x23 } }, 116 { .data = { 0x65, 0x3D } }, 117 { .data = { 0x66, 0x3C } }, 118 { .data = { 0x67, 0x3D } }, 119 { .data = { 0x68, 0x5D } }, 120 { .data = { 0x69, 0x4D } }, 121 { .data = { 0x6A, 0x56 } }, 122 { .data = { 0x6B, 0x48 } }, 123 { .data = { 0x6C, 0x45 } }, 124 { .data = { 0x6D, 0x38 } }, 125 { .data = { 0x6E, 0x25 } }, 126 { .data = { 0x6F, 0x00 } }, 127 { .data = { 0x70, 0x7C } }, 128 { .data = { 0x71, 0x65 } }, 129 { .data = { 0x72, 0x55 } }, 130 { .data = { 0x73, 0x49 } }, 131 { .data = { 0x74, 0x44 } }, 132 { .data = { 0x75, 0x35 } }, 133 { .data = { 0x76, 0x3A } }, 134 { .data = { 0x77, 0x23 } }, 135 { .data = { 0x78, 0x3D } }, 136 { .data = { 0x79, 0x3C } }, 137 { .data = { 0x7A, 0x3D } }, 138 { .data = { 0x7B, 0x5D } }, 139 { .data = { 0x7C, 0x4D } }, 140 { .data = { 0x7D, 0x56 } }, 141 { .data = { 0x7E, 0x48 } }, 142 { .data = { 0x7F, 0x45 } }, 143 { .data = { 0x80, 0x38 } }, 144 { .data = { 0x81, 0x25 } }, 145 { .data = { 0x82, 0x00 } }, 146 147 /* Switch to page 2, for GIP */ 148 { .data = { 0xE0, 0x02 } }, 149 150 { .data = { 0x00, 0x1E } }, 151 { .data = { 0x01, 0x1E } }, 152 { .data = { 0x02, 0x41 } }, 153 { .data = { 0x03, 0x41 } }, 154 { .data = { 0x04, 0x43 } }, 155 { .data = { 0x05, 0x43 } }, 156 { .data = { 0x06, 0x1F } }, 157 { .data = { 0x07, 0x1F } }, 158 { .data = { 0x08, 0x1F } }, 159 { .data = { 0x09, 0x1F } }, 160 { .data = { 0x0A, 0x1E } }, 161 { .data = { 0x0B, 0x1E } }, 162 { .data = { 0x0C, 0x1F } }, 163 { .data = { 0x0D, 0x47 } }, 164 { .data = { 0x0E, 0x47 } }, 165 { .data = { 0x0F, 0x45 } }, 166 { .data = { 0x10, 0x45 } }, 167 { .data = { 0x11, 0x4B } }, 168 { .data = { 0x12, 0x4B } }, 169 { .data = { 0x13, 0x49 } }, 170 { .data = { 0x14, 0x49 } }, 171 { .data = { 0x15, 0x1F } }, 172 173 { .data = { 0x16, 0x1E } }, 174 { .data = { 0x17, 0x1E } }, 175 { .data = { 0x18, 0x40 } }, 176 { .data = { 0x19, 0x40 } }, 177 { .data = { 0x1A, 0x42 } }, 178 { .data = { 0x1B, 0x42 } }, 179 { .data = { 0x1C, 0x1F } }, 180 { .data = { 0x1D, 0x1F } }, 181 { .data = { 0x1E, 0x1F } }, 182 { .data = { 0x1F, 0x1f } }, 183 { .data = { 0x20, 0x1E } }, 184 { .data = { 0x21, 0x1E } }, 185 { .data = { 0x22, 0x1f } }, 186 { .data = { 0x23, 0x46 } }, 187 { .data = { 0x24, 0x46 } }, 188 { .data = { 0x25, 0x44 } }, 189 { .data = { 0x26, 0x44 } }, 190 { .data = { 0x27, 0x4A } }, 191 { .data = { 0x28, 0x4A } }, 192 { .data = { 0x29, 0x48 } }, 193 { .data = { 0x2A, 0x48 } }, 194 { .data = { 0x2B, 0x1f } }, 195 196 { .data = { 0x2C, 0x1F } }, 197 { .data = { 0x2D, 0x1F } }, 198 { .data = { 0x2E, 0x42 } }, 199 { .data = { 0x2F, 0x42 } }, 200 { .data = { 0x30, 0x40 } }, 201 { .data = { 0x31, 0x40 } }, 202 { .data = { 0x32, 0x1E } }, 203 { .data = { 0x33, 0x1E } }, 204 { .data = { 0x34, 0x1F } }, 205 { .data = { 0x35, 0x1F } }, 206 { .data = { 0x36, 0x1E } }, 207 { .data = { 0x37, 0x1E } }, 208 { .data = { 0x38, 0x1F } }, 209 { .data = { 0x39, 0x48 } }, 210 { .data = { 0x3A, 0x48 } }, 211 { .data = { 0x3B, 0x4A } }, 212 { .data = { 0x3C, 0x4A } }, 213 { .data = { 0x3D, 0x44 } }, 214 { .data = { 0x3E, 0x44 } }, 215 { .data = { 0x3F, 0x46 } }, 216 { .data = { 0x40, 0x46 } }, 217 { .data = { 0x41, 0x1F } }, 218 219 { .data = { 0x42, 0x1F } }, 220 { .data = { 0x43, 0x1F } }, 221 { .data = { 0x44, 0x43 } }, 222 { .data = { 0x45, 0x43 } }, 223 { .data = { 0x46, 0x41 } }, 224 { .data = { 0x47, 0x41 } }, 225 { .data = { 0x48, 0x1E } }, 226 { .data = { 0x49, 0x1E } }, 227 { .data = { 0x4A, 0x1E } }, 228 { .data = { 0x4B, 0x1F } }, 229 { .data = { 0x4C, 0x1E } }, 230 { .data = { 0x4D, 0x1E } }, 231 { .data = { 0x4E, 0x1F } }, 232 { .data = { 0x4F, 0x49 } }, 233 { .data = { 0x50, 0x49 } }, 234 { .data = { 0x51, 0x4B } }, 235 { .data = { 0x52, 0x4B } }, 236 { .data = { 0x53, 0x45 } }, 237 { .data = { 0x54, 0x45 } }, 238 { .data = { 0x55, 0x47 } }, 239 { .data = { 0x56, 0x47 } }, 240 { .data = { 0x57, 0x1F } }, 241 242 { .data = { 0x58, 0x10 } }, 243 { .data = { 0x59, 0x00 } }, 244 { .data = { 0x5A, 0x00 } }, 245 { .data = { 0x5B, 0x30 } }, 246 { .data = { 0x5C, 0x02 } }, 247 { .data = { 0x5D, 0x40 } }, 248 { .data = { 0x5E, 0x01 } }, 249 { .data = { 0x5F, 0x02 } }, 250 { .data = { 0x60, 0x30 } }, 251 { .data = { 0x61, 0x01 } }, 252 { .data = { 0x62, 0x02 } }, 253 { .data = { 0x63, 0x6A } }, 254 { .data = { 0x64, 0x6A } }, 255 { .data = { 0x65, 0x05 } }, 256 { .data = { 0x66, 0x12 } }, 257 { .data = { 0x67, 0x74 } }, 258 { .data = { 0x68, 0x04 } }, 259 { .data = { 0x69, 0x6A } }, 260 { .data = { 0x6A, 0x6A } }, 261 { .data = { 0x6B, 0x08 } }, 262 263 { .data = { 0x6C, 0x00 } }, 264 { .data = { 0x6D, 0x04 } }, 265 { .data = { 0x6E, 0x04 } }, 266 { .data = { 0x6F, 0x88 } }, 267 { .data = { 0x70, 0x00 } }, 268 { .data = { 0x71, 0x00 } }, 269 { .data = { 0x72, 0x06 } }, 270 { .data = { 0x73, 0x7B } }, 271 { .data = { 0x74, 0x00 } }, 272 { .data = { 0x75, 0x07 } }, 273 { .data = { 0x76, 0x00 } }, 274 { .data = { 0x77, 0x5D } }, 275 { .data = { 0x78, 0x17 } }, 276 { .data = { 0x79, 0x1F } }, 277 { .data = { 0x7A, 0x00 } }, 278 { .data = { 0x7B, 0x00 } }, 279 { .data = { 0x7C, 0x00 } }, 280 { .data = { 0x7D, 0x03 } }, 281 { .data = { 0x7E, 0x7B } }, 282 283 { .data = { 0xE0, 0x04 } }, 284 { .data = { 0x2B, 0x2B } }, 285 { .data = { 0x2E, 0x44 } }, 286 287 { .data = { 0xE0, 0x01 } }, 288 { .data = { 0x0E, 0x01 } }, 289 290 { .data = { 0xE0, 0x03 } }, 291 { .data = { 0x98, 0x2F } }, 292 293 { .data = { 0xE0, 0x00 } }, 294 { .data = { 0xE6, 0x02 } }, 295 { .data = { 0xE7, 0x02 } }, 296 297 { .data = { 0x11, 0x00 } }, 298 }; 299 300 static const struct k101_im2ba02_init_cmd timed_cmds[] = { 301 { .data = { 0x29, 0x00 } }, 302 { .data = { 0x35, 0x00 } }, 303 }; 304 305 static int k101_im2ba02_prepare(struct drm_panel *panel) 306 { 307 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); 308 struct mipi_dsi_device *dsi = ctx->dsi; 309 unsigned int i; 310 int ret; 311 312 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 313 if (ret) 314 return ret; 315 316 msleep(30); 317 318 gpiod_set_value(ctx->reset, 1); 319 msleep(50); 320 321 gpiod_set_value(ctx->reset, 0); 322 msleep(50); 323 324 gpiod_set_value(ctx->reset, 1); 325 msleep(200); 326 327 for (i = 0; i < ARRAY_SIZE(k101_im2ba02_init_cmds); i++) { 328 const struct k101_im2ba02_init_cmd *cmd = &k101_im2ba02_init_cmds[i]; 329 330 ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN); 331 if (ret < 0) 332 goto powerdown; 333 } 334 335 return 0; 336 337 powerdown: 338 gpiod_set_value(ctx->reset, 0); 339 msleep(50); 340 341 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 342 } 343 344 static int k101_im2ba02_enable(struct drm_panel *panel) 345 { 346 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); 347 const struct k101_im2ba02_init_cmd *cmd = &timed_cmds[1]; 348 int ret; 349 350 msleep(150); 351 352 ret = mipi_dsi_dcs_set_display_on(ctx->dsi); 353 if (ret < 0) 354 return ret; 355 356 msleep(50); 357 358 return mipi_dsi_dcs_write_buffer(ctx->dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN); 359 } 360 361 static int k101_im2ba02_disable(struct drm_panel *panel) 362 { 363 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); 364 365 return mipi_dsi_dcs_set_display_off(ctx->dsi); 366 } 367 368 static int k101_im2ba02_unprepare(struct drm_panel *panel) 369 { 370 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); 371 int ret; 372 373 ret = mipi_dsi_dcs_set_display_off(ctx->dsi); 374 if (ret < 0) 375 dev_err(panel->dev, "failed to set display off: %d\n", ret); 376 377 ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi); 378 if (ret < 0) 379 dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret); 380 381 msleep(200); 382 383 gpiod_set_value(ctx->reset, 0); 384 msleep(20); 385 386 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 387 } 388 389 static const struct drm_display_mode k101_im2ba02_default_mode = { 390 .clock = 70000, 391 392 .hdisplay = 800, 393 .hsync_start = 800 + 20, 394 .hsync_end = 800 + 20 + 20, 395 .htotal = 800 + 20 + 20 + 20, 396 397 .vdisplay = 1280, 398 .vsync_start = 1280 + 16, 399 .vsync_end = 1280 + 16 + 4, 400 .vtotal = 1280 + 16 + 4 + 4, 401 402 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 403 .width_mm = 136, 404 .height_mm = 217, 405 }; 406 407 static int k101_im2ba02_get_modes(struct drm_panel *panel, 408 struct drm_connector *connector) 409 { 410 struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); 411 struct drm_display_mode *mode; 412 413 mode = drm_mode_duplicate(connector->dev, &k101_im2ba02_default_mode); 414 if (!mode) { 415 dev_err(&ctx->dsi->dev, "failed to add mode %ux%u@%u\n", 416 k101_im2ba02_default_mode.hdisplay, 417 k101_im2ba02_default_mode.vdisplay, 418 drm_mode_vrefresh(&k101_im2ba02_default_mode)); 419 return -ENOMEM; 420 } 421 422 drm_mode_set_name(mode); 423 424 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 425 connector->display_info.width_mm = mode->width_mm; 426 connector->display_info.height_mm = mode->height_mm; 427 drm_mode_probed_add(connector, mode); 428 429 return 1; 430 } 431 432 static const struct drm_panel_funcs k101_im2ba02_funcs = { 433 .disable = k101_im2ba02_disable, 434 .unprepare = k101_im2ba02_unprepare, 435 .prepare = k101_im2ba02_prepare, 436 .enable = k101_im2ba02_enable, 437 .get_modes = k101_im2ba02_get_modes, 438 }; 439 440 static int k101_im2ba02_dsi_probe(struct mipi_dsi_device *dsi) 441 { 442 struct k101_im2ba02 *ctx; 443 unsigned int i; 444 int ret; 445 446 ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL); 447 if (!ctx) 448 return -ENOMEM; 449 450 mipi_dsi_set_drvdata(dsi, ctx); 451 ctx->dsi = dsi; 452 453 for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) 454 ctx->supplies[i].supply = regulator_names[i]; 455 456 ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(ctx->supplies), 457 ctx->supplies); 458 if (ret < 0) 459 return dev_err_probe(&dsi->dev, ret, "Couldn't get regulators\n"); 460 461 ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); 462 if (IS_ERR(ctx->reset)) 463 return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset), 464 "Couldn't get our reset GPIO\n"); 465 466 drm_panel_init(&ctx->panel, &dsi->dev, &k101_im2ba02_funcs, 467 DRM_MODE_CONNECTOR_DSI); 468 469 ret = drm_panel_of_backlight(&ctx->panel); 470 if (ret) 471 return ret; 472 473 drm_panel_add(&ctx->panel); 474 475 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 476 dsi->format = MIPI_DSI_FMT_RGB888; 477 dsi->lanes = 4; 478 479 ret = mipi_dsi_attach(dsi); 480 if (ret < 0) { 481 drm_panel_remove(&ctx->panel); 482 return ret; 483 } 484 485 return 0; 486 } 487 488 static void k101_im2ba02_dsi_remove(struct mipi_dsi_device *dsi) 489 { 490 struct k101_im2ba02 *ctx = mipi_dsi_get_drvdata(dsi); 491 492 mipi_dsi_detach(dsi); 493 drm_panel_remove(&ctx->panel); 494 } 495 496 static const struct of_device_id k101_im2ba02_of_match[] = { 497 { .compatible = "feixin,k101-im2ba02", }, 498 { /* sentinel */ } 499 }; 500 MODULE_DEVICE_TABLE(of, k101_im2ba02_of_match); 501 502 static struct mipi_dsi_driver k101_im2ba02_driver = { 503 .probe = k101_im2ba02_dsi_probe, 504 .remove = k101_im2ba02_dsi_remove, 505 .driver = { 506 .name = "feixin-k101-im2ba02", 507 .of_match_table = k101_im2ba02_of_match, 508 }, 509 }; 510 module_mipi_dsi_driver(k101_im2ba02_driver); 511 512 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); 513 MODULE_DESCRIPTION("Feixin K101 IM2BA02 MIPI-DSI LCD panel"); 514 MODULE_LICENSE("GPL"); 515