xref: /linux/drivers/gpu/drm/omapdrm/dss/venc.c (revision bcb63314e2c23f1ed622418b65f9409512659c73)
1 /*
2  * linux/drivers/video/omap2/dss/venc.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * VENC settings from TI's DSS driver
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms of the GNU General Public License version 2 as published by
11  * the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program.  If not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #define DSS_SUBSYS_NAME "VENC"
23 
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/of.h>
38 #include <linux/component.h>
39 
40 #include "omapdss.h"
41 #include "dss.h"
42 #include "dss_features.h"
43 
44 /* Venc registers */
45 #define VENC_REV_ID				0x00
46 #define VENC_STATUS				0x04
47 #define VENC_F_CONTROL				0x08
48 #define VENC_VIDOUT_CTRL			0x10
49 #define VENC_SYNC_CTRL				0x14
50 #define VENC_LLEN				0x1C
51 #define VENC_FLENS				0x20
52 #define VENC_HFLTR_CTRL				0x24
53 #define VENC_CC_CARR_WSS_CARR			0x28
54 #define VENC_C_PHASE				0x2C
55 #define VENC_GAIN_U				0x30
56 #define VENC_GAIN_V				0x34
57 #define VENC_GAIN_Y				0x38
58 #define VENC_BLACK_LEVEL			0x3C
59 #define VENC_BLANK_LEVEL			0x40
60 #define VENC_X_COLOR				0x44
61 #define VENC_M_CONTROL				0x48
62 #define VENC_BSTAMP_WSS_DATA			0x4C
63 #define VENC_S_CARR				0x50
64 #define VENC_LINE21				0x54
65 #define VENC_LN_SEL				0x58
66 #define VENC_L21__WC_CTL			0x5C
67 #define VENC_HTRIGGER_VTRIGGER			0x60
68 #define VENC_SAVID__EAVID			0x64
69 #define VENC_FLEN__FAL				0x68
70 #define VENC_LAL__PHASE_RESET			0x6C
71 #define VENC_HS_INT_START_STOP_X		0x70
72 #define VENC_HS_EXT_START_STOP_X		0x74
73 #define VENC_VS_INT_START_X			0x78
74 #define VENC_VS_INT_STOP_X__VS_INT_START_Y	0x7C
75 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X	0x80
76 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y	0x84
77 #define VENC_VS_EXT_STOP_Y			0x88
78 #define VENC_AVID_START_STOP_X			0x90
79 #define VENC_AVID_START_STOP_Y			0x94
80 #define VENC_FID_INT_START_X__FID_INT_START_Y	0xA0
81 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X	0xA4
82 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y	0xA8
83 #define VENC_TVDETGP_INT_START_STOP_X		0xB0
84 #define VENC_TVDETGP_INT_START_STOP_Y		0xB4
85 #define VENC_GEN_CTRL				0xB8
86 #define VENC_OUTPUT_CONTROL			0xC4
87 #define VENC_OUTPUT_TEST			0xC8
88 #define VENC_DAC_B__DAC_C			0xC8
89 
90 struct venc_config {
91 	u32 f_control;
92 	u32 vidout_ctrl;
93 	u32 sync_ctrl;
94 	u32 llen;
95 	u32 flens;
96 	u32 hfltr_ctrl;
97 	u32 cc_carr_wss_carr;
98 	u32 c_phase;
99 	u32 gain_u;
100 	u32 gain_v;
101 	u32 gain_y;
102 	u32 black_level;
103 	u32 blank_level;
104 	u32 x_color;
105 	u32 m_control;
106 	u32 bstamp_wss_data;
107 	u32 s_carr;
108 	u32 line21;
109 	u32 ln_sel;
110 	u32 l21__wc_ctl;
111 	u32 htrigger_vtrigger;
112 	u32 savid__eavid;
113 	u32 flen__fal;
114 	u32 lal__phase_reset;
115 	u32 hs_int_start_stop_x;
116 	u32 hs_ext_start_stop_x;
117 	u32 vs_int_start_x;
118 	u32 vs_int_stop_x__vs_int_start_y;
119 	u32 vs_int_stop_y__vs_ext_start_x;
120 	u32 vs_ext_stop_x__vs_ext_start_y;
121 	u32 vs_ext_stop_y;
122 	u32 avid_start_stop_x;
123 	u32 avid_start_stop_y;
124 	u32 fid_int_start_x__fid_int_start_y;
125 	u32 fid_int_offset_y__fid_ext_start_x;
126 	u32 fid_ext_start_y__fid_ext_offset_y;
127 	u32 tvdetgp_int_start_stop_x;
128 	u32 tvdetgp_int_start_stop_y;
129 	u32 gen_ctrl;
130 };
131 
132 /* from TRM */
133 static const struct venc_config venc_config_pal_trm = {
134 	.f_control				= 0,
135 	.vidout_ctrl				= 1,
136 	.sync_ctrl				= 0x40,
137 	.llen					= 0x35F, /* 863 */
138 	.flens					= 0x270, /* 624 */
139 	.hfltr_ctrl				= 0,
140 	.cc_carr_wss_carr			= 0x2F7225ED,
141 	.c_phase				= 0,
142 	.gain_u					= 0x111,
143 	.gain_v					= 0x181,
144 	.gain_y					= 0x140,
145 	.black_level				= 0x3B,
146 	.blank_level				= 0x3B,
147 	.x_color				= 0x7,
148 	.m_control				= 0x2,
149 	.bstamp_wss_data			= 0x3F,
150 	.s_carr					= 0x2A098ACB,
151 	.line21					= 0,
152 	.ln_sel					= 0x01290015,
153 	.l21__wc_ctl				= 0x0000F603,
154 	.htrigger_vtrigger			= 0,
155 
156 	.savid__eavid				= 0x06A70108,
157 	.flen__fal				= 0x00180270,
158 	.lal__phase_reset			= 0x00040135,
159 	.hs_int_start_stop_x			= 0x00880358,
160 	.hs_ext_start_stop_x			= 0x000F035F,
161 	.vs_int_start_x				= 0x01A70000,
162 	.vs_int_stop_x__vs_int_start_y		= 0x000001A7,
163 	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0000,
164 	.vs_ext_stop_x__vs_ext_start_y		= 0x000101AF,
165 	.vs_ext_stop_y				= 0x00000025,
166 	.avid_start_stop_x			= 0x03530083,
167 	.avid_start_stop_y			= 0x026C002E,
168 	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
169 	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
170 	.fid_ext_start_y__fid_ext_offset_y	= 0x01380001,
171 
172 	.tvdetgp_int_start_stop_x		= 0x00140001,
173 	.tvdetgp_int_start_stop_y		= 0x00010001,
174 	.gen_ctrl				= 0x00FF0000,
175 };
176 
177 /* from TRM */
178 static const struct venc_config venc_config_ntsc_trm = {
179 	.f_control				= 0,
180 	.vidout_ctrl				= 1,
181 	.sync_ctrl				= 0x8040,
182 	.llen					= 0x359,
183 	.flens					= 0x20C,
184 	.hfltr_ctrl				= 0,
185 	.cc_carr_wss_carr			= 0x043F2631,
186 	.c_phase				= 0,
187 	.gain_u					= 0x102,
188 	.gain_v					= 0x16C,
189 	.gain_y					= 0x12F,
190 	.black_level				= 0x43,
191 	.blank_level				= 0x38,
192 	.x_color				= 0x7,
193 	.m_control				= 0x1,
194 	.bstamp_wss_data			= 0x38,
195 	.s_carr					= 0x21F07C1F,
196 	.line21					= 0,
197 	.ln_sel					= 0x01310011,
198 	.l21__wc_ctl				= 0x0000F003,
199 	.htrigger_vtrigger			= 0,
200 
201 	.savid__eavid				= 0x069300F4,
202 	.flen__fal				= 0x0016020C,
203 	.lal__phase_reset			= 0x00060107,
204 	.hs_int_start_stop_x			= 0x008E0350,
205 	.hs_ext_start_stop_x			= 0x000F0359,
206 	.vs_int_start_x				= 0x01A00000,
207 	.vs_int_stop_x__vs_int_start_y		= 0x020701A0,
208 	.vs_int_stop_y__vs_ext_start_x		= 0x01AC0024,
209 	.vs_ext_stop_x__vs_ext_start_y		= 0x020D01AC,
210 	.vs_ext_stop_y				= 0x00000006,
211 	.avid_start_stop_x			= 0x03480078,
212 	.avid_start_stop_y			= 0x02060024,
213 	.fid_int_start_x__fid_int_start_y	= 0x0001008A,
214 	.fid_int_offset_y__fid_ext_start_x	= 0x01AC0106,
215 	.fid_ext_start_y__fid_ext_offset_y	= 0x01060006,
216 
217 	.tvdetgp_int_start_stop_x		= 0x00140001,
218 	.tvdetgp_int_start_stop_y		= 0x00010001,
219 	.gen_ctrl				= 0x00F90000,
220 };
221 
222 static const struct venc_config venc_config_pal_bdghi = {
223 	.f_control				= 0,
224 	.vidout_ctrl				= 0,
225 	.sync_ctrl				= 0,
226 	.hfltr_ctrl				= 0,
227 	.x_color				= 0,
228 	.line21					= 0,
229 	.ln_sel					= 21,
230 	.htrigger_vtrigger			= 0,
231 	.tvdetgp_int_start_stop_x		= 0x00140001,
232 	.tvdetgp_int_start_stop_y		= 0x00010001,
233 	.gen_ctrl				= 0x00FB0000,
234 
235 	.llen					= 864-1,
236 	.flens					= 625-1,
237 	.cc_carr_wss_carr			= 0x2F7625ED,
238 	.c_phase				= 0xDF,
239 	.gain_u					= 0x111,
240 	.gain_v					= 0x181,
241 	.gain_y					= 0x140,
242 	.black_level				= 0x3e,
243 	.blank_level				= 0x3e,
244 	.m_control				= 0<<2 | 1<<1,
245 	.bstamp_wss_data			= 0x42,
246 	.s_carr					= 0x2a098acb,
247 	.l21__wc_ctl				= 0<<13 | 0x16<<8 | 0<<0,
248 	.savid__eavid				= 0x06A70108,
249 	.flen__fal				= 23<<16 | 624<<0,
250 	.lal__phase_reset			= 2<<17 | 310<<0,
251 	.hs_int_start_stop_x			= 0x00920358,
252 	.hs_ext_start_stop_x			= 0x000F035F,
253 	.vs_int_start_x				= 0x1a7<<16,
254 	.vs_int_stop_x__vs_int_start_y		= 0x000601A7,
255 	.vs_int_stop_y__vs_ext_start_x		= 0x01AF0036,
256 	.vs_ext_stop_x__vs_ext_start_y		= 0x27101af,
257 	.vs_ext_stop_y				= 0x05,
258 	.avid_start_stop_x			= 0x03530082,
259 	.avid_start_stop_y			= 0x0270002E,
260 	.fid_int_start_x__fid_int_start_y	= 0x0005008A,
261 	.fid_int_offset_y__fid_ext_start_x	= 0x002E0138,
262 	.fid_ext_start_y__fid_ext_offset_y	= 0x01380005,
263 };
264 
265 const struct videomode omap_dss_pal_vm = {
266 	.hactive	= 720,
267 	.vactive	= 574,
268 	.pixelclock	= 13500000,
269 	.hsync_len	= 64,
270 	.hfront_porch	= 12,
271 	.hback_porch	= 68,
272 	.vsync_len	= 5,
273 	.vfront_porch	= 5,
274 	.vback_porch	= 41,
275 
276 	.flags		= DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
277 			  DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
278 			  DISPLAY_FLAGS_PIXDATA_POSEDGE |
279 			  DISPLAY_FLAGS_SYNC_NEGEDGE,
280 };
281 EXPORT_SYMBOL(omap_dss_pal_vm);
282 
283 const struct videomode omap_dss_ntsc_vm = {
284 	.hactive	= 720,
285 	.vactive	= 482,
286 	.pixelclock	= 13500000,
287 	.hsync_len	= 64,
288 	.hfront_porch	= 16,
289 	.hback_porch	= 58,
290 	.vsync_len	= 6,
291 	.vfront_porch	= 6,
292 	.vback_porch	= 31,
293 
294 	.flags		= DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
295 			  DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
296 			  DISPLAY_FLAGS_PIXDATA_POSEDGE |
297 			  DISPLAY_FLAGS_SYNC_NEGEDGE,
298 };
299 EXPORT_SYMBOL(omap_dss_ntsc_vm);
300 
301 static struct {
302 	struct platform_device *pdev;
303 	void __iomem *base;
304 	struct mutex venc_lock;
305 	u32 wss_data;
306 	struct regulator *vdda_dac_reg;
307 
308 	struct clk	*tv_dac_clk;
309 
310 	struct videomode vm;
311 	enum omap_dss_venc_type type;
312 	bool invert_polarity;
313 
314 	struct omap_dss_device output;
315 } venc;
316 
317 static inline void venc_write_reg(int idx, u32 val)
318 {
319 	__raw_writel(val, venc.base + idx);
320 }
321 
322 static inline u32 venc_read_reg(int idx)
323 {
324 	u32 l = __raw_readl(venc.base + idx);
325 	return l;
326 }
327 
328 static void venc_write_config(const struct venc_config *config)
329 {
330 	DSSDBG("write venc conf\n");
331 
332 	venc_write_reg(VENC_LLEN, config->llen);
333 	venc_write_reg(VENC_FLENS, config->flens);
334 	venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
335 	venc_write_reg(VENC_C_PHASE, config->c_phase);
336 	venc_write_reg(VENC_GAIN_U, config->gain_u);
337 	venc_write_reg(VENC_GAIN_V, config->gain_v);
338 	venc_write_reg(VENC_GAIN_Y, config->gain_y);
339 	venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
340 	venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
341 	venc_write_reg(VENC_M_CONTROL, config->m_control);
342 	venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
343 			venc.wss_data);
344 	venc_write_reg(VENC_S_CARR, config->s_carr);
345 	venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
346 	venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
347 	venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
348 	venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
349 	venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
350 	venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
351 	venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
352 	venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
353 		       config->vs_int_stop_x__vs_int_start_y);
354 	venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
355 		       config->vs_int_stop_y__vs_ext_start_x);
356 	venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
357 		       config->vs_ext_stop_x__vs_ext_start_y);
358 	venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
359 	venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
360 	venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
361 	venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
362 		       config->fid_int_start_x__fid_int_start_y);
363 	venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
364 		       config->fid_int_offset_y__fid_ext_start_x);
365 	venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
366 		       config->fid_ext_start_y__fid_ext_offset_y);
367 
368 	venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
369 	venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
370 	venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
371 	venc_write_reg(VENC_X_COLOR, config->x_color);
372 	venc_write_reg(VENC_LINE21, config->line21);
373 	venc_write_reg(VENC_LN_SEL, config->ln_sel);
374 	venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
375 	venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
376 		       config->tvdetgp_int_start_stop_x);
377 	venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
378 		       config->tvdetgp_int_start_stop_y);
379 	venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
380 	venc_write_reg(VENC_F_CONTROL, config->f_control);
381 	venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
382 }
383 
384 static void venc_reset(void)
385 {
386 	int t = 1000;
387 
388 	venc_write_reg(VENC_F_CONTROL, 1<<8);
389 	while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
390 		if (--t == 0) {
391 			DSSERR("Failed to reset venc\n");
392 			return;
393 		}
394 	}
395 
396 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
397 	/* the magical sleep that makes things work */
398 	/* XXX more info? What bug this circumvents? */
399 	msleep(20);
400 #endif
401 }
402 
403 static int venc_runtime_get(void)
404 {
405 	int r;
406 
407 	DSSDBG("venc_runtime_get\n");
408 
409 	r = pm_runtime_get_sync(&venc.pdev->dev);
410 	WARN_ON(r < 0);
411 	return r < 0 ? r : 0;
412 }
413 
414 static void venc_runtime_put(void)
415 {
416 	int r;
417 
418 	DSSDBG("venc_runtime_put\n");
419 
420 	r = pm_runtime_put_sync(&venc.pdev->dev);
421 	WARN_ON(r < 0 && r != -ENOSYS);
422 }
423 
424 static const struct venc_config *venc_timings_to_config(struct videomode *vm)
425 {
426 	if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
427 		return &venc_config_pal_trm;
428 
429 	if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
430 		return &venc_config_ntsc_trm;
431 
432 	BUG();
433 	return NULL;
434 }
435 
436 static int venc_power_on(struct omap_dss_device *dssdev)
437 {
438 	enum omap_channel channel = dssdev->dispc_channel;
439 	u32 l;
440 	int r;
441 
442 	r = venc_runtime_get();
443 	if (r)
444 		goto err0;
445 
446 	venc_reset();
447 	venc_write_config(venc_timings_to_config(&venc.vm));
448 
449 	dss_set_venc_output(venc.type);
450 	dss_set_dac_pwrdn_bgz(1);
451 
452 	l = 0;
453 
454 	if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
455 		l |= 1 << 1;
456 	else /* S-Video */
457 		l |= (1 << 0) | (1 << 2);
458 
459 	if (venc.invert_polarity == false)
460 		l |= 1 << 3;
461 
462 	venc_write_reg(VENC_OUTPUT_CONTROL, l);
463 
464 	dss_mgr_set_timings(channel, &venc.vm);
465 
466 	r = regulator_enable(venc.vdda_dac_reg);
467 	if (r)
468 		goto err1;
469 
470 	r = dss_mgr_enable(channel);
471 	if (r)
472 		goto err2;
473 
474 	return 0;
475 
476 err2:
477 	regulator_disable(venc.vdda_dac_reg);
478 err1:
479 	venc_write_reg(VENC_OUTPUT_CONTROL, 0);
480 	dss_set_dac_pwrdn_bgz(0);
481 
482 	venc_runtime_put();
483 err0:
484 	return r;
485 }
486 
487 static void venc_power_off(struct omap_dss_device *dssdev)
488 {
489 	enum omap_channel channel = dssdev->dispc_channel;
490 
491 	venc_write_reg(VENC_OUTPUT_CONTROL, 0);
492 	dss_set_dac_pwrdn_bgz(0);
493 
494 	dss_mgr_disable(channel);
495 
496 	regulator_disable(venc.vdda_dac_reg);
497 
498 	venc_runtime_put();
499 }
500 
501 static int venc_display_enable(struct omap_dss_device *dssdev)
502 {
503 	struct omap_dss_device *out = &venc.output;
504 	int r;
505 
506 	DSSDBG("venc_display_enable\n");
507 
508 	mutex_lock(&venc.venc_lock);
509 
510 	if (!out->dispc_channel_connected) {
511 		DSSERR("Failed to enable display: no output/manager\n");
512 		r = -ENODEV;
513 		goto err0;
514 	}
515 
516 	r = venc_power_on(dssdev);
517 	if (r)
518 		goto err0;
519 
520 	venc.wss_data = 0;
521 
522 	mutex_unlock(&venc.venc_lock);
523 
524 	return 0;
525 err0:
526 	mutex_unlock(&venc.venc_lock);
527 	return r;
528 }
529 
530 static void venc_display_disable(struct omap_dss_device *dssdev)
531 {
532 	DSSDBG("venc_display_disable\n");
533 
534 	mutex_lock(&venc.venc_lock);
535 
536 	venc_power_off(dssdev);
537 
538 	mutex_unlock(&venc.venc_lock);
539 }
540 
541 static void venc_set_timings(struct omap_dss_device *dssdev,
542 			     struct videomode *vm)
543 {
544 	DSSDBG("venc_set_timings\n");
545 
546 	mutex_lock(&venc.venc_lock);
547 
548 	/* Reset WSS data when the TV standard changes. */
549 	if (memcmp(&venc.vm, vm, sizeof(*vm)))
550 		venc.wss_data = 0;
551 
552 	venc.vm = *vm;
553 
554 	dispc_set_tv_pclk(13500000);
555 
556 	mutex_unlock(&venc.venc_lock);
557 }
558 
559 static int venc_check_timings(struct omap_dss_device *dssdev,
560 			      struct videomode *vm)
561 {
562 	DSSDBG("venc_check_timings\n");
563 
564 	if (memcmp(&omap_dss_pal_vm, vm, sizeof(*vm)) == 0)
565 		return 0;
566 
567 	if (memcmp(&omap_dss_ntsc_vm, vm, sizeof(*vm)) == 0)
568 		return 0;
569 
570 	return -EINVAL;
571 }
572 
573 static void venc_get_timings(struct omap_dss_device *dssdev,
574 			     struct videomode *vm)
575 {
576 	mutex_lock(&venc.venc_lock);
577 
578 	*vm = venc.vm;
579 
580 	mutex_unlock(&venc.venc_lock);
581 }
582 
583 static u32 venc_get_wss(struct omap_dss_device *dssdev)
584 {
585 	/* Invert due to VENC_L21_WC_CTL:INV=1 */
586 	return (venc.wss_data >> 8) ^ 0xfffff;
587 }
588 
589 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
590 {
591 	const struct venc_config *config;
592 	int r;
593 
594 	DSSDBG("venc_set_wss\n");
595 
596 	mutex_lock(&venc.venc_lock);
597 
598 	config = venc_timings_to_config(&venc.vm);
599 
600 	/* Invert due to VENC_L21_WC_CTL:INV=1 */
601 	venc.wss_data = (wss ^ 0xfffff) << 8;
602 
603 	r = venc_runtime_get();
604 	if (r)
605 		goto err;
606 
607 	venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
608 			venc.wss_data);
609 
610 	venc_runtime_put();
611 
612 err:
613 	mutex_unlock(&venc.venc_lock);
614 
615 	return r;
616 }
617 
618 static void venc_set_type(struct omap_dss_device *dssdev,
619 		enum omap_dss_venc_type type)
620 {
621 	mutex_lock(&venc.venc_lock);
622 
623 	venc.type = type;
624 
625 	mutex_unlock(&venc.venc_lock);
626 }
627 
628 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
629 		bool invert_polarity)
630 {
631 	mutex_lock(&venc.venc_lock);
632 
633 	venc.invert_polarity = invert_polarity;
634 
635 	mutex_unlock(&venc.venc_lock);
636 }
637 
638 static int venc_init_regulator(void)
639 {
640 	struct regulator *vdda_dac;
641 
642 	if (venc.vdda_dac_reg != NULL)
643 		return 0;
644 
645 	if (venc.pdev->dev.of_node)
646 		vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
647 	else
648 		vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
649 
650 	if (IS_ERR(vdda_dac)) {
651 		if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
652 			DSSERR("can't get VDDA_DAC regulator\n");
653 		return PTR_ERR(vdda_dac);
654 	}
655 
656 	venc.vdda_dac_reg = vdda_dac;
657 
658 	return 0;
659 }
660 
661 static void venc_dump_regs(struct seq_file *s)
662 {
663 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
664 
665 	if (venc_runtime_get())
666 		return;
667 
668 	DUMPREG(VENC_F_CONTROL);
669 	DUMPREG(VENC_VIDOUT_CTRL);
670 	DUMPREG(VENC_SYNC_CTRL);
671 	DUMPREG(VENC_LLEN);
672 	DUMPREG(VENC_FLENS);
673 	DUMPREG(VENC_HFLTR_CTRL);
674 	DUMPREG(VENC_CC_CARR_WSS_CARR);
675 	DUMPREG(VENC_C_PHASE);
676 	DUMPREG(VENC_GAIN_U);
677 	DUMPREG(VENC_GAIN_V);
678 	DUMPREG(VENC_GAIN_Y);
679 	DUMPREG(VENC_BLACK_LEVEL);
680 	DUMPREG(VENC_BLANK_LEVEL);
681 	DUMPREG(VENC_X_COLOR);
682 	DUMPREG(VENC_M_CONTROL);
683 	DUMPREG(VENC_BSTAMP_WSS_DATA);
684 	DUMPREG(VENC_S_CARR);
685 	DUMPREG(VENC_LINE21);
686 	DUMPREG(VENC_LN_SEL);
687 	DUMPREG(VENC_L21__WC_CTL);
688 	DUMPREG(VENC_HTRIGGER_VTRIGGER);
689 	DUMPREG(VENC_SAVID__EAVID);
690 	DUMPREG(VENC_FLEN__FAL);
691 	DUMPREG(VENC_LAL__PHASE_RESET);
692 	DUMPREG(VENC_HS_INT_START_STOP_X);
693 	DUMPREG(VENC_HS_EXT_START_STOP_X);
694 	DUMPREG(VENC_VS_INT_START_X);
695 	DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
696 	DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
697 	DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
698 	DUMPREG(VENC_VS_EXT_STOP_Y);
699 	DUMPREG(VENC_AVID_START_STOP_X);
700 	DUMPREG(VENC_AVID_START_STOP_Y);
701 	DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
702 	DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
703 	DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
704 	DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
705 	DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
706 	DUMPREG(VENC_GEN_CTRL);
707 	DUMPREG(VENC_OUTPUT_CONTROL);
708 	DUMPREG(VENC_OUTPUT_TEST);
709 
710 	venc_runtime_put();
711 
712 #undef DUMPREG
713 }
714 
715 static int venc_get_clocks(struct platform_device *pdev)
716 {
717 	struct clk *clk;
718 
719 	if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
720 		clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
721 		if (IS_ERR(clk)) {
722 			DSSERR("can't get tv_dac_clk\n");
723 			return PTR_ERR(clk);
724 		}
725 	} else {
726 		clk = NULL;
727 	}
728 
729 	venc.tv_dac_clk = clk;
730 
731 	return 0;
732 }
733 
734 static int venc_connect(struct omap_dss_device *dssdev,
735 		struct omap_dss_device *dst)
736 {
737 	enum omap_channel channel = dssdev->dispc_channel;
738 	int r;
739 
740 	r = venc_init_regulator();
741 	if (r)
742 		return r;
743 
744 	r = dss_mgr_connect(channel, dssdev);
745 	if (r)
746 		return r;
747 
748 	r = omapdss_output_set_device(dssdev, dst);
749 	if (r) {
750 		DSSERR("failed to connect output to new device: %s\n",
751 				dst->name);
752 		dss_mgr_disconnect(channel, dssdev);
753 		return r;
754 	}
755 
756 	return 0;
757 }
758 
759 static void venc_disconnect(struct omap_dss_device *dssdev,
760 		struct omap_dss_device *dst)
761 {
762 	enum omap_channel channel = dssdev->dispc_channel;
763 
764 	WARN_ON(dst != dssdev->dst);
765 
766 	if (dst != dssdev->dst)
767 		return;
768 
769 	omapdss_output_unset_device(dssdev);
770 
771 	dss_mgr_disconnect(channel, dssdev);
772 }
773 
774 static const struct omapdss_atv_ops venc_ops = {
775 	.connect = venc_connect,
776 	.disconnect = venc_disconnect,
777 
778 	.enable = venc_display_enable,
779 	.disable = venc_display_disable,
780 
781 	.check_timings = venc_check_timings,
782 	.set_timings = venc_set_timings,
783 	.get_timings = venc_get_timings,
784 
785 	.set_type = venc_set_type,
786 	.invert_vid_out_polarity = venc_invert_vid_out_polarity,
787 
788 	.set_wss = venc_set_wss,
789 	.get_wss = venc_get_wss,
790 };
791 
792 static void venc_init_output(struct platform_device *pdev)
793 {
794 	struct omap_dss_device *out = &venc.output;
795 
796 	out->dev = &pdev->dev;
797 	out->id = OMAP_DSS_OUTPUT_VENC;
798 	out->output_type = OMAP_DISPLAY_TYPE_VENC;
799 	out->name = "venc.0";
800 	out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
801 	out->ops.atv = &venc_ops;
802 	out->owner = THIS_MODULE;
803 
804 	omapdss_register_output(out);
805 }
806 
807 static void venc_uninit_output(struct platform_device *pdev)
808 {
809 	struct omap_dss_device *out = &venc.output;
810 
811 	omapdss_unregister_output(out);
812 }
813 
814 static int venc_probe_of(struct platform_device *pdev)
815 {
816 	struct device_node *node = pdev->dev.of_node;
817 	struct device_node *ep;
818 	u32 channels;
819 	int r;
820 
821 	ep = omapdss_of_get_first_endpoint(node);
822 	if (!ep)
823 		return 0;
824 
825 	venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
826 
827 	r = of_property_read_u32(ep, "ti,channels", &channels);
828 	if (r) {
829 		dev_err(&pdev->dev,
830 			"failed to read property 'ti,channels': %d\n", r);
831 		goto err;
832 	}
833 
834 	switch (channels) {
835 	case 1:
836 		venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
837 		break;
838 	case 2:
839 		venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
840 		break;
841 	default:
842 		dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
843 		r = -EINVAL;
844 		goto err;
845 	}
846 
847 	of_node_put(ep);
848 
849 	return 0;
850 err:
851 	of_node_put(ep);
852 
853 	return 0;
854 }
855 
856 /* VENC HW IP initialisation */
857 static int venc_bind(struct device *dev, struct device *master, void *data)
858 {
859 	struct platform_device *pdev = to_platform_device(dev);
860 	u8 rev_id;
861 	struct resource *venc_mem;
862 	int r;
863 
864 	venc.pdev = pdev;
865 
866 	mutex_init(&venc.venc_lock);
867 
868 	venc.wss_data = 0;
869 
870 	venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
871 	if (!venc_mem) {
872 		DSSERR("can't get IORESOURCE_MEM VENC\n");
873 		return -EINVAL;
874 	}
875 
876 	venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
877 				 resource_size(venc_mem));
878 	if (!venc.base) {
879 		DSSERR("can't ioremap VENC\n");
880 		return -ENOMEM;
881 	}
882 
883 	r = venc_get_clocks(pdev);
884 	if (r)
885 		return r;
886 
887 	pm_runtime_enable(&pdev->dev);
888 
889 	r = venc_runtime_get();
890 	if (r)
891 		goto err_runtime_get;
892 
893 	rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
894 	dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
895 
896 	venc_runtime_put();
897 
898 	if (pdev->dev.of_node) {
899 		r = venc_probe_of(pdev);
900 		if (r) {
901 			DSSERR("Invalid DT data\n");
902 			goto err_probe_of;
903 		}
904 	}
905 
906 	dss_debugfs_create_file("venc", venc_dump_regs);
907 
908 	venc_init_output(pdev);
909 
910 	return 0;
911 
912 err_probe_of:
913 err_runtime_get:
914 	pm_runtime_disable(&pdev->dev);
915 	return r;
916 }
917 
918 static void venc_unbind(struct device *dev, struct device *master, void *data)
919 {
920 	struct platform_device *pdev = to_platform_device(dev);
921 
922 	venc_uninit_output(pdev);
923 
924 	pm_runtime_disable(&pdev->dev);
925 }
926 
927 static const struct component_ops venc_component_ops = {
928 	.bind	= venc_bind,
929 	.unbind	= venc_unbind,
930 };
931 
932 static int venc_probe(struct platform_device *pdev)
933 {
934 	return component_add(&pdev->dev, &venc_component_ops);
935 }
936 
937 static int venc_remove(struct platform_device *pdev)
938 {
939 	component_del(&pdev->dev, &venc_component_ops);
940 	return 0;
941 }
942 
943 static int venc_runtime_suspend(struct device *dev)
944 {
945 	if (venc.tv_dac_clk)
946 		clk_disable_unprepare(venc.tv_dac_clk);
947 
948 	dispc_runtime_put();
949 
950 	return 0;
951 }
952 
953 static int venc_runtime_resume(struct device *dev)
954 {
955 	int r;
956 
957 	r = dispc_runtime_get();
958 	if (r < 0)
959 		return r;
960 
961 	if (venc.tv_dac_clk)
962 		clk_prepare_enable(venc.tv_dac_clk);
963 
964 	return 0;
965 }
966 
967 static const struct dev_pm_ops venc_pm_ops = {
968 	.runtime_suspend = venc_runtime_suspend,
969 	.runtime_resume = venc_runtime_resume,
970 };
971 
972 static const struct of_device_id venc_of_match[] = {
973 	{ .compatible = "ti,omap2-venc", },
974 	{ .compatible = "ti,omap3-venc", },
975 	{ .compatible = "ti,omap4-venc", },
976 	{},
977 };
978 
979 static struct platform_driver omap_venchw_driver = {
980 	.probe		= venc_probe,
981 	.remove		= venc_remove,
982 	.driver         = {
983 		.name   = "omapdss_venc",
984 		.pm	= &venc_pm_ops,
985 		.of_match_table = venc_of_match,
986 		.suppress_bind_attrs = true,
987 	},
988 };
989 
990 int __init venc_init_platform_driver(void)
991 {
992 	return platform_driver_register(&omap_venchw_driver);
993 }
994 
995 void venc_uninit_platform_driver(void)
996 {
997 	platform_driver_unregister(&omap_venchw_driver);
998 }
999