1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #define DSS_SUBSYS_NAME "SDI" 8 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/export.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/string.h> 18 19 #include <drm/drm_bridge.h> 20 21 #include "dss.h" 22 #include "omapdss.h" 23 24 struct sdi_device { 25 struct platform_device *pdev; 26 struct dss_device *dss; 27 28 bool update_enabled; 29 struct regulator *vdds_sdi_reg; 30 31 struct dss_lcd_mgr_config mgr_config; 32 unsigned long pixelclock; 33 int datapairs; 34 35 struct omap_dss_device output; 36 struct drm_bridge bridge; 37 }; 38 39 #define drm_bridge_to_sdi(bridge) \ 40 container_of(bridge, struct sdi_device, bridge) 41 42 struct sdi_clk_calc_ctx { 43 struct sdi_device *sdi; 44 unsigned long pck_min, pck_max; 45 46 unsigned long fck; 47 struct dispc_clock_info dispc_cinfo; 48 }; 49 50 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 51 unsigned long pck, void *data) 52 { 53 struct sdi_clk_calc_ctx *ctx = data; 54 55 ctx->dispc_cinfo.lck_div = lckd; 56 ctx->dispc_cinfo.pck_div = pckd; 57 ctx->dispc_cinfo.lck = lck; 58 ctx->dispc_cinfo.pck = pck; 59 60 return true; 61 } 62 63 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 64 { 65 struct sdi_clk_calc_ctx *ctx = data; 66 67 ctx->fck = fck; 68 69 return dispc_div_calc(ctx->sdi->dss->dispc, fck, 70 ctx->pck_min, ctx->pck_max, 71 dpi_calc_dispc_cb, ctx); 72 } 73 74 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk, 75 unsigned long *fck, 76 struct dispc_clock_info *dispc_cinfo) 77 { 78 int i; 79 struct sdi_clk_calc_ctx ctx; 80 81 /* 82 * DSS fclk gives us very few possibilities, so finding a good pixel 83 * clock may not be possible. We try multiple times to find the clock, 84 * each time widening the pixel clock range we look for, up to 85 * +/- 1MHz. 86 */ 87 88 for (i = 0; i < 10; ++i) { 89 bool ok; 90 91 memset(&ctx, 0, sizeof(ctx)); 92 93 ctx.sdi = sdi; 94 95 if (pclk > 1000 * i * i * i) 96 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); 97 else 98 ctx.pck_min = 0; 99 ctx.pck_max = pclk + 1000 * i * i * i; 100 101 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min, 102 dpi_calc_dss_cb, &ctx); 103 if (ok) { 104 *fck = ctx.fck; 105 *dispc_cinfo = ctx.dispc_cinfo; 106 return 0; 107 } 108 } 109 110 return -EINVAL; 111 } 112 113 static void sdi_config_lcd_manager(struct sdi_device *sdi) 114 { 115 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 116 117 sdi->mgr_config.stallmode = false; 118 sdi->mgr_config.fifohandcheck = false; 119 120 sdi->mgr_config.video_port_width = 24; 121 sdi->mgr_config.lcden_sig_polarity = 1; 122 123 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config); 124 } 125 126 /* ----------------------------------------------------------------------------- 127 * DRM Bridge Operations 128 */ 129 130 static int sdi_bridge_attach(struct drm_bridge *bridge, 131 enum drm_bridge_attach_flags flags) 132 { 133 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 134 135 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 136 return -EINVAL; 137 138 return drm_bridge_attach(bridge->encoder, sdi->output.next_bridge, 139 bridge, flags); 140 } 141 142 static enum drm_mode_status 143 sdi_bridge_mode_valid(struct drm_bridge *bridge, 144 const struct drm_display_info *info, 145 const struct drm_display_mode *mode) 146 { 147 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 148 unsigned long pixelclock = mode->clock * 1000; 149 struct dispc_clock_info dispc_cinfo; 150 unsigned long fck; 151 int ret; 152 153 if (pixelclock == 0) 154 return MODE_NOCLOCK; 155 156 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo); 157 if (ret < 0) 158 return MODE_CLOCK_RANGE; 159 160 return MODE_OK; 161 } 162 163 static bool sdi_bridge_mode_fixup(struct drm_bridge *bridge, 164 const struct drm_display_mode *mode, 165 struct drm_display_mode *adjusted_mode) 166 { 167 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 168 unsigned long pixelclock = mode->clock * 1000; 169 struct dispc_clock_info dispc_cinfo; 170 unsigned long fck; 171 unsigned long pck; 172 int ret; 173 174 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo); 175 if (ret < 0) 176 return false; 177 178 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 179 180 if (pck != pixelclock) 181 dev_dbg(&sdi->pdev->dev, 182 "pixel clock adjusted from %lu Hz to %lu Hz\n", 183 pixelclock, pck); 184 185 adjusted_mode->clock = pck / 1000; 186 187 return true; 188 } 189 190 static void sdi_bridge_mode_set(struct drm_bridge *bridge, 191 const struct drm_display_mode *mode, 192 const struct drm_display_mode *adjusted_mode) 193 { 194 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 195 196 sdi->pixelclock = adjusted_mode->clock * 1000; 197 } 198 199 static void sdi_bridge_enable(struct drm_bridge *bridge) 200 { 201 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 202 struct dispc_clock_info dispc_cinfo; 203 unsigned long fck; 204 int r; 205 206 r = regulator_enable(sdi->vdds_sdi_reg); 207 if (r) 208 return; 209 210 r = dispc_runtime_get(sdi->dss->dispc); 211 if (r) 212 goto err_get_dispc; 213 214 r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo); 215 if (r) 216 goto err_calc_clock_div; 217 218 sdi->mgr_config.clock_info = dispc_cinfo; 219 220 r = dss_set_fck_rate(sdi->dss, fck); 221 if (r) 222 goto err_set_dss_clock_div; 223 224 sdi_config_lcd_manager(sdi); 225 226 /* 227 * LCLK and PCLK divisors are located in shadow registers, and we 228 * normally write them to DISPC registers when enabling the output. 229 * However, SDI uses pck-free as source clock for its PLL, and pck-free 230 * is affected by the divisors. And as we need the PLL before enabling 231 * the output, we need to write the divisors early. 232 * 233 * It seems just writing to the DISPC register is enough, and we don't 234 * need to care about the shadow register mechanism for pck-free. The 235 * exact reason for this is unknown. 236 */ 237 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, 238 &sdi->mgr_config.clock_info); 239 240 dss_sdi_init(sdi->dss, sdi->datapairs); 241 r = dss_sdi_enable(sdi->dss); 242 if (r) 243 goto err_sdi_enable; 244 mdelay(2); 245 246 r = dss_mgr_enable(&sdi->output); 247 if (r) 248 goto err_mgr_enable; 249 250 return; 251 252 err_mgr_enable: 253 dss_sdi_disable(sdi->dss); 254 err_sdi_enable: 255 err_set_dss_clock_div: 256 err_calc_clock_div: 257 dispc_runtime_put(sdi->dss->dispc); 258 err_get_dispc: 259 regulator_disable(sdi->vdds_sdi_reg); 260 } 261 262 static void sdi_bridge_disable(struct drm_bridge *bridge) 263 { 264 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 265 266 dss_mgr_disable(&sdi->output); 267 268 dss_sdi_disable(sdi->dss); 269 270 dispc_runtime_put(sdi->dss->dispc); 271 272 regulator_disable(sdi->vdds_sdi_reg); 273 } 274 275 static const struct drm_bridge_funcs sdi_bridge_funcs = { 276 .attach = sdi_bridge_attach, 277 .mode_valid = sdi_bridge_mode_valid, 278 .mode_fixup = sdi_bridge_mode_fixup, 279 .mode_set = sdi_bridge_mode_set, 280 .enable = sdi_bridge_enable, 281 .disable = sdi_bridge_disable, 282 }; 283 284 static void sdi_bridge_init(struct sdi_device *sdi) 285 { 286 sdi->bridge.funcs = &sdi_bridge_funcs; 287 sdi->bridge.of_node = sdi->pdev->dev.of_node; 288 sdi->bridge.type = DRM_MODE_CONNECTOR_LVDS; 289 290 drm_bridge_add(&sdi->bridge); 291 } 292 293 static void sdi_bridge_cleanup(struct sdi_device *sdi) 294 { 295 drm_bridge_remove(&sdi->bridge); 296 } 297 298 /* ----------------------------------------------------------------------------- 299 * Initialisation and Cleanup 300 */ 301 302 static int sdi_init_output(struct sdi_device *sdi) 303 { 304 struct omap_dss_device *out = &sdi->output; 305 int r; 306 307 sdi_bridge_init(sdi); 308 309 out->dev = &sdi->pdev->dev; 310 out->id = OMAP_DSS_OUTPUT_SDI; 311 out->type = OMAP_DISPLAY_TYPE_SDI; 312 out->name = "sdi.0"; 313 out->dispc_channel = OMAP_DSS_CHANNEL_LCD; 314 /* We have SDI only on OMAP3, where it's on port 1 */ 315 out->of_port = 1; 316 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE /* 15.5.9.1.2 */ 317 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE; 318 319 r = omapdss_device_init_output(out, &sdi->bridge); 320 if (r < 0) { 321 sdi_bridge_cleanup(sdi); 322 return r; 323 } 324 325 omapdss_device_register(out); 326 327 return 0; 328 } 329 330 static void sdi_uninit_output(struct sdi_device *sdi) 331 { 332 omapdss_device_unregister(&sdi->output); 333 omapdss_device_cleanup_output(&sdi->output); 334 335 sdi_bridge_cleanup(sdi); 336 } 337 338 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 339 struct device_node *port) 340 { 341 struct sdi_device *sdi; 342 struct device_node *ep; 343 u32 datapairs; 344 int r; 345 346 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL); 347 if (!sdi) 348 return -ENOMEM; 349 350 ep = of_graph_get_next_port_endpoint(port, NULL); 351 if (!ep) { 352 r = 0; 353 goto err_free; 354 } 355 356 r = of_property_read_u32(ep, "datapairs", &datapairs); 357 of_node_put(ep); 358 if (r) { 359 DSSERR("failed to parse datapairs\n"); 360 goto err_free; 361 } 362 363 sdi->datapairs = datapairs; 364 sdi->dss = dss; 365 366 sdi->pdev = pdev; 367 port->data = sdi; 368 369 sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi"); 370 if (IS_ERR(sdi->vdds_sdi_reg)) { 371 r = PTR_ERR(sdi->vdds_sdi_reg); 372 if (r != -EPROBE_DEFER) 373 DSSERR("can't get VDDS_SDI regulator\n"); 374 goto err_free; 375 } 376 377 r = sdi_init_output(sdi); 378 if (r) 379 goto err_free; 380 381 return 0; 382 383 err_free: 384 kfree(sdi); 385 386 return r; 387 } 388 389 void sdi_uninit_port(struct device_node *port) 390 { 391 struct sdi_device *sdi = port->data; 392 393 if (!sdi) 394 return; 395 396 sdi_uninit_output(sdi); 397 kfree(sdi); 398 } 399