1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #define DSS_SUBSYS_NAME "SDI" 8 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/export.h> 12 #include <linux/kernel.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/string.h> 18 19 #include <drm/drm_atomic_state_helper.h> 20 #include <drm/drm_bridge.h> 21 22 #include "dss.h" 23 #include "omapdss.h" 24 25 struct sdi_device { 26 struct platform_device *pdev; 27 struct dss_device *dss; 28 29 bool update_enabled; 30 struct regulator *vdds_sdi_reg; 31 32 struct dss_lcd_mgr_config mgr_config; 33 unsigned long pixelclock; 34 int datapairs; 35 36 struct omap_dss_device output; 37 struct drm_bridge bridge; 38 }; 39 40 #define drm_bridge_to_sdi(bridge) \ 41 container_of(bridge, struct sdi_device, bridge) 42 43 struct sdi_clk_calc_ctx { 44 struct sdi_device *sdi; 45 unsigned long pck_min, pck_max; 46 47 unsigned long fck; 48 struct dispc_clock_info dispc_cinfo; 49 }; 50 51 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 52 unsigned long pck, void *data) 53 { 54 struct sdi_clk_calc_ctx *ctx = data; 55 56 ctx->dispc_cinfo.lck_div = lckd; 57 ctx->dispc_cinfo.pck_div = pckd; 58 ctx->dispc_cinfo.lck = lck; 59 ctx->dispc_cinfo.pck = pck; 60 61 return true; 62 } 63 64 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 65 { 66 struct sdi_clk_calc_ctx *ctx = data; 67 68 ctx->fck = fck; 69 70 return dispc_div_calc(ctx->sdi->dss->dispc, fck, 71 ctx->pck_min, ctx->pck_max, 72 dpi_calc_dispc_cb, ctx); 73 } 74 75 static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk, 76 unsigned long *fck, 77 struct dispc_clock_info *dispc_cinfo) 78 { 79 int i; 80 struct sdi_clk_calc_ctx ctx; 81 82 /* 83 * DSS fclk gives us very few possibilities, so finding a good pixel 84 * clock may not be possible. We try multiple times to find the clock, 85 * each time widening the pixel clock range we look for, up to 86 * +/- 1MHz. 87 */ 88 89 for (i = 0; i < 10; ++i) { 90 bool ok; 91 92 memset(&ctx, 0, sizeof(ctx)); 93 94 ctx.sdi = sdi; 95 96 if (pclk > 1000 * i * i * i) 97 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu); 98 else 99 ctx.pck_min = 0; 100 ctx.pck_max = pclk + 1000 * i * i * i; 101 102 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min, 103 dpi_calc_dss_cb, &ctx); 104 if (ok) { 105 *fck = ctx.fck; 106 *dispc_cinfo = ctx.dispc_cinfo; 107 return 0; 108 } 109 } 110 111 return -EINVAL; 112 } 113 114 static void sdi_config_lcd_manager(struct sdi_device *sdi) 115 { 116 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 117 118 sdi->mgr_config.stallmode = false; 119 sdi->mgr_config.fifohandcheck = false; 120 121 sdi->mgr_config.video_port_width = 24; 122 sdi->mgr_config.lcden_sig_polarity = 1; 123 124 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config); 125 } 126 127 /* ----------------------------------------------------------------------------- 128 * DRM Bridge Operations 129 */ 130 131 static int sdi_bridge_attach(struct drm_bridge *bridge, 132 struct drm_encoder *encoder, 133 enum drm_bridge_attach_flags flags) 134 { 135 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 136 137 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 138 return -EINVAL; 139 140 return drm_bridge_attach(encoder, sdi->output.next_bridge, 141 bridge, flags); 142 } 143 144 static enum drm_mode_status 145 sdi_bridge_mode_valid(struct drm_bridge *bridge, 146 const struct drm_display_info *info, 147 const struct drm_display_mode *mode) 148 { 149 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 150 unsigned long pixelclock = mode->clock * 1000; 151 struct dispc_clock_info dispc_cinfo; 152 unsigned long fck; 153 int ret; 154 155 if (pixelclock == 0) 156 return MODE_NOCLOCK; 157 158 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo); 159 if (ret < 0) 160 return MODE_CLOCK_RANGE; 161 162 return MODE_OK; 163 } 164 165 static bool sdi_bridge_mode_fixup(struct drm_bridge *bridge, 166 const struct drm_display_mode *mode, 167 struct drm_display_mode *adjusted_mode) 168 { 169 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 170 unsigned long pixelclock = mode->clock * 1000; 171 struct dispc_clock_info dispc_cinfo; 172 unsigned long fck; 173 unsigned long pck; 174 int ret; 175 176 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo); 177 if (ret < 0) 178 return false; 179 180 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 181 182 if (pck != pixelclock) 183 dev_dbg(&sdi->pdev->dev, 184 "pixel clock adjusted from %lu Hz to %lu Hz\n", 185 pixelclock, pck); 186 187 adjusted_mode->clock = pck / 1000; 188 189 return true; 190 } 191 192 static void sdi_bridge_mode_set(struct drm_bridge *bridge, 193 const struct drm_display_mode *mode, 194 const struct drm_display_mode *adjusted_mode) 195 { 196 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 197 198 sdi->pixelclock = adjusted_mode->clock * 1000; 199 } 200 201 static void sdi_bridge_enable(struct drm_bridge *bridge, 202 struct drm_atomic_commit *commit) 203 { 204 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 205 struct dispc_clock_info dispc_cinfo; 206 unsigned long fck; 207 int r; 208 209 r = regulator_enable(sdi->vdds_sdi_reg); 210 if (r) 211 return; 212 213 r = dispc_runtime_get(sdi->dss->dispc); 214 if (r) 215 goto err_get_dispc; 216 217 r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo); 218 if (r) 219 goto err_calc_clock_div; 220 221 sdi->mgr_config.clock_info = dispc_cinfo; 222 223 r = dss_set_fck_rate(sdi->dss, fck); 224 if (r) 225 goto err_set_dss_clock_div; 226 227 sdi_config_lcd_manager(sdi); 228 229 /* 230 * LCLK and PCLK divisors are located in shadow registers, and we 231 * normally write them to DISPC registers when enabling the output. 232 * However, SDI uses pck-free as source clock for its PLL, and pck-free 233 * is affected by the divisors. And as we need the PLL before enabling 234 * the output, we need to write the divisors early. 235 * 236 * It seems just writing to the DISPC register is enough, and we don't 237 * need to care about the shadow register mechanism for pck-free. The 238 * exact reason for this is unknown. 239 */ 240 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, 241 &sdi->mgr_config.clock_info); 242 243 dss_sdi_init(sdi->dss, sdi->datapairs); 244 r = dss_sdi_enable(sdi->dss); 245 if (r) 246 goto err_sdi_enable; 247 mdelay(2); 248 249 r = dss_mgr_enable(&sdi->output); 250 if (r) 251 goto err_mgr_enable; 252 253 return; 254 255 err_mgr_enable: 256 dss_sdi_disable(sdi->dss); 257 err_sdi_enable: 258 err_set_dss_clock_div: 259 err_calc_clock_div: 260 dispc_runtime_put(sdi->dss->dispc); 261 err_get_dispc: 262 regulator_disable(sdi->vdds_sdi_reg); 263 } 264 265 static void sdi_bridge_disable(struct drm_bridge *bridge, 266 struct drm_atomic_commit *commit) 267 { 268 struct sdi_device *sdi = drm_bridge_to_sdi(bridge); 269 270 dss_mgr_disable(&sdi->output); 271 272 dss_sdi_disable(sdi->dss); 273 274 dispc_runtime_put(sdi->dss->dispc); 275 276 regulator_disable(sdi->vdds_sdi_reg); 277 } 278 279 static const struct drm_bridge_funcs sdi_bridge_funcs = { 280 .atomic_create_state = drm_atomic_helper_bridge_create_state, 281 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 282 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 283 .attach = sdi_bridge_attach, 284 .mode_valid = sdi_bridge_mode_valid, 285 .mode_fixup = sdi_bridge_mode_fixup, 286 .mode_set = sdi_bridge_mode_set, 287 .atomic_enable = sdi_bridge_enable, 288 .atomic_disable = sdi_bridge_disable, 289 }; 290 291 static void sdi_bridge_init(struct sdi_device *sdi) 292 { 293 sdi->bridge.of_node = sdi->pdev->dev.of_node; 294 sdi->bridge.type = DRM_MODE_CONNECTOR_LVDS; 295 296 drm_bridge_add(&sdi->bridge); 297 } 298 299 static void sdi_bridge_cleanup(struct sdi_device *sdi) 300 { 301 drm_bridge_remove(&sdi->bridge); 302 } 303 304 /* ----------------------------------------------------------------------------- 305 * Initialisation and Cleanup 306 */ 307 308 static int sdi_init_output(struct sdi_device *sdi) 309 { 310 struct omap_dss_device *out = &sdi->output; 311 int r; 312 313 sdi_bridge_init(sdi); 314 315 out->dev = &sdi->pdev->dev; 316 out->id = OMAP_DSS_OUTPUT_SDI; 317 out->type = OMAP_DISPLAY_TYPE_SDI; 318 out->name = "sdi.0"; 319 out->dispc_channel = OMAP_DSS_CHANNEL_LCD; 320 /* We have SDI only on OMAP3, where it's on port 1 */ 321 out->of_port = 1; 322 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE /* 15.5.9.1.2 */ 323 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE; 324 325 r = omapdss_device_init_output(out, &sdi->bridge); 326 if (r < 0) { 327 sdi_bridge_cleanup(sdi); 328 return r; 329 } 330 331 omapdss_device_register(out); 332 333 return 0; 334 } 335 336 static void sdi_uninit_output(struct sdi_device *sdi) 337 { 338 omapdss_device_unregister(&sdi->output); 339 omapdss_device_cleanup_output(&sdi->output); 340 341 sdi_bridge_cleanup(sdi); 342 } 343 344 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev, 345 struct device_node *port) 346 { 347 struct sdi_device *sdi; 348 struct device_node *ep; 349 u32 datapairs; 350 int r; 351 352 sdi = devm_drm_bridge_alloc(&pdev->dev, struct sdi_device, bridge, &sdi_bridge_funcs); 353 if (IS_ERR(sdi)) 354 return PTR_ERR(sdi); 355 356 ep = of_graph_get_next_port_endpoint(port, NULL); 357 if (!ep) 358 return 0; 359 360 r = of_property_read_u32(ep, "datapairs", &datapairs); 361 of_node_put(ep); 362 if (r) { 363 DSSERR("failed to parse datapairs\n"); 364 return r; 365 } 366 367 sdi->datapairs = datapairs; 368 sdi->dss = dss; 369 370 sdi->pdev = pdev; 371 port->data = sdi; 372 373 sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi"); 374 if (IS_ERR(sdi->vdds_sdi_reg)) { 375 r = PTR_ERR(sdi->vdds_sdi_reg); 376 if (r != -EPROBE_DEFER) 377 DSSERR("can't get VDDS_SDI regulator\n"); 378 return r; 379 } 380 381 r = sdi_init_output(sdi); 382 if (r) 383 return r; 384 385 return 0; 386 } 387 388 void sdi_uninit_port(struct device_node *port) 389 { 390 struct sdi_device *sdi = port->data; 391 392 if (!sdi) 393 return; 394 395 sdi_uninit_output(sdi); 396 } 397