1 /* 2 * HDMI wrapper 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 */ 10 11 #define DSS_SUBSYS_NAME "HDMIWP" 12 13 #include <linux/kernel.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/platform_device.h> 17 #include <video/omapdss.h> 18 19 #include "dss.h" 20 #include "hdmi.h" 21 22 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) 23 { 24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) 25 26 DUMPREG(HDMI_WP_REVISION); 27 DUMPREG(HDMI_WP_SYSCONFIG); 28 DUMPREG(HDMI_WP_IRQSTATUS_RAW); 29 DUMPREG(HDMI_WP_IRQSTATUS); 30 DUMPREG(HDMI_WP_IRQENABLE_SET); 31 DUMPREG(HDMI_WP_IRQENABLE_CLR); 32 DUMPREG(HDMI_WP_IRQWAKEEN); 33 DUMPREG(HDMI_WP_PWR_CTRL); 34 DUMPREG(HDMI_WP_DEBOUNCE); 35 DUMPREG(HDMI_WP_VIDEO_CFG); 36 DUMPREG(HDMI_WP_VIDEO_SIZE); 37 DUMPREG(HDMI_WP_VIDEO_TIMING_H); 38 DUMPREG(HDMI_WP_VIDEO_TIMING_V); 39 DUMPREG(HDMI_WP_CLK); 40 DUMPREG(HDMI_WP_AUDIO_CFG); 41 DUMPREG(HDMI_WP_AUDIO_CFG2); 42 DUMPREG(HDMI_WP_AUDIO_CTRL); 43 DUMPREG(HDMI_WP_AUDIO_DATA); 44 } 45 46 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) 47 { 48 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); 49 } 50 51 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) 52 { 53 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); 54 /* flush posted write */ 55 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); 56 } 57 58 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) 59 { 60 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); 61 } 62 63 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) 64 { 65 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); 66 } 67 68 /* PHY_PWR_CMD */ 69 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val) 70 { 71 /* Return if already the state */ 72 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) 73 return 0; 74 75 /* Command for power control of HDMI PHY */ 76 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); 77 78 /* Status of the power control of HDMI PHY */ 79 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) 80 != val) { 81 DSSERR("Failed to set PHY power mode to %d\n", val); 82 return -ETIMEDOUT; 83 } 84 85 return 0; 86 } 87 88 /* PLL_PWR_CMD */ 89 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val) 90 { 91 /* Command for power control of HDMI PLL */ 92 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); 93 94 /* wait till PHY_PWR_STATUS is set */ 95 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val) 96 != val) { 97 DSSERR("Failed to set PLL_PWR_STATUS\n"); 98 return -ETIMEDOUT; 99 } 100 101 return 0; 102 } 103 104 int hdmi_wp_video_start(struct hdmi_wp_data *wp) 105 { 106 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); 107 108 return 0; 109 } 110 111 void hdmi_wp_video_stop(struct hdmi_wp_data *wp) 112 { 113 int i; 114 115 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE); 116 117 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); 118 119 for (i = 0; i < 50; ++i) { 120 u32 v; 121 122 msleep(20); 123 124 v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW); 125 if (v & HDMI_IRQ_VIDEO_FRAME_DONE) 126 return; 127 } 128 129 DSSERR("no HDMI FRAMEDONE when disabling output\n"); 130 } 131 132 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, 133 struct hdmi_video_format *video_fmt) 134 { 135 u32 l = 0; 136 137 REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 138 10, 8); 139 140 l |= FLD_VAL(video_fmt->y_res, 31, 16); 141 l |= FLD_VAL(video_fmt->x_res, 15, 0); 142 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l); 143 } 144 145 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, 146 struct omap_video_timings *timings) 147 { 148 u32 r; 149 bool vsync_pol, hsync_pol; 150 DSSDBG("Enter hdmi_wp_video_config_interface\n"); 151 152 vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 153 hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; 154 155 r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); 156 r = FLD_MOD(r, vsync_pol, 7, 7); 157 r = FLD_MOD(r, hsync_pol, 6, 6); 158 r = FLD_MOD(r, timings->interlace, 3, 3); 159 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */ 160 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r); 161 } 162 163 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, 164 struct omap_video_timings *timings) 165 { 166 u32 timing_h = 0; 167 u32 timing_v = 0; 168 unsigned hsw_offset = 1; 169 170 DSSDBG("Enter hdmi_wp_video_config_timing\n"); 171 172 /* 173 * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5 174 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1. 175 * However, we don't support OMAP5 ES1 at all, so we can just check for 176 * OMAP4 here. 177 */ 178 if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || 179 omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || 180 omapdss_get_version() == OMAPDSS_VER_OMAP4) 181 hsw_offset = 0; 182 183 timing_h |= FLD_VAL(timings->hbp, 31, 20); 184 timing_h |= FLD_VAL(timings->hfp, 19, 8); 185 timing_h |= FLD_VAL(timings->hsw - hsw_offset, 7, 0); 186 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); 187 188 timing_v |= FLD_VAL(timings->vbp, 31, 20); 189 timing_v |= FLD_VAL(timings->vfp, 19, 8); 190 timing_v |= FLD_VAL(timings->vsw, 7, 0); 191 hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v); 192 } 193 194 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, 195 struct omap_video_timings *timings, struct hdmi_config *param) 196 { 197 DSSDBG("Enter hdmi_wp_video_init_format\n"); 198 199 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; 200 video_fmt->y_res = param->timings.y_res; 201 video_fmt->x_res = param->timings.x_res; 202 203 timings->hbp = param->timings.hbp; 204 timings->hfp = param->timings.hfp; 205 timings->hsw = param->timings.hsw; 206 timings->vbp = param->timings.vbp; 207 timings->vfp = param->timings.vfp; 208 timings->vsw = param->timings.vsw; 209 210 timings->vsync_level = param->timings.vsync_level; 211 timings->hsync_level = param->timings.hsync_level; 212 timings->interlace = param->timings.interlace; 213 timings->double_pixel = param->timings.double_pixel; 214 215 if (param->timings.interlace) { 216 video_fmt->y_res /= 2; 217 timings->vbp /= 2; 218 timings->vfp /= 2; 219 timings->vsw /= 2; 220 } 221 222 if (param->timings.double_pixel) { 223 video_fmt->x_res *= 2; 224 timings->hfp *= 2; 225 timings->hsw *= 2; 226 timings->hbp *= 2; 227 } 228 } 229 230 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, 231 struct hdmi_audio_format *aud_fmt) 232 { 233 u32 r; 234 235 DSSDBG("Enter hdmi_wp_audio_config_format\n"); 236 237 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG); 238 if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || 239 omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || 240 omapdss_get_version() == OMAPDSS_VER_OMAP4) { 241 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); 242 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); 243 } 244 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); 245 r = FLD_MOD(r, aud_fmt->type, 4, 4); 246 r = FLD_MOD(r, aud_fmt->justification, 3, 3); 247 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); 248 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); 249 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); 250 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r); 251 } 252 253 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, 254 struct hdmi_audio_dma *aud_dma) 255 { 256 u32 r; 257 258 DSSDBG("Enter hdmi_wp_audio_config_dma\n"); 259 260 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2); 261 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8); 262 r = FLD_MOD(r, aud_dma->block_size, 7, 0); 263 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r); 264 265 r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL); 266 r = FLD_MOD(r, aud_dma->mode, 9, 9); 267 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0); 268 hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r); 269 } 270 271 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable) 272 { 273 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); 274 275 return 0; 276 } 277 278 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable) 279 { 280 REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); 281 282 return 0; 283 } 284 285 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp) 286 { 287 struct resource *res; 288 289 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp"); 290 if (!res) { 291 DSSERR("can't get WP mem resource\n"); 292 return -EINVAL; 293 } 294 wp->phys_base = res->start; 295 296 wp->base = devm_ioremap_resource(&pdev->dev, res); 297 if (IS_ERR(wp->base)) { 298 DSSERR("can't ioremap HDMI WP\n"); 299 return PTR_ERR(wp->base); 300 } 301 302 return 0; 303 } 304 305 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp) 306 { 307 return wp->phys_base + HDMI_WP_AUDIO_DATA; 308 } 309