1 /* 2 * linux/drivers/video/omap2/dss/dss.c 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #define DSS_SUBSYS_NAME "DSS" 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/io.h> 28 #include <linux/export.h> 29 #include <linux/err.h> 30 #include <linux/delay.h> 31 #include <linux/seq_file.h> 32 #include <linux/clk.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/platform_device.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/gfp.h> 37 #include <linux/sizes.h> 38 #include <linux/mfd/syscon.h> 39 #include <linux/regmap.h> 40 #include <linux/of.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/suspend.h> 43 #include <linux/component.h> 44 45 #include "omapdss.h" 46 #include "dss.h" 47 #include "dss_features.h" 48 49 #define DSS_SZ_REGS SZ_512 50 51 struct dss_reg { 52 u16 idx; 53 }; 54 55 #define DSS_REG(idx) ((const struct dss_reg) { idx }) 56 57 #define DSS_REVISION DSS_REG(0x0000) 58 #define DSS_SYSCONFIG DSS_REG(0x0010) 59 #define DSS_SYSSTATUS DSS_REG(0x0014) 60 #define DSS_CONTROL DSS_REG(0x0040) 61 #define DSS_SDI_CONTROL DSS_REG(0x0044) 62 #define DSS_PLL_CONTROL DSS_REG(0x0048) 63 #define DSS_SDI_STATUS DSS_REG(0x005C) 64 65 #define REG_GET(idx, start, end) \ 66 FLD_GET(dss_read_reg(idx), start, end) 67 68 #define REG_FLD_MOD(idx, val, start, end) \ 69 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 70 71 struct dss_features { 72 u8 fck_div_max; 73 u8 dss_fck_multiplier; 74 const char *parent_clk_name; 75 const enum omap_display_type *ports; 76 int num_ports; 77 int (*dpi_select_source)(int port, enum omap_channel channel); 78 int (*select_lcd_source)(enum omap_channel channel, 79 enum dss_clk_source clk_src); 80 }; 81 82 static struct { 83 struct platform_device *pdev; 84 void __iomem *base; 85 struct regmap *syscon_pll_ctrl; 86 u32 syscon_pll_ctrl_offset; 87 88 struct clk *parent_clk; 89 struct clk *dss_clk; 90 unsigned long dss_clk_rate; 91 92 unsigned long cache_req_pck; 93 unsigned long cache_prate; 94 struct dispc_clock_info cache_dispc_cinfo; 95 96 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI]; 97 enum dss_clk_source dispc_clk_source; 98 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 99 100 bool ctx_valid; 101 u32 ctx[DSS_SZ_REGS / sizeof(u32)]; 102 103 const struct dss_features *feat; 104 105 struct dss_pll *video1_pll; 106 struct dss_pll *video2_pll; 107 } dss; 108 109 static const char * const dss_generic_clk_source_names[] = { 110 [DSS_CLK_SRC_FCK] = "FCK", 111 [DSS_CLK_SRC_PLL1_1] = "PLL1:1", 112 [DSS_CLK_SRC_PLL1_2] = "PLL1:2", 113 [DSS_CLK_SRC_PLL1_3] = "PLL1:3", 114 [DSS_CLK_SRC_PLL2_1] = "PLL2:1", 115 [DSS_CLK_SRC_PLL2_2] = "PLL2:2", 116 [DSS_CLK_SRC_PLL2_3] = "PLL2:3", 117 [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", 118 }; 119 120 static inline void dss_write_reg(const struct dss_reg idx, u32 val) 121 { 122 __raw_writel(val, dss.base + idx.idx); 123 } 124 125 static inline u32 dss_read_reg(const struct dss_reg idx) 126 { 127 return __raw_readl(dss.base + idx.idx); 128 } 129 130 #define SR(reg) \ 131 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) 132 #define RR(reg) \ 133 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) 134 135 static void dss_save_context(void) 136 { 137 DSSDBG("dss_save_context\n"); 138 139 SR(CONTROL); 140 141 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & 142 OMAP_DISPLAY_TYPE_SDI) { 143 SR(SDI_CONTROL); 144 SR(PLL_CONTROL); 145 } 146 147 dss.ctx_valid = true; 148 149 DSSDBG("context saved\n"); 150 } 151 152 static void dss_restore_context(void) 153 { 154 DSSDBG("dss_restore_context\n"); 155 156 if (!dss.ctx_valid) 157 return; 158 159 RR(CONTROL); 160 161 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & 162 OMAP_DISPLAY_TYPE_SDI) { 163 RR(SDI_CONTROL); 164 RR(PLL_CONTROL); 165 } 166 167 DSSDBG("context restored\n"); 168 } 169 170 #undef SR 171 #undef RR 172 173 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable) 174 { 175 unsigned shift; 176 unsigned val; 177 178 if (!dss.syscon_pll_ctrl) 179 return; 180 181 val = !enable; 182 183 switch (pll_id) { 184 case DSS_PLL_VIDEO1: 185 shift = 0; 186 break; 187 case DSS_PLL_VIDEO2: 188 shift = 1; 189 break; 190 case DSS_PLL_HDMI: 191 shift = 2; 192 break; 193 default: 194 DSSERR("illegal DSS PLL ID %d\n", pll_id); 195 return; 196 } 197 198 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 199 1 << shift, val << shift); 200 } 201 202 static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src, 203 enum omap_channel channel) 204 { 205 unsigned shift, val; 206 207 if (!dss.syscon_pll_ctrl) 208 return -EINVAL; 209 210 switch (channel) { 211 case OMAP_DSS_CHANNEL_LCD: 212 shift = 3; 213 214 switch (clk_src) { 215 case DSS_CLK_SRC_PLL1_1: 216 val = 0; break; 217 case DSS_CLK_SRC_HDMI_PLL: 218 val = 1; break; 219 default: 220 DSSERR("error in PLL mux config for LCD\n"); 221 return -EINVAL; 222 } 223 224 break; 225 case OMAP_DSS_CHANNEL_LCD2: 226 shift = 5; 227 228 switch (clk_src) { 229 case DSS_CLK_SRC_PLL1_3: 230 val = 0; break; 231 case DSS_CLK_SRC_PLL2_3: 232 val = 1; break; 233 case DSS_CLK_SRC_HDMI_PLL: 234 val = 2; break; 235 default: 236 DSSERR("error in PLL mux config for LCD2\n"); 237 return -EINVAL; 238 } 239 240 break; 241 case OMAP_DSS_CHANNEL_LCD3: 242 shift = 7; 243 244 switch (clk_src) { 245 case DSS_CLK_SRC_PLL2_1: 246 val = 0; break; 247 case DSS_CLK_SRC_PLL1_3: 248 val = 1; break; 249 case DSS_CLK_SRC_HDMI_PLL: 250 val = 2; break; 251 default: 252 DSSERR("error in PLL mux config for LCD3\n"); 253 return -EINVAL; 254 } 255 256 break; 257 default: 258 DSSERR("error in PLL mux config\n"); 259 return -EINVAL; 260 } 261 262 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 263 0x3 << shift, val << shift); 264 265 return 0; 266 } 267 268 void dss_sdi_init(int datapairs) 269 { 270 u32 l; 271 272 BUG_ON(datapairs > 3 || datapairs < 1); 273 274 l = dss_read_reg(DSS_SDI_CONTROL); 275 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 276 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 277 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 278 dss_write_reg(DSS_SDI_CONTROL, l); 279 280 l = dss_read_reg(DSS_PLL_CONTROL); 281 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 282 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 283 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ 284 dss_write_reg(DSS_PLL_CONTROL, l); 285 } 286 287 int dss_sdi_enable(void) 288 { 289 unsigned long timeout; 290 291 dispc_pck_free_enable(1); 292 293 /* Reset SDI PLL */ 294 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 295 udelay(1); /* wait 2x PCLK */ 296 297 /* Lock SDI PLL */ 298 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 299 300 /* Waiting for PLL lock request to complete */ 301 timeout = jiffies + msecs_to_jiffies(500); 302 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { 303 if (time_after_eq(jiffies, timeout)) { 304 DSSERR("PLL lock request timed out\n"); 305 goto err1; 306 } 307 } 308 309 /* Clearing PLL_GO bit */ 310 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 311 312 /* Waiting for PLL to lock */ 313 timeout = jiffies + msecs_to_jiffies(500); 314 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { 315 if (time_after_eq(jiffies, timeout)) { 316 DSSERR("PLL lock timed out\n"); 317 goto err1; 318 } 319 } 320 321 dispc_lcd_enable_signal(1); 322 323 /* Waiting for SDI reset to complete */ 324 timeout = jiffies + msecs_to_jiffies(500); 325 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { 326 if (time_after_eq(jiffies, timeout)) { 327 DSSERR("SDI reset timed out\n"); 328 goto err2; 329 } 330 } 331 332 return 0; 333 334 err2: 335 dispc_lcd_enable_signal(0); 336 err1: 337 /* Reset SDI PLL */ 338 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 339 340 dispc_pck_free_enable(0); 341 342 return -ETIMEDOUT; 343 } 344 345 void dss_sdi_disable(void) 346 { 347 dispc_lcd_enable_signal(0); 348 349 dispc_pck_free_enable(0); 350 351 /* Reset SDI PLL */ 352 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 353 } 354 355 const char *dss_get_clk_source_name(enum dss_clk_source clk_src) 356 { 357 return dss_generic_clk_source_names[clk_src]; 358 } 359 360 void dss_dump_clocks(struct seq_file *s) 361 { 362 const char *fclk_name; 363 unsigned long fclk_rate; 364 365 if (dss_runtime_get()) 366 return; 367 368 seq_printf(s, "- DSS -\n"); 369 370 fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); 371 fclk_rate = clk_get_rate(dss.dss_clk); 372 373 seq_printf(s, "%s = %lu\n", 374 fclk_name, 375 fclk_rate); 376 377 dss_runtime_put(); 378 } 379 380 static void dss_dump_regs(struct seq_file *s) 381 { 382 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) 383 384 if (dss_runtime_get()) 385 return; 386 387 DUMPREG(DSS_REVISION); 388 DUMPREG(DSS_SYSCONFIG); 389 DUMPREG(DSS_SYSSTATUS); 390 DUMPREG(DSS_CONTROL); 391 392 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & 393 OMAP_DISPLAY_TYPE_SDI) { 394 DUMPREG(DSS_SDI_CONTROL); 395 DUMPREG(DSS_PLL_CONTROL); 396 DUMPREG(DSS_SDI_STATUS); 397 } 398 399 dss_runtime_put(); 400 #undef DUMPREG 401 } 402 403 static int dss_get_channel_index(enum omap_channel channel) 404 { 405 switch (channel) { 406 case OMAP_DSS_CHANNEL_LCD: 407 return 0; 408 case OMAP_DSS_CHANNEL_LCD2: 409 return 1; 410 case OMAP_DSS_CHANNEL_LCD3: 411 return 2; 412 default: 413 WARN_ON(1); 414 return 0; 415 } 416 } 417 418 static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) 419 { 420 int b; 421 u8 start, end; 422 423 /* 424 * We always use PRCM clock as the DISPC func clock, except on DSS3, 425 * where we don't have separate DISPC and LCD clock sources. 426 */ 427 if (WARN_ON(dss_has_feature(FEAT_LCD_CLK_SRC) && 428 clk_src != DSS_CLK_SRC_FCK)) 429 return; 430 431 switch (clk_src) { 432 case DSS_CLK_SRC_FCK: 433 b = 0; 434 break; 435 case DSS_CLK_SRC_PLL1_1: 436 b = 1; 437 break; 438 case DSS_CLK_SRC_PLL2_1: 439 b = 2; 440 break; 441 default: 442 BUG(); 443 return; 444 } 445 446 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); 447 448 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ 449 450 dss.dispc_clk_source = clk_src; 451 } 452 453 void dss_select_dsi_clk_source(int dsi_module, 454 enum dss_clk_source clk_src) 455 { 456 int b, pos; 457 458 switch (clk_src) { 459 case DSS_CLK_SRC_FCK: 460 b = 0; 461 break; 462 case DSS_CLK_SRC_PLL1_2: 463 BUG_ON(dsi_module != 0); 464 b = 1; 465 break; 466 case DSS_CLK_SRC_PLL2_2: 467 BUG_ON(dsi_module != 1); 468 b = 1; 469 break; 470 default: 471 BUG(); 472 return; 473 } 474 475 pos = dsi_module == 0 ? 1 : 10; 476 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ 477 478 dss.dsi_clk_source[dsi_module] = clk_src; 479 } 480 481 static int dss_lcd_clk_mux_dra7(enum omap_channel channel, 482 enum dss_clk_source clk_src) 483 { 484 const u8 ctrl_bits[] = { 485 [OMAP_DSS_CHANNEL_LCD] = 0, 486 [OMAP_DSS_CHANNEL_LCD2] = 12, 487 [OMAP_DSS_CHANNEL_LCD3] = 19, 488 }; 489 490 u8 ctrl_bit = ctrl_bits[channel]; 491 int r; 492 493 if (clk_src == DSS_CLK_SRC_FCK) { 494 /* LCDx_CLK_SWITCH */ 495 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 496 return -EINVAL; 497 } 498 499 r = dss_ctrl_pll_set_control_mux(clk_src, channel); 500 if (r) 501 return r; 502 503 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 504 505 return 0; 506 } 507 508 static int dss_lcd_clk_mux_omap5(enum omap_channel channel, 509 enum dss_clk_source clk_src) 510 { 511 const u8 ctrl_bits[] = { 512 [OMAP_DSS_CHANNEL_LCD] = 0, 513 [OMAP_DSS_CHANNEL_LCD2] = 12, 514 [OMAP_DSS_CHANNEL_LCD3] = 19, 515 }; 516 const enum dss_clk_source allowed_plls[] = { 517 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 518 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK, 519 [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1, 520 }; 521 522 u8 ctrl_bit = ctrl_bits[channel]; 523 524 if (clk_src == DSS_CLK_SRC_FCK) { 525 /* LCDx_CLK_SWITCH */ 526 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 527 return -EINVAL; 528 } 529 530 if (WARN_ON(allowed_plls[channel] != clk_src)) 531 return -EINVAL; 532 533 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 534 535 return 0; 536 } 537 538 static int dss_lcd_clk_mux_omap4(enum omap_channel channel, 539 enum dss_clk_source clk_src) 540 { 541 const u8 ctrl_bits[] = { 542 [OMAP_DSS_CHANNEL_LCD] = 0, 543 [OMAP_DSS_CHANNEL_LCD2] = 12, 544 }; 545 const enum dss_clk_source allowed_plls[] = { 546 [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 547 [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1, 548 }; 549 550 u8 ctrl_bit = ctrl_bits[channel]; 551 552 if (clk_src == DSS_CLK_SRC_FCK) { 553 /* LCDx_CLK_SWITCH */ 554 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 555 return 0; 556 } 557 558 if (WARN_ON(allowed_plls[channel] != clk_src)) 559 return -EINVAL; 560 561 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 562 563 return 0; 564 } 565 566 void dss_select_lcd_clk_source(enum omap_channel channel, 567 enum dss_clk_source clk_src) 568 { 569 int idx = dss_get_channel_index(channel); 570 int r; 571 572 if (!dss_has_feature(FEAT_LCD_CLK_SRC)) { 573 dss_select_dispc_clk_source(clk_src); 574 dss.lcd_clk_source[idx] = clk_src; 575 return; 576 } 577 578 r = dss.feat->select_lcd_source(channel, clk_src); 579 if (r) 580 return; 581 582 dss.lcd_clk_source[idx] = clk_src; 583 } 584 585 enum dss_clk_source dss_get_dispc_clk_source(void) 586 { 587 return dss.dispc_clk_source; 588 } 589 590 enum dss_clk_source dss_get_dsi_clk_source(int dsi_module) 591 { 592 return dss.dsi_clk_source[dsi_module]; 593 } 594 595 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) 596 { 597 if (dss_has_feature(FEAT_LCD_CLK_SRC)) { 598 int idx = dss_get_channel_index(channel); 599 return dss.lcd_clk_source[idx]; 600 } else { 601 /* LCD_CLK source is the same as DISPC_FCLK source for 602 * OMAP2 and OMAP3 */ 603 return dss.dispc_clk_source; 604 } 605 } 606 607 bool dss_div_calc(unsigned long pck, unsigned long fck_min, 608 dss_div_calc_func func, void *data) 609 { 610 int fckd, fckd_start, fckd_stop; 611 unsigned long fck; 612 unsigned long fck_hw_max; 613 unsigned long fckd_hw_max; 614 unsigned long prate; 615 unsigned m; 616 617 fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); 618 619 if (dss.parent_clk == NULL) { 620 unsigned pckd; 621 622 pckd = fck_hw_max / pck; 623 624 fck = pck * pckd; 625 626 fck = clk_round_rate(dss.dss_clk, fck); 627 628 return func(fck, data); 629 } 630 631 fckd_hw_max = dss.feat->fck_div_max; 632 633 m = dss.feat->dss_fck_multiplier; 634 prate = clk_get_rate(dss.parent_clk); 635 636 fck_min = fck_min ? fck_min : 1; 637 638 fckd_start = min(prate * m / fck_min, fckd_hw_max); 639 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); 640 641 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { 642 fck = DIV_ROUND_UP(prate, fckd) * m; 643 644 if (func(fck, data)) 645 return true; 646 } 647 648 return false; 649 } 650 651 int dss_set_fck_rate(unsigned long rate) 652 { 653 int r; 654 655 DSSDBG("set fck to %lu\n", rate); 656 657 r = clk_set_rate(dss.dss_clk, rate); 658 if (r) 659 return r; 660 661 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 662 663 WARN_ONCE(dss.dss_clk_rate != rate, 664 "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, 665 rate); 666 667 return 0; 668 } 669 670 unsigned long dss_get_dispc_clk_rate(void) 671 { 672 return dss.dss_clk_rate; 673 } 674 675 static int dss_setup_default_clock(void) 676 { 677 unsigned long max_dss_fck, prate; 678 unsigned long fck; 679 unsigned fck_div; 680 int r; 681 682 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); 683 684 if (dss.parent_clk == NULL) { 685 fck = clk_round_rate(dss.dss_clk, max_dss_fck); 686 } else { 687 prate = clk_get_rate(dss.parent_clk); 688 689 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, 690 max_dss_fck); 691 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; 692 } 693 694 r = dss_set_fck_rate(fck); 695 if (r) 696 return r; 697 698 return 0; 699 } 700 701 void dss_set_venc_output(enum omap_dss_venc_type type) 702 { 703 int l = 0; 704 705 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) 706 l = 0; 707 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) 708 l = 1; 709 else 710 BUG(); 711 712 /* venc out selection. 0 = comp, 1 = svideo */ 713 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); 714 } 715 716 void dss_set_dac_pwrdn_bgz(bool enable) 717 { 718 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ 719 } 720 721 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) 722 { 723 enum omap_display_type dp; 724 dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); 725 726 /* Complain about invalid selections */ 727 WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC)); 728 WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI)); 729 730 /* Select only if we have options */ 731 if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI)) 732 REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ 733 } 734 735 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) 736 { 737 enum omap_display_type displays; 738 739 displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); 740 if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) 741 return DSS_VENC_TV_CLK; 742 743 if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0) 744 return DSS_HDMI_M_PCLK; 745 746 return REG_GET(DSS_CONTROL, 15, 15); 747 } 748 749 static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel) 750 { 751 if (channel != OMAP_DSS_CHANNEL_LCD) 752 return -EINVAL; 753 754 return 0; 755 } 756 757 static int dss_dpi_select_source_omap4(int port, enum omap_channel channel) 758 { 759 int val; 760 761 switch (channel) { 762 case OMAP_DSS_CHANNEL_LCD2: 763 val = 0; 764 break; 765 case OMAP_DSS_CHANNEL_DIGIT: 766 val = 1; 767 break; 768 default: 769 return -EINVAL; 770 } 771 772 REG_FLD_MOD(DSS_CONTROL, val, 17, 17); 773 774 return 0; 775 } 776 777 static int dss_dpi_select_source_omap5(int port, enum omap_channel channel) 778 { 779 int val; 780 781 switch (channel) { 782 case OMAP_DSS_CHANNEL_LCD: 783 val = 1; 784 break; 785 case OMAP_DSS_CHANNEL_LCD2: 786 val = 2; 787 break; 788 case OMAP_DSS_CHANNEL_LCD3: 789 val = 3; 790 break; 791 case OMAP_DSS_CHANNEL_DIGIT: 792 val = 0; 793 break; 794 default: 795 return -EINVAL; 796 } 797 798 REG_FLD_MOD(DSS_CONTROL, val, 17, 16); 799 800 return 0; 801 } 802 803 static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel) 804 { 805 switch (port) { 806 case 0: 807 return dss_dpi_select_source_omap5(port, channel); 808 case 1: 809 if (channel != OMAP_DSS_CHANNEL_LCD2) 810 return -EINVAL; 811 break; 812 case 2: 813 if (channel != OMAP_DSS_CHANNEL_LCD3) 814 return -EINVAL; 815 break; 816 default: 817 return -EINVAL; 818 } 819 820 return 0; 821 } 822 823 int dss_dpi_select_source(int port, enum omap_channel channel) 824 { 825 return dss.feat->dpi_select_source(port, channel); 826 } 827 828 static int dss_get_clocks(void) 829 { 830 struct clk *clk; 831 832 clk = devm_clk_get(&dss.pdev->dev, "fck"); 833 if (IS_ERR(clk)) { 834 DSSERR("can't get clock fck\n"); 835 return PTR_ERR(clk); 836 } 837 838 dss.dss_clk = clk; 839 840 if (dss.feat->parent_clk_name) { 841 clk = clk_get(NULL, dss.feat->parent_clk_name); 842 if (IS_ERR(clk)) { 843 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); 844 return PTR_ERR(clk); 845 } 846 } else { 847 clk = NULL; 848 } 849 850 dss.parent_clk = clk; 851 852 return 0; 853 } 854 855 static void dss_put_clocks(void) 856 { 857 if (dss.parent_clk) 858 clk_put(dss.parent_clk); 859 } 860 861 int dss_runtime_get(void) 862 { 863 int r; 864 865 DSSDBG("dss_runtime_get\n"); 866 867 r = pm_runtime_get_sync(&dss.pdev->dev); 868 WARN_ON(r < 0); 869 return r < 0 ? r : 0; 870 } 871 872 void dss_runtime_put(void) 873 { 874 int r; 875 876 DSSDBG("dss_runtime_put\n"); 877 878 r = pm_runtime_put_sync(&dss.pdev->dev); 879 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); 880 } 881 882 /* DEBUGFS */ 883 #if defined(CONFIG_OMAP2_DSS_DEBUGFS) 884 void dss_debug_dump_clocks(struct seq_file *s) 885 { 886 dss_dump_clocks(s); 887 dispc_dump_clocks(s); 888 #ifdef CONFIG_OMAP2_DSS_DSI 889 dsi_dump_clocks(s); 890 #endif 891 } 892 #endif 893 894 895 static const enum omap_display_type omap2plus_ports[] = { 896 OMAP_DISPLAY_TYPE_DPI, 897 }; 898 899 static const enum omap_display_type omap34xx_ports[] = { 900 OMAP_DISPLAY_TYPE_DPI, 901 OMAP_DISPLAY_TYPE_SDI, 902 }; 903 904 static const enum omap_display_type dra7xx_ports[] = { 905 OMAP_DISPLAY_TYPE_DPI, 906 OMAP_DISPLAY_TYPE_DPI, 907 OMAP_DISPLAY_TYPE_DPI, 908 }; 909 910 static const struct dss_features omap24xx_dss_feats = { 911 /* 912 * fck div max is really 16, but the divider range has gaps. The range 913 * from 1 to 6 has no gaps, so let's use that as a max. 914 */ 915 .fck_div_max = 6, 916 .dss_fck_multiplier = 2, 917 .parent_clk_name = "core_ck", 918 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 919 .ports = omap2plus_ports, 920 .num_ports = ARRAY_SIZE(omap2plus_ports), 921 }; 922 923 static const struct dss_features omap34xx_dss_feats = { 924 .fck_div_max = 16, 925 .dss_fck_multiplier = 2, 926 .parent_clk_name = "dpll4_ck", 927 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 928 .ports = omap34xx_ports, 929 .num_ports = ARRAY_SIZE(omap34xx_ports), 930 }; 931 932 static const struct dss_features omap3630_dss_feats = { 933 .fck_div_max = 32, 934 .dss_fck_multiplier = 1, 935 .parent_clk_name = "dpll4_ck", 936 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 937 .ports = omap2plus_ports, 938 .num_ports = ARRAY_SIZE(omap2plus_ports), 939 }; 940 941 static const struct dss_features omap44xx_dss_feats = { 942 .fck_div_max = 32, 943 .dss_fck_multiplier = 1, 944 .parent_clk_name = "dpll_per_x2_ck", 945 .dpi_select_source = &dss_dpi_select_source_omap4, 946 .ports = omap2plus_ports, 947 .num_ports = ARRAY_SIZE(omap2plus_ports), 948 .select_lcd_source = &dss_lcd_clk_mux_omap4, 949 }; 950 951 static const struct dss_features omap54xx_dss_feats = { 952 .fck_div_max = 64, 953 .dss_fck_multiplier = 1, 954 .parent_clk_name = "dpll_per_x2_ck", 955 .dpi_select_source = &dss_dpi_select_source_omap5, 956 .ports = omap2plus_ports, 957 .num_ports = ARRAY_SIZE(omap2plus_ports), 958 .select_lcd_source = &dss_lcd_clk_mux_omap5, 959 }; 960 961 static const struct dss_features am43xx_dss_feats = { 962 .fck_div_max = 0, 963 .dss_fck_multiplier = 0, 964 .parent_clk_name = NULL, 965 .dpi_select_source = &dss_dpi_select_source_omap2_omap3, 966 .ports = omap2plus_ports, 967 .num_ports = ARRAY_SIZE(omap2plus_ports), 968 }; 969 970 static const struct dss_features dra7xx_dss_feats = { 971 .fck_div_max = 64, 972 .dss_fck_multiplier = 1, 973 .parent_clk_name = "dpll_per_x2_ck", 974 .dpi_select_source = &dss_dpi_select_source_dra7xx, 975 .ports = dra7xx_ports, 976 .num_ports = ARRAY_SIZE(dra7xx_ports), 977 .select_lcd_source = &dss_lcd_clk_mux_dra7, 978 }; 979 980 static int dss_init_features(struct platform_device *pdev) 981 { 982 const struct dss_features *src; 983 struct dss_features *dst; 984 985 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); 986 if (!dst) { 987 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n"); 988 return -ENOMEM; 989 } 990 991 switch (omapdss_get_version()) { 992 case OMAPDSS_VER_OMAP24xx: 993 src = &omap24xx_dss_feats; 994 break; 995 996 case OMAPDSS_VER_OMAP34xx_ES1: 997 case OMAPDSS_VER_OMAP34xx_ES3: 998 case OMAPDSS_VER_AM35xx: 999 src = &omap34xx_dss_feats; 1000 break; 1001 1002 case OMAPDSS_VER_OMAP3630: 1003 src = &omap3630_dss_feats; 1004 break; 1005 1006 case OMAPDSS_VER_OMAP4430_ES1: 1007 case OMAPDSS_VER_OMAP4430_ES2: 1008 case OMAPDSS_VER_OMAP4: 1009 src = &omap44xx_dss_feats; 1010 break; 1011 1012 case OMAPDSS_VER_OMAP5: 1013 src = &omap54xx_dss_feats; 1014 break; 1015 1016 case OMAPDSS_VER_AM43xx: 1017 src = &am43xx_dss_feats; 1018 break; 1019 1020 case OMAPDSS_VER_DRA7xx: 1021 src = &dra7xx_dss_feats; 1022 break; 1023 1024 default: 1025 return -ENODEV; 1026 } 1027 1028 memcpy(dst, src, sizeof(*dst)); 1029 dss.feat = dst; 1030 1031 return 0; 1032 } 1033 1034 static int dss_init_ports(struct platform_device *pdev) 1035 { 1036 struct device_node *parent = pdev->dev.of_node; 1037 struct device_node *port; 1038 int r; 1039 1040 if (parent == NULL) 1041 return 0; 1042 1043 port = omapdss_of_get_next_port(parent, NULL); 1044 if (!port) 1045 return 0; 1046 1047 if (dss.feat->num_ports == 0) 1048 return 0; 1049 1050 do { 1051 enum omap_display_type port_type; 1052 u32 reg; 1053 1054 r = of_property_read_u32(port, "reg", ®); 1055 if (r) 1056 reg = 0; 1057 1058 if (reg >= dss.feat->num_ports) 1059 continue; 1060 1061 port_type = dss.feat->ports[reg]; 1062 1063 switch (port_type) { 1064 case OMAP_DISPLAY_TYPE_DPI: 1065 dpi_init_port(pdev, port); 1066 break; 1067 case OMAP_DISPLAY_TYPE_SDI: 1068 sdi_init_port(pdev, port); 1069 break; 1070 default: 1071 break; 1072 } 1073 } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); 1074 1075 return 0; 1076 } 1077 1078 static void dss_uninit_ports(struct platform_device *pdev) 1079 { 1080 struct device_node *parent = pdev->dev.of_node; 1081 struct device_node *port; 1082 1083 if (parent == NULL) 1084 return; 1085 1086 port = omapdss_of_get_next_port(parent, NULL); 1087 if (!port) 1088 return; 1089 1090 if (dss.feat->num_ports == 0) 1091 return; 1092 1093 do { 1094 enum omap_display_type port_type; 1095 u32 reg; 1096 int r; 1097 1098 r = of_property_read_u32(port, "reg", ®); 1099 if (r) 1100 reg = 0; 1101 1102 if (reg >= dss.feat->num_ports) 1103 continue; 1104 1105 port_type = dss.feat->ports[reg]; 1106 1107 switch (port_type) { 1108 case OMAP_DISPLAY_TYPE_DPI: 1109 dpi_uninit_port(port); 1110 break; 1111 case OMAP_DISPLAY_TYPE_SDI: 1112 sdi_uninit_port(port); 1113 break; 1114 default: 1115 break; 1116 } 1117 } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); 1118 } 1119 1120 static int dss_video_pll_probe(struct platform_device *pdev) 1121 { 1122 struct device_node *np = pdev->dev.of_node; 1123 struct regulator *pll_regulator; 1124 int r; 1125 1126 if (!np) 1127 return 0; 1128 1129 if (of_property_read_bool(np, "syscon-pll-ctrl")) { 1130 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, 1131 "syscon-pll-ctrl"); 1132 if (IS_ERR(dss.syscon_pll_ctrl)) { 1133 dev_err(&pdev->dev, 1134 "failed to get syscon-pll-ctrl regmap\n"); 1135 return PTR_ERR(dss.syscon_pll_ctrl); 1136 } 1137 1138 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, 1139 &dss.syscon_pll_ctrl_offset)) { 1140 dev_err(&pdev->dev, 1141 "failed to get syscon-pll-ctrl offset\n"); 1142 return -EINVAL; 1143 } 1144 } 1145 1146 pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); 1147 if (IS_ERR(pll_regulator)) { 1148 r = PTR_ERR(pll_regulator); 1149 1150 switch (r) { 1151 case -ENOENT: 1152 pll_regulator = NULL; 1153 break; 1154 1155 case -EPROBE_DEFER: 1156 return -EPROBE_DEFER; 1157 1158 default: 1159 DSSERR("can't get DPLL VDDA regulator\n"); 1160 return r; 1161 } 1162 } 1163 1164 if (of_property_match_string(np, "reg-names", "pll1") >= 0) { 1165 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); 1166 if (IS_ERR(dss.video1_pll)) 1167 return PTR_ERR(dss.video1_pll); 1168 } 1169 1170 if (of_property_match_string(np, "reg-names", "pll2") >= 0) { 1171 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); 1172 if (IS_ERR(dss.video2_pll)) { 1173 dss_video_pll_uninit(dss.video1_pll); 1174 return PTR_ERR(dss.video2_pll); 1175 } 1176 } 1177 1178 return 0; 1179 } 1180 1181 /* DSS HW IP initialisation */ 1182 static int dss_bind(struct device *dev) 1183 { 1184 struct platform_device *pdev = to_platform_device(dev); 1185 struct resource *dss_mem; 1186 u32 rev; 1187 int r; 1188 1189 dss.pdev = pdev; 1190 1191 r = dss_init_features(dss.pdev); 1192 if (r) 1193 return r; 1194 1195 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); 1196 if (!dss_mem) { 1197 DSSERR("can't get IORESOURCE_MEM DSS\n"); 1198 return -EINVAL; 1199 } 1200 1201 dss.base = devm_ioremap(&pdev->dev, dss_mem->start, 1202 resource_size(dss_mem)); 1203 if (!dss.base) { 1204 DSSERR("can't ioremap DSS\n"); 1205 return -ENOMEM; 1206 } 1207 1208 r = dss_get_clocks(); 1209 if (r) 1210 return r; 1211 1212 r = dss_setup_default_clock(); 1213 if (r) 1214 goto err_setup_clocks; 1215 1216 r = dss_video_pll_probe(pdev); 1217 if (r) 1218 goto err_pll_init; 1219 1220 r = dss_init_ports(pdev); 1221 if (r) 1222 goto err_init_ports; 1223 1224 pm_runtime_enable(&pdev->dev); 1225 1226 r = dss_runtime_get(); 1227 if (r) 1228 goto err_runtime_get; 1229 1230 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 1231 1232 /* Select DPLL */ 1233 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); 1234 1235 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); 1236 1237 #ifdef CONFIG_OMAP2_DSS_VENC 1238 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ 1239 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ 1240 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ 1241 #endif 1242 dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK; 1243 dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK; 1244 dss.dispc_clk_source = DSS_CLK_SRC_FCK; 1245 dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; 1246 dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; 1247 1248 rev = dss_read_reg(DSS_REVISION); 1249 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 1250 1251 dss_runtime_put(); 1252 1253 r = component_bind_all(&pdev->dev, NULL); 1254 if (r) 1255 goto err_component; 1256 1257 dss_debugfs_create_file("dss", dss_dump_regs); 1258 1259 pm_set_vt_switch(0); 1260 1261 omapdss_gather_components(dev); 1262 omapdss_set_is_initialized(true); 1263 1264 return 0; 1265 1266 err_component: 1267 err_runtime_get: 1268 pm_runtime_disable(&pdev->dev); 1269 dss_uninit_ports(pdev); 1270 err_init_ports: 1271 if (dss.video1_pll) 1272 dss_video_pll_uninit(dss.video1_pll); 1273 1274 if (dss.video2_pll) 1275 dss_video_pll_uninit(dss.video2_pll); 1276 err_pll_init: 1277 err_setup_clocks: 1278 dss_put_clocks(); 1279 return r; 1280 } 1281 1282 static void dss_unbind(struct device *dev) 1283 { 1284 struct platform_device *pdev = to_platform_device(dev); 1285 1286 omapdss_set_is_initialized(false); 1287 1288 component_unbind_all(&pdev->dev, NULL); 1289 1290 if (dss.video1_pll) 1291 dss_video_pll_uninit(dss.video1_pll); 1292 1293 if (dss.video2_pll) 1294 dss_video_pll_uninit(dss.video2_pll); 1295 1296 dss_uninit_ports(pdev); 1297 1298 pm_runtime_disable(&pdev->dev); 1299 1300 dss_put_clocks(); 1301 } 1302 1303 static const struct component_master_ops dss_component_ops = { 1304 .bind = dss_bind, 1305 .unbind = dss_unbind, 1306 }; 1307 1308 static int dss_component_compare(struct device *dev, void *data) 1309 { 1310 struct device *child = data; 1311 return dev == child; 1312 } 1313 1314 static int dss_add_child_component(struct device *dev, void *data) 1315 { 1316 struct component_match **match = data; 1317 1318 /* 1319 * HACK 1320 * We don't have a working driver for rfbi, so skip it here always. 1321 * Otherwise dss will never get probed successfully, as it will wait 1322 * for rfbi to get probed. 1323 */ 1324 if (strstr(dev_name(dev), "rfbi")) 1325 return 0; 1326 1327 component_match_add(dev->parent, match, dss_component_compare, dev); 1328 1329 return 0; 1330 } 1331 1332 static int dss_probe(struct platform_device *pdev) 1333 { 1334 struct component_match *match = NULL; 1335 int r; 1336 1337 /* add all the child devices as components */ 1338 device_for_each_child(&pdev->dev, &match, dss_add_child_component); 1339 1340 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); 1341 if (r) 1342 return r; 1343 1344 return 0; 1345 } 1346 1347 static int dss_remove(struct platform_device *pdev) 1348 { 1349 component_master_del(&pdev->dev, &dss_component_ops); 1350 return 0; 1351 } 1352 1353 static int dss_runtime_suspend(struct device *dev) 1354 { 1355 dss_save_context(); 1356 dss_set_min_bus_tput(dev, 0); 1357 1358 pinctrl_pm_select_sleep_state(dev); 1359 1360 return 0; 1361 } 1362 1363 static int dss_runtime_resume(struct device *dev) 1364 { 1365 int r; 1366 1367 pinctrl_pm_select_default_state(dev); 1368 1369 /* 1370 * Set an arbitrarily high tput request to ensure OPP100. 1371 * What we should really do is to make a request to stay in OPP100, 1372 * without any tput requirements, but that is not currently possible 1373 * via the PM layer. 1374 */ 1375 1376 r = dss_set_min_bus_tput(dev, 1000000000); 1377 if (r) 1378 return r; 1379 1380 dss_restore_context(); 1381 return 0; 1382 } 1383 1384 static const struct dev_pm_ops dss_pm_ops = { 1385 .runtime_suspend = dss_runtime_suspend, 1386 .runtime_resume = dss_runtime_resume, 1387 }; 1388 1389 static const struct of_device_id dss_of_match[] = { 1390 { .compatible = "ti,omap2-dss", }, 1391 { .compatible = "ti,omap3-dss", }, 1392 { .compatible = "ti,omap4-dss", }, 1393 { .compatible = "ti,omap5-dss", }, 1394 { .compatible = "ti,dra7-dss", }, 1395 {}, 1396 }; 1397 1398 MODULE_DEVICE_TABLE(of, dss_of_match); 1399 1400 static struct platform_driver omap_dsshw_driver = { 1401 .probe = dss_probe, 1402 .remove = dss_remove, 1403 .driver = { 1404 .name = "omapdss_dss", 1405 .pm = &dss_pm_ops, 1406 .of_match_table = dss_of_match, 1407 .suppress_bind_attrs = true, 1408 }, 1409 }; 1410 1411 int __init dss_init_platform_driver(void) 1412 { 1413 return platform_driver_register(&omap_dsshw_driver); 1414 } 1415 1416 void dss_uninit_platform_driver(void) 1417 { 1418 platform_driver_unregister(&omap_dsshw_driver); 1419 } 1420