1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #define DSS_SUBSYS_NAME "DSI" 8 9 #include <linux/kernel.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/regmap.h> 12 #include <linux/io.h> 13 #include <linux/clk.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/mutex.h> 21 #include <linux/module.h> 22 #include <linux/semaphore.h> 23 #include <linux/seq_file.h> 24 #include <linux/platform_device.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/wait.h> 27 #include <linux/workqueue.h> 28 #include <linux/sched.h> 29 #include <linux/slab.h> 30 #include <linux/debugfs.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/of_graph.h> 34 #include <linux/of_platform.h> 35 #include <linux/component.h> 36 #include <linux/sys_soc.h> 37 38 #include <drm/drm_atomic_state_helper.h> 39 #include <drm/drm_bridge.h> 40 #include <drm/drm_mipi_dsi.h> 41 #include <drm/drm_panel.h> 42 #include <video/mipi_display.h> 43 44 #include "omapdss.h" 45 #include "dss.h" 46 47 #define DSI_CATCH_MISSING_TE 48 49 #include "dsi.h" 50 51 #define REG_GET(dsi, idx, start, end) \ 52 FLD_GET(dsi_read_reg(dsi, idx), start, end) 53 54 #define REG_FLD_MOD(dsi, idx, val, start, end) \ 55 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end)) 56 57 static int dsi_init_dispc(struct dsi_data *dsi); 58 static void dsi_uninit_dispc(struct dsi_data *dsi); 59 60 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel); 61 62 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, 63 const struct mipi_dsi_msg *msg); 64 65 #ifdef DSI_PERF_MEASURE 66 static bool dsi_perf; 67 module_param(dsi_perf, bool, 0644); 68 #endif 69 70 /* Note: for some reason video mode seems to work only if VC_VIDEO is 0 */ 71 #define VC_VIDEO 0 72 #define VC_CMD 1 73 74 #define drm_bridge_to_dsi(bridge) \ 75 container_of(bridge, struct dsi_data, bridge) 76 77 static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev) 78 { 79 return dev_get_drvdata(dssdev->dev); 80 } 81 82 static inline struct dsi_data *host_to_omap(struct mipi_dsi_host *host) 83 { 84 return container_of(host, struct dsi_data, host); 85 } 86 87 static inline void dsi_write_reg(struct dsi_data *dsi, 88 const struct dsi_reg idx, u32 val) 89 { 90 void __iomem *base; 91 92 switch(idx.module) { 93 case DSI_PROTO: base = dsi->proto_base; break; 94 case DSI_PHY: base = dsi->phy_base; break; 95 case DSI_PLL: base = dsi->pll_base; break; 96 default: return; 97 } 98 99 __raw_writel(val, base + idx.idx); 100 } 101 102 static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx) 103 { 104 void __iomem *base; 105 106 switch(idx.module) { 107 case DSI_PROTO: base = dsi->proto_base; break; 108 case DSI_PHY: base = dsi->phy_base; break; 109 case DSI_PLL: base = dsi->pll_base; break; 110 default: return 0; 111 } 112 113 return __raw_readl(base + idx.idx); 114 } 115 116 static void dsi_bus_lock(struct dsi_data *dsi) 117 { 118 down(&dsi->bus_lock); 119 } 120 121 static void dsi_bus_unlock(struct dsi_data *dsi) 122 { 123 up(&dsi->bus_lock); 124 } 125 126 static bool dsi_bus_is_locked(struct dsi_data *dsi) 127 { 128 return dsi->bus_lock.count == 0; 129 } 130 131 static void dsi_completion_handler(void *data, u32 mask) 132 { 133 complete((struct completion *)data); 134 } 135 136 static inline bool wait_for_bit_change(struct dsi_data *dsi, 137 const struct dsi_reg idx, 138 int bitnum, int value) 139 { 140 unsigned long timeout; 141 ktime_t wait; 142 int t; 143 144 /* first busyloop to see if the bit changes right away */ 145 t = 100; 146 while (t-- > 0) { 147 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 148 return true; 149 } 150 151 /* then loop for 500ms, sleeping for 1ms in between */ 152 timeout = jiffies + msecs_to_jiffies(500); 153 while (time_before(jiffies, timeout)) { 154 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 155 return true; 156 157 wait = ns_to_ktime(1000 * 1000); 158 set_current_state(TASK_UNINTERRUPTIBLE); 159 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 160 } 161 162 return false; 163 } 164 165 #ifdef DSI_PERF_MEASURE 166 static void dsi_perf_mark_setup(struct dsi_data *dsi) 167 { 168 dsi->perf_setup_time = ktime_get(); 169 } 170 171 static void dsi_perf_mark_start(struct dsi_data *dsi) 172 { 173 dsi->perf_start_time = ktime_get(); 174 } 175 176 static void dsi_perf_show(struct dsi_data *dsi, const char *name) 177 { 178 ktime_t t, setup_time, trans_time; 179 u32 total_bytes; 180 u32 setup_us, trans_us, total_us; 181 182 if (!dsi_perf) 183 return; 184 185 t = ktime_get(); 186 187 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 188 setup_us = (u32)ktime_to_us(setup_time); 189 if (setup_us == 0) 190 setup_us = 1; 191 192 trans_time = ktime_sub(t, dsi->perf_start_time); 193 trans_us = (u32)ktime_to_us(trans_time); 194 if (trans_us == 0) 195 trans_us = 1; 196 197 total_us = setup_us + trans_us; 198 199 total_bytes = dsi->update_bytes; 200 201 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n", 202 name, 203 setup_us, 204 trans_us, 205 total_us, 206 1000 * 1000 / total_us, 207 total_bytes, 208 total_bytes * 1000 / total_us); 209 } 210 #else 211 static inline void dsi_perf_mark_setup(struct dsi_data *dsi) 212 { 213 } 214 215 static inline void dsi_perf_mark_start(struct dsi_data *dsi) 216 { 217 } 218 219 static inline void dsi_perf_show(struct dsi_data *dsi, const char *name) 220 { 221 } 222 #endif 223 224 static int verbose_irq; 225 226 static void print_irq_status(u32 status) 227 { 228 if (status == 0) 229 return; 230 231 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 232 return; 233 234 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 235 236 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 237 status, 238 verbose_irq ? PIS(VC0) : "", 239 verbose_irq ? PIS(VC1) : "", 240 verbose_irq ? PIS(VC2) : "", 241 verbose_irq ? PIS(VC3) : "", 242 PIS(WAKEUP), 243 PIS(RESYNC), 244 PIS(PLL_LOCK), 245 PIS(PLL_UNLOCK), 246 PIS(PLL_RECALL), 247 PIS(COMPLEXIO_ERR), 248 PIS(HS_TX_TIMEOUT), 249 PIS(LP_RX_TIMEOUT), 250 PIS(TE_TRIGGER), 251 PIS(ACK_TRIGGER), 252 PIS(SYNC_LOST), 253 PIS(LDO_POWER_GOOD), 254 PIS(TA_TIMEOUT)); 255 #undef PIS 256 } 257 258 static void print_irq_status_vc(int vc, u32 status) 259 { 260 if (status == 0) 261 return; 262 263 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 264 return; 265 266 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 267 268 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 269 vc, 270 status, 271 PIS(CS), 272 PIS(ECC_CORR), 273 PIS(ECC_NO_CORR), 274 verbose_irq ? PIS(PACKET_SENT) : "", 275 PIS(BTA), 276 PIS(FIFO_TX_OVF), 277 PIS(FIFO_RX_OVF), 278 PIS(FIFO_TX_UDF), 279 PIS(PP_BUSY_CHANGE)); 280 #undef PIS 281 } 282 283 static void print_irq_status_cio(u32 status) 284 { 285 if (status == 0) 286 return; 287 288 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 289 290 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 291 status, 292 PIS(ERRSYNCESC1), 293 PIS(ERRSYNCESC2), 294 PIS(ERRSYNCESC3), 295 PIS(ERRESC1), 296 PIS(ERRESC2), 297 PIS(ERRESC3), 298 PIS(ERRCONTROL1), 299 PIS(ERRCONTROL2), 300 PIS(ERRCONTROL3), 301 PIS(STATEULPS1), 302 PIS(STATEULPS2), 303 PIS(STATEULPS3), 304 PIS(ERRCONTENTIONLP0_1), 305 PIS(ERRCONTENTIONLP1_1), 306 PIS(ERRCONTENTIONLP0_2), 307 PIS(ERRCONTENTIONLP1_2), 308 PIS(ERRCONTENTIONLP0_3), 309 PIS(ERRCONTENTIONLP1_3), 310 PIS(ULPSACTIVENOT_ALL0), 311 PIS(ULPSACTIVENOT_ALL1)); 312 #undef PIS 313 } 314 315 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 316 static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus, 317 u32 *vcstatus, u32 ciostatus) 318 { 319 int i; 320 321 spin_lock(&dsi->irq_stats_lock); 322 323 dsi->irq_stats.irq_count++; 324 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 325 326 for (i = 0; i < 4; ++i) 327 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 328 329 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 330 331 spin_unlock(&dsi->irq_stats_lock); 332 } 333 #else 334 #define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus) 335 #endif 336 337 static int debug_irq; 338 339 static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus, 340 u32 *vcstatus, u32 ciostatus) 341 { 342 int i; 343 344 if (irqstatus & DSI_IRQ_ERROR_MASK) { 345 DSSERR("DSI error, irqstatus %x\n", irqstatus); 346 print_irq_status(irqstatus); 347 spin_lock(&dsi->errors_lock); 348 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 349 spin_unlock(&dsi->errors_lock); 350 } else if (debug_irq) { 351 print_irq_status(irqstatus); 352 } 353 354 for (i = 0; i < 4; ++i) { 355 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 356 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 357 i, vcstatus[i]); 358 print_irq_status_vc(i, vcstatus[i]); 359 } else if (debug_irq) { 360 print_irq_status_vc(i, vcstatus[i]); 361 } 362 } 363 364 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 365 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 366 print_irq_status_cio(ciostatus); 367 } else if (debug_irq) { 368 print_irq_status_cio(ciostatus); 369 } 370 } 371 372 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 373 unsigned int isr_array_size, u32 irqstatus) 374 { 375 struct dsi_isr_data *isr_data; 376 int i; 377 378 for (i = 0; i < isr_array_size; i++) { 379 isr_data = &isr_array[i]; 380 if (isr_data->isr && isr_data->mask & irqstatus) 381 isr_data->isr(isr_data->arg, irqstatus); 382 } 383 } 384 385 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 386 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 387 { 388 int i; 389 390 dsi_call_isrs(isr_tables->isr_table, 391 ARRAY_SIZE(isr_tables->isr_table), 392 irqstatus); 393 394 for (i = 0; i < 4; ++i) { 395 if (vcstatus[i] == 0) 396 continue; 397 dsi_call_isrs(isr_tables->isr_table_vc[i], 398 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 399 vcstatus[i]); 400 } 401 402 if (ciostatus != 0) 403 dsi_call_isrs(isr_tables->isr_table_cio, 404 ARRAY_SIZE(isr_tables->isr_table_cio), 405 ciostatus); 406 } 407 408 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 409 { 410 struct dsi_data *dsi = arg; 411 u32 irqstatus, vcstatus[4], ciostatus; 412 int i; 413 414 if (!dsi->is_enabled) 415 return IRQ_NONE; 416 417 spin_lock(&dsi->irq_lock); 418 419 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS); 420 421 /* IRQ is not for us */ 422 if (!irqstatus) { 423 spin_unlock(&dsi->irq_lock); 424 return IRQ_NONE; 425 } 426 427 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 428 /* flush posted write */ 429 dsi_read_reg(dsi, DSI_IRQSTATUS); 430 431 for (i = 0; i < 4; ++i) { 432 if ((irqstatus & (1 << i)) == 0) { 433 vcstatus[i] = 0; 434 continue; 435 } 436 437 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 438 439 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]); 440 /* flush posted write */ 441 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 442 } 443 444 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 445 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 446 447 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 448 /* flush posted write */ 449 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 450 } else { 451 ciostatus = 0; 452 } 453 454 #ifdef DSI_CATCH_MISSING_TE 455 if (irqstatus & DSI_IRQ_TE_TRIGGER) 456 timer_delete(&dsi->te_timer); 457 #endif 458 459 /* make a copy and unlock, so that isrs can unregister 460 * themselves */ 461 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 462 sizeof(dsi->isr_tables)); 463 464 spin_unlock(&dsi->irq_lock); 465 466 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 467 468 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus); 469 470 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus); 471 472 return IRQ_HANDLED; 473 } 474 475 /* dsi->irq_lock has to be locked by the caller */ 476 static void _omap_dsi_configure_irqs(struct dsi_data *dsi, 477 struct dsi_isr_data *isr_array, 478 unsigned int isr_array_size, 479 u32 default_mask, 480 const struct dsi_reg enable_reg, 481 const struct dsi_reg status_reg) 482 { 483 struct dsi_isr_data *isr_data; 484 u32 mask; 485 u32 old_mask; 486 int i; 487 488 mask = default_mask; 489 490 for (i = 0; i < isr_array_size; i++) { 491 isr_data = &isr_array[i]; 492 493 if (isr_data->isr == NULL) 494 continue; 495 496 mask |= isr_data->mask; 497 } 498 499 old_mask = dsi_read_reg(dsi, enable_reg); 500 /* clear the irqstatus for newly enabled irqs */ 501 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask); 502 dsi_write_reg(dsi, enable_reg, mask); 503 504 /* flush posted writes */ 505 dsi_read_reg(dsi, enable_reg); 506 dsi_read_reg(dsi, status_reg); 507 } 508 509 /* dsi->irq_lock has to be locked by the caller */ 510 static void _omap_dsi_set_irqs(struct dsi_data *dsi) 511 { 512 u32 mask = DSI_IRQ_ERROR_MASK; 513 #ifdef DSI_CATCH_MISSING_TE 514 mask |= DSI_IRQ_TE_TRIGGER; 515 #endif 516 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table, 517 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 518 DSI_IRQENABLE, DSI_IRQSTATUS); 519 } 520 521 /* dsi->irq_lock has to be locked by the caller */ 522 static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc) 523 { 524 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc], 525 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 526 DSI_VC_IRQ_ERROR_MASK, 527 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 528 } 529 530 /* dsi->irq_lock has to be locked by the caller */ 531 static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi) 532 { 533 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio, 534 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 535 DSI_CIO_IRQ_ERROR_MASK, 536 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 537 } 538 539 static void _dsi_initialize_irq(struct dsi_data *dsi) 540 { 541 unsigned long flags; 542 int vc; 543 544 spin_lock_irqsave(&dsi->irq_lock, flags); 545 546 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 547 548 _omap_dsi_set_irqs(dsi); 549 for (vc = 0; vc < 4; ++vc) 550 _omap_dsi_set_irqs_vc(dsi, vc); 551 _omap_dsi_set_irqs_cio(dsi); 552 553 spin_unlock_irqrestore(&dsi->irq_lock, flags); 554 } 555 556 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 557 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 558 { 559 struct dsi_isr_data *isr_data; 560 int free_idx; 561 int i; 562 563 BUG_ON(isr == NULL); 564 565 /* check for duplicate entry and find a free slot */ 566 free_idx = -1; 567 for (i = 0; i < isr_array_size; i++) { 568 isr_data = &isr_array[i]; 569 570 if (isr_data->isr == isr && isr_data->arg == arg && 571 isr_data->mask == mask) { 572 return -EINVAL; 573 } 574 575 if (isr_data->isr == NULL && free_idx == -1) 576 free_idx = i; 577 } 578 579 if (free_idx == -1) 580 return -EBUSY; 581 582 isr_data = &isr_array[free_idx]; 583 isr_data->isr = isr; 584 isr_data->arg = arg; 585 isr_data->mask = mask; 586 587 return 0; 588 } 589 590 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 591 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 592 { 593 struct dsi_isr_data *isr_data; 594 int i; 595 596 for (i = 0; i < isr_array_size; i++) { 597 isr_data = &isr_array[i]; 598 if (isr_data->isr != isr || isr_data->arg != arg || 599 isr_data->mask != mask) 600 continue; 601 602 isr_data->isr = NULL; 603 isr_data->arg = NULL; 604 isr_data->mask = 0; 605 606 return 0; 607 } 608 609 return -EINVAL; 610 } 611 612 static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 613 void *arg, u32 mask) 614 { 615 unsigned long flags; 616 int r; 617 618 spin_lock_irqsave(&dsi->irq_lock, flags); 619 620 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 621 ARRAY_SIZE(dsi->isr_tables.isr_table)); 622 623 if (r == 0) 624 _omap_dsi_set_irqs(dsi); 625 626 spin_unlock_irqrestore(&dsi->irq_lock, flags); 627 628 return r; 629 } 630 631 static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 632 void *arg, u32 mask) 633 { 634 unsigned long flags; 635 int r; 636 637 spin_lock_irqsave(&dsi->irq_lock, flags); 638 639 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 640 ARRAY_SIZE(dsi->isr_tables.isr_table)); 641 642 if (r == 0) 643 _omap_dsi_set_irqs(dsi); 644 645 spin_unlock_irqrestore(&dsi->irq_lock, flags); 646 647 return r; 648 } 649 650 static int dsi_register_isr_vc(struct dsi_data *dsi, int vc, 651 omap_dsi_isr_t isr, void *arg, u32 mask) 652 { 653 unsigned long flags; 654 int r; 655 656 spin_lock_irqsave(&dsi->irq_lock, flags); 657 658 r = _dsi_register_isr(isr, arg, mask, 659 dsi->isr_tables.isr_table_vc[vc], 660 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); 661 662 if (r == 0) 663 _omap_dsi_set_irqs_vc(dsi, vc); 664 665 spin_unlock_irqrestore(&dsi->irq_lock, flags); 666 667 return r; 668 } 669 670 static int dsi_unregister_isr_vc(struct dsi_data *dsi, int vc, 671 omap_dsi_isr_t isr, void *arg, u32 mask) 672 { 673 unsigned long flags; 674 int r; 675 676 spin_lock_irqsave(&dsi->irq_lock, flags); 677 678 r = _dsi_unregister_isr(isr, arg, mask, 679 dsi->isr_tables.isr_table_vc[vc], 680 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); 681 682 if (r == 0) 683 _omap_dsi_set_irqs_vc(dsi, vc); 684 685 spin_unlock_irqrestore(&dsi->irq_lock, flags); 686 687 return r; 688 } 689 690 static u32 dsi_get_errors(struct dsi_data *dsi) 691 { 692 unsigned long flags; 693 u32 e; 694 695 spin_lock_irqsave(&dsi->errors_lock, flags); 696 e = dsi->errors; 697 dsi->errors = 0; 698 spin_unlock_irqrestore(&dsi->errors_lock, flags); 699 return e; 700 } 701 702 static int dsi_runtime_get(struct dsi_data *dsi) 703 { 704 int r; 705 706 DSSDBG("dsi_runtime_get\n"); 707 708 r = pm_runtime_get_sync(dsi->dev); 709 if (WARN_ON(r < 0)) { 710 pm_runtime_put_noidle(dsi->dev); 711 return r; 712 } 713 return 0; 714 } 715 716 static void dsi_runtime_put(struct dsi_data *dsi) 717 { 718 int r; 719 720 DSSDBG("dsi_runtime_put\n"); 721 722 r = pm_runtime_put_sync(dsi->dev); 723 WARN_ON(r < 0 && r != -ENOSYS); 724 } 725 726 static void _dsi_print_reset_status(struct dsi_data *dsi) 727 { 728 int b0, b1, b2; 729 730 /* A dummy read using the SCP interface to any DSIPHY register is 731 * required after DSIPHY reset to complete the reset of the DSI complex 732 * I/O. */ 733 dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 734 735 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { 736 b0 = 28; 737 b1 = 27; 738 b2 = 26; 739 } else { 740 b0 = 24; 741 b1 = 25; 742 b2 = 26; 743 } 744 745 #define DSI_FLD_GET(fld, start, end)\ 746 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end) 747 748 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 749 DSI_FLD_GET(PLL_STATUS, 0, 0), 750 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 751 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 752 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 753 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 754 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 755 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 756 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 757 758 #undef DSI_FLD_GET 759 } 760 761 static inline int dsi_if_enable(struct dsi_data *dsi, bool enable) 762 { 763 DSSDBG("dsi_if_enable(%d)\n", enable); 764 765 enable = enable ? 1 : 0; 766 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ 767 768 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) { 769 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 770 return -EIO; 771 } 772 773 return 0; 774 } 775 776 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi) 777 { 778 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 779 } 780 781 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi) 782 { 783 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 784 } 785 786 static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi) 787 { 788 return dsi->pll.cinfo.clkdco / 16; 789 } 790 791 static unsigned long dsi_fclk_rate(struct dsi_data *dsi) 792 { 793 unsigned long r; 794 enum dss_clk_source source; 795 796 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id); 797 if (source == DSS_CLK_SRC_FCK) { 798 /* DSI FCLK source is DSS_CLK_FCK */ 799 r = clk_get_rate(dsi->dss_clk); 800 } else { 801 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 802 r = dsi_get_pll_hsdiv_dsi_rate(dsi); 803 } 804 805 return r; 806 } 807 808 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 809 unsigned long lp_clk_min, unsigned long lp_clk_max, 810 struct dsi_lp_clock_info *lp_cinfo) 811 { 812 unsigned int lp_clk_div; 813 unsigned long lp_clk; 814 815 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 816 lp_clk = dsi_fclk / 2 / lp_clk_div; 817 818 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 819 return -EINVAL; 820 821 lp_cinfo->lp_clk_div = lp_clk_div; 822 lp_cinfo->lp_clk = lp_clk; 823 824 return 0; 825 } 826 827 static int dsi_set_lp_clk_divisor(struct dsi_data *dsi) 828 { 829 unsigned long dsi_fclk; 830 unsigned int lp_clk_div; 831 unsigned long lp_clk; 832 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv; 833 834 835 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 836 837 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 838 return -EINVAL; 839 840 dsi_fclk = dsi_fclk_rate(dsi); 841 842 lp_clk = dsi_fclk / 2 / lp_clk_div; 843 844 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 845 dsi->current_lp_cinfo.lp_clk = lp_clk; 846 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 847 848 /* LP_CLK_DIVISOR */ 849 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); 850 851 /* LP_RX_SYNCHRO_ENABLE */ 852 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 853 854 return 0; 855 } 856 857 static void dsi_enable_scp_clk(struct dsi_data *dsi) 858 { 859 if (dsi->scp_clk_refcount++ == 0) 860 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 861 } 862 863 static void dsi_disable_scp_clk(struct dsi_data *dsi) 864 { 865 WARN_ON(dsi->scp_clk_refcount == 0); 866 if (--dsi->scp_clk_refcount == 0) 867 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 868 } 869 870 enum dsi_pll_power_state { 871 DSI_PLL_POWER_OFF = 0x0, 872 DSI_PLL_POWER_ON_HSCLK = 0x1, 873 DSI_PLL_POWER_ON_ALL = 0x2, 874 DSI_PLL_POWER_ON_DIV = 0x3, 875 }; 876 877 static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state) 878 { 879 int t = 0; 880 881 /* DSI-PLL power command 0x3 is not working */ 882 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && 883 state == DSI_PLL_POWER_ON_DIV) 884 state = DSI_PLL_POWER_ON_ALL; 885 886 /* PLL_PWR_CMD */ 887 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); 888 889 /* PLL_PWR_STATUS */ 890 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) { 891 if (++t > 1000) { 892 DSSERR("Failed to set DSI PLL power mode to %d\n", 893 state); 894 return -ENODEV; 895 } 896 udelay(1); 897 } 898 899 return 0; 900 } 901 902 903 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi, 904 struct dss_pll_clock_info *cinfo) 905 { 906 unsigned long max_dsi_fck; 907 908 max_dsi_fck = dsi->data->max_fck_freq; 909 910 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 911 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 912 } 913 914 static int dsi_pll_enable(struct dss_pll *pll) 915 { 916 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 917 int r = 0; 918 919 DSSDBG("PLL init\n"); 920 921 r = dsi_runtime_get(dsi); 922 if (r) 923 return r; 924 925 /* 926 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 927 */ 928 dsi_enable_scp_clk(dsi); 929 930 r = regulator_enable(dsi->vdds_dsi_reg); 931 if (r) 932 goto err0; 933 934 /* XXX PLL does not come out of reset without this... */ 935 dispc_pck_free_enable(dsi->dss->dispc, 1); 936 937 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) { 938 DSSERR("PLL not coming out of reset.\n"); 939 r = -ENODEV; 940 dispc_pck_free_enable(dsi->dss->dispc, 0); 941 goto err1; 942 } 943 944 /* XXX ... but if left on, we get problems when planes do not 945 * fill the whole display. No idea about this */ 946 dispc_pck_free_enable(dsi->dss->dispc, 0); 947 948 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL); 949 950 if (r) 951 goto err1; 952 953 DSSDBG("PLL init done\n"); 954 955 return 0; 956 err1: 957 regulator_disable(dsi->vdds_dsi_reg); 958 err0: 959 dsi_disable_scp_clk(dsi); 960 dsi_runtime_put(dsi); 961 return r; 962 } 963 964 static void dsi_pll_disable(struct dss_pll *pll) 965 { 966 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 967 968 dsi_pll_power(dsi, DSI_PLL_POWER_OFF); 969 970 regulator_disable(dsi->vdds_dsi_reg); 971 972 dsi_disable_scp_clk(dsi); 973 dsi_runtime_put(dsi); 974 975 DSSDBG("PLL disable done\n"); 976 } 977 978 static int dsi_dump_dsi_clocks(struct seq_file *s, void *p) 979 { 980 struct dsi_data *dsi = s->private; 981 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 982 enum dss_clk_source dispc_clk_src, dsi_clk_src; 983 int dsi_module = dsi->module_id; 984 struct dss_pll *pll = &dsi->pll; 985 986 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss); 987 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module); 988 989 if (dsi_runtime_get(dsi)) 990 return 0; 991 992 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 993 994 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 995 996 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 997 998 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 999 cinfo->clkdco, cinfo->m); 1000 1001 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1002 dss_get_clk_source_name(dsi_module == 0 ? 1003 DSS_CLK_SRC_PLL1_1 : 1004 DSS_CLK_SRC_PLL2_1), 1005 cinfo->clkout[HSDIV_DISPC], 1006 cinfo->mX[HSDIV_DISPC], 1007 dispc_clk_src == DSS_CLK_SRC_FCK ? 1008 "off" : "on"); 1009 1010 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1011 dss_get_clk_source_name(dsi_module == 0 ? 1012 DSS_CLK_SRC_PLL1_2 : 1013 DSS_CLK_SRC_PLL2_2), 1014 cinfo->clkout[HSDIV_DSI], 1015 cinfo->mX[HSDIV_DSI], 1016 dsi_clk_src == DSS_CLK_SRC_FCK ? 1017 "off" : "on"); 1018 1019 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1020 1021 seq_printf(s, "dsi fclk source = %s\n", 1022 dss_get_clk_source_name(dsi_clk_src)); 1023 1024 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi)); 1025 1026 seq_printf(s, "DDR_CLK\t\t%lu\n", 1027 cinfo->clkdco / 4); 1028 1029 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi)); 1030 1031 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1032 1033 dsi_runtime_put(dsi); 1034 1035 return 0; 1036 } 1037 1038 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 1039 static int dsi_dump_dsi_irqs(struct seq_file *s, void *p) 1040 { 1041 struct dsi_data *dsi = s->private; 1042 unsigned long flags; 1043 struct dsi_irq_stats *stats; 1044 1045 stats = kmalloc_obj(*stats); 1046 if (!stats) 1047 return -ENOMEM; 1048 1049 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1050 1051 *stats = dsi->irq_stats; 1052 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1053 dsi->irq_stats.last_reset = jiffies; 1054 1055 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1056 1057 seq_printf(s, "period %u ms\n", 1058 jiffies_to_msecs(jiffies - stats->last_reset)); 1059 1060 seq_printf(s, "irqs %d\n", stats->irq_count); 1061 #define PIS(x) \ 1062 seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1063 1064 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1065 PIS(VC0); 1066 PIS(VC1); 1067 PIS(VC2); 1068 PIS(VC3); 1069 PIS(WAKEUP); 1070 PIS(RESYNC); 1071 PIS(PLL_LOCK); 1072 PIS(PLL_UNLOCK); 1073 PIS(PLL_RECALL); 1074 PIS(COMPLEXIO_ERR); 1075 PIS(HS_TX_TIMEOUT); 1076 PIS(LP_RX_TIMEOUT); 1077 PIS(TE_TRIGGER); 1078 PIS(ACK_TRIGGER); 1079 PIS(SYNC_LOST); 1080 PIS(LDO_POWER_GOOD); 1081 PIS(TA_TIMEOUT); 1082 #undef PIS 1083 1084 #define PIS(x) \ 1085 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1086 stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1087 stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1088 stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1089 stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1090 1091 seq_printf(s, "-- VC interrupts --\n"); 1092 PIS(CS); 1093 PIS(ECC_CORR); 1094 PIS(PACKET_SENT); 1095 PIS(FIFO_TX_OVF); 1096 PIS(FIFO_RX_OVF); 1097 PIS(BTA); 1098 PIS(ECC_NO_CORR); 1099 PIS(FIFO_TX_UDF); 1100 PIS(PP_BUSY_CHANGE); 1101 #undef PIS 1102 1103 #define PIS(x) \ 1104 seq_printf(s, "%-20s %10d\n", #x, \ 1105 stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1106 1107 seq_printf(s, "-- CIO interrupts --\n"); 1108 PIS(ERRSYNCESC1); 1109 PIS(ERRSYNCESC2); 1110 PIS(ERRSYNCESC3); 1111 PIS(ERRESC1); 1112 PIS(ERRESC2); 1113 PIS(ERRESC3); 1114 PIS(ERRCONTROL1); 1115 PIS(ERRCONTROL2); 1116 PIS(ERRCONTROL3); 1117 PIS(STATEULPS1); 1118 PIS(STATEULPS2); 1119 PIS(STATEULPS3); 1120 PIS(ERRCONTENTIONLP0_1); 1121 PIS(ERRCONTENTIONLP1_1); 1122 PIS(ERRCONTENTIONLP0_2); 1123 PIS(ERRCONTENTIONLP1_2); 1124 PIS(ERRCONTENTIONLP0_3); 1125 PIS(ERRCONTENTIONLP1_3); 1126 PIS(ULPSACTIVENOT_ALL0); 1127 PIS(ULPSACTIVENOT_ALL1); 1128 #undef PIS 1129 1130 kfree(stats); 1131 1132 return 0; 1133 } 1134 #endif 1135 1136 static int dsi_dump_dsi_regs(struct seq_file *s, void *p) 1137 { 1138 struct dsi_data *dsi = s->private; 1139 1140 if (dsi_runtime_get(dsi)) 1141 return 0; 1142 dsi_enable_scp_clk(dsi); 1143 1144 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r)) 1145 DUMPREG(DSI_REVISION); 1146 DUMPREG(DSI_SYSCONFIG); 1147 DUMPREG(DSI_SYSSTATUS); 1148 DUMPREG(DSI_IRQSTATUS); 1149 DUMPREG(DSI_IRQENABLE); 1150 DUMPREG(DSI_CTRL); 1151 DUMPREG(DSI_COMPLEXIO_CFG1); 1152 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1153 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1154 DUMPREG(DSI_CLK_CTRL); 1155 DUMPREG(DSI_TIMING1); 1156 DUMPREG(DSI_TIMING2); 1157 DUMPREG(DSI_VM_TIMING1); 1158 DUMPREG(DSI_VM_TIMING2); 1159 DUMPREG(DSI_VM_TIMING3); 1160 DUMPREG(DSI_CLK_TIMING); 1161 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1162 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1163 DUMPREG(DSI_COMPLEXIO_CFG2); 1164 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1165 DUMPREG(DSI_VM_TIMING4); 1166 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1167 DUMPREG(DSI_VM_TIMING5); 1168 DUMPREG(DSI_VM_TIMING6); 1169 DUMPREG(DSI_VM_TIMING7); 1170 DUMPREG(DSI_STOPCLK_TIMING); 1171 1172 DUMPREG(DSI_VC_CTRL(0)); 1173 DUMPREG(DSI_VC_TE(0)); 1174 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1175 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1176 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1177 DUMPREG(DSI_VC_IRQSTATUS(0)); 1178 DUMPREG(DSI_VC_IRQENABLE(0)); 1179 1180 DUMPREG(DSI_VC_CTRL(1)); 1181 DUMPREG(DSI_VC_TE(1)); 1182 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1183 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1184 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1185 DUMPREG(DSI_VC_IRQSTATUS(1)); 1186 DUMPREG(DSI_VC_IRQENABLE(1)); 1187 1188 DUMPREG(DSI_VC_CTRL(2)); 1189 DUMPREG(DSI_VC_TE(2)); 1190 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1191 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1192 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1193 DUMPREG(DSI_VC_IRQSTATUS(2)); 1194 DUMPREG(DSI_VC_IRQENABLE(2)); 1195 1196 DUMPREG(DSI_VC_CTRL(3)); 1197 DUMPREG(DSI_VC_TE(3)); 1198 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1199 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1200 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1201 DUMPREG(DSI_VC_IRQSTATUS(3)); 1202 DUMPREG(DSI_VC_IRQENABLE(3)); 1203 1204 DUMPREG(DSI_DSIPHY_CFG0); 1205 DUMPREG(DSI_DSIPHY_CFG1); 1206 DUMPREG(DSI_DSIPHY_CFG2); 1207 DUMPREG(DSI_DSIPHY_CFG5); 1208 1209 DUMPREG(DSI_PLL_CONTROL); 1210 DUMPREG(DSI_PLL_STATUS); 1211 DUMPREG(DSI_PLL_GO); 1212 DUMPREG(DSI_PLL_CONFIGURATION1); 1213 DUMPREG(DSI_PLL_CONFIGURATION2); 1214 #undef DUMPREG 1215 1216 dsi_disable_scp_clk(dsi); 1217 dsi_runtime_put(dsi); 1218 1219 return 0; 1220 } 1221 1222 enum dsi_cio_power_state { 1223 DSI_COMPLEXIO_POWER_OFF = 0x0, 1224 DSI_COMPLEXIO_POWER_ON = 0x1, 1225 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1226 }; 1227 1228 static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state) 1229 { 1230 int t = 0; 1231 1232 /* PWR_CMD */ 1233 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); 1234 1235 /* PWR_STATUS */ 1236 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1), 1237 26, 25) != state) { 1238 if (++t > 1000) { 1239 DSSERR("failed to set complexio power state to " 1240 "%d\n", state); 1241 return -ENODEV; 1242 } 1243 udelay(1); 1244 } 1245 1246 return 0; 1247 } 1248 1249 static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi) 1250 { 1251 int val; 1252 1253 /* line buffer on OMAP3 is 1024 x 24bits */ 1254 /* XXX: for some reason using full buffer size causes 1255 * considerable TX slowdown with update sizes that fill the 1256 * whole buffer */ 1257 if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) 1258 return 1023 * 3; 1259 1260 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1261 1262 switch (val) { 1263 case 1: 1264 return 512 * 3; /* 512x24 bits */ 1265 case 2: 1266 return 682 * 3; /* 682x24 bits */ 1267 case 3: 1268 return 853 * 3; /* 853x24 bits */ 1269 case 4: 1270 return 1024 * 3; /* 1024x24 bits */ 1271 case 5: 1272 return 1194 * 3; /* 1194x24 bits */ 1273 case 6: 1274 return 1365 * 3; /* 1365x24 bits */ 1275 case 7: 1276 return 1920 * 3; /* 1920x24 bits */ 1277 default: 1278 BUG(); 1279 return 0; 1280 } 1281 } 1282 1283 static int dsi_set_lane_config(struct dsi_data *dsi) 1284 { 1285 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1286 static const enum dsi_lane_function functions[] = { 1287 DSI_LANE_CLK, 1288 DSI_LANE_DATA1, 1289 DSI_LANE_DATA2, 1290 DSI_LANE_DATA3, 1291 DSI_LANE_DATA4, 1292 }; 1293 u32 r; 1294 int i; 1295 1296 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1); 1297 1298 for (i = 0; i < dsi->num_lanes_used; ++i) { 1299 unsigned int offset = offsets[i]; 1300 unsigned int polarity, lane_number; 1301 unsigned int t; 1302 1303 for (t = 0; t < dsi->num_lanes_supported; ++t) 1304 if (dsi->lanes[t].function == functions[i]) 1305 break; 1306 1307 if (t == dsi->num_lanes_supported) 1308 return -EINVAL; 1309 1310 lane_number = t; 1311 polarity = dsi->lanes[t].polarity; 1312 1313 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1314 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1315 } 1316 1317 /* clear the unused lanes */ 1318 for (; i < dsi->num_lanes_supported; ++i) { 1319 unsigned int offset = offsets[i]; 1320 1321 r = FLD_MOD(r, 0, offset + 2, offset); 1322 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1323 } 1324 1325 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r); 1326 1327 return 0; 1328 } 1329 1330 static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns) 1331 { 1332 /* convert time in ns to ddr ticks, rounding up */ 1333 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1334 1335 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1336 } 1337 1338 static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr) 1339 { 1340 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1341 1342 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1343 } 1344 1345 static void dsi_cio_timings(struct dsi_data *dsi) 1346 { 1347 u32 r; 1348 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1349 u32 tlpx_half, tclk_trail, tclk_zero; 1350 u32 tclk_prepare; 1351 1352 /* calculate timings */ 1353 1354 /* 1 * DDR_CLK = 2 * UI */ 1355 1356 /* min 40ns + 4*UI max 85ns + 6*UI */ 1357 ths_prepare = ns2ddr(dsi, 70) + 2; 1358 1359 /* min 145ns + 10*UI */ 1360 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2; 1361 1362 /* min max(8*UI, 60ns+4*UI) */ 1363 ths_trail = ns2ddr(dsi, 60) + 5; 1364 1365 /* min 100ns */ 1366 ths_exit = ns2ddr(dsi, 145); 1367 1368 /* tlpx min 50n */ 1369 tlpx_half = ns2ddr(dsi, 25); 1370 1371 /* min 60ns */ 1372 tclk_trail = ns2ddr(dsi, 60) + 2; 1373 1374 /* min 38ns, max 95ns */ 1375 tclk_prepare = ns2ddr(dsi, 65); 1376 1377 /* min tclk-prepare + tclk-zero = 300ns */ 1378 tclk_zero = ns2ddr(dsi, 260); 1379 1380 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1381 ths_prepare, ddr2ns(dsi, ths_prepare), 1382 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero)); 1383 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1384 ths_trail, ddr2ns(dsi, ths_trail), 1385 ths_exit, ddr2ns(dsi, ths_exit)); 1386 1387 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1388 "tclk_zero %u (%uns)\n", 1389 tlpx_half, ddr2ns(dsi, tlpx_half), 1390 tclk_trail, ddr2ns(dsi, tclk_trail), 1391 tclk_zero, ddr2ns(dsi, tclk_zero)); 1392 DSSDBG("tclk_prepare %u (%uns)\n", 1393 tclk_prepare, ddr2ns(dsi, tclk_prepare)); 1394 1395 /* program timings */ 1396 1397 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 1398 r = FLD_MOD(r, ths_prepare, 31, 24); 1399 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1400 r = FLD_MOD(r, ths_trail, 15, 8); 1401 r = FLD_MOD(r, ths_exit, 7, 0); 1402 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r); 1403 1404 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 1405 r = FLD_MOD(r, tlpx_half, 20, 16); 1406 r = FLD_MOD(r, tclk_trail, 15, 8); 1407 r = FLD_MOD(r, tclk_zero, 7, 0); 1408 1409 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { 1410 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1411 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1412 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1413 } 1414 1415 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r); 1416 1417 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 1418 r = FLD_MOD(r, tclk_prepare, 7, 0); 1419 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r); 1420 } 1421 1422 static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi) 1423 { 1424 int t, i; 1425 bool in_use[DSI_MAX_NR_LANES]; 1426 static const u8 offsets_old[] = { 28, 27, 26 }; 1427 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 1428 const u8 *offsets; 1429 1430 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) 1431 offsets = offsets_old; 1432 else 1433 offsets = offsets_new; 1434 1435 for (i = 0; i < dsi->num_lanes_supported; ++i) 1436 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 1437 1438 t = 100000; 1439 while (true) { 1440 u32 l; 1441 int ok; 1442 1443 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1444 1445 ok = 0; 1446 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1447 if (!in_use[i] || (l & (1 << offsets[i]))) 1448 ok++; 1449 } 1450 1451 if (ok == dsi->num_lanes_supported) 1452 break; 1453 1454 if (--t == 0) { 1455 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1456 if (!in_use[i] || (l & (1 << offsets[i]))) 1457 continue; 1458 1459 DSSERR("CIO TXCLKESC%d domain not coming " \ 1460 "out of reset\n", i); 1461 } 1462 return -EIO; 1463 } 1464 } 1465 1466 return 0; 1467 } 1468 1469 /* return bitmask of enabled lanes, lane0 being the lsb */ 1470 static unsigned int dsi_get_lane_mask(struct dsi_data *dsi) 1471 { 1472 unsigned int mask = 0; 1473 int i; 1474 1475 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1476 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 1477 mask |= 1 << i; 1478 } 1479 1480 return mask; 1481 } 1482 1483 /* OMAP4 CONTROL_DSIPHY */ 1484 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 1485 1486 #define OMAP4_DSI2_LANEENABLE_SHIFT 29 1487 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 1488 #define OMAP4_DSI1_LANEENABLE_SHIFT 24 1489 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 1490 #define OMAP4_DSI1_PIPD_SHIFT 19 1491 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) 1492 #define OMAP4_DSI2_PIPD_SHIFT 14 1493 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) 1494 1495 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1496 { 1497 u32 enable_mask, enable_shift; 1498 u32 pipd_mask, pipd_shift; 1499 1500 if (dsi->module_id == 0) { 1501 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 1502 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 1503 pipd_mask = OMAP4_DSI1_PIPD_MASK; 1504 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 1505 } else if (dsi->module_id == 1) { 1506 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 1507 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 1508 pipd_mask = OMAP4_DSI2_PIPD_MASK; 1509 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 1510 } else { 1511 return -ENODEV; 1512 } 1513 1514 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, 1515 enable_mask | pipd_mask, 1516 (lanes << enable_shift) | (lanes << pipd_shift)); 1517 } 1518 1519 /* OMAP5 CONTROL_DSIPHY */ 1520 1521 #define OMAP5_DSIPHY_SYSCON_OFFSET 0x74 1522 1523 #define OMAP5_DSI1_LANEENABLE_SHIFT 24 1524 #define OMAP5_DSI2_LANEENABLE_SHIFT 19 1525 #define OMAP5_DSI_LANEENABLE_MASK 0x1f 1526 1527 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1528 { 1529 u32 enable_shift; 1530 1531 if (dsi->module_id == 0) 1532 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT; 1533 else if (dsi->module_id == 1) 1534 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT; 1535 else 1536 return -ENODEV; 1537 1538 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, 1539 OMAP5_DSI_LANEENABLE_MASK << enable_shift, 1540 lanes << enable_shift); 1541 } 1542 1543 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) 1544 { 1545 if (dsi->data->model == DSI_MODEL_OMAP4) 1546 return dsi_omap4_mux_pads(dsi, lane_mask); 1547 if (dsi->data->model == DSI_MODEL_OMAP5) 1548 return dsi_omap5_mux_pads(dsi, lane_mask); 1549 return 0; 1550 } 1551 1552 static void dsi_disable_pads(struct dsi_data *dsi) 1553 { 1554 if (dsi->data->model == DSI_MODEL_OMAP4) 1555 dsi_omap4_mux_pads(dsi, 0); 1556 else if (dsi->data->model == DSI_MODEL_OMAP5) 1557 dsi_omap5_mux_pads(dsi, 0); 1558 } 1559 1560 static int dsi_cio_init(struct dsi_data *dsi) 1561 { 1562 int r; 1563 u32 l; 1564 1565 DSSDBG("DSI CIO init starts"); 1566 1567 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi)); 1568 if (r) 1569 return r; 1570 1571 dsi_enable_scp_clk(dsi); 1572 1573 /* A dummy read using the SCP interface to any DSIPHY register is 1574 * required after DSIPHY reset to complete the reset of the DSI complex 1575 * I/O. */ 1576 dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1577 1578 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) { 1579 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 1580 r = -EIO; 1581 goto err_scp_clk_dom; 1582 } 1583 1584 r = dsi_set_lane_config(dsi); 1585 if (r) 1586 goto err_scp_clk_dom; 1587 1588 /* set TX STOP MODE timer to maximum for this operation */ 1589 l = dsi_read_reg(dsi, DSI_TIMING1); 1590 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 1591 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 1592 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 1593 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 1594 dsi_write_reg(dsi, DSI_TIMING1, l); 1595 1596 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON); 1597 if (r) 1598 goto err_cio_pwr; 1599 1600 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) { 1601 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 1602 r = -ENODEV; 1603 goto err_cio_pwr_dom; 1604 } 1605 1606 dsi_if_enable(dsi, true); 1607 dsi_if_enable(dsi, false); 1608 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 1609 1610 r = dsi_cio_wait_tx_clk_esc_reset(dsi); 1611 if (r) 1612 goto err_tx_clk_esc_rst; 1613 1614 /* FORCE_TX_STOP_MODE_IO */ 1615 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); 1616 1617 dsi_cio_timings(dsi); 1618 1619 /* DDR_CLK_ALWAYS_ON */ 1620 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1621 !(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS), 1622 13, 13); 1623 1624 DSSDBG("CIO init done\n"); 1625 1626 return 0; 1627 1628 err_tx_clk_esc_rst: 1629 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 1630 err_cio_pwr_dom: 1631 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 1632 err_cio_pwr: 1633 err_scp_clk_dom: 1634 dsi_disable_scp_clk(dsi); 1635 dsi_disable_pads(dsi); 1636 return r; 1637 } 1638 1639 static void dsi_cio_uninit(struct dsi_data *dsi) 1640 { 1641 /* DDR_CLK_ALWAYS_ON */ 1642 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); 1643 1644 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 1645 dsi_disable_scp_clk(dsi); 1646 dsi_disable_pads(dsi); 1647 } 1648 1649 static void dsi_config_tx_fifo(struct dsi_data *dsi, 1650 enum fifo_size size1, enum fifo_size size2, 1651 enum fifo_size size3, enum fifo_size size4) 1652 { 1653 u32 r = 0; 1654 int add = 0; 1655 int i; 1656 1657 dsi->vc[0].tx_fifo_size = size1; 1658 dsi->vc[1].tx_fifo_size = size2; 1659 dsi->vc[2].tx_fifo_size = size3; 1660 dsi->vc[3].tx_fifo_size = size4; 1661 1662 for (i = 0; i < 4; i++) { 1663 u8 v; 1664 int size = dsi->vc[i].tx_fifo_size; 1665 1666 if (add + size > 4) { 1667 DSSERR("Illegal FIFO configuration\n"); 1668 BUG(); 1669 return; 1670 } 1671 1672 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 1673 r |= v << (8 * i); 1674 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 1675 add += size; 1676 } 1677 1678 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r); 1679 } 1680 1681 static void dsi_config_rx_fifo(struct dsi_data *dsi, 1682 enum fifo_size size1, enum fifo_size size2, 1683 enum fifo_size size3, enum fifo_size size4) 1684 { 1685 u32 r = 0; 1686 int add = 0; 1687 int i; 1688 1689 dsi->vc[0].rx_fifo_size = size1; 1690 dsi->vc[1].rx_fifo_size = size2; 1691 dsi->vc[2].rx_fifo_size = size3; 1692 dsi->vc[3].rx_fifo_size = size4; 1693 1694 for (i = 0; i < 4; i++) { 1695 u8 v; 1696 int size = dsi->vc[i].rx_fifo_size; 1697 1698 if (add + size > 4) { 1699 DSSERR("Illegal FIFO configuration\n"); 1700 BUG(); 1701 return; 1702 } 1703 1704 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 1705 r |= v << (8 * i); 1706 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 1707 add += size; 1708 } 1709 1710 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r); 1711 } 1712 1713 static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi) 1714 { 1715 u32 r; 1716 1717 r = dsi_read_reg(dsi, DSI_TIMING1); 1718 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 1719 dsi_write_reg(dsi, DSI_TIMING1, r); 1720 1721 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) { 1722 DSSERR("TX_STOP bit not going down\n"); 1723 return -EIO; 1724 } 1725 1726 return 0; 1727 } 1728 1729 static bool dsi_vc_is_enabled(struct dsi_data *dsi, int vc) 1730 { 1731 return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0); 1732 } 1733 1734 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 1735 { 1736 struct dsi_packet_sent_handler_data *vp_data = 1737 (struct dsi_packet_sent_handler_data *) data; 1738 struct dsi_data *dsi = vp_data->dsi; 1739 const int vc = dsi->update_vc; 1740 u8 bit = dsi->te_enabled ? 30 : 31; 1741 1742 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit) == 0) 1743 complete(vp_data->completion); 1744 } 1745 1746 static int dsi_sync_vc_vp(struct dsi_data *dsi, int vc) 1747 { 1748 DECLARE_COMPLETION_ONSTACK(completion); 1749 struct dsi_packet_sent_handler_data vp_data = { 1750 .dsi = dsi, 1751 .completion = &completion 1752 }; 1753 int r = 0; 1754 u8 bit; 1755 1756 bit = dsi->te_enabled ? 30 : 31; 1757 1758 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, 1759 &vp_data, DSI_VC_IRQ_PACKET_SENT); 1760 if (r) 1761 goto err0; 1762 1763 /* Wait for completion only if TE_EN/TE_START is still set */ 1764 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit)) { 1765 if (wait_for_completion_timeout(&completion, 1766 msecs_to_jiffies(10)) == 0) { 1767 DSSERR("Failed to complete previous frame transfer\n"); 1768 r = -EIO; 1769 goto err1; 1770 } 1771 } 1772 1773 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, 1774 &vp_data, DSI_VC_IRQ_PACKET_SENT); 1775 1776 return 0; 1777 err1: 1778 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, 1779 &vp_data, DSI_VC_IRQ_PACKET_SENT); 1780 err0: 1781 return r; 1782 } 1783 1784 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 1785 { 1786 struct dsi_packet_sent_handler_data *l4_data = 1787 (struct dsi_packet_sent_handler_data *) data; 1788 struct dsi_data *dsi = l4_data->dsi; 1789 const int vc = dsi->update_vc; 1790 1791 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0) 1792 complete(l4_data->completion); 1793 } 1794 1795 static int dsi_sync_vc_l4(struct dsi_data *dsi, int vc) 1796 { 1797 DECLARE_COMPLETION_ONSTACK(completion); 1798 struct dsi_packet_sent_handler_data l4_data = { 1799 .dsi = dsi, 1800 .completion = &completion 1801 }; 1802 int r = 0; 1803 1804 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, 1805 &l4_data, DSI_VC_IRQ_PACKET_SENT); 1806 if (r) 1807 goto err0; 1808 1809 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 1810 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) { 1811 if (wait_for_completion_timeout(&completion, 1812 msecs_to_jiffies(10)) == 0) { 1813 DSSERR("Failed to complete previous l4 transfer\n"); 1814 r = -EIO; 1815 goto err1; 1816 } 1817 } 1818 1819 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, 1820 &l4_data, DSI_VC_IRQ_PACKET_SENT); 1821 1822 return 0; 1823 err1: 1824 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, 1825 &l4_data, DSI_VC_IRQ_PACKET_SENT); 1826 err0: 1827 return r; 1828 } 1829 1830 static int dsi_sync_vc(struct dsi_data *dsi, int vc) 1831 { 1832 WARN_ON(!dsi_bus_is_locked(dsi)); 1833 1834 WARN_ON(in_interrupt()); 1835 1836 if (!dsi_vc_is_enabled(dsi, vc)) 1837 return 0; 1838 1839 switch (dsi->vc[vc].source) { 1840 case DSI_VC_SOURCE_VP: 1841 return dsi_sync_vc_vp(dsi, vc); 1842 case DSI_VC_SOURCE_L4: 1843 return dsi_sync_vc_l4(dsi, vc); 1844 default: 1845 BUG(); 1846 return -EINVAL; 1847 } 1848 } 1849 1850 static int dsi_vc_enable(struct dsi_data *dsi, int vc, bool enable) 1851 { 1852 DSSDBG("dsi_vc_enable vc %d, enable %d\n", 1853 vc, enable); 1854 1855 enable = enable ? 1 : 0; 1856 1857 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 0, 0); 1858 1859 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(vc), 0, enable)) { 1860 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 1861 return -EIO; 1862 } 1863 1864 return 0; 1865 } 1866 1867 static void dsi_vc_initial_config(struct dsi_data *dsi, int vc) 1868 { 1869 u32 r; 1870 1871 DSSDBG("Initial config of VC %d", vc); 1872 1873 r = dsi_read_reg(dsi, DSI_VC_CTRL(vc)); 1874 1875 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 1876 DSSERR("VC(%d) busy when trying to configure it!\n", 1877 vc); 1878 1879 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 1880 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 1881 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 1882 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 1883 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 1884 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 1885 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 1886 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) 1887 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 1888 1889 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 1890 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 1891 1892 dsi_write_reg(dsi, DSI_VC_CTRL(vc), r); 1893 1894 dsi->vc[vc].source = DSI_VC_SOURCE_L4; 1895 } 1896 1897 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int vc, 1898 bool enable) 1899 { 1900 struct dsi_data *dsi = to_dsi_data(dssdev); 1901 1902 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", vc, enable); 1903 1904 if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable) 1905 return; 1906 1907 WARN_ON(!dsi_bus_is_locked(dsi)); 1908 1909 dsi_vc_enable(dsi, vc, 0); 1910 dsi_if_enable(dsi, 0); 1911 1912 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 9, 9); 1913 1914 dsi_vc_enable(dsi, vc, 1); 1915 dsi_if_enable(dsi, 1); 1916 1917 dsi_force_tx_stop_mode_io(dsi); 1918 } 1919 1920 static void dsi_vc_flush_long_data(struct dsi_data *dsi, int vc) 1921 { 1922 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 1923 u32 val; 1924 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); 1925 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 1926 (val >> 0) & 0xff, 1927 (val >> 8) & 0xff, 1928 (val >> 16) & 0xff, 1929 (val >> 24) & 0xff); 1930 } 1931 } 1932 1933 static void dsi_show_rx_ack_with_err(u16 err) 1934 { 1935 DSSERR("\tACK with ERROR (%#x):\n", err); 1936 if (err & (1 << 0)) 1937 DSSERR("\t\tSoT Error\n"); 1938 if (err & (1 << 1)) 1939 DSSERR("\t\tSoT Sync Error\n"); 1940 if (err & (1 << 2)) 1941 DSSERR("\t\tEoT Sync Error\n"); 1942 if (err & (1 << 3)) 1943 DSSERR("\t\tEscape Mode Entry Command Error\n"); 1944 if (err & (1 << 4)) 1945 DSSERR("\t\tLP Transmit Sync Error\n"); 1946 if (err & (1 << 5)) 1947 DSSERR("\t\tHS Receive Timeout Error\n"); 1948 if (err & (1 << 6)) 1949 DSSERR("\t\tFalse Control Error\n"); 1950 if (err & (1 << 7)) 1951 DSSERR("\t\t(reserved7)\n"); 1952 if (err & (1 << 8)) 1953 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 1954 if (err & (1 << 9)) 1955 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 1956 if (err & (1 << 10)) 1957 DSSERR("\t\tChecksum Error\n"); 1958 if (err & (1 << 11)) 1959 DSSERR("\t\tData type not recognized\n"); 1960 if (err & (1 << 12)) 1961 DSSERR("\t\tInvalid VC ID\n"); 1962 if (err & (1 << 13)) 1963 DSSERR("\t\tInvalid Transmission Length\n"); 1964 if (err & (1 << 14)) 1965 DSSERR("\t\t(reserved14)\n"); 1966 if (err & (1 << 15)) 1967 DSSERR("\t\tDSI Protocol Violation\n"); 1968 } 1969 1970 static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int vc) 1971 { 1972 /* RX_FIFO_NOT_EMPTY */ 1973 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 1974 u32 val; 1975 u8 dt; 1976 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); 1977 DSSERR("\trawval %#08x\n", val); 1978 dt = FLD_GET(val, 5, 0); 1979 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 1980 u16 err = FLD_GET(val, 23, 8); 1981 dsi_show_rx_ack_with_err(err); 1982 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 1983 DSSERR("\tDCS short response, 1 byte: %#x\n", 1984 FLD_GET(val, 23, 8)); 1985 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 1986 DSSERR("\tDCS short response, 2 byte: %#x\n", 1987 FLD_GET(val, 23, 8)); 1988 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 1989 DSSERR("\tDCS long response, len %d\n", 1990 FLD_GET(val, 23, 8)); 1991 dsi_vc_flush_long_data(dsi, vc); 1992 } else { 1993 DSSERR("\tunknown datatype 0x%02x\n", dt); 1994 } 1995 } 1996 return 0; 1997 } 1998 1999 static int dsi_vc_send_bta(struct dsi_data *dsi, int vc) 2000 { 2001 if (dsi->debug_write || dsi->debug_read) 2002 DSSDBG("dsi_vc_send_bta %d\n", vc); 2003 2004 WARN_ON(!dsi_bus_is_locked(dsi)); 2005 2006 /* RX_FIFO_NOT_EMPTY */ 2007 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 2008 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2009 dsi_vc_flush_receive_data(dsi, vc); 2010 } 2011 2012 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 6, 6); /* BTA_EN */ 2013 2014 /* flush posted write */ 2015 dsi_read_reg(dsi, DSI_VC_CTRL(vc)); 2016 2017 return 0; 2018 } 2019 2020 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int vc) 2021 { 2022 struct dsi_data *dsi = to_dsi_data(dssdev); 2023 DECLARE_COMPLETION_ONSTACK(completion); 2024 int r = 0; 2025 u32 err; 2026 2027 r = dsi_register_isr_vc(dsi, vc, dsi_completion_handler, 2028 &completion, DSI_VC_IRQ_BTA); 2029 if (r) 2030 goto err0; 2031 2032 r = dsi_register_isr(dsi, dsi_completion_handler, &completion, 2033 DSI_IRQ_ERROR_MASK); 2034 if (r) 2035 goto err1; 2036 2037 r = dsi_vc_send_bta(dsi, vc); 2038 if (r) 2039 goto err2; 2040 2041 if (wait_for_completion_timeout(&completion, 2042 msecs_to_jiffies(500)) == 0) { 2043 DSSERR("Failed to receive BTA\n"); 2044 r = -EIO; 2045 goto err2; 2046 } 2047 2048 err = dsi_get_errors(dsi); 2049 if (err) { 2050 DSSERR("Error while sending BTA: %x\n", err); 2051 r = -EIO; 2052 goto err2; 2053 } 2054 err2: 2055 dsi_unregister_isr(dsi, dsi_completion_handler, &completion, 2056 DSI_IRQ_ERROR_MASK); 2057 err1: 2058 dsi_unregister_isr_vc(dsi, vc, dsi_completion_handler, 2059 &completion, DSI_VC_IRQ_BTA); 2060 err0: 2061 return r; 2062 } 2063 2064 static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int vc, 2065 int channel, u8 data_type, u16 len, 2066 u8 ecc) 2067 { 2068 u32 val; 2069 u8 data_id; 2070 2071 WARN_ON(!dsi_bus_is_locked(dsi)); 2072 2073 data_id = data_type | channel << 6; 2074 2075 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2076 FLD_VAL(ecc, 31, 24); 2077 2078 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(vc), val); 2079 } 2080 2081 static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int vc, 2082 u8 b1, u8 b2, u8 b3, u8 b4) 2083 { 2084 u32 val; 2085 2086 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2087 2088 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2089 b1, b2, b3, b4, val); */ 2090 2091 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(vc), val); 2092 } 2093 2094 static int dsi_vc_send_long(struct dsi_data *dsi, int vc, 2095 const struct mipi_dsi_msg *msg) 2096 { 2097 /*u32 val; */ 2098 int i; 2099 const u8 *p; 2100 int r = 0; 2101 u8 b1, b2, b3, b4; 2102 2103 if (dsi->debug_write) 2104 DSSDBG("dsi_vc_send_long, %zu bytes\n", msg->tx_len); 2105 2106 /* len + header */ 2107 if (dsi->vc[vc].tx_fifo_size * 32 * 4 < msg->tx_len + 4) { 2108 DSSERR("unable to send long packet: packet too long.\n"); 2109 return -EINVAL; 2110 } 2111 2112 dsi_vc_write_long_header(dsi, vc, msg->channel, msg->type, msg->tx_len, 0); 2113 2114 p = msg->tx_buf; 2115 for (i = 0; i < msg->tx_len >> 2; i++) { 2116 if (dsi->debug_write) 2117 DSSDBG("\tsending full packet %d\n", i); 2118 2119 b1 = *p++; 2120 b2 = *p++; 2121 b3 = *p++; 2122 b4 = *p++; 2123 2124 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, b4); 2125 } 2126 2127 i = msg->tx_len % 4; 2128 if (i) { 2129 b1 = 0; b2 = 0; b3 = 0; 2130 2131 if (dsi->debug_write) 2132 DSSDBG("\tsending remainder bytes %d\n", i); 2133 2134 switch (i) { 2135 case 3: 2136 b1 = *p++; 2137 b2 = *p++; 2138 b3 = *p++; 2139 break; 2140 case 2: 2141 b1 = *p++; 2142 b2 = *p++; 2143 break; 2144 case 1: 2145 b1 = *p++; 2146 break; 2147 } 2148 2149 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, 0); 2150 } 2151 2152 return r; 2153 } 2154 2155 static int dsi_vc_send_short(struct dsi_data *dsi, int vc, 2156 const struct mipi_dsi_msg *msg) 2157 { 2158 struct mipi_dsi_packet pkt; 2159 int ret; 2160 u32 r; 2161 2162 ret = mipi_dsi_create_packet(&pkt, msg); 2163 if (ret < 0) 2164 return ret; 2165 2166 WARN_ON(!dsi_bus_is_locked(dsi)); 2167 2168 if (dsi->debug_write) 2169 DSSDBG("dsi_vc_send_short(vc%d, dt %#x, b1 %#x, b2 %#x)\n", 2170 vc, msg->type, pkt.header[1], pkt.header[2]); 2171 2172 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(vc)), 16, 16)) { 2173 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2174 return -EINVAL; 2175 } 2176 2177 r = pkt.header[3] << 24 | pkt.header[2] << 16 | pkt.header[1] << 8 | 2178 pkt.header[0]; 2179 2180 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc), r); 2181 2182 return 0; 2183 } 2184 2185 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel) 2186 { 2187 const struct mipi_dsi_msg msg = { 2188 .channel = channel, 2189 .type = MIPI_DSI_NULL_PACKET, 2190 }; 2191 2192 return dsi_vc_send_long(dsi, vc, &msg); 2193 } 2194 2195 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int vc, 2196 const struct mipi_dsi_msg *msg) 2197 { 2198 struct dsi_data *dsi = to_dsi_data(dssdev); 2199 int r; 2200 2201 if (mipi_dsi_packet_format_is_short(msg->type)) 2202 r = dsi_vc_send_short(dsi, vc, msg); 2203 else 2204 r = dsi_vc_send_long(dsi, vc, msg); 2205 2206 if (r < 0) 2207 return r; 2208 2209 /* 2210 * TODO: we do not always have to do the BTA sync, for example 2211 * we can improve performance by setting the update window 2212 * information without sending BTA sync between the commands. 2213 * In that case we can return early. 2214 */ 2215 2216 r = dsi_vc_send_bta_sync(dssdev, vc); 2217 if (r) { 2218 DSSERR("bta sync failed\n"); 2219 return r; 2220 } 2221 2222 /* RX_FIFO_NOT_EMPTY */ 2223 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 2224 DSSERR("rx fifo not empty after write, dumping data:\n"); 2225 dsi_vc_flush_receive_data(dsi, vc); 2226 return -EIO; 2227 } 2228 2229 return 0; 2230 } 2231 2232 static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int vc, u8 *buf, 2233 int buflen, enum dss_dsi_content_type type) 2234 { 2235 u32 val; 2236 u8 dt; 2237 int r; 2238 2239 /* RX_FIFO_NOT_EMPTY */ 2240 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20) == 0) { 2241 DSSERR("RX fifo empty when trying to read.\n"); 2242 r = -EIO; 2243 goto err; 2244 } 2245 2246 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); 2247 if (dsi->debug_read) 2248 DSSDBG("\theader: %08x\n", val); 2249 dt = FLD_GET(val, 5, 0); 2250 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2251 u16 err = FLD_GET(val, 23, 8); 2252 dsi_show_rx_ack_with_err(err); 2253 r = -EIO; 2254 goto err; 2255 2256 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2257 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2258 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2259 u8 data = FLD_GET(val, 15, 8); 2260 if (dsi->debug_read) 2261 DSSDBG("\t%s short response, 1 byte: %02x\n", 2262 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2263 "DCS", data); 2264 2265 if (buflen < 1) { 2266 r = -EIO; 2267 goto err; 2268 } 2269 2270 buf[0] = data; 2271 2272 return 1; 2273 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2274 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2275 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2276 u16 data = FLD_GET(val, 23, 8); 2277 if (dsi->debug_read) 2278 DSSDBG("\t%s short response, 2 byte: %04x\n", 2279 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2280 "DCS", data); 2281 2282 if (buflen < 2) { 2283 r = -EIO; 2284 goto err; 2285 } 2286 2287 buf[0] = data & 0xff; 2288 buf[1] = (data >> 8) & 0xff; 2289 2290 return 2; 2291 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2292 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 2293 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 2294 int w; 2295 int len = FLD_GET(val, 23, 8); 2296 if (dsi->debug_read) 2297 DSSDBG("\t%s long response, len %d\n", 2298 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2299 "DCS", len); 2300 2301 if (len > buflen) { 2302 r = -EIO; 2303 goto err; 2304 } 2305 2306 /* two byte checksum ends the packet, not included in len */ 2307 for (w = 0; w < len + 2;) { 2308 int b; 2309 val = dsi_read_reg(dsi, 2310 DSI_VC_SHORT_PACKET_HEADER(vc)); 2311 if (dsi->debug_read) 2312 DSSDBG("\t\t%02x %02x %02x %02x\n", 2313 (val >> 0) & 0xff, 2314 (val >> 8) & 0xff, 2315 (val >> 16) & 0xff, 2316 (val >> 24) & 0xff); 2317 2318 for (b = 0; b < 4; ++b) { 2319 if (w < len) 2320 buf[w] = (val >> (b * 8)) & 0xff; 2321 /* we discard the 2 byte checksum */ 2322 ++w; 2323 } 2324 } 2325 2326 return len; 2327 } else { 2328 DSSERR("\tunknown datatype 0x%02x\n", dt); 2329 r = -EIO; 2330 goto err; 2331 } 2332 2333 err: 2334 DSSERR("dsi_vc_read_rx_fifo(vc %d type %s) failed\n", vc, 2335 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 2336 2337 return r; 2338 } 2339 2340 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int vc, 2341 const struct mipi_dsi_msg *msg) 2342 { 2343 struct dsi_data *dsi = to_dsi_data(dssdev); 2344 u8 cmd = ((u8 *)msg->tx_buf)[0]; 2345 int r; 2346 2347 if (dsi->debug_read) 2348 DSSDBG("%s(vc %d, cmd %x)\n", __func__, vc, cmd); 2349 2350 r = dsi_vc_send_short(dsi, vc, msg); 2351 if (r) 2352 goto err; 2353 2354 r = dsi_vc_send_bta_sync(dssdev, vc); 2355 if (r) 2356 goto err; 2357 2358 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, 2359 DSS_DSI_CONTENT_DCS); 2360 if (r < 0) 2361 goto err; 2362 2363 if (r != msg->rx_len) { 2364 r = -EIO; 2365 goto err; 2366 } 2367 2368 return 0; 2369 err: 2370 DSSERR("%s(vc %d, cmd 0x%02x) failed\n", __func__, vc, cmd); 2371 return r; 2372 } 2373 2374 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int vc, 2375 const struct mipi_dsi_msg *msg) 2376 { 2377 struct dsi_data *dsi = to_dsi_data(dssdev); 2378 int r; 2379 2380 r = dsi_vc_send_short(dsi, vc, msg); 2381 if (r) 2382 goto err; 2383 2384 r = dsi_vc_send_bta_sync(dssdev, vc); 2385 if (r) 2386 goto err; 2387 2388 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, 2389 DSS_DSI_CONTENT_GENERIC); 2390 if (r < 0) 2391 goto err; 2392 2393 if (r != msg->rx_len) { 2394 r = -EIO; 2395 goto err; 2396 } 2397 2398 return 0; 2399 err: 2400 DSSERR("%s(vc %d, reqlen %zu) failed\n", __func__, vc, msg->tx_len); 2401 return r; 2402 } 2403 2404 static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks, 2405 bool x4, bool x16) 2406 { 2407 unsigned long fck; 2408 unsigned long total_ticks; 2409 u32 r; 2410 2411 BUG_ON(ticks > 0x1fff); 2412 2413 /* ticks in DSI_FCK */ 2414 fck = dsi_fclk_rate(dsi); 2415 2416 r = dsi_read_reg(dsi, DSI_TIMING2); 2417 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 2418 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 2419 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 2420 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 2421 dsi_write_reg(dsi, DSI_TIMING2, r); 2422 2423 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 2424 2425 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 2426 total_ticks, 2427 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 2428 (total_ticks * 1000) / (fck / 1000 / 1000)); 2429 } 2430 2431 static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks, 2432 bool x8, bool x16) 2433 { 2434 unsigned long fck; 2435 unsigned long total_ticks; 2436 u32 r; 2437 2438 BUG_ON(ticks > 0x1fff); 2439 2440 /* ticks in DSI_FCK */ 2441 fck = dsi_fclk_rate(dsi); 2442 2443 r = dsi_read_reg(dsi, DSI_TIMING1); 2444 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 2445 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 2446 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 2447 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 2448 dsi_write_reg(dsi, DSI_TIMING1, r); 2449 2450 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 2451 2452 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 2453 total_ticks, 2454 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 2455 (total_ticks * 1000) / (fck / 1000 / 1000)); 2456 } 2457 2458 static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks, 2459 bool x4, bool x16) 2460 { 2461 unsigned long fck; 2462 unsigned long total_ticks; 2463 u32 r; 2464 2465 BUG_ON(ticks > 0x1fff); 2466 2467 /* ticks in DSI_FCK */ 2468 fck = dsi_fclk_rate(dsi); 2469 2470 r = dsi_read_reg(dsi, DSI_TIMING1); 2471 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2472 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 2473 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 2474 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 2475 dsi_write_reg(dsi, DSI_TIMING1, r); 2476 2477 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 2478 2479 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 2480 total_ticks, 2481 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 2482 (total_ticks * 1000) / (fck / 1000 / 1000)); 2483 } 2484 2485 static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks, 2486 bool x4, bool x16) 2487 { 2488 unsigned long fck; 2489 unsigned long total_ticks; 2490 u32 r; 2491 2492 BUG_ON(ticks > 0x1fff); 2493 2494 /* ticks in TxByteClkHS */ 2495 fck = dsi_get_txbyteclkhs(dsi); 2496 2497 r = dsi_read_reg(dsi, DSI_TIMING2); 2498 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 2499 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 2500 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 2501 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 2502 dsi_write_reg(dsi, DSI_TIMING2, r); 2503 2504 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 2505 2506 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 2507 total_ticks, 2508 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 2509 (total_ticks * 1000) / (fck / 1000 / 1000)); 2510 } 2511 2512 static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi) 2513 { 2514 int num_line_buffers; 2515 2516 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2517 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2518 const struct videomode *vm = &dsi->vm; 2519 /* 2520 * Don't use line buffers if width is greater than the video 2521 * port's line buffer size 2522 */ 2523 if (dsi->line_buffer_size <= vm->hactive * bpp / 8) 2524 num_line_buffers = 0; 2525 else 2526 num_line_buffers = 2; 2527 } else { 2528 /* Use maximum number of line buffers in command mode */ 2529 num_line_buffers = 2; 2530 } 2531 2532 /* LINE_BUFFER */ 2533 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12); 2534 } 2535 2536 static void dsi_config_vp_sync_events(struct dsi_data *dsi) 2537 { 2538 bool sync_end; 2539 u32 r; 2540 2541 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 2542 sync_end = true; 2543 else 2544 sync_end = false; 2545 2546 r = dsi_read_reg(dsi, DSI_CTRL); 2547 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 2548 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 2549 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 2550 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 2551 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 2552 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 2553 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 2554 dsi_write_reg(dsi, DSI_CTRL, r); 2555 } 2556 2557 static void dsi_config_blanking_modes(struct dsi_data *dsi) 2558 { 2559 int blanking_mode = dsi->vm_timings.blanking_mode; 2560 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 2561 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 2562 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 2563 u32 r; 2564 2565 /* 2566 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 2567 * 1 = Long blanking packets are sent in corresponding blanking periods 2568 */ 2569 r = dsi_read_reg(dsi, DSI_CTRL); 2570 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 2571 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 2572 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 2573 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 2574 dsi_write_reg(dsi, DSI_CTRL, r); 2575 } 2576 2577 /* 2578 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 2579 * results in maximum transition time for data and clock lanes to enter and 2580 * exit HS mode. Hence, this is the scenario where the least amount of command 2581 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 2582 * clock cycles that can be used to interleave command mode data in HS so that 2583 * all scenarios are satisfied. 2584 */ 2585 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 2586 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 2587 { 2588 int transition; 2589 2590 /* 2591 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 2592 * time of data lanes only, if it isn't set, we need to consider HS 2593 * transition time of both data and clock lanes. HS transition time 2594 * of Scenario 3 is considered. 2595 */ 2596 if (ddr_alwon) { 2597 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 2598 } else { 2599 int trans1, trans2; 2600 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 2601 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 2602 enter_hs + 1; 2603 transition = max(trans1, trans2); 2604 } 2605 2606 return blank > transition ? blank - transition : 0; 2607 } 2608 2609 /* 2610 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 2611 * results in maximum transition time for data lanes to enter and exit LP mode. 2612 * Hence, this is the scenario where the least amount of command mode data can 2613 * be interleaved. We program the minimum amount of bytes that can be 2614 * interleaved in LP so that all scenarios are satisfied. 2615 */ 2616 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 2617 int lp_clk_div, int tdsi_fclk) 2618 { 2619 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 2620 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 2621 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 2622 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 2623 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 2624 2625 /* maximum LP transition time according to Scenario 1 */ 2626 trans_lp = exit_hs + max(enter_hs, 2) + 1; 2627 2628 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 2629 tlp_avail = thsbyte_clk * (blank - trans_lp); 2630 2631 ttxclkesc = tdsi_fclk * lp_clk_div; 2632 2633 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 2634 26) / 16; 2635 2636 return max(lp_inter, 0); 2637 } 2638 2639 static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi) 2640 { 2641 int blanking_mode; 2642 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 2643 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 2644 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 2645 int tclk_trail, ths_exit, exiths_clk; 2646 bool ddr_alwon; 2647 const struct videomode *vm = &dsi->vm; 2648 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2649 int ndl = dsi->num_lanes_used - 1; 2650 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 2651 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 2652 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 2653 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 2654 int bl_interleave_hs = 0, bl_interleave_lp = 0; 2655 u32 r; 2656 2657 r = dsi_read_reg(dsi, DSI_CTRL); 2658 blanking_mode = FLD_GET(r, 20, 20); 2659 hfp_blanking_mode = FLD_GET(r, 21, 21); 2660 hbp_blanking_mode = FLD_GET(r, 22, 22); 2661 hsa_blanking_mode = FLD_GET(r, 23, 23); 2662 2663 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 2664 hbp = FLD_GET(r, 11, 0); 2665 hfp = FLD_GET(r, 23, 12); 2666 hsa = FLD_GET(r, 31, 24); 2667 2668 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 2669 ddr_clk_post = FLD_GET(r, 7, 0); 2670 ddr_clk_pre = FLD_GET(r, 15, 8); 2671 2672 r = dsi_read_reg(dsi, DSI_VM_TIMING7); 2673 exit_hs_mode_lat = FLD_GET(r, 15, 0); 2674 enter_hs_mode_lat = FLD_GET(r, 31, 16); 2675 2676 r = dsi_read_reg(dsi, DSI_CLK_CTRL); 2677 lp_clk_div = FLD_GET(r, 12, 0); 2678 ddr_alwon = FLD_GET(r, 13, 13); 2679 2680 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 2681 ths_exit = FLD_GET(r, 7, 0); 2682 2683 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 2684 tclk_trail = FLD_GET(r, 15, 8); 2685 2686 exiths_clk = ths_exit + tclk_trail; 2687 2688 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 2689 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 2690 2691 if (!hsa_blanking_mode) { 2692 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 2693 enter_hs_mode_lat, exit_hs_mode_lat, 2694 exiths_clk, ddr_clk_pre, ddr_clk_post); 2695 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 2696 enter_hs_mode_lat, exit_hs_mode_lat, 2697 lp_clk_div, dsi_fclk_hsdiv); 2698 } 2699 2700 if (!hfp_blanking_mode) { 2701 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 2702 enter_hs_mode_lat, exit_hs_mode_lat, 2703 exiths_clk, ddr_clk_pre, ddr_clk_post); 2704 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 2705 enter_hs_mode_lat, exit_hs_mode_lat, 2706 lp_clk_div, dsi_fclk_hsdiv); 2707 } 2708 2709 if (!hbp_blanking_mode) { 2710 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 2711 enter_hs_mode_lat, exit_hs_mode_lat, 2712 exiths_clk, ddr_clk_pre, ddr_clk_post); 2713 2714 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 2715 enter_hs_mode_lat, exit_hs_mode_lat, 2716 lp_clk_div, dsi_fclk_hsdiv); 2717 } 2718 2719 if (!blanking_mode) { 2720 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 2721 enter_hs_mode_lat, exit_hs_mode_lat, 2722 exiths_clk, ddr_clk_pre, ddr_clk_post); 2723 2724 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 2725 enter_hs_mode_lat, exit_hs_mode_lat, 2726 lp_clk_div, dsi_fclk_hsdiv); 2727 } 2728 2729 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 2730 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 2731 bl_interleave_hs); 2732 2733 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 2734 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 2735 bl_interleave_lp); 2736 2737 r = dsi_read_reg(dsi, DSI_VM_TIMING4); 2738 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 2739 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 2740 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 2741 dsi_write_reg(dsi, DSI_VM_TIMING4, r); 2742 2743 r = dsi_read_reg(dsi, DSI_VM_TIMING5); 2744 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 2745 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 2746 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 2747 dsi_write_reg(dsi, DSI_VM_TIMING5, r); 2748 2749 r = dsi_read_reg(dsi, DSI_VM_TIMING6); 2750 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 2751 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 2752 dsi_write_reg(dsi, DSI_VM_TIMING6, r); 2753 } 2754 2755 static int dsi_proto_config(struct dsi_data *dsi) 2756 { 2757 u32 r; 2758 int buswidth = 0; 2759 2760 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32, 2761 DSI_FIFO_SIZE_32, 2762 DSI_FIFO_SIZE_32, 2763 DSI_FIFO_SIZE_32); 2764 2765 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32, 2766 DSI_FIFO_SIZE_32, 2767 DSI_FIFO_SIZE_32, 2768 DSI_FIFO_SIZE_32); 2769 2770 /* XXX what values for the timeouts? */ 2771 dsi_set_stop_state_counter(dsi, 0x1000, false, false); 2772 dsi_set_ta_timeout(dsi, 0x1fff, true, true); 2773 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true); 2774 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true); 2775 2776 switch (mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt)) { 2777 case 16: 2778 buswidth = 0; 2779 break; 2780 case 18: 2781 buswidth = 1; 2782 break; 2783 case 24: 2784 buswidth = 2; 2785 break; 2786 default: 2787 BUG(); 2788 return -EINVAL; 2789 } 2790 2791 r = dsi_read_reg(dsi, DSI_CTRL); 2792 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 2793 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 2794 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 2795 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 2796 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 2797 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 2798 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 2799 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 2800 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { 2801 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 2802 /* DCS_CMD_CODE, 1=start, 0=continue */ 2803 r = FLD_MOD(r, 0, 25, 25); 2804 } 2805 2806 dsi_write_reg(dsi, DSI_CTRL, r); 2807 2808 dsi_config_vp_num_line_buffers(dsi); 2809 2810 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2811 dsi_config_vp_sync_events(dsi); 2812 dsi_config_blanking_modes(dsi); 2813 dsi_config_cmd_mode_interleaving(dsi); 2814 } 2815 2816 dsi_vc_initial_config(dsi, 0); 2817 dsi_vc_initial_config(dsi, 1); 2818 dsi_vc_initial_config(dsi, 2); 2819 dsi_vc_initial_config(dsi, 3); 2820 2821 return 0; 2822 } 2823 2824 static void dsi_proto_timings(struct dsi_data *dsi) 2825 { 2826 unsigned int tlpx, tclk_zero, tclk_prepare; 2827 unsigned int tclk_pre, tclk_post; 2828 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero; 2829 unsigned int ths_trail, ths_exit; 2830 unsigned int ddr_clk_pre, ddr_clk_post; 2831 unsigned int enter_hs_mode_lat, exit_hs_mode_lat; 2832 unsigned int ths_eot; 2833 int ndl = dsi->num_lanes_used - 1; 2834 u32 r; 2835 2836 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 2837 ths_prepare = FLD_GET(r, 31, 24); 2838 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 2839 ths_zero = ths_prepare_ths_zero - ths_prepare; 2840 ths_trail = FLD_GET(r, 15, 8); 2841 ths_exit = FLD_GET(r, 7, 0); 2842 2843 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 2844 tlpx = FLD_GET(r, 20, 16) * 2; 2845 tclk_zero = FLD_GET(r, 7, 0); 2846 2847 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 2848 tclk_prepare = FLD_GET(r, 7, 0); 2849 2850 /* min 8*UI */ 2851 tclk_pre = 20; 2852 /* min 60ns + 52*UI */ 2853 tclk_post = ns2ddr(dsi, 60) + 26; 2854 2855 ths_eot = DIV_ROUND_UP(4, ndl); 2856 2857 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 2858 4); 2859 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 2860 2861 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 2862 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 2863 2864 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 2865 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 2866 r = FLD_MOD(r, ddr_clk_post, 7, 0); 2867 dsi_write_reg(dsi, DSI_CLK_TIMING, r); 2868 2869 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 2870 ddr_clk_pre, 2871 ddr_clk_post); 2872 2873 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 2874 DIV_ROUND_UP(ths_prepare, 4) + 2875 DIV_ROUND_UP(ths_zero + 3, 4); 2876 2877 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 2878 2879 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 2880 FLD_VAL(exit_hs_mode_lat, 15, 0); 2881 dsi_write_reg(dsi, DSI_VM_TIMING7, r); 2882 2883 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 2884 enter_hs_mode_lat, exit_hs_mode_lat); 2885 2886 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2887 /* TODO: Implement a video mode check_timings function */ 2888 int hsa = dsi->vm_timings.hsa; 2889 int hfp = dsi->vm_timings.hfp; 2890 int hbp = dsi->vm_timings.hbp; 2891 int vsa = dsi->vm_timings.vsa; 2892 int vfp = dsi->vm_timings.vfp; 2893 int vbp = dsi->vm_timings.vbp; 2894 int window_sync = dsi->vm_timings.window_sync; 2895 bool hsync_end; 2896 const struct videomode *vm = &dsi->vm; 2897 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2898 int tl, t_he, width_bytes; 2899 2900 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 2901 t_he = hsync_end ? 2902 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 2903 2904 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 2905 2906 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 2907 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 2908 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 2909 2910 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 2911 hfp, hsync_end ? hsa : 0, tl); 2912 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 2913 vsa, vm->vactive); 2914 2915 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 2916 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 2917 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 2918 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 2919 dsi_write_reg(dsi, DSI_VM_TIMING1, r); 2920 2921 r = dsi_read_reg(dsi, DSI_VM_TIMING2); 2922 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 2923 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 2924 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 2925 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 2926 dsi_write_reg(dsi, DSI_VM_TIMING2, r); 2927 2928 r = dsi_read_reg(dsi, DSI_VM_TIMING3); 2929 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ 2930 r = FLD_MOD(r, tl, 31, 16); /* TL */ 2931 dsi_write_reg(dsi, DSI_VM_TIMING3, r); 2932 } 2933 } 2934 2935 static int dsi_configure_pins(struct dsi_data *dsi, 2936 int num_pins, const u32 *pins) 2937 { 2938 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 2939 int num_lanes; 2940 int i; 2941 2942 static const enum dsi_lane_function functions[] = { 2943 DSI_LANE_CLK, 2944 DSI_LANE_DATA1, 2945 DSI_LANE_DATA2, 2946 DSI_LANE_DATA3, 2947 DSI_LANE_DATA4, 2948 }; 2949 2950 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 2951 || num_pins % 2 != 0) 2952 return -EINVAL; 2953 2954 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 2955 lanes[i].function = DSI_LANE_UNUSED; 2956 2957 num_lanes = 0; 2958 2959 for (i = 0; i < num_pins; i += 2) { 2960 u8 lane, pol; 2961 u32 dx, dy; 2962 2963 dx = pins[i]; 2964 dy = pins[i + 1]; 2965 2966 if (dx >= dsi->num_lanes_supported * 2) 2967 return -EINVAL; 2968 2969 if (dy >= dsi->num_lanes_supported * 2) 2970 return -EINVAL; 2971 2972 if (dx & 1) { 2973 if (dy != dx - 1) 2974 return -EINVAL; 2975 pol = 1; 2976 } else { 2977 if (dy != dx + 1) 2978 return -EINVAL; 2979 pol = 0; 2980 } 2981 2982 lane = dx / 2; 2983 2984 lanes[lane].function = functions[i / 2]; 2985 lanes[lane].polarity = pol; 2986 num_lanes++; 2987 } 2988 2989 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 2990 dsi->num_lanes_used = num_lanes; 2991 2992 return 0; 2993 } 2994 2995 static int dsi_enable_video_mode(struct dsi_data *dsi, int vc) 2996 { 2997 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2998 u8 data_type; 2999 u16 word_count; 3000 3001 switch (dsi->pix_fmt) { 3002 case MIPI_DSI_FMT_RGB888: 3003 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3004 break; 3005 case MIPI_DSI_FMT_RGB666: 3006 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3007 break; 3008 case MIPI_DSI_FMT_RGB666_PACKED: 3009 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3010 break; 3011 case MIPI_DSI_FMT_RGB565: 3012 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3013 break; 3014 default: 3015 return -EINVAL; 3016 } 3017 3018 dsi_if_enable(dsi, false); 3019 dsi_vc_enable(dsi, vc, false); 3020 3021 /* MODE, 1 = video mode */ 3022 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 4, 4); 3023 3024 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); 3025 3026 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, data_type, 3027 word_count, 0); 3028 3029 dsi_vc_enable(dsi, vc, true); 3030 dsi_if_enable(dsi, true); 3031 3032 return 0; 3033 } 3034 3035 static void dsi_disable_video_mode(struct dsi_data *dsi, int vc) 3036 { 3037 dsi_if_enable(dsi, false); 3038 dsi_vc_enable(dsi, vc, false); 3039 3040 /* MODE, 0 = command mode */ 3041 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 0, 4, 4); 3042 3043 dsi_vc_enable(dsi, vc, true); 3044 dsi_if_enable(dsi, true); 3045 } 3046 3047 static void dsi_enable_video_output(struct omap_dss_device *dssdev, int vc) 3048 { 3049 struct dsi_data *dsi = to_dsi_data(dssdev); 3050 int r; 3051 3052 r = dsi_init_dispc(dsi); 3053 if (r) { 3054 dev_err(dsi->dev, "failed to init dispc!\n"); 3055 return; 3056 } 3057 3058 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3059 r = dsi_enable_video_mode(dsi, vc); 3060 if (r) 3061 goto err_video_mode; 3062 } 3063 3064 r = dss_mgr_enable(&dsi->output); 3065 if (r) 3066 goto err_mgr_enable; 3067 3068 return; 3069 3070 err_mgr_enable: 3071 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3072 dsi_if_enable(dsi, false); 3073 dsi_vc_enable(dsi, vc, false); 3074 } 3075 err_video_mode: 3076 dsi_uninit_dispc(dsi); 3077 dev_err(dsi->dev, "failed to enable DSI encoder!\n"); 3078 return; 3079 } 3080 3081 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int vc) 3082 { 3083 struct dsi_data *dsi = to_dsi_data(dssdev); 3084 3085 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) 3086 dsi_disable_video_mode(dsi, vc); 3087 3088 dss_mgr_disable(&dsi->output); 3089 3090 dsi_uninit_dispc(dsi); 3091 } 3092 3093 static void dsi_update_screen_dispc(struct dsi_data *dsi) 3094 { 3095 unsigned int bytespp; 3096 unsigned int bytespl; 3097 unsigned int bytespf; 3098 unsigned int total_len; 3099 unsigned int packet_payload; 3100 unsigned int packet_len; 3101 u32 l; 3102 int r; 3103 const unsigned vc = dsi->update_vc; 3104 const unsigned int line_buf_size = dsi->line_buffer_size; 3105 u16 w = dsi->vm.hactive; 3106 u16 h = dsi->vm.vactive; 3107 3108 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3109 3110 bytespp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8; 3111 bytespl = w * bytespp; 3112 bytespf = bytespl * h; 3113 3114 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3115 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3116 3117 if (bytespf < line_buf_size) 3118 packet_payload = bytespf; 3119 else 3120 packet_payload = (line_buf_size) / bytespl * bytespl; 3121 3122 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3123 total_len = (bytespf / packet_payload) * packet_len; 3124 3125 if (bytespf % packet_payload) 3126 total_len += (bytespf % packet_payload) + 1; 3127 3128 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3129 dsi_write_reg(dsi, DSI_VC_TE(vc), l); 3130 3131 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, MIPI_DSI_DCS_LONG_WRITE, 3132 packet_len, 0); 3133 3134 if (dsi->te_enabled) 3135 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3136 else 3137 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3138 dsi_write_reg(dsi, DSI_VC_TE(vc), l); 3139 3140 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3141 * because DSS interrupts are not capable of waking up the CPU and the 3142 * framedone interrupt could be delayed for quite a long time. I think 3143 * the same goes for any DSS interrupts, but for some reason I have not 3144 * seen the problem anywhere else than here. 3145 */ 3146 dispc_disable_sidle(dsi->dss->dispc); 3147 3148 dsi_perf_mark_start(dsi); 3149 3150 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3151 msecs_to_jiffies(250)); 3152 BUG_ON(r == 0); 3153 3154 dss_mgr_start_update(&dsi->output); 3155 3156 if (dsi->te_enabled) { 3157 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3158 * for TE is longer than the timer allows */ 3159 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3160 3161 dsi_vc_send_bta(dsi, vc); 3162 3163 #ifdef DSI_CATCH_MISSING_TE 3164 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3165 #endif 3166 } 3167 } 3168 3169 #ifdef DSI_CATCH_MISSING_TE 3170 static void dsi_te_timeout(struct timer_list *unused) 3171 { 3172 DSSERR("TE not received for 250ms!\n"); 3173 } 3174 #endif 3175 3176 static void dsi_handle_framedone(struct dsi_data *dsi, int error) 3177 { 3178 /* SIDLEMODE back to smart-idle */ 3179 dispc_enable_sidle(dsi->dss->dispc); 3180 3181 if (dsi->te_enabled) { 3182 /* enable LP_RX_TO again after the TE */ 3183 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 3184 } 3185 3186 dsi_bus_unlock(dsi); 3187 3188 if (!error) 3189 dsi_perf_show(dsi, "DISPC"); 3190 } 3191 3192 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 3193 { 3194 struct dsi_data *dsi = container_of(work, struct dsi_data, 3195 framedone_timeout_work.work); 3196 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 3197 * 250ms which would conflict with this timeout work. What should be 3198 * done is first cancel the transfer on the HW, and then cancel the 3199 * possibly scheduled framedone work. However, cancelling the transfer 3200 * on the HW is buggy, and would probably require resetting the whole 3201 * DSI */ 3202 3203 DSSERR("Framedone not received for 250ms!\n"); 3204 3205 dsi_handle_framedone(dsi, -ETIMEDOUT); 3206 } 3207 3208 static void dsi_framedone_irq_callback(void *data) 3209 { 3210 struct dsi_data *dsi = data; 3211 3212 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 3213 * turns itself off. However, DSI still has the pixels in its buffers, 3214 * and is sending the data. 3215 */ 3216 3217 cancel_delayed_work(&dsi->framedone_timeout_work); 3218 3219 DSSDBG("Framedone received!\n"); 3220 3221 dsi_handle_framedone(dsi, 0); 3222 } 3223 3224 static int _dsi_update(struct dsi_data *dsi) 3225 { 3226 dsi_perf_mark_setup(dsi); 3227 3228 #ifdef DSI_PERF_MEASURE 3229 dsi->update_bytes = dsi->vm.hactive * dsi->vm.vactive * 3230 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8; 3231 #endif 3232 dsi_update_screen_dispc(dsi); 3233 3234 return 0; 3235 } 3236 3237 static int _dsi_send_nop(struct dsi_data *dsi, int vc, int channel) 3238 { 3239 const u8 payload[] = { MIPI_DCS_NOP }; 3240 const struct mipi_dsi_msg msg = { 3241 .channel = channel, 3242 .type = MIPI_DSI_DCS_SHORT_WRITE, 3243 .tx_len = 1, 3244 .tx_buf = payload, 3245 }; 3246 3247 WARN_ON(!dsi_bus_is_locked(dsi)); 3248 3249 return _omap_dsi_host_transfer(dsi, vc, &msg); 3250 } 3251 3252 static int dsi_update_channel(struct omap_dss_device *dssdev, int vc) 3253 { 3254 struct dsi_data *dsi = to_dsi_data(dssdev); 3255 int r; 3256 3257 dsi_bus_lock(dsi); 3258 3259 if (!dsi->video_enabled) { 3260 r = -EIO; 3261 goto err; 3262 } 3263 3264 if (dsi->vm.hactive == 0 || dsi->vm.vactive == 0) { 3265 r = -EINVAL; 3266 goto err; 3267 } 3268 3269 DSSDBG("dsi_update_channel: %d", vc); 3270 3271 /* 3272 * Send NOP between the frames. If we don't send something here, the 3273 * updates stop working. This is probably related to DSI spec stating 3274 * that the DSI host should transition to LP at least once per frame. 3275 */ 3276 r = _dsi_send_nop(dsi, VC_CMD, dsi->dsidev->channel); 3277 if (r < 0) { 3278 DSSWARN("failed to send nop between frames: %d\n", r); 3279 goto err; 3280 } 3281 3282 dsi->update_vc = vc; 3283 3284 if (dsi->te_enabled && dsi->te_gpio) { 3285 schedule_delayed_work(&dsi->te_timeout_work, 3286 msecs_to_jiffies(250)); 3287 atomic_set(&dsi->do_ext_te_update, 1); 3288 } else { 3289 _dsi_update(dsi); 3290 } 3291 3292 return 0; 3293 3294 err: 3295 dsi_bus_unlock(dsi); 3296 return r; 3297 } 3298 3299 static int dsi_update_all(struct omap_dss_device *dssdev) 3300 { 3301 return dsi_update_channel(dssdev, VC_VIDEO); 3302 } 3303 3304 /* Display funcs */ 3305 3306 static int dsi_configure_dispc_clocks(struct dsi_data *dsi) 3307 { 3308 struct dispc_clock_info dispc_cinfo; 3309 int r; 3310 unsigned long fck; 3311 3312 fck = dsi_get_pll_hsdiv_dispc_rate(dsi); 3313 3314 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 3315 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 3316 3317 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); 3318 if (r) { 3319 DSSERR("Failed to calc dispc clocks\n"); 3320 return r; 3321 } 3322 3323 dsi->mgr_config.clock_info = dispc_cinfo; 3324 3325 return 0; 3326 } 3327 3328 static int dsi_init_dispc(struct dsi_data *dsi) 3329 { 3330 enum omap_channel dispc_channel = dsi->output.dispc_channel; 3331 int r; 3332 3333 dss_select_lcd_clk_source(dsi->dss, dispc_channel, dsi->module_id == 0 ? 3334 DSS_CLK_SRC_PLL1_1 : 3335 DSS_CLK_SRC_PLL2_1); 3336 3337 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 3338 r = dss_mgr_register_framedone_handler(&dsi->output, 3339 dsi_framedone_irq_callback, dsi); 3340 if (r) { 3341 DSSERR("can't register FRAMEDONE handler\n"); 3342 goto err; 3343 } 3344 3345 dsi->mgr_config.stallmode = true; 3346 dsi->mgr_config.fifohandcheck = true; 3347 } else { 3348 dsi->mgr_config.stallmode = false; 3349 dsi->mgr_config.fifohandcheck = false; 3350 } 3351 3352 r = dsi_configure_dispc_clocks(dsi); 3353 if (r) 3354 goto err1; 3355 3356 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 3357 dsi->mgr_config.video_port_width = 3358 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 3359 dsi->mgr_config.lcden_sig_polarity = 0; 3360 3361 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config); 3362 3363 return 0; 3364 err1: 3365 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 3366 dss_mgr_unregister_framedone_handler(&dsi->output, 3367 dsi_framedone_irq_callback, dsi); 3368 err: 3369 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); 3370 return r; 3371 } 3372 3373 static void dsi_uninit_dispc(struct dsi_data *dsi) 3374 { 3375 enum omap_channel dispc_channel = dsi->output.dispc_channel; 3376 3377 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 3378 dss_mgr_unregister_framedone_handler(&dsi->output, 3379 dsi_framedone_irq_callback, dsi); 3380 3381 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); 3382 } 3383 3384 static int dsi_configure_dsi_clocks(struct dsi_data *dsi) 3385 { 3386 struct dss_pll_clock_info cinfo; 3387 int r; 3388 3389 cinfo = dsi->user_dsi_cinfo; 3390 3391 r = dss_pll_set_config(&dsi->pll, &cinfo); 3392 if (r) { 3393 DSSERR("Failed to set dsi clocks\n"); 3394 return r; 3395 } 3396 3397 return 0; 3398 } 3399 3400 static void dsi_setup_dsi_vcs(struct dsi_data *dsi) 3401 { 3402 /* Setup VC_CMD for LP and cpu transfers */ 3403 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 9, 9); /* LP */ 3404 3405 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 1, 1); /* SOURCE_L4 */ 3406 dsi->vc[VC_CMD].source = DSI_VC_SOURCE_L4; 3407 3408 /* Setup VC_VIDEO for HS and dispc transfers */ 3409 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 9, 9); /* HS */ 3410 3411 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 1, 1); /* SOURCE_VP */ 3412 dsi->vc[VC_VIDEO].source = DSI_VC_SOURCE_VP; 3413 3414 if ((dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) && 3415 !(dsi->dsidev->mode_flags & MIPI_DSI_MODE_VIDEO)) 3416 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 30, 30); /* DCS_CMD_ENABLE */ 3417 3418 dsi_vc_enable(dsi, VC_CMD, 1); 3419 dsi_vc_enable(dsi, VC_VIDEO, 1); 3420 3421 dsi_if_enable(dsi, 1); 3422 3423 dsi_force_tx_stop_mode_io(dsi); 3424 3425 /* start the DDR clock by sending a NULL packet */ 3426 if (!(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 3427 dsi_vc_send_null(dsi, VC_CMD, dsi->dsidev->channel); 3428 } 3429 3430 static int dsi_init_dsi(struct dsi_data *dsi) 3431 { 3432 int r; 3433 3434 r = dss_pll_enable(&dsi->pll); 3435 if (r) 3436 return r; 3437 3438 r = dsi_configure_dsi_clocks(dsi); 3439 if (r) 3440 goto err0; 3441 3442 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, 3443 dsi->module_id == 0 ? 3444 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2); 3445 3446 DSSDBG("PLL OK\n"); 3447 3448 if (!dsi->vdds_dsi_enabled) { 3449 r = regulator_enable(dsi->vdds_dsi_reg); 3450 if (r) 3451 goto err1; 3452 3453 dsi->vdds_dsi_enabled = true; 3454 } 3455 3456 r = dsi_cio_init(dsi); 3457 if (r) 3458 goto err2; 3459 3460 _dsi_print_reset_status(dsi); 3461 3462 dsi_proto_timings(dsi); 3463 dsi_set_lp_clk_divisor(dsi); 3464 3465 if (1) 3466 _dsi_print_reset_status(dsi); 3467 3468 r = dsi_proto_config(dsi); 3469 if (r) 3470 goto err3; 3471 3472 dsi_setup_dsi_vcs(dsi); 3473 3474 return 0; 3475 err3: 3476 dsi_cio_uninit(dsi); 3477 err2: 3478 regulator_disable(dsi->vdds_dsi_reg); 3479 dsi->vdds_dsi_enabled = false; 3480 err1: 3481 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 3482 err0: 3483 dss_pll_disable(&dsi->pll); 3484 3485 return r; 3486 } 3487 3488 static void dsi_uninit_dsi(struct dsi_data *dsi) 3489 { 3490 /* disable interface */ 3491 dsi_if_enable(dsi, 0); 3492 dsi_vc_enable(dsi, 0, 0); 3493 dsi_vc_enable(dsi, 1, 0); 3494 dsi_vc_enable(dsi, 2, 0); 3495 dsi_vc_enable(dsi, 3, 0); 3496 3497 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 3498 dsi_cio_uninit(dsi); 3499 dss_pll_disable(&dsi->pll); 3500 3501 regulator_disable(dsi->vdds_dsi_reg); 3502 dsi->vdds_dsi_enabled = false; 3503 } 3504 3505 static void dsi_enable(struct dsi_data *dsi) 3506 { 3507 int r; 3508 3509 WARN_ON(!dsi_bus_is_locked(dsi)); 3510 3511 if (WARN_ON(dsi->iface_enabled)) 3512 return; 3513 3514 mutex_lock(&dsi->lock); 3515 3516 r = dsi_runtime_get(dsi); 3517 if (r) 3518 goto err_get_dsi; 3519 3520 _dsi_initialize_irq(dsi); 3521 3522 r = dsi_init_dsi(dsi); 3523 if (r) 3524 goto err_init_dsi; 3525 3526 dsi->iface_enabled = true; 3527 3528 mutex_unlock(&dsi->lock); 3529 3530 return; 3531 3532 err_init_dsi: 3533 dsi_runtime_put(dsi); 3534 err_get_dsi: 3535 mutex_unlock(&dsi->lock); 3536 DSSDBG("dsi_enable FAILED\n"); 3537 } 3538 3539 static void dsi_disable(struct dsi_data *dsi) 3540 { 3541 WARN_ON(!dsi_bus_is_locked(dsi)); 3542 3543 if (WARN_ON(!dsi->iface_enabled)) 3544 return; 3545 3546 mutex_lock(&dsi->lock); 3547 3548 dsi_sync_vc(dsi, 0); 3549 dsi_sync_vc(dsi, 1); 3550 dsi_sync_vc(dsi, 2); 3551 dsi_sync_vc(dsi, 3); 3552 3553 dsi_uninit_dsi(dsi); 3554 3555 dsi_runtime_put(dsi); 3556 3557 dsi->iface_enabled = false; 3558 3559 mutex_unlock(&dsi->lock); 3560 } 3561 3562 static int dsi_enable_te(struct dsi_data *dsi, bool enable) 3563 { 3564 dsi->te_enabled = enable; 3565 3566 if (dsi->te_gpio) { 3567 if (enable) 3568 enable_irq(dsi->te_irq); 3569 else 3570 disable_irq(dsi->te_irq); 3571 } 3572 3573 return 0; 3574 } 3575 3576 #ifdef PRINT_VERBOSE_VM_TIMINGS 3577 static void print_dsi_vm(const char *str, 3578 const struct omap_dss_dsi_videomode_timings *t) 3579 { 3580 unsigned long byteclk = t->hsclk / 4; 3581 int bl, wc, pps, tot; 3582 3583 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 3584 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 3585 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 3586 tot = bl + pps; 3587 3588 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 3589 3590 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 3591 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 3592 str, 3593 byteclk, 3594 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 3595 bl, pps, tot, 3596 TO_DSI_T(t->hss), 3597 TO_DSI_T(t->hsa), 3598 TO_DSI_T(t->hse), 3599 TO_DSI_T(t->hbp), 3600 TO_DSI_T(pps), 3601 TO_DSI_T(t->hfp), 3602 3603 TO_DSI_T(bl), 3604 TO_DSI_T(pps), 3605 3606 TO_DSI_T(tot)); 3607 #undef TO_DSI_T 3608 } 3609 3610 static void print_dispc_vm(const char *str, const struct videomode *vm) 3611 { 3612 unsigned long pck = vm->pixelclock; 3613 int hact, bl, tot; 3614 3615 hact = vm->hactive; 3616 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; 3617 tot = hact + bl; 3618 3619 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 3620 3621 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 3622 "%u/%u/%u/%u = %u + %u = %u\n", 3623 str, 3624 pck, 3625 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, 3626 bl, hact, tot, 3627 TO_DISPC_T(vm->hsync_len), 3628 TO_DISPC_T(vm->hback_porch), 3629 TO_DISPC_T(hact), 3630 TO_DISPC_T(vm->hfront_porch), 3631 TO_DISPC_T(bl), 3632 TO_DISPC_T(hact), 3633 TO_DISPC_T(tot)); 3634 #undef TO_DISPC_T 3635 } 3636 3637 /* note: this is not quite accurate */ 3638 static void print_dsi_dispc_vm(const char *str, 3639 const struct omap_dss_dsi_videomode_timings *t) 3640 { 3641 struct videomode vm = { 0 }; 3642 unsigned long byteclk = t->hsclk / 4; 3643 unsigned long pck; 3644 u64 dsi_tput; 3645 int dsi_hact, dsi_htot; 3646 3647 dsi_tput = (u64)byteclk * t->ndl * 8; 3648 pck = (u32)div64_u64(dsi_tput, t->bitspp); 3649 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 3650 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 3651 3652 vm.pixelclock = pck; 3653 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 3654 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); 3655 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); 3656 vm.hactive = t->hact; 3657 3658 print_dispc_vm(str, &vm); 3659 } 3660 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 3661 3662 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 3663 unsigned long pck, void *data) 3664 { 3665 struct dsi_clk_calc_ctx *ctx = data; 3666 struct videomode *vm = &ctx->vm; 3667 3668 ctx->dispc_cinfo.lck_div = lckd; 3669 ctx->dispc_cinfo.pck_div = pckd; 3670 ctx->dispc_cinfo.lck = lck; 3671 ctx->dispc_cinfo.pck = pck; 3672 3673 *vm = *ctx->config->vm; 3674 vm->pixelclock = pck; 3675 vm->hactive = ctx->config->vm->hactive; 3676 vm->vactive = ctx->config->vm->vactive; 3677 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; 3678 vm->vfront_porch = vm->vback_porch = 0; 3679 3680 return true; 3681 } 3682 3683 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 3684 void *data) 3685 { 3686 struct dsi_clk_calc_ctx *ctx = data; 3687 3688 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 3689 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 3690 3691 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 3692 ctx->req_pck_min, ctx->req_pck_max, 3693 dsi_cm_calc_dispc_cb, ctx); 3694 } 3695 3696 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 3697 unsigned long clkdco, void *data) 3698 { 3699 struct dsi_clk_calc_ctx *ctx = data; 3700 struct dsi_data *dsi = ctx->dsi; 3701 3702 ctx->dsi_cinfo.n = n; 3703 ctx->dsi_cinfo.m = m; 3704 ctx->dsi_cinfo.fint = fint; 3705 ctx->dsi_cinfo.clkdco = clkdco; 3706 3707 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 3708 dsi->data->max_fck_freq, 3709 dsi_cm_calc_hsdiv_cb, ctx); 3710 } 3711 3712 static bool dsi_cm_calc(struct dsi_data *dsi, 3713 const struct omap_dss_dsi_config *cfg, 3714 struct dsi_clk_calc_ctx *ctx) 3715 { 3716 unsigned long clkin; 3717 int bitspp, ndl; 3718 unsigned long pll_min, pll_max; 3719 unsigned long pck, txbyteclk; 3720 3721 clkin = clk_get_rate(dsi->pll.clkin); 3722 bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); 3723 ndl = dsi->num_lanes_used - 1; 3724 3725 /* 3726 * Here we should calculate minimum txbyteclk to be able to send the 3727 * frame in time, and also to handle TE. That's not very simple, though, 3728 * especially as we go to LP between each pixel packet due to HW 3729 * "feature". So let's just estimate very roughly and multiply by 1.5. 3730 */ 3731 pck = cfg->vm->pixelclock; 3732 pck = pck * 3 / 2; 3733 txbyteclk = pck * bitspp / 8 / ndl; 3734 3735 memset(ctx, 0, sizeof(*ctx)); 3736 ctx->dsi = dsi; 3737 ctx->pll = &dsi->pll; 3738 ctx->config = cfg; 3739 ctx->req_pck_min = pck; 3740 ctx->req_pck_nom = pck; 3741 ctx->req_pck_max = pck * 3 / 2; 3742 3743 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 3744 pll_max = cfg->hs_clk_max * 4; 3745 3746 return dss_pll_calc_a(ctx->pll, clkin, 3747 pll_min, pll_max, 3748 dsi_cm_calc_pll_cb, ctx); 3749 } 3750 3751 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 3752 { 3753 struct dsi_data *dsi = ctx->dsi; 3754 const struct omap_dss_dsi_config *cfg = ctx->config; 3755 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); 3756 int ndl = dsi->num_lanes_used - 1; 3757 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 3758 unsigned long byteclk = hsclk / 4; 3759 3760 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 3761 int xres; 3762 int panel_htot, panel_hbl; /* pixels */ 3763 int dispc_htot, dispc_hbl; /* pixels */ 3764 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 3765 int hfp, hsa, hbp; 3766 const struct videomode *req_vm; 3767 struct videomode *dispc_vm; 3768 struct omap_dss_dsi_videomode_timings *dsi_vm; 3769 u64 dsi_tput, dispc_tput; 3770 3771 dsi_tput = (u64)byteclk * ndl * 8; 3772 3773 req_vm = cfg->vm; 3774 req_pck_min = ctx->req_pck_min; 3775 req_pck_max = ctx->req_pck_max; 3776 req_pck_nom = ctx->req_pck_nom; 3777 3778 dispc_pck = ctx->dispc_cinfo.pck; 3779 dispc_tput = (u64)dispc_pck * bitspp; 3780 3781 xres = req_vm->hactive; 3782 3783 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + 3784 req_vm->hsync_len; 3785 panel_htot = xres + panel_hbl; 3786 3787 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 3788 3789 /* 3790 * When there are no line buffers, DISPC and DSI must have the 3791 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 3792 */ 3793 if (dsi->line_buffer_size < xres * bitspp / 8) { 3794 if (dispc_tput != dsi_tput) 3795 return false; 3796 } else { 3797 if (dispc_tput < dsi_tput) 3798 return false; 3799 } 3800 3801 /* DSI tput must be over the min requirement */ 3802 if (dsi_tput < (u64)bitspp * req_pck_min) 3803 return false; 3804 3805 /* When non-burst mode, DSI tput must be below max requirement. */ 3806 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 3807 if (dsi_tput > (u64)bitspp * req_pck_max) 3808 return false; 3809 } 3810 3811 hss = DIV_ROUND_UP(4, ndl); 3812 3813 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 3814 if (ndl == 3 && req_vm->hsync_len == 0) 3815 hse = 1; 3816 else 3817 hse = DIV_ROUND_UP(4, ndl); 3818 } else { 3819 hse = 0; 3820 } 3821 3822 /* DSI htot to match the panel's nominal pck */ 3823 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 3824 3825 /* fail if there would be no time for blanking */ 3826 if (dsi_htot < hss + hse + dsi_hact) 3827 return false; 3828 3829 /* total DSI blanking needed to achieve panel's TL */ 3830 dsi_hbl = dsi_htot - dsi_hact; 3831 3832 /* DISPC htot to match the DSI TL */ 3833 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 3834 3835 /* verify that the DSI and DISPC TLs are the same */ 3836 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 3837 return false; 3838 3839 dispc_hbl = dispc_htot - xres; 3840 3841 /* setup DSI videomode */ 3842 3843 dsi_vm = &ctx->dsi_vm; 3844 memset(dsi_vm, 0, sizeof(*dsi_vm)); 3845 3846 dsi_vm->hsclk = hsclk; 3847 3848 dsi_vm->ndl = ndl; 3849 dsi_vm->bitspp = bitspp; 3850 3851 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 3852 hsa = 0; 3853 } else if (ndl == 3 && req_vm->hsync_len == 0) { 3854 hsa = 0; 3855 } else { 3856 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); 3857 hsa = max(hsa - hse, 1); 3858 } 3859 3860 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); 3861 hbp = max(hbp, 1); 3862 3863 hfp = dsi_hbl - (hss + hsa + hse + hbp); 3864 if (hfp < 1) { 3865 int t; 3866 /* we need to take cycles from hbp */ 3867 3868 t = 1 - hfp; 3869 hbp = max(hbp - t, 1); 3870 hfp = dsi_hbl - (hss + hsa + hse + hbp); 3871 3872 if (hfp < 1 && hsa > 0) { 3873 /* we need to take cycles from hsa */ 3874 t = 1 - hfp; 3875 hsa = max(hsa - t, 1); 3876 hfp = dsi_hbl - (hss + hsa + hse + hbp); 3877 } 3878 } 3879 3880 if (hfp < 1) 3881 return false; 3882 3883 dsi_vm->hss = hss; 3884 dsi_vm->hsa = hsa; 3885 dsi_vm->hse = hse; 3886 dsi_vm->hbp = hbp; 3887 dsi_vm->hact = xres; 3888 dsi_vm->hfp = hfp; 3889 3890 dsi_vm->vsa = req_vm->vsync_len; 3891 dsi_vm->vbp = req_vm->vback_porch; 3892 dsi_vm->vact = req_vm->vactive; 3893 dsi_vm->vfp = req_vm->vfront_porch; 3894 3895 dsi_vm->trans_mode = cfg->trans_mode; 3896 3897 dsi_vm->blanking_mode = 0; 3898 dsi_vm->hsa_blanking_mode = 1; 3899 dsi_vm->hfp_blanking_mode = 1; 3900 dsi_vm->hbp_blanking_mode = 1; 3901 3902 dsi_vm->window_sync = 4; 3903 3904 /* setup DISPC videomode */ 3905 3906 dispc_vm = &ctx->vm; 3907 *dispc_vm = *req_vm; 3908 dispc_vm->pixelclock = dispc_pck; 3909 3910 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 3911 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, 3912 req_pck_nom); 3913 hsa = max(hsa, 1); 3914 } else { 3915 hsa = 1; 3916 } 3917 3918 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); 3919 hbp = max(hbp, 1); 3920 3921 hfp = dispc_hbl - hsa - hbp; 3922 if (hfp < 1) { 3923 int t; 3924 /* we need to take cycles from hbp */ 3925 3926 t = 1 - hfp; 3927 hbp = max(hbp - t, 1); 3928 hfp = dispc_hbl - hsa - hbp; 3929 3930 if (hfp < 1) { 3931 /* we need to take cycles from hsa */ 3932 t = 1 - hfp; 3933 hsa = max(hsa - t, 1); 3934 hfp = dispc_hbl - hsa - hbp; 3935 } 3936 } 3937 3938 if (hfp < 1) 3939 return false; 3940 3941 dispc_vm->hfront_porch = hfp; 3942 dispc_vm->hsync_len = hsa; 3943 dispc_vm->hback_porch = hbp; 3944 3945 return true; 3946 } 3947 3948 3949 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 3950 unsigned long pck, void *data) 3951 { 3952 struct dsi_clk_calc_ctx *ctx = data; 3953 3954 ctx->dispc_cinfo.lck_div = lckd; 3955 ctx->dispc_cinfo.pck_div = pckd; 3956 ctx->dispc_cinfo.lck = lck; 3957 ctx->dispc_cinfo.pck = pck; 3958 3959 if (dsi_vm_calc_blanking(ctx) == false) 3960 return false; 3961 3962 #ifdef PRINT_VERBOSE_VM_TIMINGS 3963 print_dispc_vm("dispc", &ctx->vm); 3964 print_dsi_vm("dsi ", &ctx->dsi_vm); 3965 print_dispc_vm("req ", ctx->config->vm); 3966 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 3967 #endif 3968 3969 return true; 3970 } 3971 3972 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 3973 void *data) 3974 { 3975 struct dsi_clk_calc_ctx *ctx = data; 3976 unsigned long pck_max; 3977 3978 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 3979 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 3980 3981 /* 3982 * In burst mode we can let the dispc pck be arbitrarily high, but it 3983 * limits our scaling abilities. So for now, don't aim too high. 3984 */ 3985 3986 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 3987 pck_max = ctx->req_pck_max + 10000000; 3988 else 3989 pck_max = ctx->req_pck_max; 3990 3991 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 3992 ctx->req_pck_min, pck_max, 3993 dsi_vm_calc_dispc_cb, ctx); 3994 } 3995 3996 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 3997 unsigned long clkdco, void *data) 3998 { 3999 struct dsi_clk_calc_ctx *ctx = data; 4000 struct dsi_data *dsi = ctx->dsi; 4001 4002 ctx->dsi_cinfo.n = n; 4003 ctx->dsi_cinfo.m = m; 4004 ctx->dsi_cinfo.fint = fint; 4005 ctx->dsi_cinfo.clkdco = clkdco; 4006 4007 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4008 dsi->data->max_fck_freq, 4009 dsi_vm_calc_hsdiv_cb, ctx); 4010 } 4011 4012 static bool dsi_vm_calc(struct dsi_data *dsi, 4013 const struct omap_dss_dsi_config *cfg, 4014 struct dsi_clk_calc_ctx *ctx) 4015 { 4016 const struct videomode *vm = cfg->vm; 4017 unsigned long clkin; 4018 unsigned long pll_min; 4019 unsigned long pll_max; 4020 int ndl = dsi->num_lanes_used - 1; 4021 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); 4022 unsigned long byteclk_min; 4023 4024 clkin = clk_get_rate(dsi->pll.clkin); 4025 4026 memset(ctx, 0, sizeof(*ctx)); 4027 ctx->dsi = dsi; 4028 ctx->pll = &dsi->pll; 4029 ctx->config = cfg; 4030 4031 /* these limits should come from the panel driver */ 4032 ctx->req_pck_min = vm->pixelclock - 1000; 4033 ctx->req_pck_nom = vm->pixelclock; 4034 ctx->req_pck_max = vm->pixelclock + 1000; 4035 4036 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4037 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4038 4039 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4040 pll_max = cfg->hs_clk_max * 4; 4041 } else { 4042 unsigned long byteclk_max; 4043 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4044 ndl * 8); 4045 4046 pll_max = byteclk_max * 4 * 4; 4047 } 4048 4049 return dss_pll_calc_a(ctx->pll, clkin, 4050 pll_min, pll_max, 4051 dsi_vm_calc_pll_cb, ctx); 4052 } 4053 4054 static bool dsi_is_video_mode(struct omap_dss_device *dssdev) 4055 { 4056 struct dsi_data *dsi = to_dsi_data(dssdev); 4057 4058 return dsi->mode == OMAP_DSS_DSI_VIDEO_MODE; 4059 } 4060 4061 static int __dsi_calc_config(struct dsi_data *dsi, 4062 const struct drm_display_mode *mode, 4063 struct dsi_clk_calc_ctx *ctx) 4064 { 4065 struct omap_dss_dsi_config cfg = dsi->config; 4066 struct videomode vm; 4067 bool ok; 4068 int r; 4069 4070 drm_display_mode_to_videomode(mode, &vm); 4071 4072 cfg.vm = &vm; 4073 cfg.mode = dsi->mode; 4074 cfg.pixel_format = dsi->pix_fmt; 4075 4076 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) 4077 ok = dsi_vm_calc(dsi, &cfg, ctx); 4078 else 4079 ok = dsi_cm_calc(dsi, &cfg, ctx); 4080 4081 if (!ok) 4082 return -EINVAL; 4083 4084 dsi_pll_calc_dsi_fck(dsi, &ctx->dsi_cinfo); 4085 4086 r = dsi_lp_clock_calc(ctx->dsi_cinfo.clkout[HSDIV_DSI], 4087 cfg.lp_clk_min, cfg.lp_clk_max, &ctx->lp_cinfo); 4088 if (r) 4089 return r; 4090 4091 return 0; 4092 } 4093 4094 static int dsi_set_config(struct omap_dss_device *dssdev, 4095 const struct drm_display_mode *mode) 4096 { 4097 struct dsi_data *dsi = to_dsi_data(dssdev); 4098 struct dsi_clk_calc_ctx ctx; 4099 int r; 4100 4101 mutex_lock(&dsi->lock); 4102 4103 r = __dsi_calc_config(dsi, mode, &ctx); 4104 if (r) { 4105 DSSERR("failed to find suitable DSI clock settings\n"); 4106 goto err; 4107 } 4108 4109 dsi->user_lp_cinfo = ctx.lp_cinfo; 4110 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4111 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4112 4113 dsi->vm = ctx.vm; 4114 4115 /* 4116 * override interlace, logic level and edge related parameters in 4117 * videomode with default values 4118 */ 4119 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; 4120 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 4121 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 4122 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 4123 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 4124 /* 4125 * HACK: These flags should be handled through the omap_dss_device bus 4126 * flags, but this will only be possible when the DSI encoder will be 4127 * converted to the omapdrm-managed encoder model. 4128 */ 4129 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 4130 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 4131 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW; 4132 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH; 4133 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4134 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4135 4136 dss_mgr_set_timings(&dsi->output, &dsi->vm); 4137 4138 dsi->vm_timings = ctx.dsi_vm; 4139 4140 mutex_unlock(&dsi->lock); 4141 4142 return 0; 4143 err: 4144 mutex_unlock(&dsi->lock); 4145 4146 return r; 4147 } 4148 4149 /* 4150 * Return a hardcoded dispc channel for the DSI output. This should work for 4151 * current use cases, but this can be later expanded to either resolve 4152 * the channel in some more dynamic manner, or get the channel as a user 4153 * parameter. 4154 */ 4155 static enum omap_channel dsi_get_dispc_channel(struct dsi_data *dsi) 4156 { 4157 switch (dsi->data->model) { 4158 case DSI_MODEL_OMAP3: 4159 return OMAP_DSS_CHANNEL_LCD; 4160 4161 case DSI_MODEL_OMAP4: 4162 switch (dsi->module_id) { 4163 case 0: 4164 return OMAP_DSS_CHANNEL_LCD; 4165 case 1: 4166 return OMAP_DSS_CHANNEL_LCD2; 4167 default: 4168 DSSWARN("unsupported module id\n"); 4169 return OMAP_DSS_CHANNEL_LCD; 4170 } 4171 4172 case DSI_MODEL_OMAP5: 4173 switch (dsi->module_id) { 4174 case 0: 4175 return OMAP_DSS_CHANNEL_LCD; 4176 case 1: 4177 return OMAP_DSS_CHANNEL_LCD3; 4178 default: 4179 DSSWARN("unsupported module id\n"); 4180 return OMAP_DSS_CHANNEL_LCD; 4181 } 4182 4183 default: 4184 DSSWARN("unsupported DSS version\n"); 4185 return OMAP_DSS_CHANNEL_LCD; 4186 } 4187 } 4188 4189 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, 4190 const struct mipi_dsi_msg *msg) 4191 { 4192 struct omap_dss_device *dssdev = &dsi->output; 4193 int r; 4194 4195 dsi_vc_enable_hs(dssdev, vc, !(msg->flags & MIPI_DSI_MSG_USE_LPM)); 4196 4197 switch (msg->type) { 4198 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 4199 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 4200 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 4201 case MIPI_DSI_GENERIC_LONG_WRITE: 4202 case MIPI_DSI_DCS_SHORT_WRITE: 4203 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 4204 case MIPI_DSI_DCS_LONG_WRITE: 4205 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 4206 case MIPI_DSI_NULL_PACKET: 4207 r = dsi_vc_write_common(dssdev, vc, msg); 4208 break; 4209 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 4210 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 4211 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 4212 r = dsi_vc_generic_read(dssdev, vc, msg); 4213 break; 4214 case MIPI_DSI_DCS_READ: 4215 r = dsi_vc_dcs_read(dssdev, vc, msg); 4216 break; 4217 default: 4218 r = -EINVAL; 4219 break; 4220 } 4221 4222 if (r < 0) 4223 return r; 4224 4225 if (msg->type == MIPI_DSI_DCS_SHORT_WRITE || 4226 msg->type == MIPI_DSI_DCS_SHORT_WRITE_PARAM) { 4227 u8 cmd = ((u8 *)msg->tx_buf)[0]; 4228 4229 if (cmd == MIPI_DCS_SET_TEAR_OFF) 4230 dsi_enable_te(dsi, false); 4231 else if (cmd == MIPI_DCS_SET_TEAR_ON) 4232 dsi_enable_te(dsi, true); 4233 } 4234 4235 return 0; 4236 } 4237 4238 static ssize_t omap_dsi_host_transfer(struct mipi_dsi_host *host, 4239 const struct mipi_dsi_msg *msg) 4240 { 4241 struct dsi_data *dsi = host_to_omap(host); 4242 int r; 4243 int vc = VC_CMD; 4244 4245 dsi_bus_lock(dsi); 4246 4247 if (!dsi->iface_enabled) { 4248 dsi_enable(dsi); 4249 schedule_delayed_work(&dsi->dsi_disable_work, msecs_to_jiffies(2000)); 4250 } 4251 4252 r = _omap_dsi_host_transfer(dsi, vc, msg); 4253 4254 dsi_bus_unlock(dsi); 4255 4256 return r; 4257 } 4258 4259 static int dsi_get_clocks(struct dsi_data *dsi) 4260 { 4261 struct clk *clk; 4262 4263 clk = devm_clk_get(dsi->dev, "fck"); 4264 if (IS_ERR(clk)) { 4265 DSSERR("can't get fck\n"); 4266 return PTR_ERR(clk); 4267 } 4268 4269 dsi->dss_clk = clk; 4270 4271 return 0; 4272 } 4273 4274 static const struct omapdss_dsi_ops dsi_ops = { 4275 .update = dsi_update_all, 4276 .is_video_mode = dsi_is_video_mode, 4277 }; 4278 4279 static irqreturn_t omap_dsi_te_irq_handler(int irq, void *dev_id) 4280 { 4281 struct dsi_data *dsi = (struct dsi_data *)dev_id; 4282 int old; 4283 4284 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0); 4285 if (old) { 4286 cancel_delayed_work(&dsi->te_timeout_work); 4287 _dsi_update(dsi); 4288 } 4289 4290 return IRQ_HANDLED; 4291 } 4292 4293 static void omap_dsi_te_timeout_work_callback(struct work_struct *work) 4294 { 4295 struct dsi_data *dsi = 4296 container_of(work, struct dsi_data, te_timeout_work.work); 4297 int old; 4298 4299 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0); 4300 if (old) { 4301 dev_err(dsi->dev, "TE not received for 250ms!\n"); 4302 _dsi_update(dsi); 4303 } 4304 } 4305 4306 static int omap_dsi_register_te_irq(struct dsi_data *dsi, 4307 struct mipi_dsi_device *client) 4308 { 4309 int err; 4310 int te_irq; 4311 4312 dsi->te_gpio = gpiod_get(&client->dev, "te-gpios", GPIOD_IN); 4313 if (IS_ERR(dsi->te_gpio)) { 4314 err = PTR_ERR(dsi->te_gpio); 4315 4316 if (err == -ENOENT) { 4317 dsi->te_gpio = NULL; 4318 return 0; 4319 } 4320 4321 dev_err(dsi->dev, "Could not get TE gpio: %d\n", err); 4322 return err; 4323 } 4324 4325 te_irq = gpiod_to_irq(dsi->te_gpio); 4326 if (te_irq < 0) { 4327 gpiod_put(dsi->te_gpio); 4328 dsi->te_gpio = NULL; 4329 return -EINVAL; 4330 } 4331 4332 dsi->te_irq = te_irq; 4333 4334 irq_set_status_flags(te_irq, IRQ_NOAUTOEN); 4335 4336 err = request_threaded_irq(te_irq, NULL, omap_dsi_te_irq_handler, 4337 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 4338 "TE", dsi); 4339 if (err) { 4340 dev_err(dsi->dev, "request irq failed with %d\n", err); 4341 gpiod_put(dsi->te_gpio); 4342 dsi->te_gpio = NULL; 4343 return err; 4344 } 4345 4346 INIT_DEFERRABLE_WORK(&dsi->te_timeout_work, 4347 omap_dsi_te_timeout_work_callback); 4348 4349 dev_dbg(dsi->dev, "Using GPIO TE\n"); 4350 4351 return 0; 4352 } 4353 4354 static void omap_dsi_unregister_te_irq(struct dsi_data *dsi) 4355 { 4356 if (dsi->te_gpio) { 4357 free_irq(dsi->te_irq, dsi); 4358 cancel_delayed_work(&dsi->te_timeout_work); 4359 gpiod_put(dsi->te_gpio); 4360 dsi->te_gpio = NULL; 4361 } 4362 } 4363 4364 static int omap_dsi_host_attach(struct mipi_dsi_host *host, 4365 struct mipi_dsi_device *client) 4366 { 4367 struct dsi_data *dsi = host_to_omap(host); 4368 int r; 4369 4370 if (dsi->dsidev) { 4371 DSSERR("dsi client already attached\n"); 4372 return -EBUSY; 4373 } 4374 4375 if (mipi_dsi_pixel_format_to_bpp(client->format) < 0) { 4376 DSSERR("invalid pixel format\n"); 4377 return -EINVAL; 4378 } 4379 4380 atomic_set(&dsi->do_ext_te_update, 0); 4381 4382 if (client->mode_flags & MIPI_DSI_MODE_VIDEO) { 4383 dsi->mode = OMAP_DSS_DSI_VIDEO_MODE; 4384 } else { 4385 r = omap_dsi_register_te_irq(dsi, client); 4386 if (r) 4387 return r; 4388 4389 dsi->mode = OMAP_DSS_DSI_CMD_MODE; 4390 } 4391 4392 dsi->dsidev = client; 4393 dsi->pix_fmt = client->format; 4394 4395 dsi->config.hs_clk_min = 150000000; // TODO: get from client? 4396 dsi->config.hs_clk_max = client->hs_rate; 4397 dsi->config.lp_clk_min = 7000000; // TODO: get from client? 4398 dsi->config.lp_clk_max = client->lp_rate; 4399 4400 if (client->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 4401 dsi->config.trans_mode = OMAP_DSS_DSI_BURST_MODE; 4402 else if (client->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 4403 dsi->config.trans_mode = OMAP_DSS_DSI_PULSE_MODE; 4404 else 4405 dsi->config.trans_mode = OMAP_DSS_DSI_EVENT_MODE; 4406 4407 return 0; 4408 } 4409 4410 static int omap_dsi_host_detach(struct mipi_dsi_host *host, 4411 struct mipi_dsi_device *client) 4412 { 4413 struct dsi_data *dsi = host_to_omap(host); 4414 4415 if (WARN_ON(dsi->dsidev != client)) 4416 return -EINVAL; 4417 4418 cancel_delayed_work_sync(&dsi->dsi_disable_work); 4419 4420 dsi_bus_lock(dsi); 4421 4422 if (dsi->iface_enabled) 4423 dsi_disable(dsi); 4424 4425 dsi_bus_unlock(dsi); 4426 4427 omap_dsi_unregister_te_irq(dsi); 4428 dsi->dsidev = NULL; 4429 return 0; 4430 } 4431 4432 static const struct mipi_dsi_host_ops omap_dsi_host_ops = { 4433 .attach = omap_dsi_host_attach, 4434 .detach = omap_dsi_host_detach, 4435 .transfer = omap_dsi_host_transfer, 4436 }; 4437 4438 /* ----------------------------------------------------------------------------- 4439 * PLL 4440 */ 4441 4442 static const struct dss_pll_ops dsi_pll_ops = { 4443 .enable = dsi_pll_enable, 4444 .disable = dsi_pll_disable, 4445 .set_config = dss_pll_write_config_type_a, 4446 }; 4447 4448 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 4449 .type = DSS_PLL_TYPE_A, 4450 4451 .n_max = (1 << 7) - 1, 4452 .m_max = (1 << 11) - 1, 4453 .mX_max = (1 << 4) - 1, 4454 .fint_min = 750000, 4455 .fint_max = 2100000, 4456 .clkdco_low = 1000000000, 4457 .clkdco_max = 1800000000, 4458 4459 .n_msb = 7, 4460 .n_lsb = 1, 4461 .m_msb = 18, 4462 .m_lsb = 8, 4463 4464 .mX_msb[0] = 22, 4465 .mX_lsb[0] = 19, 4466 .mX_msb[1] = 26, 4467 .mX_lsb[1] = 23, 4468 4469 .has_stopmode = true, 4470 .has_freqsel = true, 4471 .has_selfreqdco = false, 4472 .has_refsel = false, 4473 }; 4474 4475 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 4476 .type = DSS_PLL_TYPE_A, 4477 4478 .n_max = (1 << 8) - 1, 4479 .m_max = (1 << 12) - 1, 4480 .mX_max = (1 << 5) - 1, 4481 .fint_min = 500000, 4482 .fint_max = 2500000, 4483 .clkdco_low = 1000000000, 4484 .clkdco_max = 1800000000, 4485 4486 .n_msb = 8, 4487 .n_lsb = 1, 4488 .m_msb = 20, 4489 .m_lsb = 9, 4490 4491 .mX_msb[0] = 25, 4492 .mX_lsb[0] = 21, 4493 .mX_msb[1] = 30, 4494 .mX_lsb[1] = 26, 4495 4496 .has_stopmode = true, 4497 .has_freqsel = false, 4498 .has_selfreqdco = false, 4499 .has_refsel = false, 4500 }; 4501 4502 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 4503 .type = DSS_PLL_TYPE_A, 4504 4505 .n_max = (1 << 8) - 1, 4506 .m_max = (1 << 12) - 1, 4507 .mX_max = (1 << 5) - 1, 4508 .fint_min = 150000, 4509 .fint_max = 52000000, 4510 .clkdco_low = 1000000000, 4511 .clkdco_max = 1800000000, 4512 4513 .n_msb = 8, 4514 .n_lsb = 1, 4515 .m_msb = 20, 4516 .m_lsb = 9, 4517 4518 .mX_msb[0] = 25, 4519 .mX_lsb[0] = 21, 4520 .mX_msb[1] = 30, 4521 .mX_lsb[1] = 26, 4522 4523 .has_stopmode = true, 4524 .has_freqsel = false, 4525 .has_selfreqdco = true, 4526 .has_refsel = true, 4527 }; 4528 4529 static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi) 4530 { 4531 struct dss_pll *pll = &dsi->pll; 4532 struct clk *clk; 4533 int r; 4534 4535 clk = devm_clk_get(dsi->dev, "sys_clk"); 4536 if (IS_ERR(clk)) { 4537 DSSERR("can't get sys_clk\n"); 4538 return PTR_ERR(clk); 4539 } 4540 4541 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 4542 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 4543 pll->clkin = clk; 4544 pll->base = dsi->pll_base; 4545 pll->hw = dsi->data->pll_hw; 4546 pll->ops = &dsi_pll_ops; 4547 4548 r = dss_pll_register(dss, pll); 4549 if (r) 4550 return r; 4551 4552 return 0; 4553 } 4554 4555 /* ----------------------------------------------------------------------------- 4556 * Component Bind & Unbind 4557 */ 4558 4559 static int dsi_bind(struct device *dev, struct device *master, void *data) 4560 { 4561 struct dss_device *dss = dss_get_device(master); 4562 struct dsi_data *dsi = dev_get_drvdata(dev); 4563 char name[10]; 4564 u32 rev; 4565 int r; 4566 4567 dsi->dss = dss; 4568 4569 dsi_init_pll_data(dss, dsi); 4570 4571 r = dsi_runtime_get(dsi); 4572 if (r) 4573 return r; 4574 4575 rev = dsi_read_reg(dsi, DSI_REVISION); 4576 dev_dbg(dev, "OMAP DSI rev %d.%d\n", 4577 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 4578 4579 dsi->line_buffer_size = dsi_get_line_buf_size(dsi); 4580 4581 dsi_runtime_put(dsi); 4582 4583 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1); 4584 dsi->debugfs.regs = dss_debugfs_create_file(dss, name, 4585 dsi_dump_dsi_regs, dsi); 4586 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 4587 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1); 4588 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name, 4589 dsi_dump_dsi_irqs, dsi); 4590 #endif 4591 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1); 4592 dsi->debugfs.clks = dss_debugfs_create_file(dss, name, 4593 dsi_dump_dsi_clocks, dsi); 4594 4595 return 0; 4596 } 4597 4598 static void dsi_unbind(struct device *dev, struct device *master, void *data) 4599 { 4600 struct dsi_data *dsi = dev_get_drvdata(dev); 4601 4602 dss_debugfs_remove_file(dsi->debugfs.clks); 4603 dss_debugfs_remove_file(dsi->debugfs.irqs); 4604 dss_debugfs_remove_file(dsi->debugfs.regs); 4605 4606 WARN_ON(dsi->scp_clk_refcount > 0); 4607 4608 dss_pll_unregister(&dsi->pll); 4609 } 4610 4611 static const struct component_ops dsi_component_ops = { 4612 .bind = dsi_bind, 4613 .unbind = dsi_unbind, 4614 }; 4615 4616 /* ----------------------------------------------------------------------------- 4617 * DRM Bridge Operations 4618 */ 4619 4620 static int dsi_bridge_attach(struct drm_bridge *bridge, 4621 struct drm_encoder *encoder, 4622 enum drm_bridge_attach_flags flags) 4623 { 4624 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4625 4626 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 4627 return -EINVAL; 4628 4629 return drm_bridge_attach(encoder, dsi->output.next_bridge, 4630 bridge, flags); 4631 } 4632 4633 static enum drm_mode_status 4634 dsi_bridge_mode_valid(struct drm_bridge *bridge, 4635 const struct drm_display_info *info, 4636 const struct drm_display_mode *mode) 4637 { 4638 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4639 struct dsi_clk_calc_ctx ctx; 4640 int r; 4641 4642 mutex_lock(&dsi->lock); 4643 r = __dsi_calc_config(dsi, mode, &ctx); 4644 mutex_unlock(&dsi->lock); 4645 4646 return r ? MODE_CLOCK_RANGE : MODE_OK; 4647 } 4648 4649 static void dsi_bridge_mode_set(struct drm_bridge *bridge, 4650 const struct drm_display_mode *mode, 4651 const struct drm_display_mode *adjusted_mode) 4652 { 4653 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4654 4655 dsi_set_config(&dsi->output, adjusted_mode); 4656 } 4657 4658 static void dsi_bridge_enable(struct drm_bridge *bridge, 4659 struct drm_atomic_commit *commit) 4660 { 4661 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4662 struct omap_dss_device *dssdev = &dsi->output; 4663 4664 cancel_delayed_work_sync(&dsi->dsi_disable_work); 4665 4666 dsi_bus_lock(dsi); 4667 4668 if (!dsi->iface_enabled) 4669 dsi_enable(dsi); 4670 4671 dsi_enable_video_output(dssdev, VC_VIDEO); 4672 4673 dsi->video_enabled = true; 4674 4675 dsi_bus_unlock(dsi); 4676 } 4677 4678 static void dsi_bridge_disable(struct drm_bridge *bridge, 4679 struct drm_atomic_commit *commit) 4680 { 4681 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4682 struct omap_dss_device *dssdev = &dsi->output; 4683 4684 cancel_delayed_work_sync(&dsi->dsi_disable_work); 4685 4686 dsi_bus_lock(dsi); 4687 4688 dsi->video_enabled = false; 4689 4690 dsi_disable_video_output(dssdev, VC_VIDEO); 4691 4692 dsi_disable(dsi); 4693 4694 dsi_bus_unlock(dsi); 4695 } 4696 4697 static const struct drm_bridge_funcs dsi_bridge_funcs = { 4698 .atomic_create_state = drm_atomic_helper_bridge_create_state, 4699 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 4700 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 4701 .attach = dsi_bridge_attach, 4702 .mode_valid = dsi_bridge_mode_valid, 4703 .mode_set = dsi_bridge_mode_set, 4704 .atomic_enable = dsi_bridge_enable, 4705 .atomic_disable = dsi_bridge_disable, 4706 }; 4707 4708 static void dsi_bridge_init(struct dsi_data *dsi) 4709 { 4710 dsi->bridge.of_node = dsi->host.dev->of_node; 4711 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 4712 4713 drm_bridge_add(&dsi->bridge); 4714 } 4715 4716 static void dsi_bridge_cleanup(struct dsi_data *dsi) 4717 { 4718 drm_bridge_remove(&dsi->bridge); 4719 } 4720 4721 /* ----------------------------------------------------------------------------- 4722 * Probe & Remove, Suspend & Resume 4723 */ 4724 4725 static int dsi_init_output(struct dsi_data *dsi) 4726 { 4727 struct omap_dss_device *out = &dsi->output; 4728 int r; 4729 4730 dsi_bridge_init(dsi); 4731 4732 out->dev = dsi->dev; 4733 out->id = dsi->module_id == 0 ? 4734 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 4735 4736 out->type = OMAP_DISPLAY_TYPE_DSI; 4737 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 4738 out->dispc_channel = dsi_get_dispc_channel(dsi); 4739 out->dsi_ops = &dsi_ops; 4740 out->of_port = 0; 4741 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE 4742 | DRM_BUS_FLAG_DE_HIGH 4743 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 4744 4745 r = omapdss_device_init_output(out, &dsi->bridge); 4746 if (r < 0) { 4747 dsi_bridge_cleanup(dsi); 4748 return r; 4749 } 4750 4751 omapdss_device_register(out); 4752 4753 return 0; 4754 } 4755 4756 static void dsi_uninit_output(struct dsi_data *dsi) 4757 { 4758 struct omap_dss_device *out = &dsi->output; 4759 4760 omapdss_device_unregister(out); 4761 omapdss_device_cleanup_output(out); 4762 dsi_bridge_cleanup(dsi); 4763 } 4764 4765 static int dsi_probe_of(struct dsi_data *dsi) 4766 { 4767 struct device_node *node = dsi->dev->of_node; 4768 struct property *prop; 4769 u32 lane_arr[10]; 4770 int len, num_pins; 4771 int r; 4772 struct device_node *ep; 4773 4774 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 4775 if (!ep) 4776 return 0; 4777 4778 prop = of_find_property(ep, "lanes", &len); 4779 if (prop == NULL) { 4780 dev_err(dsi->dev, "failed to find lane data\n"); 4781 r = -EINVAL; 4782 goto err; 4783 } 4784 4785 num_pins = len / sizeof(u32); 4786 4787 if (num_pins < 4 || num_pins % 2 != 0 || 4788 num_pins > dsi->num_lanes_supported * 2) { 4789 dev_err(dsi->dev, "bad number of lanes\n"); 4790 r = -EINVAL; 4791 goto err; 4792 } 4793 4794 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 4795 if (r) { 4796 dev_err(dsi->dev, "failed to read lane data\n"); 4797 goto err; 4798 } 4799 4800 r = dsi_configure_pins(dsi, num_pins, lane_arr); 4801 if (r) { 4802 dev_err(dsi->dev, "failed to configure pins"); 4803 goto err; 4804 } 4805 4806 of_node_put(ep); 4807 4808 return 0; 4809 4810 err: 4811 of_node_put(ep); 4812 return r; 4813 } 4814 4815 static const struct dsi_of_data dsi_of_data_omap34xx = { 4816 .model = DSI_MODEL_OMAP3, 4817 .pll_hw = &dss_omap3_dsi_pll_hw, 4818 .modules = (const struct dsi_module_id_data[]) { 4819 { .address = 0x4804fc00, .id = 0, }, 4820 { }, 4821 }, 4822 .max_fck_freq = 173000000, 4823 .max_pll_lpdiv = (1 << 13) - 1, 4824 .quirks = DSI_QUIRK_REVERSE_TXCLKESC, 4825 }; 4826 4827 static const struct dsi_of_data dsi_of_data_omap36xx = { 4828 .model = DSI_MODEL_OMAP3, 4829 .pll_hw = &dss_omap3_dsi_pll_hw, 4830 .modules = (const struct dsi_module_id_data[]) { 4831 { .address = 0x4804fc00, .id = 0, }, 4832 { }, 4833 }, 4834 .max_fck_freq = 173000000, 4835 .max_pll_lpdiv = (1 << 13) - 1, 4836 .quirks = DSI_QUIRK_PLL_PWR_BUG, 4837 }; 4838 4839 static const struct dsi_of_data dsi_of_data_omap4 = { 4840 .model = DSI_MODEL_OMAP4, 4841 .pll_hw = &dss_omap4_dsi_pll_hw, 4842 .modules = (const struct dsi_module_id_data[]) { 4843 { .address = 0x58004000, .id = 0, }, 4844 { .address = 0x58005000, .id = 1, }, 4845 { }, 4846 }, 4847 .max_fck_freq = 170000000, 4848 .max_pll_lpdiv = (1 << 13) - 1, 4849 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 4850 | DSI_QUIRK_GNQ, 4851 }; 4852 4853 static const struct dsi_of_data dsi_of_data_omap5 = { 4854 .model = DSI_MODEL_OMAP5, 4855 .pll_hw = &dss_omap5_dsi_pll_hw, 4856 .modules = (const struct dsi_module_id_data[]) { 4857 { .address = 0x58004000, .id = 0, }, 4858 { .address = 0x58009000, .id = 1, }, 4859 { }, 4860 }, 4861 .max_fck_freq = 209250000, 4862 .max_pll_lpdiv = (1 << 13) - 1, 4863 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 4864 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC, 4865 }; 4866 4867 static const struct of_device_id dsi_of_match[] = { 4868 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, }, 4869 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, }, 4870 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, }, 4871 {}, 4872 }; 4873 4874 static const struct soc_device_attribute dsi_soc_devices[] = { 4875 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx }, 4876 { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, 4877 { /* sentinel */ } 4878 }; 4879 4880 static void omap_dsi_disable_work_callback(struct work_struct *work) 4881 { 4882 struct dsi_data *dsi = container_of(work, struct dsi_data, dsi_disable_work.work); 4883 4884 dsi_bus_lock(dsi); 4885 4886 if (dsi->iface_enabled && !dsi->video_enabled) 4887 dsi_disable(dsi); 4888 4889 dsi_bus_unlock(dsi); 4890 } 4891 4892 static int dsi_probe(struct platform_device *pdev) 4893 { 4894 const struct soc_device_attribute *soc; 4895 const struct dsi_module_id_data *d; 4896 struct device *dev = &pdev->dev; 4897 struct dsi_data *dsi; 4898 struct resource *dsi_mem; 4899 unsigned int i; 4900 int r; 4901 4902 dsi = devm_drm_bridge_alloc(dev, struct dsi_data, bridge, &dsi_bridge_funcs); 4903 if (IS_ERR(dsi)) 4904 return PTR_ERR(dsi); 4905 4906 dsi->dev = dev; 4907 dev_set_drvdata(dev, dsi); 4908 4909 spin_lock_init(&dsi->irq_lock); 4910 spin_lock_init(&dsi->errors_lock); 4911 dsi->errors = 0; 4912 4913 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 4914 spin_lock_init(&dsi->irq_stats_lock); 4915 dsi->irq_stats.last_reset = jiffies; 4916 #endif 4917 4918 mutex_init(&dsi->lock); 4919 sema_init(&dsi->bus_lock, 1); 4920 4921 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 4922 dsi_framedone_timeout_work_callback); 4923 4924 INIT_DEFERRABLE_WORK(&dsi->dsi_disable_work, omap_dsi_disable_work_callback); 4925 4926 #ifdef DSI_CATCH_MISSING_TE 4927 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); 4928 #endif 4929 4930 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto"); 4931 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem); 4932 if (IS_ERR(dsi->proto_base)) 4933 return PTR_ERR(dsi->proto_base); 4934 4935 dsi->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy"); 4936 if (IS_ERR(dsi->phy_base)) 4937 return PTR_ERR(dsi->phy_base); 4938 4939 dsi->pll_base = devm_platform_ioremap_resource_byname(pdev, "pll"); 4940 if (IS_ERR(dsi->pll_base)) 4941 return PTR_ERR(dsi->pll_base); 4942 4943 dsi->irq = platform_get_irq(pdev, 0); 4944 if (dsi->irq < 0) { 4945 DSSERR("platform_get_irq failed\n"); 4946 return -ENODEV; 4947 } 4948 4949 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler, 4950 IRQF_SHARED, dev_name(dev), dsi); 4951 if (r < 0) { 4952 DSSERR("request_irq failed\n"); 4953 return r; 4954 } 4955 4956 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd"); 4957 if (IS_ERR(dsi->vdds_dsi_reg)) { 4958 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER) 4959 DSSERR("can't get DSI VDD regulator\n"); 4960 return PTR_ERR(dsi->vdds_dsi_reg); 4961 } 4962 4963 soc = soc_device_match(dsi_soc_devices); 4964 if (soc) 4965 dsi->data = soc->data; 4966 else 4967 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; 4968 4969 d = dsi->data->modules; 4970 while (d->address != 0 && d->address != dsi_mem->start) 4971 d++; 4972 4973 if (d->address == 0) { 4974 DSSERR("unsupported DSI module\n"); 4975 return -ENODEV; 4976 } 4977 4978 dsi->module_id = d->id; 4979 4980 if (dsi->data->model == DSI_MODEL_OMAP4 || 4981 dsi->data->model == DSI_MODEL_OMAP5) { 4982 struct device_node *np; 4983 4984 /* 4985 * The OMAP4/5 display DT bindings don't reference the padconf 4986 * syscon. Our only option to retrieve it is to find it by name. 4987 */ 4988 np = of_find_node_by_name(NULL, 4989 dsi->data->model == DSI_MODEL_OMAP4 ? 4990 "omap4_padconf_global" : "omap5_padconf_global"); 4991 if (!np) 4992 return -ENODEV; 4993 4994 dsi->syscon = syscon_node_to_regmap(np); 4995 of_node_put(np); 4996 } 4997 4998 /* DSI VCs initialization */ 4999 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) 5000 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5001 5002 r = dsi_get_clocks(dsi); 5003 if (r) 5004 return r; 5005 5006 pm_runtime_enable(dev); 5007 5008 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5009 * of data to 3 by default */ 5010 if (dsi->data->quirks & DSI_QUIRK_GNQ) { 5011 dsi_runtime_get(dsi); 5012 /* NB_DATA_LANES */ 5013 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); 5014 dsi_runtime_put(dsi); 5015 } else { 5016 dsi->num_lanes_supported = 3; 5017 } 5018 5019 dsi->host.ops = &omap_dsi_host_ops; 5020 dsi->host.dev = &pdev->dev; 5021 5022 r = dsi_probe_of(dsi); 5023 if (r) { 5024 DSSERR("Invalid DSI DT data\n"); 5025 goto err_pm_disable; 5026 } 5027 5028 r = mipi_dsi_host_register(&dsi->host); 5029 if (r < 0) { 5030 dev_err(&pdev->dev, "failed to register DSI host: %d\n", r); 5031 goto err_pm_disable; 5032 } 5033 5034 r = dsi_init_output(dsi); 5035 if (r) 5036 goto err_dsi_host_unregister; 5037 5038 r = component_add(&pdev->dev, &dsi_component_ops); 5039 if (r) 5040 goto err_uninit_output; 5041 5042 return 0; 5043 5044 err_uninit_output: 5045 dsi_uninit_output(dsi); 5046 err_dsi_host_unregister: 5047 mipi_dsi_host_unregister(&dsi->host); 5048 err_pm_disable: 5049 pm_runtime_disable(dev); 5050 return r; 5051 } 5052 5053 static void dsi_remove(struct platform_device *pdev) 5054 { 5055 struct dsi_data *dsi = platform_get_drvdata(pdev); 5056 5057 component_del(&pdev->dev, &dsi_component_ops); 5058 5059 dsi_uninit_output(dsi); 5060 5061 mipi_dsi_host_unregister(&dsi->host); 5062 5063 pm_runtime_disable(&pdev->dev); 5064 5065 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5066 regulator_disable(dsi->vdds_dsi_reg); 5067 dsi->vdds_dsi_enabled = false; 5068 } 5069 } 5070 5071 static __maybe_unused int dsi_runtime_suspend(struct device *dev) 5072 { 5073 struct dsi_data *dsi = dev_get_drvdata(dev); 5074 5075 dsi->is_enabled = false; 5076 /* ensure the irq handler sees the is_enabled value */ 5077 smp_wmb(); 5078 /* wait for current handler to finish before turning the DSI off */ 5079 synchronize_irq(dsi->irq); 5080 5081 return 0; 5082 } 5083 5084 static __maybe_unused int dsi_runtime_resume(struct device *dev) 5085 { 5086 struct dsi_data *dsi = dev_get_drvdata(dev); 5087 5088 dsi->is_enabled = true; 5089 /* ensure the irq handler sees the is_enabled value */ 5090 smp_wmb(); 5091 5092 return 0; 5093 } 5094 5095 static const struct dev_pm_ops dsi_pm_ops = { 5096 SET_RUNTIME_PM_OPS(dsi_runtime_suspend, dsi_runtime_resume, NULL) 5097 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 5098 }; 5099 5100 struct platform_driver omap_dsihw_driver = { 5101 .probe = dsi_probe, 5102 .remove = dsi_remove, 5103 .driver = { 5104 .name = "omapdss_dsi", 5105 .pm = &dsi_pm_ops, 5106 .of_match_table = dsi_of_match, 5107 .suppress_bind_attrs = true, 5108 }, 5109 }; 5110