1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7 #define DSS_SUBSYS_NAME "DSI" 8 9 #include <linux/kernel.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/regmap.h> 12 #include <linux/io.h> 13 #include <linux/clk.h> 14 #include <linux/device.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/delay.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/mutex.h> 21 #include <linux/module.h> 22 #include <linux/semaphore.h> 23 #include <linux/seq_file.h> 24 #include <linux/platform_device.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/wait.h> 27 #include <linux/workqueue.h> 28 #include <linux/sched.h> 29 #include <linux/slab.h> 30 #include <linux/debugfs.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/of_graph.h> 34 #include <linux/of_platform.h> 35 #include <linux/component.h> 36 #include <linux/sys_soc.h> 37 38 #include <drm/drm_atomic_state_helper.h> 39 #include <drm/drm_bridge.h> 40 #include <drm/drm_mipi_dsi.h> 41 #include <drm/drm_panel.h> 42 #include <video/mipi_display.h> 43 44 #include "omapdss.h" 45 #include "dss.h" 46 47 #define DSI_CATCH_MISSING_TE 48 49 #include "dsi.h" 50 51 #define REG_GET(dsi, idx, start, end) \ 52 FLD_GET(dsi_read_reg(dsi, idx), start, end) 53 54 #define REG_FLD_MOD(dsi, idx, val, start, end) \ 55 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end)) 56 57 static int dsi_init_dispc(struct dsi_data *dsi); 58 static void dsi_uninit_dispc(struct dsi_data *dsi); 59 60 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel); 61 62 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, 63 const struct mipi_dsi_msg *msg); 64 65 #ifdef DSI_PERF_MEASURE 66 static bool dsi_perf; 67 module_param(dsi_perf, bool, 0644); 68 #endif 69 70 /* Note: for some reason video mode seems to work only if VC_VIDEO is 0 */ 71 #define VC_VIDEO 0 72 #define VC_CMD 1 73 74 #define drm_bridge_to_dsi(bridge) \ 75 container_of(bridge, struct dsi_data, bridge) 76 77 static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev) 78 { 79 return dev_get_drvdata(dssdev->dev); 80 } 81 82 static inline struct dsi_data *host_to_omap(struct mipi_dsi_host *host) 83 { 84 return container_of(host, struct dsi_data, host); 85 } 86 87 static inline void dsi_write_reg(struct dsi_data *dsi, 88 const struct dsi_reg idx, u32 val) 89 { 90 void __iomem *base; 91 92 switch(idx.module) { 93 case DSI_PROTO: base = dsi->proto_base; break; 94 case DSI_PHY: base = dsi->phy_base; break; 95 case DSI_PLL: base = dsi->pll_base; break; 96 default: return; 97 } 98 99 __raw_writel(val, base + idx.idx); 100 } 101 102 static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx) 103 { 104 void __iomem *base; 105 106 switch(idx.module) { 107 case DSI_PROTO: base = dsi->proto_base; break; 108 case DSI_PHY: base = dsi->phy_base; break; 109 case DSI_PLL: base = dsi->pll_base; break; 110 default: return 0; 111 } 112 113 return __raw_readl(base + idx.idx); 114 } 115 116 static void dsi_bus_lock(struct dsi_data *dsi) 117 { 118 down(&dsi->bus_lock); 119 } 120 121 static void dsi_bus_unlock(struct dsi_data *dsi) 122 { 123 up(&dsi->bus_lock); 124 } 125 126 static bool dsi_bus_is_locked(struct dsi_data *dsi) 127 { 128 return dsi->bus_lock.count == 0; 129 } 130 131 static void dsi_completion_handler(void *data, u32 mask) 132 { 133 complete((struct completion *)data); 134 } 135 136 static inline bool wait_for_bit_change(struct dsi_data *dsi, 137 const struct dsi_reg idx, 138 int bitnum, int value) 139 { 140 unsigned long timeout; 141 ktime_t wait; 142 int t; 143 144 /* first busyloop to see if the bit changes right away */ 145 t = 100; 146 while (t-- > 0) { 147 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 148 return true; 149 } 150 151 /* then loop for 500ms, sleeping for 1ms in between */ 152 timeout = jiffies + msecs_to_jiffies(500); 153 while (time_before(jiffies, timeout)) { 154 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 155 return true; 156 157 wait = ns_to_ktime(1000 * 1000); 158 set_current_state(TASK_UNINTERRUPTIBLE); 159 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 160 } 161 162 return false; 163 } 164 165 #ifdef DSI_PERF_MEASURE 166 static void dsi_perf_mark_setup(struct dsi_data *dsi) 167 { 168 dsi->perf_setup_time = ktime_get(); 169 } 170 171 static void dsi_perf_mark_start(struct dsi_data *dsi) 172 { 173 dsi->perf_start_time = ktime_get(); 174 } 175 176 static void dsi_perf_show(struct dsi_data *dsi, const char *name) 177 { 178 ktime_t t, setup_time, trans_time; 179 u32 total_bytes; 180 u32 setup_us, trans_us, total_us; 181 182 if (!dsi_perf) 183 return; 184 185 t = ktime_get(); 186 187 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 188 setup_us = (u32)ktime_to_us(setup_time); 189 if (setup_us == 0) 190 setup_us = 1; 191 192 trans_time = ktime_sub(t, dsi->perf_start_time); 193 trans_us = (u32)ktime_to_us(trans_time); 194 if (trans_us == 0) 195 trans_us = 1; 196 197 total_us = setup_us + trans_us; 198 199 total_bytes = dsi->update_bytes; 200 201 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n", 202 name, 203 setup_us, 204 trans_us, 205 total_us, 206 1000 * 1000 / total_us, 207 total_bytes, 208 total_bytes * 1000 / total_us); 209 } 210 #else 211 static inline void dsi_perf_mark_setup(struct dsi_data *dsi) 212 { 213 } 214 215 static inline void dsi_perf_mark_start(struct dsi_data *dsi) 216 { 217 } 218 219 static inline void dsi_perf_show(struct dsi_data *dsi, const char *name) 220 { 221 } 222 #endif 223 224 static int verbose_irq; 225 226 static void print_irq_status(u32 status) 227 { 228 if (status == 0) 229 return; 230 231 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 232 return; 233 234 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 235 236 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 237 status, 238 verbose_irq ? PIS(VC0) : "", 239 verbose_irq ? PIS(VC1) : "", 240 verbose_irq ? PIS(VC2) : "", 241 verbose_irq ? PIS(VC3) : "", 242 PIS(WAKEUP), 243 PIS(RESYNC), 244 PIS(PLL_LOCK), 245 PIS(PLL_UNLOCK), 246 PIS(PLL_RECALL), 247 PIS(COMPLEXIO_ERR), 248 PIS(HS_TX_TIMEOUT), 249 PIS(LP_RX_TIMEOUT), 250 PIS(TE_TRIGGER), 251 PIS(ACK_TRIGGER), 252 PIS(SYNC_LOST), 253 PIS(LDO_POWER_GOOD), 254 PIS(TA_TIMEOUT)); 255 #undef PIS 256 } 257 258 static void print_irq_status_vc(int vc, u32 status) 259 { 260 if (status == 0) 261 return; 262 263 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 264 return; 265 266 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 267 268 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 269 vc, 270 status, 271 PIS(CS), 272 PIS(ECC_CORR), 273 PIS(ECC_NO_CORR), 274 verbose_irq ? PIS(PACKET_SENT) : "", 275 PIS(BTA), 276 PIS(FIFO_TX_OVF), 277 PIS(FIFO_RX_OVF), 278 PIS(FIFO_TX_UDF), 279 PIS(PP_BUSY_CHANGE)); 280 #undef PIS 281 } 282 283 static void print_irq_status_cio(u32 status) 284 { 285 if (status == 0) 286 return; 287 288 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 289 290 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 291 status, 292 PIS(ERRSYNCESC1), 293 PIS(ERRSYNCESC2), 294 PIS(ERRSYNCESC3), 295 PIS(ERRESC1), 296 PIS(ERRESC2), 297 PIS(ERRESC3), 298 PIS(ERRCONTROL1), 299 PIS(ERRCONTROL2), 300 PIS(ERRCONTROL3), 301 PIS(STATEULPS1), 302 PIS(STATEULPS2), 303 PIS(STATEULPS3), 304 PIS(ERRCONTENTIONLP0_1), 305 PIS(ERRCONTENTIONLP1_1), 306 PIS(ERRCONTENTIONLP0_2), 307 PIS(ERRCONTENTIONLP1_2), 308 PIS(ERRCONTENTIONLP0_3), 309 PIS(ERRCONTENTIONLP1_3), 310 PIS(ULPSACTIVENOT_ALL0), 311 PIS(ULPSACTIVENOT_ALL1)); 312 #undef PIS 313 } 314 315 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 316 static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus, 317 u32 *vcstatus, u32 ciostatus) 318 { 319 int i; 320 321 spin_lock(&dsi->irq_stats_lock); 322 323 dsi->irq_stats.irq_count++; 324 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 325 326 for (i = 0; i < 4; ++i) 327 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 328 329 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 330 331 spin_unlock(&dsi->irq_stats_lock); 332 } 333 #else 334 #define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus) 335 #endif 336 337 static int debug_irq; 338 339 static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus, 340 u32 *vcstatus, u32 ciostatus) 341 { 342 int i; 343 344 if (irqstatus & DSI_IRQ_ERROR_MASK) { 345 DSSERR("DSI error, irqstatus %x\n", irqstatus); 346 print_irq_status(irqstatus); 347 spin_lock(&dsi->errors_lock); 348 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 349 spin_unlock(&dsi->errors_lock); 350 } else if (debug_irq) { 351 print_irq_status(irqstatus); 352 } 353 354 for (i = 0; i < 4; ++i) { 355 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 356 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 357 i, vcstatus[i]); 358 print_irq_status_vc(i, vcstatus[i]); 359 } else if (debug_irq) { 360 print_irq_status_vc(i, vcstatus[i]); 361 } 362 } 363 364 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 365 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 366 print_irq_status_cio(ciostatus); 367 } else if (debug_irq) { 368 print_irq_status_cio(ciostatus); 369 } 370 } 371 372 static void dsi_call_isrs(struct dsi_isr_data *isr_array, 373 unsigned int isr_array_size, u32 irqstatus) 374 { 375 struct dsi_isr_data *isr_data; 376 int i; 377 378 for (i = 0; i < isr_array_size; i++) { 379 isr_data = &isr_array[i]; 380 if (isr_data->isr && isr_data->mask & irqstatus) 381 isr_data->isr(isr_data->arg, irqstatus); 382 } 383 } 384 385 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 386 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 387 { 388 int i; 389 390 dsi_call_isrs(isr_tables->isr_table, 391 ARRAY_SIZE(isr_tables->isr_table), 392 irqstatus); 393 394 for (i = 0; i < 4; ++i) { 395 if (vcstatus[i] == 0) 396 continue; 397 dsi_call_isrs(isr_tables->isr_table_vc[i], 398 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 399 vcstatus[i]); 400 } 401 402 if (ciostatus != 0) 403 dsi_call_isrs(isr_tables->isr_table_cio, 404 ARRAY_SIZE(isr_tables->isr_table_cio), 405 ciostatus); 406 } 407 408 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 409 { 410 struct dsi_data *dsi = arg; 411 u32 irqstatus, vcstatus[4], ciostatus; 412 int i; 413 414 if (!dsi->is_enabled) 415 return IRQ_NONE; 416 417 spin_lock(&dsi->irq_lock); 418 419 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS); 420 421 /* IRQ is not for us */ 422 if (!irqstatus) { 423 spin_unlock(&dsi->irq_lock); 424 return IRQ_NONE; 425 } 426 427 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 428 /* flush posted write */ 429 dsi_read_reg(dsi, DSI_IRQSTATUS); 430 431 for (i = 0; i < 4; ++i) { 432 if ((irqstatus & (1 << i)) == 0) { 433 vcstatus[i] = 0; 434 continue; 435 } 436 437 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 438 439 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]); 440 /* flush posted write */ 441 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 442 } 443 444 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 445 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 446 447 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 448 /* flush posted write */ 449 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 450 } else { 451 ciostatus = 0; 452 } 453 454 #ifdef DSI_CATCH_MISSING_TE 455 if (irqstatus & DSI_IRQ_TE_TRIGGER) 456 timer_delete(&dsi->te_timer); 457 #endif 458 459 dsi_handle_isrs(&dsi->isr_tables, irqstatus, vcstatus, ciostatus); 460 461 spin_unlock(&dsi->irq_lock); 462 463 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus); 464 465 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus); 466 467 return IRQ_HANDLED; 468 } 469 470 /* dsi->irq_lock has to be locked by the caller */ 471 static void _omap_dsi_configure_irqs(struct dsi_data *dsi, 472 struct dsi_isr_data *isr_array, 473 unsigned int isr_array_size, 474 u32 default_mask, 475 const struct dsi_reg enable_reg, 476 const struct dsi_reg status_reg) 477 { 478 struct dsi_isr_data *isr_data; 479 u32 mask; 480 u32 old_mask; 481 int i; 482 483 mask = default_mask; 484 485 for (i = 0; i < isr_array_size; i++) { 486 isr_data = &isr_array[i]; 487 488 if (isr_data->isr == NULL) 489 continue; 490 491 mask |= isr_data->mask; 492 } 493 494 old_mask = dsi_read_reg(dsi, enable_reg); 495 /* clear the irqstatus for newly enabled irqs */ 496 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask); 497 dsi_write_reg(dsi, enable_reg, mask); 498 499 /* flush posted writes */ 500 dsi_read_reg(dsi, enable_reg); 501 dsi_read_reg(dsi, status_reg); 502 } 503 504 /* dsi->irq_lock has to be locked by the caller */ 505 static void _omap_dsi_set_irqs(struct dsi_data *dsi) 506 { 507 u32 mask = DSI_IRQ_ERROR_MASK; 508 #ifdef DSI_CATCH_MISSING_TE 509 mask |= DSI_IRQ_TE_TRIGGER; 510 #endif 511 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table, 512 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 513 DSI_IRQENABLE, DSI_IRQSTATUS); 514 } 515 516 /* dsi->irq_lock has to be locked by the caller */ 517 static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc) 518 { 519 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc], 520 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 521 DSI_VC_IRQ_ERROR_MASK, 522 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 523 } 524 525 /* dsi->irq_lock has to be locked by the caller */ 526 static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi) 527 { 528 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio, 529 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 530 DSI_CIO_IRQ_ERROR_MASK, 531 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 532 } 533 534 static void _dsi_initialize_irq(struct dsi_data *dsi) 535 { 536 unsigned long flags; 537 int vc; 538 539 spin_lock_irqsave(&dsi->irq_lock, flags); 540 541 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 542 543 _omap_dsi_set_irqs(dsi); 544 for (vc = 0; vc < 4; ++vc) 545 _omap_dsi_set_irqs_vc(dsi, vc); 546 _omap_dsi_set_irqs_cio(dsi); 547 548 spin_unlock_irqrestore(&dsi->irq_lock, flags); 549 } 550 551 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 552 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 553 { 554 struct dsi_isr_data *isr_data; 555 int free_idx; 556 int i; 557 558 BUG_ON(isr == NULL); 559 560 /* check for duplicate entry and find a free slot */ 561 free_idx = -1; 562 for (i = 0; i < isr_array_size; i++) { 563 isr_data = &isr_array[i]; 564 565 if (isr_data->isr == isr && isr_data->arg == arg && 566 isr_data->mask == mask) { 567 return -EINVAL; 568 } 569 570 if (isr_data->isr == NULL && free_idx == -1) 571 free_idx = i; 572 } 573 574 if (free_idx == -1) 575 return -EBUSY; 576 577 isr_data = &isr_array[free_idx]; 578 isr_data->isr = isr; 579 isr_data->arg = arg; 580 isr_data->mask = mask; 581 582 return 0; 583 } 584 585 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 586 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 587 { 588 struct dsi_isr_data *isr_data; 589 int i; 590 591 for (i = 0; i < isr_array_size; i++) { 592 isr_data = &isr_array[i]; 593 if (isr_data->isr != isr || isr_data->arg != arg || 594 isr_data->mask != mask) 595 continue; 596 597 isr_data->isr = NULL; 598 isr_data->arg = NULL; 599 isr_data->mask = 0; 600 601 return 0; 602 } 603 604 return -EINVAL; 605 } 606 607 static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 608 void *arg, u32 mask) 609 { 610 unsigned long flags; 611 int r; 612 613 spin_lock_irqsave(&dsi->irq_lock, flags); 614 615 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 616 ARRAY_SIZE(dsi->isr_tables.isr_table)); 617 618 if (r == 0) 619 _omap_dsi_set_irqs(dsi); 620 621 spin_unlock_irqrestore(&dsi->irq_lock, flags); 622 623 return r; 624 } 625 626 static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 627 void *arg, u32 mask) 628 { 629 unsigned long flags; 630 int r; 631 632 spin_lock_irqsave(&dsi->irq_lock, flags); 633 634 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 635 ARRAY_SIZE(dsi->isr_tables.isr_table)); 636 637 if (r == 0) 638 _omap_dsi_set_irqs(dsi); 639 640 spin_unlock_irqrestore(&dsi->irq_lock, flags); 641 642 return r; 643 } 644 645 static int dsi_register_isr_vc(struct dsi_data *dsi, int vc, 646 omap_dsi_isr_t isr, void *arg, u32 mask) 647 { 648 unsigned long flags; 649 int r; 650 651 spin_lock_irqsave(&dsi->irq_lock, flags); 652 653 r = _dsi_register_isr(isr, arg, mask, 654 dsi->isr_tables.isr_table_vc[vc], 655 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); 656 657 if (r == 0) 658 _omap_dsi_set_irqs_vc(dsi, vc); 659 660 spin_unlock_irqrestore(&dsi->irq_lock, flags); 661 662 return r; 663 } 664 665 static int dsi_unregister_isr_vc(struct dsi_data *dsi, int vc, 666 omap_dsi_isr_t isr, void *arg, u32 mask) 667 { 668 unsigned long flags; 669 int r; 670 671 spin_lock_irqsave(&dsi->irq_lock, flags); 672 673 r = _dsi_unregister_isr(isr, arg, mask, 674 dsi->isr_tables.isr_table_vc[vc], 675 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc])); 676 677 if (r == 0) 678 _omap_dsi_set_irqs_vc(dsi, vc); 679 680 spin_unlock_irqrestore(&dsi->irq_lock, flags); 681 682 return r; 683 } 684 685 static u32 dsi_get_errors(struct dsi_data *dsi) 686 { 687 unsigned long flags; 688 u32 e; 689 690 spin_lock_irqsave(&dsi->errors_lock, flags); 691 e = dsi->errors; 692 dsi->errors = 0; 693 spin_unlock_irqrestore(&dsi->errors_lock, flags); 694 return e; 695 } 696 697 static int dsi_runtime_get(struct dsi_data *dsi) 698 { 699 int r; 700 701 DSSDBG("dsi_runtime_get\n"); 702 703 r = pm_runtime_get_sync(dsi->dev); 704 if (WARN_ON(r < 0)) { 705 pm_runtime_put_noidle(dsi->dev); 706 return r; 707 } 708 return 0; 709 } 710 711 static void dsi_runtime_put(struct dsi_data *dsi) 712 { 713 int r; 714 715 DSSDBG("dsi_runtime_put\n"); 716 717 r = pm_runtime_put_sync(dsi->dev); 718 WARN_ON(r < 0 && r != -ENOSYS); 719 } 720 721 static void _dsi_print_reset_status(struct dsi_data *dsi) 722 { 723 int b0, b1, b2; 724 725 /* A dummy read using the SCP interface to any DSIPHY register is 726 * required after DSIPHY reset to complete the reset of the DSI complex 727 * I/O. */ 728 dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 729 730 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { 731 b0 = 28; 732 b1 = 27; 733 b2 = 26; 734 } else { 735 b0 = 24; 736 b1 = 25; 737 b2 = 26; 738 } 739 740 #define DSI_FLD_GET(fld, start, end)\ 741 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end) 742 743 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 744 DSI_FLD_GET(PLL_STATUS, 0, 0), 745 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 746 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 747 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 748 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 749 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 750 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 751 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 752 753 #undef DSI_FLD_GET 754 } 755 756 static inline int dsi_if_enable(struct dsi_data *dsi, bool enable) 757 { 758 DSSDBG("dsi_if_enable(%d)\n", enable); 759 760 enable = enable ? 1 : 0; 761 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ 762 763 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) { 764 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 765 return -EIO; 766 } 767 768 return 0; 769 } 770 771 static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi) 772 { 773 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 774 } 775 776 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi) 777 { 778 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 779 } 780 781 static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi) 782 { 783 return dsi->pll.cinfo.clkdco / 16; 784 } 785 786 static unsigned long dsi_fclk_rate(struct dsi_data *dsi) 787 { 788 unsigned long r; 789 enum dss_clk_source source; 790 791 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id); 792 if (source == DSS_CLK_SRC_FCK) { 793 /* DSI FCLK source is DSS_CLK_FCK */ 794 r = clk_get_rate(dsi->dss_clk); 795 } else { 796 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 797 r = dsi_get_pll_hsdiv_dsi_rate(dsi); 798 } 799 800 return r; 801 } 802 803 static int dsi_lp_clock_calc(unsigned long dsi_fclk, 804 unsigned long lp_clk_min, unsigned long lp_clk_max, 805 struct dsi_lp_clock_info *lp_cinfo) 806 { 807 unsigned int lp_clk_div; 808 unsigned long lp_clk; 809 810 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 811 lp_clk = dsi_fclk / 2 / lp_clk_div; 812 813 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 814 return -EINVAL; 815 816 lp_cinfo->lp_clk_div = lp_clk_div; 817 lp_cinfo->lp_clk = lp_clk; 818 819 return 0; 820 } 821 822 static int dsi_set_lp_clk_divisor(struct dsi_data *dsi) 823 { 824 unsigned long dsi_fclk; 825 unsigned int lp_clk_div; 826 unsigned long lp_clk; 827 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv; 828 829 830 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 831 832 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 833 return -EINVAL; 834 835 dsi_fclk = dsi_fclk_rate(dsi); 836 837 lp_clk = dsi_fclk / 2 / lp_clk_div; 838 839 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 840 dsi->current_lp_cinfo.lp_clk = lp_clk; 841 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 842 843 /* LP_CLK_DIVISOR */ 844 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); 845 846 /* LP_RX_SYNCHRO_ENABLE */ 847 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 848 849 return 0; 850 } 851 852 static void dsi_enable_scp_clk(struct dsi_data *dsi) 853 { 854 if (dsi->scp_clk_refcount++ == 0) 855 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 856 } 857 858 static void dsi_disable_scp_clk(struct dsi_data *dsi) 859 { 860 WARN_ON(dsi->scp_clk_refcount == 0); 861 if (--dsi->scp_clk_refcount == 0) 862 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 863 } 864 865 enum dsi_pll_power_state { 866 DSI_PLL_POWER_OFF = 0x0, 867 DSI_PLL_POWER_ON_HSCLK = 0x1, 868 DSI_PLL_POWER_ON_ALL = 0x2, 869 DSI_PLL_POWER_ON_DIV = 0x3, 870 }; 871 872 static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state) 873 { 874 int t = 0; 875 876 /* DSI-PLL power command 0x3 is not working */ 877 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && 878 state == DSI_PLL_POWER_ON_DIV) 879 state = DSI_PLL_POWER_ON_ALL; 880 881 /* PLL_PWR_CMD */ 882 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); 883 884 /* PLL_PWR_STATUS */ 885 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) { 886 if (++t > 1000) { 887 DSSERR("Failed to set DSI PLL power mode to %d\n", 888 state); 889 return -ENODEV; 890 } 891 udelay(1); 892 } 893 894 return 0; 895 } 896 897 898 static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi, 899 struct dss_pll_clock_info *cinfo) 900 { 901 unsigned long max_dsi_fck; 902 903 max_dsi_fck = dsi->data->max_fck_freq; 904 905 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 906 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 907 } 908 909 static int dsi_pll_enable(struct dss_pll *pll) 910 { 911 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 912 int r = 0; 913 914 DSSDBG("PLL init\n"); 915 916 r = dsi_runtime_get(dsi); 917 if (r) 918 return r; 919 920 /* 921 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 922 */ 923 dsi_enable_scp_clk(dsi); 924 925 r = regulator_enable(dsi->vdds_dsi_reg); 926 if (r) 927 goto err0; 928 929 /* XXX PLL does not come out of reset without this... */ 930 dispc_pck_free_enable(dsi->dss->dispc, 1); 931 932 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) { 933 DSSERR("PLL not coming out of reset.\n"); 934 r = -ENODEV; 935 dispc_pck_free_enable(dsi->dss->dispc, 0); 936 goto err1; 937 } 938 939 /* XXX ... but if left on, we get problems when planes do not 940 * fill the whole display. No idea about this */ 941 dispc_pck_free_enable(dsi->dss->dispc, 0); 942 943 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL); 944 945 if (r) 946 goto err1; 947 948 DSSDBG("PLL init done\n"); 949 950 return 0; 951 err1: 952 regulator_disable(dsi->vdds_dsi_reg); 953 err0: 954 dsi_disable_scp_clk(dsi); 955 dsi_runtime_put(dsi); 956 return r; 957 } 958 959 static void dsi_pll_disable(struct dss_pll *pll) 960 { 961 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 962 963 dsi_pll_power(dsi, DSI_PLL_POWER_OFF); 964 965 regulator_disable(dsi->vdds_dsi_reg); 966 967 dsi_disable_scp_clk(dsi); 968 dsi_runtime_put(dsi); 969 970 DSSDBG("PLL disable done\n"); 971 } 972 973 static int dsi_dump_dsi_clocks(struct seq_file *s, void *p) 974 { 975 struct dsi_data *dsi = s->private; 976 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 977 enum dss_clk_source dispc_clk_src, dsi_clk_src; 978 int dsi_module = dsi->module_id; 979 struct dss_pll *pll = &dsi->pll; 980 981 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss); 982 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module); 983 984 if (dsi_runtime_get(dsi)) 985 return 0; 986 987 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 988 989 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 990 991 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 992 993 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 994 cinfo->clkdco, cinfo->m); 995 996 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 997 dss_get_clk_source_name(dsi_module == 0 ? 998 DSS_CLK_SRC_PLL1_1 : 999 DSS_CLK_SRC_PLL2_1), 1000 cinfo->clkout[HSDIV_DISPC], 1001 cinfo->mX[HSDIV_DISPC], 1002 dispc_clk_src == DSS_CLK_SRC_FCK ? 1003 "off" : "on"); 1004 1005 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1006 dss_get_clk_source_name(dsi_module == 0 ? 1007 DSS_CLK_SRC_PLL1_2 : 1008 DSS_CLK_SRC_PLL2_2), 1009 cinfo->clkout[HSDIV_DSI], 1010 cinfo->mX[HSDIV_DSI], 1011 dsi_clk_src == DSS_CLK_SRC_FCK ? 1012 "off" : "on"); 1013 1014 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1015 1016 seq_printf(s, "dsi fclk source = %s\n", 1017 dss_get_clk_source_name(dsi_clk_src)); 1018 1019 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi)); 1020 1021 seq_printf(s, "DDR_CLK\t\t%lu\n", 1022 cinfo->clkdco / 4); 1023 1024 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi)); 1025 1026 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1027 1028 dsi_runtime_put(dsi); 1029 1030 return 0; 1031 } 1032 1033 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 1034 static int dsi_dump_dsi_irqs(struct seq_file *s, void *p) 1035 { 1036 struct dsi_data *dsi = s->private; 1037 unsigned long flags; 1038 struct dsi_irq_stats *stats; 1039 1040 stats = kmalloc_obj(*stats); 1041 if (!stats) 1042 return -ENOMEM; 1043 1044 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1045 1046 *stats = dsi->irq_stats; 1047 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1048 dsi->irq_stats.last_reset = jiffies; 1049 1050 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1051 1052 seq_printf(s, "period %u ms\n", 1053 jiffies_to_msecs(jiffies - stats->last_reset)); 1054 1055 seq_printf(s, "irqs %d\n", stats->irq_count); 1056 #define PIS(x) \ 1057 seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1058 1059 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1060 PIS(VC0); 1061 PIS(VC1); 1062 PIS(VC2); 1063 PIS(VC3); 1064 PIS(WAKEUP); 1065 PIS(RESYNC); 1066 PIS(PLL_LOCK); 1067 PIS(PLL_UNLOCK); 1068 PIS(PLL_RECALL); 1069 PIS(COMPLEXIO_ERR); 1070 PIS(HS_TX_TIMEOUT); 1071 PIS(LP_RX_TIMEOUT); 1072 PIS(TE_TRIGGER); 1073 PIS(ACK_TRIGGER); 1074 PIS(SYNC_LOST); 1075 PIS(LDO_POWER_GOOD); 1076 PIS(TA_TIMEOUT); 1077 #undef PIS 1078 1079 #define PIS(x) \ 1080 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1081 stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1082 stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1083 stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1084 stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1085 1086 seq_printf(s, "-- VC interrupts --\n"); 1087 PIS(CS); 1088 PIS(ECC_CORR); 1089 PIS(PACKET_SENT); 1090 PIS(FIFO_TX_OVF); 1091 PIS(FIFO_RX_OVF); 1092 PIS(BTA); 1093 PIS(ECC_NO_CORR); 1094 PIS(FIFO_TX_UDF); 1095 PIS(PP_BUSY_CHANGE); 1096 #undef PIS 1097 1098 #define PIS(x) \ 1099 seq_printf(s, "%-20s %10d\n", #x, \ 1100 stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1101 1102 seq_printf(s, "-- CIO interrupts --\n"); 1103 PIS(ERRSYNCESC1); 1104 PIS(ERRSYNCESC2); 1105 PIS(ERRSYNCESC3); 1106 PIS(ERRESC1); 1107 PIS(ERRESC2); 1108 PIS(ERRESC3); 1109 PIS(ERRCONTROL1); 1110 PIS(ERRCONTROL2); 1111 PIS(ERRCONTROL3); 1112 PIS(STATEULPS1); 1113 PIS(STATEULPS2); 1114 PIS(STATEULPS3); 1115 PIS(ERRCONTENTIONLP0_1); 1116 PIS(ERRCONTENTIONLP1_1); 1117 PIS(ERRCONTENTIONLP0_2); 1118 PIS(ERRCONTENTIONLP1_2); 1119 PIS(ERRCONTENTIONLP0_3); 1120 PIS(ERRCONTENTIONLP1_3); 1121 PIS(ULPSACTIVENOT_ALL0); 1122 PIS(ULPSACTIVENOT_ALL1); 1123 #undef PIS 1124 1125 kfree(stats); 1126 1127 return 0; 1128 } 1129 #endif 1130 1131 static int dsi_dump_dsi_regs(struct seq_file *s, void *p) 1132 { 1133 struct dsi_data *dsi = s->private; 1134 1135 if (dsi_runtime_get(dsi)) 1136 return 0; 1137 dsi_enable_scp_clk(dsi); 1138 1139 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r)) 1140 DUMPREG(DSI_REVISION); 1141 DUMPREG(DSI_SYSCONFIG); 1142 DUMPREG(DSI_SYSSTATUS); 1143 DUMPREG(DSI_IRQSTATUS); 1144 DUMPREG(DSI_IRQENABLE); 1145 DUMPREG(DSI_CTRL); 1146 DUMPREG(DSI_COMPLEXIO_CFG1); 1147 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1148 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1149 DUMPREG(DSI_CLK_CTRL); 1150 DUMPREG(DSI_TIMING1); 1151 DUMPREG(DSI_TIMING2); 1152 DUMPREG(DSI_VM_TIMING1); 1153 DUMPREG(DSI_VM_TIMING2); 1154 DUMPREG(DSI_VM_TIMING3); 1155 DUMPREG(DSI_CLK_TIMING); 1156 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1157 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1158 DUMPREG(DSI_COMPLEXIO_CFG2); 1159 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1160 DUMPREG(DSI_VM_TIMING4); 1161 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1162 DUMPREG(DSI_VM_TIMING5); 1163 DUMPREG(DSI_VM_TIMING6); 1164 DUMPREG(DSI_VM_TIMING7); 1165 DUMPREG(DSI_STOPCLK_TIMING); 1166 1167 DUMPREG(DSI_VC_CTRL(0)); 1168 DUMPREG(DSI_VC_TE(0)); 1169 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1170 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1171 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1172 DUMPREG(DSI_VC_IRQSTATUS(0)); 1173 DUMPREG(DSI_VC_IRQENABLE(0)); 1174 1175 DUMPREG(DSI_VC_CTRL(1)); 1176 DUMPREG(DSI_VC_TE(1)); 1177 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1178 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1179 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1180 DUMPREG(DSI_VC_IRQSTATUS(1)); 1181 DUMPREG(DSI_VC_IRQENABLE(1)); 1182 1183 DUMPREG(DSI_VC_CTRL(2)); 1184 DUMPREG(DSI_VC_TE(2)); 1185 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1186 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1187 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1188 DUMPREG(DSI_VC_IRQSTATUS(2)); 1189 DUMPREG(DSI_VC_IRQENABLE(2)); 1190 1191 DUMPREG(DSI_VC_CTRL(3)); 1192 DUMPREG(DSI_VC_TE(3)); 1193 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1194 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1195 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1196 DUMPREG(DSI_VC_IRQSTATUS(3)); 1197 DUMPREG(DSI_VC_IRQENABLE(3)); 1198 1199 DUMPREG(DSI_DSIPHY_CFG0); 1200 DUMPREG(DSI_DSIPHY_CFG1); 1201 DUMPREG(DSI_DSIPHY_CFG2); 1202 DUMPREG(DSI_DSIPHY_CFG5); 1203 1204 DUMPREG(DSI_PLL_CONTROL); 1205 DUMPREG(DSI_PLL_STATUS); 1206 DUMPREG(DSI_PLL_GO); 1207 DUMPREG(DSI_PLL_CONFIGURATION1); 1208 DUMPREG(DSI_PLL_CONFIGURATION2); 1209 #undef DUMPREG 1210 1211 dsi_disable_scp_clk(dsi); 1212 dsi_runtime_put(dsi); 1213 1214 return 0; 1215 } 1216 1217 enum dsi_cio_power_state { 1218 DSI_COMPLEXIO_POWER_OFF = 0x0, 1219 DSI_COMPLEXIO_POWER_ON = 0x1, 1220 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1221 }; 1222 1223 static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state) 1224 { 1225 int t = 0; 1226 1227 /* PWR_CMD */ 1228 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); 1229 1230 /* PWR_STATUS */ 1231 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1), 1232 26, 25) != state) { 1233 if (++t > 1000) { 1234 DSSERR("failed to set complexio power state to " 1235 "%d\n", state); 1236 return -ENODEV; 1237 } 1238 udelay(1); 1239 } 1240 1241 return 0; 1242 } 1243 1244 static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi) 1245 { 1246 int val; 1247 1248 /* line buffer on OMAP3 is 1024 x 24bits */ 1249 /* XXX: for some reason using full buffer size causes 1250 * considerable TX slowdown with update sizes that fill the 1251 * whole buffer */ 1252 if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) 1253 return 1023 * 3; 1254 1255 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1256 1257 switch (val) { 1258 case 1: 1259 return 512 * 3; /* 512x24 bits */ 1260 case 2: 1261 return 682 * 3; /* 682x24 bits */ 1262 case 3: 1263 return 853 * 3; /* 853x24 bits */ 1264 case 4: 1265 return 1024 * 3; /* 1024x24 bits */ 1266 case 5: 1267 return 1194 * 3; /* 1194x24 bits */ 1268 case 6: 1269 return 1365 * 3; /* 1365x24 bits */ 1270 case 7: 1271 return 1920 * 3; /* 1920x24 bits */ 1272 default: 1273 BUG(); 1274 return 0; 1275 } 1276 } 1277 1278 static int dsi_set_lane_config(struct dsi_data *dsi) 1279 { 1280 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1281 static const enum dsi_lane_function functions[] = { 1282 DSI_LANE_CLK, 1283 DSI_LANE_DATA1, 1284 DSI_LANE_DATA2, 1285 DSI_LANE_DATA3, 1286 DSI_LANE_DATA4, 1287 }; 1288 u32 r; 1289 int i; 1290 1291 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1); 1292 1293 for (i = 0; i < dsi->num_lanes_used; ++i) { 1294 unsigned int offset = offsets[i]; 1295 unsigned int polarity, lane_number; 1296 unsigned int t; 1297 1298 for (t = 0; t < dsi->num_lanes_supported; ++t) 1299 if (dsi->lanes[t].function == functions[i]) 1300 break; 1301 1302 if (t == dsi->num_lanes_supported) 1303 return -EINVAL; 1304 1305 lane_number = t; 1306 polarity = dsi->lanes[t].polarity; 1307 1308 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1309 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1310 } 1311 1312 /* clear the unused lanes */ 1313 for (; i < dsi->num_lanes_supported; ++i) { 1314 unsigned int offset = offsets[i]; 1315 1316 r = FLD_MOD(r, 0, offset + 2, offset); 1317 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1318 } 1319 1320 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r); 1321 1322 return 0; 1323 } 1324 1325 static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns) 1326 { 1327 /* convert time in ns to ddr ticks, rounding up */ 1328 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1329 1330 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1331 } 1332 1333 static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr) 1334 { 1335 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1336 1337 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1338 } 1339 1340 static void dsi_cio_timings(struct dsi_data *dsi) 1341 { 1342 u32 r; 1343 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1344 u32 tlpx_half, tclk_trail, tclk_zero; 1345 u32 tclk_prepare; 1346 1347 /* calculate timings */ 1348 1349 /* 1 * DDR_CLK = 2 * UI */ 1350 1351 /* min 40ns + 4*UI max 85ns + 6*UI */ 1352 ths_prepare = ns2ddr(dsi, 70) + 2; 1353 1354 /* min 145ns + 10*UI */ 1355 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2; 1356 1357 /* min max(8*UI, 60ns+4*UI) */ 1358 ths_trail = ns2ddr(dsi, 60) + 5; 1359 1360 /* min 100ns */ 1361 ths_exit = ns2ddr(dsi, 145); 1362 1363 /* tlpx min 50n */ 1364 tlpx_half = ns2ddr(dsi, 25); 1365 1366 /* min 60ns */ 1367 tclk_trail = ns2ddr(dsi, 60) + 2; 1368 1369 /* min 38ns, max 95ns */ 1370 tclk_prepare = ns2ddr(dsi, 65); 1371 1372 /* min tclk-prepare + tclk-zero = 300ns */ 1373 tclk_zero = ns2ddr(dsi, 260); 1374 1375 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1376 ths_prepare, ddr2ns(dsi, ths_prepare), 1377 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero)); 1378 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1379 ths_trail, ddr2ns(dsi, ths_trail), 1380 ths_exit, ddr2ns(dsi, ths_exit)); 1381 1382 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1383 "tclk_zero %u (%uns)\n", 1384 tlpx_half, ddr2ns(dsi, tlpx_half), 1385 tclk_trail, ddr2ns(dsi, tclk_trail), 1386 tclk_zero, ddr2ns(dsi, tclk_zero)); 1387 DSSDBG("tclk_prepare %u (%uns)\n", 1388 tclk_prepare, ddr2ns(dsi, tclk_prepare)); 1389 1390 /* program timings */ 1391 1392 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 1393 r = FLD_MOD(r, ths_prepare, 31, 24); 1394 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1395 r = FLD_MOD(r, ths_trail, 15, 8); 1396 r = FLD_MOD(r, ths_exit, 7, 0); 1397 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r); 1398 1399 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 1400 r = FLD_MOD(r, tlpx_half, 20, 16); 1401 r = FLD_MOD(r, tclk_trail, 15, 8); 1402 r = FLD_MOD(r, tclk_zero, 7, 0); 1403 1404 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { 1405 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1406 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1407 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1408 } 1409 1410 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r); 1411 1412 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 1413 r = FLD_MOD(r, tclk_prepare, 7, 0); 1414 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r); 1415 } 1416 1417 static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi) 1418 { 1419 int t, i; 1420 bool in_use[DSI_MAX_NR_LANES]; 1421 static const u8 offsets_old[] = { 28, 27, 26 }; 1422 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 1423 const u8 *offsets; 1424 1425 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) 1426 offsets = offsets_old; 1427 else 1428 offsets = offsets_new; 1429 1430 for (i = 0; i < dsi->num_lanes_supported; ++i) 1431 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 1432 1433 t = 100000; 1434 while (true) { 1435 u32 l; 1436 int ok; 1437 1438 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1439 1440 ok = 0; 1441 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1442 if (!in_use[i] || (l & (1 << offsets[i]))) 1443 ok++; 1444 } 1445 1446 if (ok == dsi->num_lanes_supported) 1447 break; 1448 1449 if (--t == 0) { 1450 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1451 if (!in_use[i] || (l & (1 << offsets[i]))) 1452 continue; 1453 1454 DSSERR("CIO TXCLKESC%d domain not coming " \ 1455 "out of reset\n", i); 1456 } 1457 return -EIO; 1458 } 1459 } 1460 1461 return 0; 1462 } 1463 1464 /* return bitmask of enabled lanes, lane0 being the lsb */ 1465 static unsigned int dsi_get_lane_mask(struct dsi_data *dsi) 1466 { 1467 unsigned int mask = 0; 1468 int i; 1469 1470 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1471 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 1472 mask |= 1 << i; 1473 } 1474 1475 return mask; 1476 } 1477 1478 /* OMAP4 CONTROL_DSIPHY */ 1479 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 1480 1481 #define OMAP4_DSI2_LANEENABLE_SHIFT 29 1482 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 1483 #define OMAP4_DSI1_LANEENABLE_SHIFT 24 1484 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 1485 #define OMAP4_DSI1_PIPD_SHIFT 19 1486 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) 1487 #define OMAP4_DSI2_PIPD_SHIFT 14 1488 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) 1489 1490 static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1491 { 1492 u32 enable_mask, enable_shift; 1493 u32 pipd_mask, pipd_shift; 1494 1495 if (dsi->module_id == 0) { 1496 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 1497 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 1498 pipd_mask = OMAP4_DSI1_PIPD_MASK; 1499 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 1500 } else if (dsi->module_id == 1) { 1501 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 1502 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 1503 pipd_mask = OMAP4_DSI2_PIPD_MASK; 1504 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 1505 } else { 1506 return -ENODEV; 1507 } 1508 1509 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, 1510 enable_mask | pipd_mask, 1511 (lanes << enable_shift) | (lanes << pipd_shift)); 1512 } 1513 1514 /* OMAP5 CONTROL_DSIPHY */ 1515 1516 #define OMAP5_DSIPHY_SYSCON_OFFSET 0x74 1517 1518 #define OMAP5_DSI1_LANEENABLE_SHIFT 24 1519 #define OMAP5_DSI2_LANEENABLE_SHIFT 19 1520 #define OMAP5_DSI_LANEENABLE_MASK 0x1f 1521 1522 static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1523 { 1524 u32 enable_shift; 1525 1526 if (dsi->module_id == 0) 1527 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT; 1528 else if (dsi->module_id == 1) 1529 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT; 1530 else 1531 return -ENODEV; 1532 1533 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, 1534 OMAP5_DSI_LANEENABLE_MASK << enable_shift, 1535 lanes << enable_shift); 1536 } 1537 1538 static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) 1539 { 1540 if (dsi->data->model == DSI_MODEL_OMAP4) 1541 return dsi_omap4_mux_pads(dsi, lane_mask); 1542 if (dsi->data->model == DSI_MODEL_OMAP5) 1543 return dsi_omap5_mux_pads(dsi, lane_mask); 1544 return 0; 1545 } 1546 1547 static void dsi_disable_pads(struct dsi_data *dsi) 1548 { 1549 if (dsi->data->model == DSI_MODEL_OMAP4) 1550 dsi_omap4_mux_pads(dsi, 0); 1551 else if (dsi->data->model == DSI_MODEL_OMAP5) 1552 dsi_omap5_mux_pads(dsi, 0); 1553 } 1554 1555 static int dsi_cio_init(struct dsi_data *dsi) 1556 { 1557 int r; 1558 u32 l; 1559 1560 DSSDBG("DSI CIO init starts"); 1561 1562 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi)); 1563 if (r) 1564 return r; 1565 1566 dsi_enable_scp_clk(dsi); 1567 1568 /* A dummy read using the SCP interface to any DSIPHY register is 1569 * required after DSIPHY reset to complete the reset of the DSI complex 1570 * I/O. */ 1571 dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1572 1573 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) { 1574 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 1575 r = -EIO; 1576 goto err_scp_clk_dom; 1577 } 1578 1579 r = dsi_set_lane_config(dsi); 1580 if (r) 1581 goto err_scp_clk_dom; 1582 1583 /* set TX STOP MODE timer to maximum for this operation */ 1584 l = dsi_read_reg(dsi, DSI_TIMING1); 1585 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 1586 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 1587 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 1588 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 1589 dsi_write_reg(dsi, DSI_TIMING1, l); 1590 1591 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON); 1592 if (r) 1593 goto err_cio_pwr; 1594 1595 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) { 1596 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 1597 r = -ENODEV; 1598 goto err_cio_pwr_dom; 1599 } 1600 1601 dsi_if_enable(dsi, true); 1602 dsi_if_enable(dsi, false); 1603 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 1604 1605 r = dsi_cio_wait_tx_clk_esc_reset(dsi); 1606 if (r) 1607 goto err_tx_clk_esc_rst; 1608 1609 /* FORCE_TX_STOP_MODE_IO */ 1610 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); 1611 1612 dsi_cio_timings(dsi); 1613 1614 /* DDR_CLK_ALWAYS_ON */ 1615 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1616 !(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS), 1617 13, 13); 1618 1619 DSSDBG("CIO init done\n"); 1620 1621 return 0; 1622 1623 err_tx_clk_esc_rst: 1624 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 1625 err_cio_pwr_dom: 1626 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 1627 err_cio_pwr: 1628 err_scp_clk_dom: 1629 dsi_disable_scp_clk(dsi); 1630 dsi_disable_pads(dsi); 1631 return r; 1632 } 1633 1634 static void dsi_cio_uninit(struct dsi_data *dsi) 1635 { 1636 /* DDR_CLK_ALWAYS_ON */ 1637 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); 1638 1639 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 1640 dsi_disable_scp_clk(dsi); 1641 dsi_disable_pads(dsi); 1642 } 1643 1644 static void dsi_config_tx_fifo(struct dsi_data *dsi, 1645 enum fifo_size size1, enum fifo_size size2, 1646 enum fifo_size size3, enum fifo_size size4) 1647 { 1648 u32 r = 0; 1649 int add = 0; 1650 int i; 1651 1652 dsi->vc[0].tx_fifo_size = size1; 1653 dsi->vc[1].tx_fifo_size = size2; 1654 dsi->vc[2].tx_fifo_size = size3; 1655 dsi->vc[3].tx_fifo_size = size4; 1656 1657 for (i = 0; i < 4; i++) { 1658 u8 v; 1659 int size = dsi->vc[i].tx_fifo_size; 1660 1661 if (add + size > 4) { 1662 DSSERR("Illegal FIFO configuration\n"); 1663 BUG(); 1664 return; 1665 } 1666 1667 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 1668 r |= v << (8 * i); 1669 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 1670 add += size; 1671 } 1672 1673 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r); 1674 } 1675 1676 static void dsi_config_rx_fifo(struct dsi_data *dsi, 1677 enum fifo_size size1, enum fifo_size size2, 1678 enum fifo_size size3, enum fifo_size size4) 1679 { 1680 u32 r = 0; 1681 int add = 0; 1682 int i; 1683 1684 dsi->vc[0].rx_fifo_size = size1; 1685 dsi->vc[1].rx_fifo_size = size2; 1686 dsi->vc[2].rx_fifo_size = size3; 1687 dsi->vc[3].rx_fifo_size = size4; 1688 1689 for (i = 0; i < 4; i++) { 1690 u8 v; 1691 int size = dsi->vc[i].rx_fifo_size; 1692 1693 if (add + size > 4) { 1694 DSSERR("Illegal FIFO configuration\n"); 1695 BUG(); 1696 return; 1697 } 1698 1699 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 1700 r |= v << (8 * i); 1701 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 1702 add += size; 1703 } 1704 1705 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r); 1706 } 1707 1708 static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi) 1709 { 1710 u32 r; 1711 1712 r = dsi_read_reg(dsi, DSI_TIMING1); 1713 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 1714 dsi_write_reg(dsi, DSI_TIMING1, r); 1715 1716 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) { 1717 DSSERR("TX_STOP bit not going down\n"); 1718 return -EIO; 1719 } 1720 1721 return 0; 1722 } 1723 1724 static bool dsi_vc_is_enabled(struct dsi_data *dsi, int vc) 1725 { 1726 return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0); 1727 } 1728 1729 static void dsi_packet_sent_handler_vp(void *data, u32 mask) 1730 { 1731 struct dsi_packet_sent_handler_data *vp_data = 1732 (struct dsi_packet_sent_handler_data *) data; 1733 struct dsi_data *dsi = vp_data->dsi; 1734 const int vc = dsi->update_vc; 1735 u8 bit = dsi->te_enabled ? 30 : 31; 1736 1737 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit) == 0) 1738 complete(vp_data->completion); 1739 } 1740 1741 static int dsi_sync_vc_vp(struct dsi_data *dsi, int vc) 1742 { 1743 DECLARE_COMPLETION_ONSTACK(completion); 1744 struct dsi_packet_sent_handler_data vp_data = { 1745 .dsi = dsi, 1746 .completion = &completion 1747 }; 1748 int r = 0; 1749 u8 bit; 1750 1751 bit = dsi->te_enabled ? 30 : 31; 1752 1753 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, 1754 &vp_data, DSI_VC_IRQ_PACKET_SENT); 1755 if (r) 1756 goto err0; 1757 1758 /* Wait for completion only if TE_EN/TE_START is still set */ 1759 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit)) { 1760 if (wait_for_completion_timeout(&completion, 1761 msecs_to_jiffies(10)) == 0) { 1762 DSSERR("Failed to complete previous frame transfer\n"); 1763 r = -EIO; 1764 goto err1; 1765 } 1766 } 1767 1768 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, 1769 &vp_data, DSI_VC_IRQ_PACKET_SENT); 1770 1771 return 0; 1772 err1: 1773 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_vp, 1774 &vp_data, DSI_VC_IRQ_PACKET_SENT); 1775 err0: 1776 return r; 1777 } 1778 1779 static void dsi_packet_sent_handler_l4(void *data, u32 mask) 1780 { 1781 struct dsi_packet_sent_handler_data *l4_data = 1782 (struct dsi_packet_sent_handler_data *) data; 1783 struct dsi_data *dsi = l4_data->dsi; 1784 const int vc = dsi->update_vc; 1785 1786 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0) 1787 complete(l4_data->completion); 1788 } 1789 1790 static int dsi_sync_vc_l4(struct dsi_data *dsi, int vc) 1791 { 1792 DECLARE_COMPLETION_ONSTACK(completion); 1793 struct dsi_packet_sent_handler_data l4_data = { 1794 .dsi = dsi, 1795 .completion = &completion 1796 }; 1797 int r = 0; 1798 1799 r = dsi_register_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, 1800 &l4_data, DSI_VC_IRQ_PACKET_SENT); 1801 if (r) 1802 goto err0; 1803 1804 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 1805 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) { 1806 if (wait_for_completion_timeout(&completion, 1807 msecs_to_jiffies(10)) == 0) { 1808 DSSERR("Failed to complete previous l4 transfer\n"); 1809 r = -EIO; 1810 goto err1; 1811 } 1812 } 1813 1814 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, 1815 &l4_data, DSI_VC_IRQ_PACKET_SENT); 1816 1817 return 0; 1818 err1: 1819 dsi_unregister_isr_vc(dsi, vc, dsi_packet_sent_handler_l4, 1820 &l4_data, DSI_VC_IRQ_PACKET_SENT); 1821 err0: 1822 return r; 1823 } 1824 1825 static int dsi_sync_vc(struct dsi_data *dsi, int vc) 1826 { 1827 WARN_ON(!dsi_bus_is_locked(dsi)); 1828 1829 WARN_ON(in_interrupt()); 1830 1831 if (!dsi_vc_is_enabled(dsi, vc)) 1832 return 0; 1833 1834 switch (dsi->vc[vc].source) { 1835 case DSI_VC_SOURCE_VP: 1836 return dsi_sync_vc_vp(dsi, vc); 1837 case DSI_VC_SOURCE_L4: 1838 return dsi_sync_vc_l4(dsi, vc); 1839 default: 1840 BUG(); 1841 return -EINVAL; 1842 } 1843 } 1844 1845 static int dsi_vc_enable(struct dsi_data *dsi, int vc, bool enable) 1846 { 1847 DSSDBG("dsi_vc_enable vc %d, enable %d\n", 1848 vc, enable); 1849 1850 enable = enable ? 1 : 0; 1851 1852 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 0, 0); 1853 1854 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(vc), 0, enable)) { 1855 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 1856 return -EIO; 1857 } 1858 1859 return 0; 1860 } 1861 1862 static void dsi_vc_initial_config(struct dsi_data *dsi, int vc) 1863 { 1864 u32 r; 1865 1866 DSSDBG("Initial config of VC %d", vc); 1867 1868 r = dsi_read_reg(dsi, DSI_VC_CTRL(vc)); 1869 1870 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 1871 DSSERR("VC(%d) busy when trying to configure it!\n", 1872 vc); 1873 1874 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 1875 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 1876 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 1877 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 1878 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 1879 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 1880 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 1881 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) 1882 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 1883 1884 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 1885 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 1886 1887 dsi_write_reg(dsi, DSI_VC_CTRL(vc), r); 1888 1889 dsi->vc[vc].source = DSI_VC_SOURCE_L4; 1890 } 1891 1892 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int vc, 1893 bool enable) 1894 { 1895 struct dsi_data *dsi = to_dsi_data(dssdev); 1896 1897 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", vc, enable); 1898 1899 if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable) 1900 return; 1901 1902 WARN_ON(!dsi_bus_is_locked(dsi)); 1903 1904 dsi_vc_enable(dsi, vc, 0); 1905 dsi_if_enable(dsi, 0); 1906 1907 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 9, 9); 1908 1909 dsi_vc_enable(dsi, vc, 1); 1910 dsi_if_enable(dsi, 1); 1911 1912 dsi_force_tx_stop_mode_io(dsi); 1913 } 1914 1915 static void dsi_vc_flush_long_data(struct dsi_data *dsi, int vc) 1916 { 1917 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 1918 u32 val; 1919 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); 1920 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 1921 (val >> 0) & 0xff, 1922 (val >> 8) & 0xff, 1923 (val >> 16) & 0xff, 1924 (val >> 24) & 0xff); 1925 } 1926 } 1927 1928 static void dsi_show_rx_ack_with_err(u16 err) 1929 { 1930 DSSERR("\tACK with ERROR (%#x):\n", err); 1931 if (err & (1 << 0)) 1932 DSSERR("\t\tSoT Error\n"); 1933 if (err & (1 << 1)) 1934 DSSERR("\t\tSoT Sync Error\n"); 1935 if (err & (1 << 2)) 1936 DSSERR("\t\tEoT Sync Error\n"); 1937 if (err & (1 << 3)) 1938 DSSERR("\t\tEscape Mode Entry Command Error\n"); 1939 if (err & (1 << 4)) 1940 DSSERR("\t\tLP Transmit Sync Error\n"); 1941 if (err & (1 << 5)) 1942 DSSERR("\t\tHS Receive Timeout Error\n"); 1943 if (err & (1 << 6)) 1944 DSSERR("\t\tFalse Control Error\n"); 1945 if (err & (1 << 7)) 1946 DSSERR("\t\t(reserved7)\n"); 1947 if (err & (1 << 8)) 1948 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 1949 if (err & (1 << 9)) 1950 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 1951 if (err & (1 << 10)) 1952 DSSERR("\t\tChecksum Error\n"); 1953 if (err & (1 << 11)) 1954 DSSERR("\t\tData type not recognized\n"); 1955 if (err & (1 << 12)) 1956 DSSERR("\t\tInvalid VC ID\n"); 1957 if (err & (1 << 13)) 1958 DSSERR("\t\tInvalid Transmission Length\n"); 1959 if (err & (1 << 14)) 1960 DSSERR("\t\t(reserved14)\n"); 1961 if (err & (1 << 15)) 1962 DSSERR("\t\tDSI Protocol Violation\n"); 1963 } 1964 1965 static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int vc) 1966 { 1967 /* RX_FIFO_NOT_EMPTY */ 1968 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 1969 u32 val; 1970 u8 dt; 1971 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); 1972 DSSERR("\trawval %#08x\n", val); 1973 dt = FLD_GET(val, 5, 0); 1974 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 1975 u16 err = FLD_GET(val, 23, 8); 1976 dsi_show_rx_ack_with_err(err); 1977 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 1978 DSSERR("\tDCS short response, 1 byte: %#x\n", 1979 FLD_GET(val, 23, 8)); 1980 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 1981 DSSERR("\tDCS short response, 2 byte: %#x\n", 1982 FLD_GET(val, 23, 8)); 1983 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 1984 DSSERR("\tDCS long response, len %d\n", 1985 FLD_GET(val, 23, 8)); 1986 dsi_vc_flush_long_data(dsi, vc); 1987 } else { 1988 DSSERR("\tunknown datatype 0x%02x\n", dt); 1989 } 1990 } 1991 return 0; 1992 } 1993 1994 static int dsi_vc_send_bta(struct dsi_data *dsi, int vc) 1995 { 1996 if (dsi->debug_write || dsi->debug_read) 1997 DSSDBG("dsi_vc_send_bta %d\n", vc); 1998 1999 WARN_ON(!dsi_bus_is_locked(dsi)); 2000 2001 /* RX_FIFO_NOT_EMPTY */ 2002 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 2003 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2004 dsi_vc_flush_receive_data(dsi, vc); 2005 } 2006 2007 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 6, 6); /* BTA_EN */ 2008 2009 /* flush posted write */ 2010 dsi_read_reg(dsi, DSI_VC_CTRL(vc)); 2011 2012 return 0; 2013 } 2014 2015 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int vc) 2016 { 2017 struct dsi_data *dsi = to_dsi_data(dssdev); 2018 DECLARE_COMPLETION_ONSTACK(completion); 2019 int r = 0; 2020 u32 err; 2021 2022 r = dsi_register_isr_vc(dsi, vc, dsi_completion_handler, 2023 &completion, DSI_VC_IRQ_BTA); 2024 if (r) 2025 goto err0; 2026 2027 r = dsi_register_isr(dsi, dsi_completion_handler, &completion, 2028 DSI_IRQ_ERROR_MASK); 2029 if (r) 2030 goto err1; 2031 2032 r = dsi_vc_send_bta(dsi, vc); 2033 if (r) 2034 goto err2; 2035 2036 if (wait_for_completion_timeout(&completion, 2037 msecs_to_jiffies(500)) == 0) { 2038 DSSERR("Failed to receive BTA\n"); 2039 r = -EIO; 2040 goto err2; 2041 } 2042 2043 err = dsi_get_errors(dsi); 2044 if (err) { 2045 DSSERR("Error while sending BTA: %x\n", err); 2046 r = -EIO; 2047 goto err2; 2048 } 2049 err2: 2050 dsi_unregister_isr(dsi, dsi_completion_handler, &completion, 2051 DSI_IRQ_ERROR_MASK); 2052 err1: 2053 dsi_unregister_isr_vc(dsi, vc, dsi_completion_handler, 2054 &completion, DSI_VC_IRQ_BTA); 2055 err0: 2056 return r; 2057 } 2058 2059 static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int vc, 2060 int channel, u8 data_type, u16 len, 2061 u8 ecc) 2062 { 2063 u32 val; 2064 u8 data_id; 2065 2066 WARN_ON(!dsi_bus_is_locked(dsi)); 2067 2068 data_id = data_type | channel << 6; 2069 2070 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2071 FLD_VAL(ecc, 31, 24); 2072 2073 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(vc), val); 2074 } 2075 2076 static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int vc, 2077 u8 b1, u8 b2, u8 b3, u8 b4) 2078 { 2079 u32 val; 2080 2081 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2082 2083 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2084 b1, b2, b3, b4, val); */ 2085 2086 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(vc), val); 2087 } 2088 2089 static int dsi_vc_send_long(struct dsi_data *dsi, int vc, 2090 const struct mipi_dsi_msg *msg) 2091 { 2092 /*u32 val; */ 2093 int i; 2094 const u8 *p; 2095 int r = 0; 2096 u8 b1, b2, b3, b4; 2097 2098 if (dsi->debug_write) 2099 DSSDBG("dsi_vc_send_long, %zu bytes\n", msg->tx_len); 2100 2101 /* len + header */ 2102 if (dsi->vc[vc].tx_fifo_size * 32 * 4 < msg->tx_len + 4) { 2103 DSSERR("unable to send long packet: packet too long.\n"); 2104 return -EINVAL; 2105 } 2106 2107 dsi_vc_write_long_header(dsi, vc, msg->channel, msg->type, msg->tx_len, 0); 2108 2109 p = msg->tx_buf; 2110 for (i = 0; i < msg->tx_len >> 2; i++) { 2111 if (dsi->debug_write) 2112 DSSDBG("\tsending full packet %d\n", i); 2113 2114 b1 = *p++; 2115 b2 = *p++; 2116 b3 = *p++; 2117 b4 = *p++; 2118 2119 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, b4); 2120 } 2121 2122 i = msg->tx_len % 4; 2123 if (i) { 2124 b1 = 0; b2 = 0; b3 = 0; 2125 2126 if (dsi->debug_write) 2127 DSSDBG("\tsending remainder bytes %d\n", i); 2128 2129 switch (i) { 2130 case 3: 2131 b1 = *p++; 2132 b2 = *p++; 2133 b3 = *p++; 2134 break; 2135 case 2: 2136 b1 = *p++; 2137 b2 = *p++; 2138 break; 2139 case 1: 2140 b1 = *p++; 2141 break; 2142 } 2143 2144 dsi_vc_write_long_payload(dsi, vc, b1, b2, b3, 0); 2145 } 2146 2147 return r; 2148 } 2149 2150 static int dsi_vc_send_short(struct dsi_data *dsi, int vc, 2151 const struct mipi_dsi_msg *msg) 2152 { 2153 struct mipi_dsi_packet pkt; 2154 int ret; 2155 u32 r; 2156 2157 ret = mipi_dsi_create_packet(&pkt, msg); 2158 if (ret < 0) 2159 return ret; 2160 2161 WARN_ON(!dsi_bus_is_locked(dsi)); 2162 2163 if (dsi->debug_write) 2164 DSSDBG("dsi_vc_send_short(vc%d, dt %#x, b1 %#x, b2 %#x)\n", 2165 vc, msg->type, pkt.header[1], pkt.header[2]); 2166 2167 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(vc)), 16, 16)) { 2168 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2169 return -EINVAL; 2170 } 2171 2172 r = pkt.header[3] << 24 | pkt.header[2] << 16 | pkt.header[1] << 8 | 2173 pkt.header[0]; 2174 2175 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc), r); 2176 2177 return 0; 2178 } 2179 2180 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel) 2181 { 2182 const struct mipi_dsi_msg msg = { 2183 .channel = channel, 2184 .type = MIPI_DSI_NULL_PACKET, 2185 }; 2186 2187 return dsi_vc_send_long(dsi, vc, &msg); 2188 } 2189 2190 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int vc, 2191 const struct mipi_dsi_msg *msg) 2192 { 2193 struct dsi_data *dsi = to_dsi_data(dssdev); 2194 int r; 2195 2196 if (mipi_dsi_packet_format_is_short(msg->type)) 2197 r = dsi_vc_send_short(dsi, vc, msg); 2198 else 2199 r = dsi_vc_send_long(dsi, vc, msg); 2200 2201 if (r < 0) 2202 return r; 2203 2204 /* 2205 * TODO: we do not always have to do the BTA sync, for example 2206 * we can improve performance by setting the update window 2207 * information without sending BTA sync between the commands. 2208 * In that case we can return early. 2209 */ 2210 2211 r = dsi_vc_send_bta_sync(dssdev, vc); 2212 if (r) { 2213 DSSERR("bta sync failed\n"); 2214 return r; 2215 } 2216 2217 /* RX_FIFO_NOT_EMPTY */ 2218 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { 2219 DSSERR("rx fifo not empty after write, dumping data:\n"); 2220 dsi_vc_flush_receive_data(dsi, vc); 2221 return -EIO; 2222 } 2223 2224 return 0; 2225 } 2226 2227 static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int vc, u8 *buf, 2228 int buflen, enum dss_dsi_content_type type) 2229 { 2230 u32 val; 2231 u8 dt; 2232 int r; 2233 2234 /* RX_FIFO_NOT_EMPTY */ 2235 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20) == 0) { 2236 DSSERR("RX fifo empty when trying to read.\n"); 2237 r = -EIO; 2238 goto err; 2239 } 2240 2241 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc)); 2242 if (dsi->debug_read) 2243 DSSDBG("\theader: %08x\n", val); 2244 dt = FLD_GET(val, 5, 0); 2245 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2246 u16 err = FLD_GET(val, 23, 8); 2247 dsi_show_rx_ack_with_err(err); 2248 r = -EIO; 2249 goto err; 2250 2251 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2252 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2253 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2254 u8 data = FLD_GET(val, 15, 8); 2255 if (dsi->debug_read) 2256 DSSDBG("\t%s short response, 1 byte: %02x\n", 2257 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2258 "DCS", data); 2259 2260 if (buflen < 1) { 2261 r = -EIO; 2262 goto err; 2263 } 2264 2265 buf[0] = data; 2266 2267 return 1; 2268 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2269 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2270 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2271 u16 data = FLD_GET(val, 23, 8); 2272 if (dsi->debug_read) 2273 DSSDBG("\t%s short response, 2 byte: %04x\n", 2274 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2275 "DCS", data); 2276 2277 if (buflen < 2) { 2278 r = -EIO; 2279 goto err; 2280 } 2281 2282 buf[0] = data & 0xff; 2283 buf[1] = (data >> 8) & 0xff; 2284 2285 return 2; 2286 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2287 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 2288 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 2289 int w; 2290 int len = FLD_GET(val, 23, 8); 2291 if (dsi->debug_read) 2292 DSSDBG("\t%s long response, len %d\n", 2293 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2294 "DCS", len); 2295 2296 if (len > buflen) { 2297 r = -EIO; 2298 goto err; 2299 } 2300 2301 /* two byte checksum ends the packet, not included in len */ 2302 for (w = 0; w < len + 2;) { 2303 int b; 2304 val = dsi_read_reg(dsi, 2305 DSI_VC_SHORT_PACKET_HEADER(vc)); 2306 if (dsi->debug_read) 2307 DSSDBG("\t\t%02x %02x %02x %02x\n", 2308 (val >> 0) & 0xff, 2309 (val >> 8) & 0xff, 2310 (val >> 16) & 0xff, 2311 (val >> 24) & 0xff); 2312 2313 for (b = 0; b < 4; ++b) { 2314 if (w < len) 2315 buf[w] = (val >> (b * 8)) & 0xff; 2316 /* we discard the 2 byte checksum */ 2317 ++w; 2318 } 2319 } 2320 2321 return len; 2322 } else { 2323 DSSERR("\tunknown datatype 0x%02x\n", dt); 2324 r = -EIO; 2325 goto err; 2326 } 2327 2328 err: 2329 DSSERR("dsi_vc_read_rx_fifo(vc %d type %s) failed\n", vc, 2330 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 2331 2332 return r; 2333 } 2334 2335 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int vc, 2336 const struct mipi_dsi_msg *msg) 2337 { 2338 struct dsi_data *dsi = to_dsi_data(dssdev); 2339 u8 cmd = ((u8 *)msg->tx_buf)[0]; 2340 int r; 2341 2342 if (dsi->debug_read) 2343 DSSDBG("%s(vc %d, cmd %x)\n", __func__, vc, cmd); 2344 2345 r = dsi_vc_send_short(dsi, vc, msg); 2346 if (r) 2347 goto err; 2348 2349 r = dsi_vc_send_bta_sync(dssdev, vc); 2350 if (r) 2351 goto err; 2352 2353 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, 2354 DSS_DSI_CONTENT_DCS); 2355 if (r < 0) 2356 goto err; 2357 2358 if (r != msg->rx_len) { 2359 r = -EIO; 2360 goto err; 2361 } 2362 2363 return 0; 2364 err: 2365 DSSERR("%s(vc %d, cmd 0x%02x) failed\n", __func__, vc, cmd); 2366 return r; 2367 } 2368 2369 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int vc, 2370 const struct mipi_dsi_msg *msg) 2371 { 2372 struct dsi_data *dsi = to_dsi_data(dssdev); 2373 int r; 2374 2375 r = dsi_vc_send_short(dsi, vc, msg); 2376 if (r) 2377 goto err; 2378 2379 r = dsi_vc_send_bta_sync(dssdev, vc); 2380 if (r) 2381 goto err; 2382 2383 r = dsi_vc_read_rx_fifo(dsi, vc, msg->rx_buf, msg->rx_len, 2384 DSS_DSI_CONTENT_GENERIC); 2385 if (r < 0) 2386 goto err; 2387 2388 if (r != msg->rx_len) { 2389 r = -EIO; 2390 goto err; 2391 } 2392 2393 return 0; 2394 err: 2395 DSSERR("%s(vc %d, reqlen %zu) failed\n", __func__, vc, msg->tx_len); 2396 return r; 2397 } 2398 2399 static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks, 2400 bool x4, bool x16) 2401 { 2402 unsigned long fck; 2403 unsigned long total_ticks; 2404 u32 r; 2405 2406 BUG_ON(ticks > 0x1fff); 2407 2408 /* ticks in DSI_FCK */ 2409 fck = dsi_fclk_rate(dsi); 2410 2411 r = dsi_read_reg(dsi, DSI_TIMING2); 2412 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 2413 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 2414 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 2415 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 2416 dsi_write_reg(dsi, DSI_TIMING2, r); 2417 2418 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 2419 2420 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 2421 total_ticks, 2422 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 2423 (total_ticks * 1000) / (fck / 1000 / 1000)); 2424 } 2425 2426 static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks, 2427 bool x8, bool x16) 2428 { 2429 unsigned long fck; 2430 unsigned long total_ticks; 2431 u32 r; 2432 2433 BUG_ON(ticks > 0x1fff); 2434 2435 /* ticks in DSI_FCK */ 2436 fck = dsi_fclk_rate(dsi); 2437 2438 r = dsi_read_reg(dsi, DSI_TIMING1); 2439 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 2440 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 2441 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 2442 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 2443 dsi_write_reg(dsi, DSI_TIMING1, r); 2444 2445 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 2446 2447 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 2448 total_ticks, 2449 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 2450 (total_ticks * 1000) / (fck / 1000 / 1000)); 2451 } 2452 2453 static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks, 2454 bool x4, bool x16) 2455 { 2456 unsigned long fck; 2457 unsigned long total_ticks; 2458 u32 r; 2459 2460 BUG_ON(ticks > 0x1fff); 2461 2462 /* ticks in DSI_FCK */ 2463 fck = dsi_fclk_rate(dsi); 2464 2465 r = dsi_read_reg(dsi, DSI_TIMING1); 2466 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2467 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 2468 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 2469 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 2470 dsi_write_reg(dsi, DSI_TIMING1, r); 2471 2472 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 2473 2474 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 2475 total_ticks, 2476 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 2477 (total_ticks * 1000) / (fck / 1000 / 1000)); 2478 } 2479 2480 static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks, 2481 bool x4, bool x16) 2482 { 2483 unsigned long fck; 2484 unsigned long total_ticks; 2485 u32 r; 2486 2487 BUG_ON(ticks > 0x1fff); 2488 2489 /* ticks in TxByteClkHS */ 2490 fck = dsi_get_txbyteclkhs(dsi); 2491 2492 r = dsi_read_reg(dsi, DSI_TIMING2); 2493 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 2494 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 2495 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 2496 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 2497 dsi_write_reg(dsi, DSI_TIMING2, r); 2498 2499 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 2500 2501 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 2502 total_ticks, 2503 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 2504 (total_ticks * 1000) / (fck / 1000 / 1000)); 2505 } 2506 2507 static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi) 2508 { 2509 int num_line_buffers; 2510 2511 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2512 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2513 const struct videomode *vm = &dsi->vm; 2514 /* 2515 * Don't use line buffers if width is greater than the video 2516 * port's line buffer size 2517 */ 2518 if (dsi->line_buffer_size <= vm->hactive * bpp / 8) 2519 num_line_buffers = 0; 2520 else 2521 num_line_buffers = 2; 2522 } else { 2523 /* Use maximum number of line buffers in command mode */ 2524 num_line_buffers = 2; 2525 } 2526 2527 /* LINE_BUFFER */ 2528 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12); 2529 } 2530 2531 static void dsi_config_vp_sync_events(struct dsi_data *dsi) 2532 { 2533 bool sync_end; 2534 u32 r; 2535 2536 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 2537 sync_end = true; 2538 else 2539 sync_end = false; 2540 2541 r = dsi_read_reg(dsi, DSI_CTRL); 2542 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 2543 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 2544 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 2545 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 2546 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 2547 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 2548 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 2549 dsi_write_reg(dsi, DSI_CTRL, r); 2550 } 2551 2552 static void dsi_config_blanking_modes(struct dsi_data *dsi) 2553 { 2554 int blanking_mode = dsi->vm_timings.blanking_mode; 2555 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 2556 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 2557 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 2558 u32 r; 2559 2560 /* 2561 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 2562 * 1 = Long blanking packets are sent in corresponding blanking periods 2563 */ 2564 r = dsi_read_reg(dsi, DSI_CTRL); 2565 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 2566 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 2567 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 2568 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 2569 dsi_write_reg(dsi, DSI_CTRL, r); 2570 } 2571 2572 /* 2573 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 2574 * results in maximum transition time for data and clock lanes to enter and 2575 * exit HS mode. Hence, this is the scenario where the least amount of command 2576 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 2577 * clock cycles that can be used to interleave command mode data in HS so that 2578 * all scenarios are satisfied. 2579 */ 2580 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 2581 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 2582 { 2583 int transition; 2584 2585 /* 2586 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 2587 * time of data lanes only, if it isn't set, we need to consider HS 2588 * transition time of both data and clock lanes. HS transition time 2589 * of Scenario 3 is considered. 2590 */ 2591 if (ddr_alwon) { 2592 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 2593 } else { 2594 int trans1, trans2; 2595 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 2596 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 2597 enter_hs + 1; 2598 transition = max(trans1, trans2); 2599 } 2600 2601 return blank > transition ? blank - transition : 0; 2602 } 2603 2604 /* 2605 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 2606 * results in maximum transition time for data lanes to enter and exit LP mode. 2607 * Hence, this is the scenario where the least amount of command mode data can 2608 * be interleaved. We program the minimum amount of bytes that can be 2609 * interleaved in LP so that all scenarios are satisfied. 2610 */ 2611 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 2612 int lp_clk_div, int tdsi_fclk) 2613 { 2614 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 2615 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 2616 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 2617 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 2618 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 2619 2620 /* maximum LP transition time according to Scenario 1 */ 2621 trans_lp = exit_hs + max(enter_hs, 2) + 1; 2622 2623 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 2624 tlp_avail = thsbyte_clk * (blank - trans_lp); 2625 2626 ttxclkesc = tdsi_fclk * lp_clk_div; 2627 2628 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 2629 26) / 16; 2630 2631 return max(lp_inter, 0); 2632 } 2633 2634 static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi) 2635 { 2636 int blanking_mode; 2637 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 2638 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 2639 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 2640 int tclk_trail, ths_exit, exiths_clk; 2641 bool ddr_alwon; 2642 const struct videomode *vm = &dsi->vm; 2643 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2644 int ndl = dsi->num_lanes_used - 1; 2645 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 2646 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 2647 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 2648 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 2649 int bl_interleave_hs = 0, bl_interleave_lp = 0; 2650 u32 r; 2651 2652 r = dsi_read_reg(dsi, DSI_CTRL); 2653 blanking_mode = FLD_GET(r, 20, 20); 2654 hfp_blanking_mode = FLD_GET(r, 21, 21); 2655 hbp_blanking_mode = FLD_GET(r, 22, 22); 2656 hsa_blanking_mode = FLD_GET(r, 23, 23); 2657 2658 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 2659 hbp = FLD_GET(r, 11, 0); 2660 hfp = FLD_GET(r, 23, 12); 2661 hsa = FLD_GET(r, 31, 24); 2662 2663 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 2664 ddr_clk_post = FLD_GET(r, 7, 0); 2665 ddr_clk_pre = FLD_GET(r, 15, 8); 2666 2667 r = dsi_read_reg(dsi, DSI_VM_TIMING7); 2668 exit_hs_mode_lat = FLD_GET(r, 15, 0); 2669 enter_hs_mode_lat = FLD_GET(r, 31, 16); 2670 2671 r = dsi_read_reg(dsi, DSI_CLK_CTRL); 2672 lp_clk_div = FLD_GET(r, 12, 0); 2673 ddr_alwon = FLD_GET(r, 13, 13); 2674 2675 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 2676 ths_exit = FLD_GET(r, 7, 0); 2677 2678 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 2679 tclk_trail = FLD_GET(r, 15, 8); 2680 2681 exiths_clk = ths_exit + tclk_trail; 2682 2683 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 2684 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 2685 2686 if (!hsa_blanking_mode) { 2687 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 2688 enter_hs_mode_lat, exit_hs_mode_lat, 2689 exiths_clk, ddr_clk_pre, ddr_clk_post); 2690 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 2691 enter_hs_mode_lat, exit_hs_mode_lat, 2692 lp_clk_div, dsi_fclk_hsdiv); 2693 } 2694 2695 if (!hfp_blanking_mode) { 2696 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 2697 enter_hs_mode_lat, exit_hs_mode_lat, 2698 exiths_clk, ddr_clk_pre, ddr_clk_post); 2699 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 2700 enter_hs_mode_lat, exit_hs_mode_lat, 2701 lp_clk_div, dsi_fclk_hsdiv); 2702 } 2703 2704 if (!hbp_blanking_mode) { 2705 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 2706 enter_hs_mode_lat, exit_hs_mode_lat, 2707 exiths_clk, ddr_clk_pre, ddr_clk_post); 2708 2709 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 2710 enter_hs_mode_lat, exit_hs_mode_lat, 2711 lp_clk_div, dsi_fclk_hsdiv); 2712 } 2713 2714 if (!blanking_mode) { 2715 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 2716 enter_hs_mode_lat, exit_hs_mode_lat, 2717 exiths_clk, ddr_clk_pre, ddr_clk_post); 2718 2719 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 2720 enter_hs_mode_lat, exit_hs_mode_lat, 2721 lp_clk_div, dsi_fclk_hsdiv); 2722 } 2723 2724 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 2725 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 2726 bl_interleave_hs); 2727 2728 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 2729 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 2730 bl_interleave_lp); 2731 2732 r = dsi_read_reg(dsi, DSI_VM_TIMING4); 2733 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 2734 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 2735 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 2736 dsi_write_reg(dsi, DSI_VM_TIMING4, r); 2737 2738 r = dsi_read_reg(dsi, DSI_VM_TIMING5); 2739 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 2740 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 2741 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 2742 dsi_write_reg(dsi, DSI_VM_TIMING5, r); 2743 2744 r = dsi_read_reg(dsi, DSI_VM_TIMING6); 2745 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 2746 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 2747 dsi_write_reg(dsi, DSI_VM_TIMING6, r); 2748 } 2749 2750 static int dsi_proto_config(struct dsi_data *dsi) 2751 { 2752 u32 r; 2753 int buswidth = 0; 2754 2755 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32, 2756 DSI_FIFO_SIZE_32, 2757 DSI_FIFO_SIZE_32, 2758 DSI_FIFO_SIZE_32); 2759 2760 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32, 2761 DSI_FIFO_SIZE_32, 2762 DSI_FIFO_SIZE_32, 2763 DSI_FIFO_SIZE_32); 2764 2765 /* XXX what values for the timeouts? */ 2766 dsi_set_stop_state_counter(dsi, 0x1000, false, false); 2767 dsi_set_ta_timeout(dsi, 0x1fff, true, true); 2768 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true); 2769 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true); 2770 2771 switch (mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt)) { 2772 case 16: 2773 buswidth = 0; 2774 break; 2775 case 18: 2776 buswidth = 1; 2777 break; 2778 case 24: 2779 buswidth = 2; 2780 break; 2781 default: 2782 BUG(); 2783 return -EINVAL; 2784 } 2785 2786 r = dsi_read_reg(dsi, DSI_CTRL); 2787 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 2788 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 2789 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 2790 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 2791 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 2792 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 2793 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 2794 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 2795 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { 2796 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 2797 /* DCS_CMD_CODE, 1=start, 0=continue */ 2798 r = FLD_MOD(r, 0, 25, 25); 2799 } 2800 2801 dsi_write_reg(dsi, DSI_CTRL, r); 2802 2803 dsi_config_vp_num_line_buffers(dsi); 2804 2805 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2806 dsi_config_vp_sync_events(dsi); 2807 dsi_config_blanking_modes(dsi); 2808 dsi_config_cmd_mode_interleaving(dsi); 2809 } 2810 2811 dsi_vc_initial_config(dsi, 0); 2812 dsi_vc_initial_config(dsi, 1); 2813 dsi_vc_initial_config(dsi, 2); 2814 dsi_vc_initial_config(dsi, 3); 2815 2816 return 0; 2817 } 2818 2819 static void dsi_proto_timings(struct dsi_data *dsi) 2820 { 2821 unsigned int tlpx, tclk_zero, tclk_prepare; 2822 unsigned int tclk_pre, tclk_post; 2823 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero; 2824 unsigned int ths_trail, ths_exit; 2825 unsigned int ddr_clk_pre, ddr_clk_post; 2826 unsigned int enter_hs_mode_lat, exit_hs_mode_lat; 2827 unsigned int ths_eot; 2828 int ndl = dsi->num_lanes_used - 1; 2829 u32 r; 2830 2831 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 2832 ths_prepare = FLD_GET(r, 31, 24); 2833 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 2834 ths_zero = ths_prepare_ths_zero - ths_prepare; 2835 ths_trail = FLD_GET(r, 15, 8); 2836 ths_exit = FLD_GET(r, 7, 0); 2837 2838 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 2839 tlpx = FLD_GET(r, 20, 16) * 2; 2840 tclk_zero = FLD_GET(r, 7, 0); 2841 2842 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 2843 tclk_prepare = FLD_GET(r, 7, 0); 2844 2845 /* min 8*UI */ 2846 tclk_pre = 20; 2847 /* min 60ns + 52*UI */ 2848 tclk_post = ns2ddr(dsi, 60) + 26; 2849 2850 ths_eot = DIV_ROUND_UP(4, ndl); 2851 2852 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 2853 4); 2854 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 2855 2856 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 2857 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 2858 2859 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 2860 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 2861 r = FLD_MOD(r, ddr_clk_post, 7, 0); 2862 dsi_write_reg(dsi, DSI_CLK_TIMING, r); 2863 2864 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 2865 ddr_clk_pre, 2866 ddr_clk_post); 2867 2868 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 2869 DIV_ROUND_UP(ths_prepare, 4) + 2870 DIV_ROUND_UP(ths_zero + 3, 4); 2871 2872 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 2873 2874 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 2875 FLD_VAL(exit_hs_mode_lat, 15, 0); 2876 dsi_write_reg(dsi, DSI_VM_TIMING7, r); 2877 2878 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 2879 enter_hs_mode_lat, exit_hs_mode_lat); 2880 2881 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2882 /* TODO: Implement a video mode check_timings function */ 2883 int hsa = dsi->vm_timings.hsa; 2884 int hfp = dsi->vm_timings.hfp; 2885 int hbp = dsi->vm_timings.hbp; 2886 int vsa = dsi->vm_timings.vsa; 2887 int vfp = dsi->vm_timings.vfp; 2888 int vbp = dsi->vm_timings.vbp; 2889 int window_sync = dsi->vm_timings.window_sync; 2890 bool hsync_end; 2891 const struct videomode *vm = &dsi->vm; 2892 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2893 int tl, t_he, width_bytes; 2894 2895 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 2896 t_he = hsync_end ? 2897 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 2898 2899 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 2900 2901 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 2902 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 2903 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 2904 2905 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 2906 hfp, hsync_end ? hsa : 0, tl); 2907 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 2908 vsa, vm->vactive); 2909 2910 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 2911 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 2912 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 2913 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 2914 dsi_write_reg(dsi, DSI_VM_TIMING1, r); 2915 2916 r = dsi_read_reg(dsi, DSI_VM_TIMING2); 2917 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 2918 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 2919 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 2920 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 2921 dsi_write_reg(dsi, DSI_VM_TIMING2, r); 2922 2923 r = dsi_read_reg(dsi, DSI_VM_TIMING3); 2924 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ 2925 r = FLD_MOD(r, tl, 31, 16); /* TL */ 2926 dsi_write_reg(dsi, DSI_VM_TIMING3, r); 2927 } 2928 } 2929 2930 static int dsi_configure_pins(struct dsi_data *dsi, 2931 int num_pins, const u32 *pins) 2932 { 2933 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 2934 int num_lanes; 2935 int i; 2936 2937 static const enum dsi_lane_function functions[] = { 2938 DSI_LANE_CLK, 2939 DSI_LANE_DATA1, 2940 DSI_LANE_DATA2, 2941 DSI_LANE_DATA3, 2942 DSI_LANE_DATA4, 2943 }; 2944 2945 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 2946 || num_pins % 2 != 0) 2947 return -EINVAL; 2948 2949 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 2950 lanes[i].function = DSI_LANE_UNUSED; 2951 2952 num_lanes = 0; 2953 2954 for (i = 0; i < num_pins; i += 2) { 2955 u8 lane, pol; 2956 u32 dx, dy; 2957 2958 dx = pins[i]; 2959 dy = pins[i + 1]; 2960 2961 if (dx >= dsi->num_lanes_supported * 2) 2962 return -EINVAL; 2963 2964 if (dy >= dsi->num_lanes_supported * 2) 2965 return -EINVAL; 2966 2967 if (dx & 1) { 2968 if (dy != dx - 1) 2969 return -EINVAL; 2970 pol = 1; 2971 } else { 2972 if (dy != dx + 1) 2973 return -EINVAL; 2974 pol = 0; 2975 } 2976 2977 lane = dx / 2; 2978 2979 lanes[lane].function = functions[i / 2]; 2980 lanes[lane].polarity = pol; 2981 num_lanes++; 2982 } 2983 2984 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 2985 dsi->num_lanes_used = num_lanes; 2986 2987 return 0; 2988 } 2989 2990 static int dsi_enable_video_mode(struct dsi_data *dsi, int vc) 2991 { 2992 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 2993 u8 data_type; 2994 u16 word_count; 2995 2996 switch (dsi->pix_fmt) { 2997 case MIPI_DSI_FMT_RGB888: 2998 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 2999 break; 3000 case MIPI_DSI_FMT_RGB666: 3001 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3002 break; 3003 case MIPI_DSI_FMT_RGB666_PACKED: 3004 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3005 break; 3006 case MIPI_DSI_FMT_RGB565: 3007 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3008 break; 3009 default: 3010 return -EINVAL; 3011 } 3012 3013 dsi_if_enable(dsi, false); 3014 dsi_vc_enable(dsi, vc, false); 3015 3016 /* MODE, 1 = video mode */ 3017 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 4, 4); 3018 3019 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); 3020 3021 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, data_type, 3022 word_count, 0); 3023 3024 dsi_vc_enable(dsi, vc, true); 3025 dsi_if_enable(dsi, true); 3026 3027 return 0; 3028 } 3029 3030 static void dsi_disable_video_mode(struct dsi_data *dsi, int vc) 3031 { 3032 dsi_if_enable(dsi, false); 3033 dsi_vc_enable(dsi, vc, false); 3034 3035 /* MODE, 0 = command mode */ 3036 REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 0, 4, 4); 3037 3038 dsi_vc_enable(dsi, vc, true); 3039 dsi_if_enable(dsi, true); 3040 } 3041 3042 static void dsi_enable_video_output(struct omap_dss_device *dssdev, int vc) 3043 { 3044 struct dsi_data *dsi = to_dsi_data(dssdev); 3045 int r; 3046 3047 r = dsi_init_dispc(dsi); 3048 if (r) { 3049 dev_err(dsi->dev, "failed to init dispc!\n"); 3050 return; 3051 } 3052 3053 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3054 r = dsi_enable_video_mode(dsi, vc); 3055 if (r) 3056 goto err_video_mode; 3057 } 3058 3059 r = dss_mgr_enable(&dsi->output); 3060 if (r) 3061 goto err_mgr_enable; 3062 3063 return; 3064 3065 err_mgr_enable: 3066 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3067 dsi_if_enable(dsi, false); 3068 dsi_vc_enable(dsi, vc, false); 3069 } 3070 err_video_mode: 3071 dsi_uninit_dispc(dsi); 3072 dev_err(dsi->dev, "failed to enable DSI encoder!\n"); 3073 return; 3074 } 3075 3076 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int vc) 3077 { 3078 struct dsi_data *dsi = to_dsi_data(dssdev); 3079 3080 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) 3081 dsi_disable_video_mode(dsi, vc); 3082 3083 dss_mgr_disable(&dsi->output); 3084 3085 dsi_uninit_dispc(dsi); 3086 } 3087 3088 static void dsi_update_screen_dispc(struct dsi_data *dsi) 3089 { 3090 unsigned int bytespp; 3091 unsigned int bytespl; 3092 unsigned int bytespf; 3093 unsigned int total_len; 3094 unsigned int packet_payload; 3095 unsigned int packet_len; 3096 u32 l; 3097 int r; 3098 const unsigned vc = dsi->update_vc; 3099 const unsigned int line_buf_size = dsi->line_buffer_size; 3100 u16 w = dsi->vm.hactive; 3101 u16 h = dsi->vm.vactive; 3102 3103 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3104 3105 bytespp = mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8; 3106 bytespl = w * bytespp; 3107 bytespf = bytespl * h; 3108 3109 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3110 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3111 3112 if (bytespf < line_buf_size) 3113 packet_payload = bytespf; 3114 else 3115 packet_payload = (line_buf_size) / bytespl * bytespl; 3116 3117 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3118 total_len = (bytespf / packet_payload) * packet_len; 3119 3120 if (bytespf % packet_payload) 3121 total_len += (bytespf % packet_payload) + 1; 3122 3123 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3124 dsi_write_reg(dsi, DSI_VC_TE(vc), l); 3125 3126 dsi_vc_write_long_header(dsi, vc, dsi->dsidev->channel, MIPI_DSI_DCS_LONG_WRITE, 3127 packet_len, 0); 3128 3129 if (dsi->te_enabled) 3130 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3131 else 3132 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3133 dsi_write_reg(dsi, DSI_VC_TE(vc), l); 3134 3135 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3136 * because DSS interrupts are not capable of waking up the CPU and the 3137 * framedone interrupt could be delayed for quite a long time. I think 3138 * the same goes for any DSS interrupts, but for some reason I have not 3139 * seen the problem anywhere else than here. 3140 */ 3141 dispc_disable_sidle(dsi->dss->dispc); 3142 3143 dsi_perf_mark_start(dsi); 3144 3145 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3146 msecs_to_jiffies(250)); 3147 BUG_ON(r == 0); 3148 3149 dss_mgr_start_update(&dsi->output); 3150 3151 if (dsi->te_enabled) { 3152 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3153 * for TE is longer than the timer allows */ 3154 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3155 3156 dsi_vc_send_bta(dsi, vc); 3157 3158 #ifdef DSI_CATCH_MISSING_TE 3159 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3160 #endif 3161 } 3162 } 3163 3164 #ifdef DSI_CATCH_MISSING_TE 3165 static void dsi_te_timeout(struct timer_list *unused) 3166 { 3167 DSSERR("TE not received for 250ms!\n"); 3168 } 3169 #endif 3170 3171 static void dsi_handle_framedone(struct dsi_data *dsi, int error) 3172 { 3173 /* SIDLEMODE back to smart-idle */ 3174 dispc_enable_sidle(dsi->dss->dispc); 3175 3176 if (dsi->te_enabled) { 3177 /* enable LP_RX_TO again after the TE */ 3178 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 3179 } 3180 3181 dsi_bus_unlock(dsi); 3182 3183 if (!error) 3184 dsi_perf_show(dsi, "DISPC"); 3185 } 3186 3187 static void dsi_framedone_timeout_work_callback(struct work_struct *work) 3188 { 3189 struct dsi_data *dsi = container_of(work, struct dsi_data, 3190 framedone_timeout_work.work); 3191 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 3192 * 250ms which would conflict with this timeout work. What should be 3193 * done is first cancel the transfer on the HW, and then cancel the 3194 * possibly scheduled framedone work. However, cancelling the transfer 3195 * on the HW is buggy, and would probably require resetting the whole 3196 * DSI */ 3197 3198 DSSERR("Framedone not received for 250ms!\n"); 3199 3200 dsi_handle_framedone(dsi, -ETIMEDOUT); 3201 } 3202 3203 static void dsi_framedone_irq_callback(void *data) 3204 { 3205 struct dsi_data *dsi = data; 3206 3207 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 3208 * turns itself off. However, DSI still has the pixels in its buffers, 3209 * and is sending the data. 3210 */ 3211 3212 cancel_delayed_work(&dsi->framedone_timeout_work); 3213 3214 DSSDBG("Framedone received!\n"); 3215 3216 dsi_handle_framedone(dsi, 0); 3217 } 3218 3219 static int _dsi_update(struct dsi_data *dsi) 3220 { 3221 dsi_perf_mark_setup(dsi); 3222 3223 #ifdef DSI_PERF_MEASURE 3224 dsi->update_bytes = dsi->vm.hactive * dsi->vm.vactive * 3225 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt) / 8; 3226 #endif 3227 dsi_update_screen_dispc(dsi); 3228 3229 return 0; 3230 } 3231 3232 static int _dsi_send_nop(struct dsi_data *dsi, int vc, int channel) 3233 { 3234 const u8 payload[] = { MIPI_DCS_NOP }; 3235 const struct mipi_dsi_msg msg = { 3236 .channel = channel, 3237 .type = MIPI_DSI_DCS_SHORT_WRITE, 3238 .tx_len = 1, 3239 .tx_buf = payload, 3240 }; 3241 3242 WARN_ON(!dsi_bus_is_locked(dsi)); 3243 3244 return _omap_dsi_host_transfer(dsi, vc, &msg); 3245 } 3246 3247 static int dsi_update_channel(struct omap_dss_device *dssdev, int vc) 3248 { 3249 struct dsi_data *dsi = to_dsi_data(dssdev); 3250 int r; 3251 3252 dsi_bus_lock(dsi); 3253 3254 if (!dsi->video_enabled) { 3255 r = -EIO; 3256 goto err; 3257 } 3258 3259 if (dsi->vm.hactive == 0 || dsi->vm.vactive == 0) { 3260 r = -EINVAL; 3261 goto err; 3262 } 3263 3264 DSSDBG("dsi_update_channel: %d", vc); 3265 3266 /* 3267 * Send NOP between the frames. If we don't send something here, the 3268 * updates stop working. This is probably related to DSI spec stating 3269 * that the DSI host should transition to LP at least once per frame. 3270 */ 3271 r = _dsi_send_nop(dsi, VC_CMD, dsi->dsidev->channel); 3272 if (r < 0) { 3273 DSSWARN("failed to send nop between frames: %d\n", r); 3274 goto err; 3275 } 3276 3277 dsi->update_vc = vc; 3278 3279 if (dsi->te_enabled && dsi->te_gpio) { 3280 schedule_delayed_work(&dsi->te_timeout_work, 3281 msecs_to_jiffies(250)); 3282 atomic_set(&dsi->do_ext_te_update, 1); 3283 } else { 3284 _dsi_update(dsi); 3285 } 3286 3287 return 0; 3288 3289 err: 3290 dsi_bus_unlock(dsi); 3291 return r; 3292 } 3293 3294 static int dsi_update_all(struct omap_dss_device *dssdev) 3295 { 3296 return dsi_update_channel(dssdev, VC_VIDEO); 3297 } 3298 3299 /* Display funcs */ 3300 3301 static int dsi_configure_dispc_clocks(struct dsi_data *dsi) 3302 { 3303 struct dispc_clock_info dispc_cinfo; 3304 int r; 3305 unsigned long fck; 3306 3307 fck = dsi_get_pll_hsdiv_dispc_rate(dsi); 3308 3309 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 3310 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 3311 3312 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); 3313 if (r) { 3314 DSSERR("Failed to calc dispc clocks\n"); 3315 return r; 3316 } 3317 3318 dsi->mgr_config.clock_info = dispc_cinfo; 3319 3320 return 0; 3321 } 3322 3323 static int dsi_init_dispc(struct dsi_data *dsi) 3324 { 3325 enum omap_channel dispc_channel = dsi->output.dispc_channel; 3326 int r; 3327 3328 dss_select_lcd_clk_source(dsi->dss, dispc_channel, dsi->module_id == 0 ? 3329 DSS_CLK_SRC_PLL1_1 : 3330 DSS_CLK_SRC_PLL2_1); 3331 3332 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 3333 r = dss_mgr_register_framedone_handler(&dsi->output, 3334 dsi_framedone_irq_callback, dsi); 3335 if (r) { 3336 DSSERR("can't register FRAMEDONE handler\n"); 3337 goto err; 3338 } 3339 3340 dsi->mgr_config.stallmode = true; 3341 dsi->mgr_config.fifohandcheck = true; 3342 } else { 3343 dsi->mgr_config.stallmode = false; 3344 dsi->mgr_config.fifohandcheck = false; 3345 } 3346 3347 r = dsi_configure_dispc_clocks(dsi); 3348 if (r) 3349 goto err1; 3350 3351 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 3352 dsi->mgr_config.video_port_width = 3353 mipi_dsi_pixel_format_to_bpp(dsi->pix_fmt); 3354 dsi->mgr_config.lcden_sig_polarity = 0; 3355 3356 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config); 3357 3358 return 0; 3359 err1: 3360 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 3361 dss_mgr_unregister_framedone_handler(&dsi->output, 3362 dsi_framedone_irq_callback, dsi); 3363 err: 3364 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); 3365 return r; 3366 } 3367 3368 static void dsi_uninit_dispc(struct dsi_data *dsi) 3369 { 3370 enum omap_channel dispc_channel = dsi->output.dispc_channel; 3371 3372 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 3373 dss_mgr_unregister_framedone_handler(&dsi->output, 3374 dsi_framedone_irq_callback, dsi); 3375 3376 dss_select_lcd_clk_source(dsi->dss, dispc_channel, DSS_CLK_SRC_FCK); 3377 } 3378 3379 static int dsi_configure_dsi_clocks(struct dsi_data *dsi) 3380 { 3381 struct dss_pll_clock_info cinfo; 3382 int r; 3383 3384 cinfo = dsi->user_dsi_cinfo; 3385 3386 r = dss_pll_set_config(&dsi->pll, &cinfo); 3387 if (r) { 3388 DSSERR("Failed to set dsi clocks\n"); 3389 return r; 3390 } 3391 3392 return 0; 3393 } 3394 3395 static void dsi_setup_dsi_vcs(struct dsi_data *dsi) 3396 { 3397 /* Setup VC_CMD for LP and cpu transfers */ 3398 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 9, 9); /* LP */ 3399 3400 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 1, 1); /* SOURCE_L4 */ 3401 dsi->vc[VC_CMD].source = DSI_VC_SOURCE_L4; 3402 3403 /* Setup VC_VIDEO for HS and dispc transfers */ 3404 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 9, 9); /* HS */ 3405 3406 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 1, 1); /* SOURCE_VP */ 3407 dsi->vc[VC_VIDEO].source = DSI_VC_SOURCE_VP; 3408 3409 if ((dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) && 3410 !(dsi->dsidev->mode_flags & MIPI_DSI_MODE_VIDEO)) 3411 REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 30, 30); /* DCS_CMD_ENABLE */ 3412 3413 dsi_vc_enable(dsi, VC_CMD, 1); 3414 dsi_vc_enable(dsi, VC_VIDEO, 1); 3415 3416 dsi_if_enable(dsi, 1); 3417 3418 dsi_force_tx_stop_mode_io(dsi); 3419 3420 /* start the DDR clock by sending a NULL packet */ 3421 if (!(dsi->dsidev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 3422 dsi_vc_send_null(dsi, VC_CMD, dsi->dsidev->channel); 3423 } 3424 3425 static int dsi_init_dsi(struct dsi_data *dsi) 3426 { 3427 int r; 3428 3429 r = dss_pll_enable(&dsi->pll); 3430 if (r) 3431 return r; 3432 3433 r = dsi_configure_dsi_clocks(dsi); 3434 if (r) 3435 goto err0; 3436 3437 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, 3438 dsi->module_id == 0 ? 3439 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2); 3440 3441 DSSDBG("PLL OK\n"); 3442 3443 if (!dsi->vdds_dsi_enabled) { 3444 r = regulator_enable(dsi->vdds_dsi_reg); 3445 if (r) 3446 goto err1; 3447 3448 dsi->vdds_dsi_enabled = true; 3449 } 3450 3451 r = dsi_cio_init(dsi); 3452 if (r) 3453 goto err2; 3454 3455 _dsi_print_reset_status(dsi); 3456 3457 dsi_proto_timings(dsi); 3458 dsi_set_lp_clk_divisor(dsi); 3459 3460 if (1) 3461 _dsi_print_reset_status(dsi); 3462 3463 r = dsi_proto_config(dsi); 3464 if (r) 3465 goto err3; 3466 3467 dsi_setup_dsi_vcs(dsi); 3468 3469 return 0; 3470 err3: 3471 dsi_cio_uninit(dsi); 3472 err2: 3473 regulator_disable(dsi->vdds_dsi_reg); 3474 dsi->vdds_dsi_enabled = false; 3475 err1: 3476 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 3477 err0: 3478 dss_pll_disable(&dsi->pll); 3479 3480 return r; 3481 } 3482 3483 static void dsi_uninit_dsi(struct dsi_data *dsi) 3484 { 3485 /* disable interface */ 3486 dsi_if_enable(dsi, 0); 3487 dsi_vc_enable(dsi, 0, 0); 3488 dsi_vc_enable(dsi, 1, 0); 3489 dsi_vc_enable(dsi, 2, 0); 3490 dsi_vc_enable(dsi, 3, 0); 3491 3492 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 3493 dsi_cio_uninit(dsi); 3494 dss_pll_disable(&dsi->pll); 3495 3496 regulator_disable(dsi->vdds_dsi_reg); 3497 dsi->vdds_dsi_enabled = false; 3498 } 3499 3500 static void dsi_enable(struct dsi_data *dsi) 3501 { 3502 int r; 3503 3504 WARN_ON(!dsi_bus_is_locked(dsi)); 3505 3506 if (WARN_ON(dsi->iface_enabled)) 3507 return; 3508 3509 mutex_lock(&dsi->lock); 3510 3511 r = dsi_runtime_get(dsi); 3512 if (r) 3513 goto err_get_dsi; 3514 3515 _dsi_initialize_irq(dsi); 3516 3517 r = dsi_init_dsi(dsi); 3518 if (r) 3519 goto err_init_dsi; 3520 3521 dsi->iface_enabled = true; 3522 3523 mutex_unlock(&dsi->lock); 3524 3525 return; 3526 3527 err_init_dsi: 3528 dsi_runtime_put(dsi); 3529 err_get_dsi: 3530 mutex_unlock(&dsi->lock); 3531 DSSDBG("dsi_enable FAILED\n"); 3532 } 3533 3534 static void dsi_disable(struct dsi_data *dsi) 3535 { 3536 WARN_ON(!dsi_bus_is_locked(dsi)); 3537 3538 if (WARN_ON(!dsi->iface_enabled)) 3539 return; 3540 3541 mutex_lock(&dsi->lock); 3542 3543 dsi_sync_vc(dsi, 0); 3544 dsi_sync_vc(dsi, 1); 3545 dsi_sync_vc(dsi, 2); 3546 dsi_sync_vc(dsi, 3); 3547 3548 dsi_uninit_dsi(dsi); 3549 3550 dsi_runtime_put(dsi); 3551 3552 dsi->iface_enabled = false; 3553 3554 mutex_unlock(&dsi->lock); 3555 } 3556 3557 static int dsi_enable_te(struct dsi_data *dsi, bool enable) 3558 { 3559 dsi->te_enabled = enable; 3560 3561 if (dsi->te_gpio) { 3562 if (enable) 3563 enable_irq(dsi->te_irq); 3564 else 3565 disable_irq(dsi->te_irq); 3566 } 3567 3568 return 0; 3569 } 3570 3571 #ifdef PRINT_VERBOSE_VM_TIMINGS 3572 static void print_dsi_vm(const char *str, 3573 const struct omap_dss_dsi_videomode_timings *t) 3574 { 3575 unsigned long byteclk = t->hsclk / 4; 3576 int bl, wc, pps, tot; 3577 3578 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 3579 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 3580 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 3581 tot = bl + pps; 3582 3583 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 3584 3585 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 3586 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 3587 str, 3588 byteclk, 3589 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 3590 bl, pps, tot, 3591 TO_DSI_T(t->hss), 3592 TO_DSI_T(t->hsa), 3593 TO_DSI_T(t->hse), 3594 TO_DSI_T(t->hbp), 3595 TO_DSI_T(pps), 3596 TO_DSI_T(t->hfp), 3597 3598 TO_DSI_T(bl), 3599 TO_DSI_T(pps), 3600 3601 TO_DSI_T(tot)); 3602 #undef TO_DSI_T 3603 } 3604 3605 static void print_dispc_vm(const char *str, const struct videomode *vm) 3606 { 3607 unsigned long pck = vm->pixelclock; 3608 int hact, bl, tot; 3609 3610 hact = vm->hactive; 3611 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; 3612 tot = hact + bl; 3613 3614 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 3615 3616 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 3617 "%u/%u/%u/%u = %u + %u = %u\n", 3618 str, 3619 pck, 3620 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, 3621 bl, hact, tot, 3622 TO_DISPC_T(vm->hsync_len), 3623 TO_DISPC_T(vm->hback_porch), 3624 TO_DISPC_T(hact), 3625 TO_DISPC_T(vm->hfront_porch), 3626 TO_DISPC_T(bl), 3627 TO_DISPC_T(hact), 3628 TO_DISPC_T(tot)); 3629 #undef TO_DISPC_T 3630 } 3631 3632 /* note: this is not quite accurate */ 3633 static void print_dsi_dispc_vm(const char *str, 3634 const struct omap_dss_dsi_videomode_timings *t) 3635 { 3636 struct videomode vm = { 0 }; 3637 unsigned long byteclk = t->hsclk / 4; 3638 unsigned long pck; 3639 u64 dsi_tput; 3640 int dsi_hact, dsi_htot; 3641 3642 dsi_tput = (u64)byteclk * t->ndl * 8; 3643 pck = (u32)div64_u64(dsi_tput, t->bitspp); 3644 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 3645 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 3646 3647 vm.pixelclock = pck; 3648 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 3649 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); 3650 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); 3651 vm.hactive = t->hact; 3652 3653 print_dispc_vm(str, &vm); 3654 } 3655 #endif /* PRINT_VERBOSE_VM_TIMINGS */ 3656 3657 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 3658 unsigned long pck, void *data) 3659 { 3660 struct dsi_clk_calc_ctx *ctx = data; 3661 struct videomode *vm = &ctx->vm; 3662 3663 ctx->dispc_cinfo.lck_div = lckd; 3664 ctx->dispc_cinfo.pck_div = pckd; 3665 ctx->dispc_cinfo.lck = lck; 3666 ctx->dispc_cinfo.pck = pck; 3667 3668 *vm = *ctx->config->vm; 3669 vm->pixelclock = pck; 3670 vm->hactive = ctx->config->vm->hactive; 3671 vm->vactive = ctx->config->vm->vactive; 3672 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; 3673 vm->vfront_porch = vm->vback_porch = 0; 3674 3675 return true; 3676 } 3677 3678 static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 3679 void *data) 3680 { 3681 struct dsi_clk_calc_ctx *ctx = data; 3682 3683 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 3684 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 3685 3686 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 3687 ctx->req_pck_min, ctx->req_pck_max, 3688 dsi_cm_calc_dispc_cb, ctx); 3689 } 3690 3691 static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 3692 unsigned long clkdco, void *data) 3693 { 3694 struct dsi_clk_calc_ctx *ctx = data; 3695 struct dsi_data *dsi = ctx->dsi; 3696 3697 ctx->dsi_cinfo.n = n; 3698 ctx->dsi_cinfo.m = m; 3699 ctx->dsi_cinfo.fint = fint; 3700 ctx->dsi_cinfo.clkdco = clkdco; 3701 3702 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 3703 dsi->data->max_fck_freq, 3704 dsi_cm_calc_hsdiv_cb, ctx); 3705 } 3706 3707 static bool dsi_cm_calc(struct dsi_data *dsi, 3708 const struct omap_dss_dsi_config *cfg, 3709 struct dsi_clk_calc_ctx *ctx) 3710 { 3711 unsigned long clkin; 3712 int bitspp, ndl; 3713 unsigned long pll_min, pll_max; 3714 unsigned long pck, txbyteclk; 3715 3716 clkin = clk_get_rate(dsi->pll.clkin); 3717 bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); 3718 ndl = dsi->num_lanes_used - 1; 3719 3720 /* 3721 * Here we should calculate minimum txbyteclk to be able to send the 3722 * frame in time, and also to handle TE. That's not very simple, though, 3723 * especially as we go to LP between each pixel packet due to HW 3724 * "feature". So let's just estimate very roughly and multiply by 1.5. 3725 */ 3726 pck = cfg->vm->pixelclock; 3727 pck = pck * 3 / 2; 3728 txbyteclk = pck * bitspp / 8 / ndl; 3729 3730 memset(ctx, 0, sizeof(*ctx)); 3731 ctx->dsi = dsi; 3732 ctx->pll = &dsi->pll; 3733 ctx->config = cfg; 3734 ctx->req_pck_min = pck; 3735 ctx->req_pck_nom = pck; 3736 ctx->req_pck_max = pck * 3 / 2; 3737 3738 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 3739 pll_max = cfg->hs_clk_max * 4; 3740 3741 return dss_pll_calc_a(ctx->pll, clkin, 3742 pll_min, pll_max, 3743 dsi_cm_calc_pll_cb, ctx); 3744 } 3745 3746 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 3747 { 3748 struct dsi_data *dsi = ctx->dsi; 3749 const struct omap_dss_dsi_config *cfg = ctx->config; 3750 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); 3751 int ndl = dsi->num_lanes_used - 1; 3752 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 3753 unsigned long byteclk = hsclk / 4; 3754 3755 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 3756 int xres; 3757 int panel_htot, panel_hbl; /* pixels */ 3758 int dispc_htot, dispc_hbl; /* pixels */ 3759 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 3760 int hfp, hsa, hbp; 3761 const struct videomode *req_vm; 3762 struct videomode *dispc_vm; 3763 struct omap_dss_dsi_videomode_timings *dsi_vm; 3764 u64 dsi_tput, dispc_tput; 3765 3766 dsi_tput = (u64)byteclk * ndl * 8; 3767 3768 req_vm = cfg->vm; 3769 req_pck_min = ctx->req_pck_min; 3770 req_pck_max = ctx->req_pck_max; 3771 req_pck_nom = ctx->req_pck_nom; 3772 3773 dispc_pck = ctx->dispc_cinfo.pck; 3774 dispc_tput = (u64)dispc_pck * bitspp; 3775 3776 xres = req_vm->hactive; 3777 3778 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + 3779 req_vm->hsync_len; 3780 panel_htot = xres + panel_hbl; 3781 3782 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 3783 3784 /* 3785 * When there are no line buffers, DISPC and DSI must have the 3786 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 3787 */ 3788 if (dsi->line_buffer_size < xres * bitspp / 8) { 3789 if (dispc_tput != dsi_tput) 3790 return false; 3791 } else { 3792 if (dispc_tput < dsi_tput) 3793 return false; 3794 } 3795 3796 /* DSI tput must be over the min requirement */ 3797 if (dsi_tput < (u64)bitspp * req_pck_min) 3798 return false; 3799 3800 /* When non-burst mode, DSI tput must be below max requirement. */ 3801 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 3802 if (dsi_tput > (u64)bitspp * req_pck_max) 3803 return false; 3804 } 3805 3806 hss = DIV_ROUND_UP(4, ndl); 3807 3808 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 3809 if (ndl == 3 && req_vm->hsync_len == 0) 3810 hse = 1; 3811 else 3812 hse = DIV_ROUND_UP(4, ndl); 3813 } else { 3814 hse = 0; 3815 } 3816 3817 /* DSI htot to match the panel's nominal pck */ 3818 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 3819 3820 /* fail if there would be no time for blanking */ 3821 if (dsi_htot < hss + hse + dsi_hact) 3822 return false; 3823 3824 /* total DSI blanking needed to achieve panel's TL */ 3825 dsi_hbl = dsi_htot - dsi_hact; 3826 3827 /* DISPC htot to match the DSI TL */ 3828 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 3829 3830 /* verify that the DSI and DISPC TLs are the same */ 3831 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 3832 return false; 3833 3834 dispc_hbl = dispc_htot - xres; 3835 3836 /* setup DSI videomode */ 3837 3838 dsi_vm = &ctx->dsi_vm; 3839 memset(dsi_vm, 0, sizeof(*dsi_vm)); 3840 3841 dsi_vm->hsclk = hsclk; 3842 3843 dsi_vm->ndl = ndl; 3844 dsi_vm->bitspp = bitspp; 3845 3846 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 3847 hsa = 0; 3848 } else if (ndl == 3 && req_vm->hsync_len == 0) { 3849 hsa = 0; 3850 } else { 3851 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); 3852 hsa = max(hsa - hse, 1); 3853 } 3854 3855 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); 3856 hbp = max(hbp, 1); 3857 3858 hfp = dsi_hbl - (hss + hsa + hse + hbp); 3859 if (hfp < 1) { 3860 int t; 3861 /* we need to take cycles from hbp */ 3862 3863 t = 1 - hfp; 3864 hbp = max(hbp - t, 1); 3865 hfp = dsi_hbl - (hss + hsa + hse + hbp); 3866 3867 if (hfp < 1 && hsa > 0) { 3868 /* we need to take cycles from hsa */ 3869 t = 1 - hfp; 3870 hsa = max(hsa - t, 1); 3871 hfp = dsi_hbl - (hss + hsa + hse + hbp); 3872 } 3873 } 3874 3875 if (hfp < 1) 3876 return false; 3877 3878 dsi_vm->hss = hss; 3879 dsi_vm->hsa = hsa; 3880 dsi_vm->hse = hse; 3881 dsi_vm->hbp = hbp; 3882 dsi_vm->hact = xres; 3883 dsi_vm->hfp = hfp; 3884 3885 dsi_vm->vsa = req_vm->vsync_len; 3886 dsi_vm->vbp = req_vm->vback_porch; 3887 dsi_vm->vact = req_vm->vactive; 3888 dsi_vm->vfp = req_vm->vfront_porch; 3889 3890 dsi_vm->trans_mode = cfg->trans_mode; 3891 3892 dsi_vm->blanking_mode = 0; 3893 dsi_vm->hsa_blanking_mode = 1; 3894 dsi_vm->hfp_blanking_mode = 1; 3895 dsi_vm->hbp_blanking_mode = 1; 3896 3897 dsi_vm->window_sync = 4; 3898 3899 /* setup DISPC videomode */ 3900 3901 dispc_vm = &ctx->vm; 3902 *dispc_vm = *req_vm; 3903 dispc_vm->pixelclock = dispc_pck; 3904 3905 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 3906 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, 3907 req_pck_nom); 3908 hsa = max(hsa, 1); 3909 } else { 3910 hsa = 1; 3911 } 3912 3913 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); 3914 hbp = max(hbp, 1); 3915 3916 hfp = dispc_hbl - hsa - hbp; 3917 if (hfp < 1) { 3918 int t; 3919 /* we need to take cycles from hbp */ 3920 3921 t = 1 - hfp; 3922 hbp = max(hbp - t, 1); 3923 hfp = dispc_hbl - hsa - hbp; 3924 3925 if (hfp < 1) { 3926 /* we need to take cycles from hsa */ 3927 t = 1 - hfp; 3928 hsa = max(hsa - t, 1); 3929 hfp = dispc_hbl - hsa - hbp; 3930 } 3931 } 3932 3933 if (hfp < 1) 3934 return false; 3935 3936 dispc_vm->hfront_porch = hfp; 3937 dispc_vm->hsync_len = hsa; 3938 dispc_vm->hback_porch = hbp; 3939 3940 return true; 3941 } 3942 3943 3944 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 3945 unsigned long pck, void *data) 3946 { 3947 struct dsi_clk_calc_ctx *ctx = data; 3948 3949 ctx->dispc_cinfo.lck_div = lckd; 3950 ctx->dispc_cinfo.pck_div = pckd; 3951 ctx->dispc_cinfo.lck = lck; 3952 ctx->dispc_cinfo.pck = pck; 3953 3954 if (dsi_vm_calc_blanking(ctx) == false) 3955 return false; 3956 3957 #ifdef PRINT_VERBOSE_VM_TIMINGS 3958 print_dispc_vm("dispc", &ctx->vm); 3959 print_dsi_vm("dsi ", &ctx->dsi_vm); 3960 print_dispc_vm("req ", ctx->config->vm); 3961 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 3962 #endif 3963 3964 return true; 3965 } 3966 3967 static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 3968 void *data) 3969 { 3970 struct dsi_clk_calc_ctx *ctx = data; 3971 unsigned long pck_max; 3972 3973 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 3974 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 3975 3976 /* 3977 * In burst mode we can let the dispc pck be arbitrarily high, but it 3978 * limits our scaling abilities. So for now, don't aim too high. 3979 */ 3980 3981 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 3982 pck_max = ctx->req_pck_max + 10000000; 3983 else 3984 pck_max = ctx->req_pck_max; 3985 3986 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 3987 ctx->req_pck_min, pck_max, 3988 dsi_vm_calc_dispc_cb, ctx); 3989 } 3990 3991 static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 3992 unsigned long clkdco, void *data) 3993 { 3994 struct dsi_clk_calc_ctx *ctx = data; 3995 struct dsi_data *dsi = ctx->dsi; 3996 3997 ctx->dsi_cinfo.n = n; 3998 ctx->dsi_cinfo.m = m; 3999 ctx->dsi_cinfo.fint = fint; 4000 ctx->dsi_cinfo.clkdco = clkdco; 4001 4002 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4003 dsi->data->max_fck_freq, 4004 dsi_vm_calc_hsdiv_cb, ctx); 4005 } 4006 4007 static bool dsi_vm_calc(struct dsi_data *dsi, 4008 const struct omap_dss_dsi_config *cfg, 4009 struct dsi_clk_calc_ctx *ctx) 4010 { 4011 const struct videomode *vm = cfg->vm; 4012 unsigned long clkin; 4013 unsigned long pll_min; 4014 unsigned long pll_max; 4015 int ndl = dsi->num_lanes_used - 1; 4016 int bitspp = mipi_dsi_pixel_format_to_bpp(cfg->pixel_format); 4017 unsigned long byteclk_min; 4018 4019 clkin = clk_get_rate(dsi->pll.clkin); 4020 4021 memset(ctx, 0, sizeof(*ctx)); 4022 ctx->dsi = dsi; 4023 ctx->pll = &dsi->pll; 4024 ctx->config = cfg; 4025 4026 /* these limits should come from the panel driver */ 4027 ctx->req_pck_min = vm->pixelclock - 1000; 4028 ctx->req_pck_nom = vm->pixelclock; 4029 ctx->req_pck_max = vm->pixelclock + 1000; 4030 4031 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4032 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4033 4034 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4035 pll_max = cfg->hs_clk_max * 4; 4036 } else { 4037 unsigned long byteclk_max; 4038 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4039 ndl * 8); 4040 4041 pll_max = byteclk_max * 4 * 4; 4042 } 4043 4044 return dss_pll_calc_a(ctx->pll, clkin, 4045 pll_min, pll_max, 4046 dsi_vm_calc_pll_cb, ctx); 4047 } 4048 4049 static bool dsi_is_video_mode(struct omap_dss_device *dssdev) 4050 { 4051 struct dsi_data *dsi = to_dsi_data(dssdev); 4052 4053 return dsi->mode == OMAP_DSS_DSI_VIDEO_MODE; 4054 } 4055 4056 static int __dsi_calc_config(struct dsi_data *dsi, 4057 const struct drm_display_mode *mode, 4058 struct dsi_clk_calc_ctx *ctx) 4059 { 4060 struct omap_dss_dsi_config cfg = dsi->config; 4061 struct videomode vm; 4062 bool ok; 4063 int r; 4064 4065 drm_display_mode_to_videomode(mode, &vm); 4066 4067 cfg.vm = &vm; 4068 cfg.mode = dsi->mode; 4069 cfg.pixel_format = dsi->pix_fmt; 4070 4071 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) 4072 ok = dsi_vm_calc(dsi, &cfg, ctx); 4073 else 4074 ok = dsi_cm_calc(dsi, &cfg, ctx); 4075 4076 if (!ok) 4077 return -EINVAL; 4078 4079 dsi_pll_calc_dsi_fck(dsi, &ctx->dsi_cinfo); 4080 4081 r = dsi_lp_clock_calc(ctx->dsi_cinfo.clkout[HSDIV_DSI], 4082 cfg.lp_clk_min, cfg.lp_clk_max, &ctx->lp_cinfo); 4083 if (r) 4084 return r; 4085 4086 return 0; 4087 } 4088 4089 static int dsi_set_config(struct omap_dss_device *dssdev, 4090 const struct drm_display_mode *mode) 4091 { 4092 struct dsi_data *dsi = to_dsi_data(dssdev); 4093 struct dsi_clk_calc_ctx ctx; 4094 int r; 4095 4096 mutex_lock(&dsi->lock); 4097 4098 r = __dsi_calc_config(dsi, mode, &ctx); 4099 if (r) { 4100 DSSERR("failed to find suitable DSI clock settings\n"); 4101 goto err; 4102 } 4103 4104 dsi->user_lp_cinfo = ctx.lp_cinfo; 4105 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4106 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4107 4108 dsi->vm = ctx.vm; 4109 4110 /* 4111 * override interlace, logic level and edge related parameters in 4112 * videomode with default values 4113 */ 4114 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; 4115 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 4116 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 4117 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 4118 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 4119 /* 4120 * HACK: These flags should be handled through the omap_dss_device bus 4121 * flags, but this will only be possible when the DSI encoder will be 4122 * converted to the omapdrm-managed encoder model. 4123 */ 4124 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 4125 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 4126 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW; 4127 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH; 4128 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4129 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4130 4131 dss_mgr_set_timings(&dsi->output, &dsi->vm); 4132 4133 dsi->vm_timings = ctx.dsi_vm; 4134 4135 mutex_unlock(&dsi->lock); 4136 4137 return 0; 4138 err: 4139 mutex_unlock(&dsi->lock); 4140 4141 return r; 4142 } 4143 4144 /* 4145 * Return a hardcoded dispc channel for the DSI output. This should work for 4146 * current use cases, but this can be later expanded to either resolve 4147 * the channel in some more dynamic manner, or get the channel as a user 4148 * parameter. 4149 */ 4150 static enum omap_channel dsi_get_dispc_channel(struct dsi_data *dsi) 4151 { 4152 switch (dsi->data->model) { 4153 case DSI_MODEL_OMAP3: 4154 return OMAP_DSS_CHANNEL_LCD; 4155 4156 case DSI_MODEL_OMAP4: 4157 switch (dsi->module_id) { 4158 case 0: 4159 return OMAP_DSS_CHANNEL_LCD; 4160 case 1: 4161 return OMAP_DSS_CHANNEL_LCD2; 4162 default: 4163 DSSWARN("unsupported module id\n"); 4164 return OMAP_DSS_CHANNEL_LCD; 4165 } 4166 4167 case DSI_MODEL_OMAP5: 4168 switch (dsi->module_id) { 4169 case 0: 4170 return OMAP_DSS_CHANNEL_LCD; 4171 case 1: 4172 return OMAP_DSS_CHANNEL_LCD3; 4173 default: 4174 DSSWARN("unsupported module id\n"); 4175 return OMAP_DSS_CHANNEL_LCD; 4176 } 4177 4178 default: 4179 DSSWARN("unsupported DSS version\n"); 4180 return OMAP_DSS_CHANNEL_LCD; 4181 } 4182 } 4183 4184 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc, 4185 const struct mipi_dsi_msg *msg) 4186 { 4187 struct omap_dss_device *dssdev = &dsi->output; 4188 int r; 4189 4190 dsi_vc_enable_hs(dssdev, vc, !(msg->flags & MIPI_DSI_MSG_USE_LPM)); 4191 4192 switch (msg->type) { 4193 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 4194 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 4195 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 4196 case MIPI_DSI_GENERIC_LONG_WRITE: 4197 case MIPI_DSI_DCS_SHORT_WRITE: 4198 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 4199 case MIPI_DSI_DCS_LONG_WRITE: 4200 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: 4201 case MIPI_DSI_NULL_PACKET: 4202 r = dsi_vc_write_common(dssdev, vc, msg); 4203 break; 4204 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 4205 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 4206 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 4207 r = dsi_vc_generic_read(dssdev, vc, msg); 4208 break; 4209 case MIPI_DSI_DCS_READ: 4210 r = dsi_vc_dcs_read(dssdev, vc, msg); 4211 break; 4212 default: 4213 r = -EINVAL; 4214 break; 4215 } 4216 4217 if (r < 0) 4218 return r; 4219 4220 if (msg->type == MIPI_DSI_DCS_SHORT_WRITE || 4221 msg->type == MIPI_DSI_DCS_SHORT_WRITE_PARAM) { 4222 u8 cmd = ((u8 *)msg->tx_buf)[0]; 4223 4224 if (cmd == MIPI_DCS_SET_TEAR_OFF) 4225 dsi_enable_te(dsi, false); 4226 else if (cmd == MIPI_DCS_SET_TEAR_ON) 4227 dsi_enable_te(dsi, true); 4228 } 4229 4230 return 0; 4231 } 4232 4233 static ssize_t omap_dsi_host_transfer(struct mipi_dsi_host *host, 4234 const struct mipi_dsi_msg *msg) 4235 { 4236 struct dsi_data *dsi = host_to_omap(host); 4237 int r; 4238 int vc = VC_CMD; 4239 4240 dsi_bus_lock(dsi); 4241 4242 if (!dsi->iface_enabled) { 4243 dsi_enable(dsi); 4244 schedule_delayed_work(&dsi->dsi_disable_work, msecs_to_jiffies(2000)); 4245 } 4246 4247 r = _omap_dsi_host_transfer(dsi, vc, msg); 4248 4249 dsi_bus_unlock(dsi); 4250 4251 return r; 4252 } 4253 4254 static int dsi_get_clocks(struct dsi_data *dsi) 4255 { 4256 struct clk *clk; 4257 4258 clk = devm_clk_get(dsi->dev, "fck"); 4259 if (IS_ERR(clk)) { 4260 DSSERR("can't get fck\n"); 4261 return PTR_ERR(clk); 4262 } 4263 4264 dsi->dss_clk = clk; 4265 4266 return 0; 4267 } 4268 4269 static const struct omapdss_dsi_ops dsi_ops = { 4270 .update = dsi_update_all, 4271 .is_video_mode = dsi_is_video_mode, 4272 }; 4273 4274 static irqreturn_t omap_dsi_te_irq_handler(int irq, void *dev_id) 4275 { 4276 struct dsi_data *dsi = (struct dsi_data *)dev_id; 4277 int old; 4278 4279 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0); 4280 if (old) { 4281 cancel_delayed_work(&dsi->te_timeout_work); 4282 _dsi_update(dsi); 4283 } 4284 4285 return IRQ_HANDLED; 4286 } 4287 4288 static void omap_dsi_te_timeout_work_callback(struct work_struct *work) 4289 { 4290 struct dsi_data *dsi = 4291 container_of(work, struct dsi_data, te_timeout_work.work); 4292 int old; 4293 4294 old = atomic_cmpxchg(&dsi->do_ext_te_update, 1, 0); 4295 if (old) { 4296 dev_err(dsi->dev, "TE not received for 250ms!\n"); 4297 _dsi_update(dsi); 4298 } 4299 } 4300 4301 static int omap_dsi_register_te_irq(struct dsi_data *dsi, 4302 struct mipi_dsi_device *client) 4303 { 4304 int err; 4305 int te_irq; 4306 4307 dsi->te_gpio = gpiod_get(&client->dev, "te-gpios", GPIOD_IN); 4308 if (IS_ERR(dsi->te_gpio)) { 4309 err = PTR_ERR(dsi->te_gpio); 4310 4311 if (err == -ENOENT) { 4312 dsi->te_gpio = NULL; 4313 return 0; 4314 } 4315 4316 dev_err(dsi->dev, "Could not get TE gpio: %d\n", err); 4317 return err; 4318 } 4319 4320 te_irq = gpiod_to_irq(dsi->te_gpio); 4321 if (te_irq < 0) { 4322 gpiod_put(dsi->te_gpio); 4323 dsi->te_gpio = NULL; 4324 return -EINVAL; 4325 } 4326 4327 dsi->te_irq = te_irq; 4328 4329 irq_set_status_flags(te_irq, IRQ_NOAUTOEN); 4330 4331 err = request_threaded_irq(te_irq, NULL, omap_dsi_te_irq_handler, 4332 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 4333 "TE", dsi); 4334 if (err) { 4335 dev_err(dsi->dev, "request irq failed with %d\n", err); 4336 gpiod_put(dsi->te_gpio); 4337 dsi->te_gpio = NULL; 4338 return err; 4339 } 4340 4341 INIT_DEFERRABLE_WORK(&dsi->te_timeout_work, 4342 omap_dsi_te_timeout_work_callback); 4343 4344 dev_dbg(dsi->dev, "Using GPIO TE\n"); 4345 4346 return 0; 4347 } 4348 4349 static void omap_dsi_unregister_te_irq(struct dsi_data *dsi) 4350 { 4351 if (dsi->te_gpio) { 4352 free_irq(dsi->te_irq, dsi); 4353 cancel_delayed_work(&dsi->te_timeout_work); 4354 gpiod_put(dsi->te_gpio); 4355 dsi->te_gpio = NULL; 4356 } 4357 } 4358 4359 static int omap_dsi_host_attach(struct mipi_dsi_host *host, 4360 struct mipi_dsi_device *client) 4361 { 4362 struct dsi_data *dsi = host_to_omap(host); 4363 int r; 4364 4365 if (dsi->dsidev) { 4366 DSSERR("dsi client already attached\n"); 4367 return -EBUSY; 4368 } 4369 4370 if (mipi_dsi_pixel_format_to_bpp(client->format) < 0) { 4371 DSSERR("invalid pixel format\n"); 4372 return -EINVAL; 4373 } 4374 4375 atomic_set(&dsi->do_ext_te_update, 0); 4376 4377 if (client->mode_flags & MIPI_DSI_MODE_VIDEO) { 4378 dsi->mode = OMAP_DSS_DSI_VIDEO_MODE; 4379 } else { 4380 r = omap_dsi_register_te_irq(dsi, client); 4381 if (r) 4382 return r; 4383 4384 dsi->mode = OMAP_DSS_DSI_CMD_MODE; 4385 } 4386 4387 dsi->dsidev = client; 4388 dsi->pix_fmt = client->format; 4389 4390 dsi->config.hs_clk_min = 150000000; // TODO: get from client? 4391 dsi->config.hs_clk_max = client->hs_rate; 4392 dsi->config.lp_clk_min = 7000000; // TODO: get from client? 4393 dsi->config.lp_clk_max = client->lp_rate; 4394 4395 if (client->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 4396 dsi->config.trans_mode = OMAP_DSS_DSI_BURST_MODE; 4397 else if (client->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 4398 dsi->config.trans_mode = OMAP_DSS_DSI_PULSE_MODE; 4399 else 4400 dsi->config.trans_mode = OMAP_DSS_DSI_EVENT_MODE; 4401 4402 return 0; 4403 } 4404 4405 static int omap_dsi_host_detach(struct mipi_dsi_host *host, 4406 struct mipi_dsi_device *client) 4407 { 4408 struct dsi_data *dsi = host_to_omap(host); 4409 4410 if (WARN_ON(dsi->dsidev != client)) 4411 return -EINVAL; 4412 4413 cancel_delayed_work_sync(&dsi->dsi_disable_work); 4414 4415 dsi_bus_lock(dsi); 4416 4417 if (dsi->iface_enabled) 4418 dsi_disable(dsi); 4419 4420 dsi_bus_unlock(dsi); 4421 4422 omap_dsi_unregister_te_irq(dsi); 4423 dsi->dsidev = NULL; 4424 return 0; 4425 } 4426 4427 static const struct mipi_dsi_host_ops omap_dsi_host_ops = { 4428 .attach = omap_dsi_host_attach, 4429 .detach = omap_dsi_host_detach, 4430 .transfer = omap_dsi_host_transfer, 4431 }; 4432 4433 /* ----------------------------------------------------------------------------- 4434 * PLL 4435 */ 4436 4437 static const struct dss_pll_ops dsi_pll_ops = { 4438 .enable = dsi_pll_enable, 4439 .disable = dsi_pll_disable, 4440 .set_config = dss_pll_write_config_type_a, 4441 }; 4442 4443 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 4444 .type = DSS_PLL_TYPE_A, 4445 4446 .n_max = (1 << 7) - 1, 4447 .m_max = (1 << 11) - 1, 4448 .mX_max = (1 << 4) - 1, 4449 .fint_min = 750000, 4450 .fint_max = 2100000, 4451 .clkdco_low = 1000000000, 4452 .clkdco_max = 1800000000, 4453 4454 .n_msb = 7, 4455 .n_lsb = 1, 4456 .m_msb = 18, 4457 .m_lsb = 8, 4458 4459 .mX_msb[0] = 22, 4460 .mX_lsb[0] = 19, 4461 .mX_msb[1] = 26, 4462 .mX_lsb[1] = 23, 4463 4464 .has_stopmode = true, 4465 .has_freqsel = true, 4466 .has_selfreqdco = false, 4467 .has_refsel = false, 4468 }; 4469 4470 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 4471 .type = DSS_PLL_TYPE_A, 4472 4473 .n_max = (1 << 8) - 1, 4474 .m_max = (1 << 12) - 1, 4475 .mX_max = (1 << 5) - 1, 4476 .fint_min = 500000, 4477 .fint_max = 2500000, 4478 .clkdco_low = 1000000000, 4479 .clkdco_max = 1800000000, 4480 4481 .n_msb = 8, 4482 .n_lsb = 1, 4483 .m_msb = 20, 4484 .m_lsb = 9, 4485 4486 .mX_msb[0] = 25, 4487 .mX_lsb[0] = 21, 4488 .mX_msb[1] = 30, 4489 .mX_lsb[1] = 26, 4490 4491 .has_stopmode = true, 4492 .has_freqsel = false, 4493 .has_selfreqdco = false, 4494 .has_refsel = false, 4495 }; 4496 4497 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 4498 .type = DSS_PLL_TYPE_A, 4499 4500 .n_max = (1 << 8) - 1, 4501 .m_max = (1 << 12) - 1, 4502 .mX_max = (1 << 5) - 1, 4503 .fint_min = 150000, 4504 .fint_max = 52000000, 4505 .clkdco_low = 1000000000, 4506 .clkdco_max = 1800000000, 4507 4508 .n_msb = 8, 4509 .n_lsb = 1, 4510 .m_msb = 20, 4511 .m_lsb = 9, 4512 4513 .mX_msb[0] = 25, 4514 .mX_lsb[0] = 21, 4515 .mX_msb[1] = 30, 4516 .mX_lsb[1] = 26, 4517 4518 .has_stopmode = true, 4519 .has_freqsel = false, 4520 .has_selfreqdco = true, 4521 .has_refsel = true, 4522 }; 4523 4524 static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi) 4525 { 4526 struct dss_pll *pll = &dsi->pll; 4527 struct clk *clk; 4528 int r; 4529 4530 clk = devm_clk_get(dsi->dev, "sys_clk"); 4531 if (IS_ERR(clk)) { 4532 DSSERR("can't get sys_clk\n"); 4533 return PTR_ERR(clk); 4534 } 4535 4536 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 4537 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 4538 pll->clkin = clk; 4539 pll->base = dsi->pll_base; 4540 pll->hw = dsi->data->pll_hw; 4541 pll->ops = &dsi_pll_ops; 4542 4543 r = dss_pll_register(dss, pll); 4544 if (r) 4545 return r; 4546 4547 return 0; 4548 } 4549 4550 /* ----------------------------------------------------------------------------- 4551 * Component Bind & Unbind 4552 */ 4553 4554 static int dsi_bind(struct device *dev, struct device *master, void *data) 4555 { 4556 struct dss_device *dss = dss_get_device(master); 4557 struct dsi_data *dsi = dev_get_drvdata(dev); 4558 char name[10]; 4559 u32 rev; 4560 int r; 4561 4562 dsi->dss = dss; 4563 4564 dsi_init_pll_data(dss, dsi); 4565 4566 r = dsi_runtime_get(dsi); 4567 if (r) 4568 return r; 4569 4570 rev = dsi_read_reg(dsi, DSI_REVISION); 4571 dev_dbg(dev, "OMAP DSI rev %d.%d\n", 4572 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 4573 4574 dsi->line_buffer_size = dsi_get_line_buf_size(dsi); 4575 4576 dsi_runtime_put(dsi); 4577 4578 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1); 4579 dsi->debugfs.regs = dss_debugfs_create_file(dss, name, 4580 dsi_dump_dsi_regs, dsi); 4581 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 4582 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1); 4583 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name, 4584 dsi_dump_dsi_irqs, dsi); 4585 #endif 4586 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1); 4587 dsi->debugfs.clks = dss_debugfs_create_file(dss, name, 4588 dsi_dump_dsi_clocks, dsi); 4589 4590 return 0; 4591 } 4592 4593 static void dsi_unbind(struct device *dev, struct device *master, void *data) 4594 { 4595 struct dsi_data *dsi = dev_get_drvdata(dev); 4596 4597 dss_debugfs_remove_file(dsi->debugfs.clks); 4598 dss_debugfs_remove_file(dsi->debugfs.irqs); 4599 dss_debugfs_remove_file(dsi->debugfs.regs); 4600 4601 WARN_ON(dsi->scp_clk_refcount > 0); 4602 4603 dss_pll_unregister(&dsi->pll); 4604 } 4605 4606 static const struct component_ops dsi_component_ops = { 4607 .bind = dsi_bind, 4608 .unbind = dsi_unbind, 4609 }; 4610 4611 /* ----------------------------------------------------------------------------- 4612 * DRM Bridge Operations 4613 */ 4614 4615 static int dsi_bridge_attach(struct drm_bridge *bridge, 4616 struct drm_encoder *encoder, 4617 enum drm_bridge_attach_flags flags) 4618 { 4619 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4620 4621 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 4622 return -EINVAL; 4623 4624 return drm_bridge_attach(encoder, dsi->output.next_bridge, 4625 bridge, flags); 4626 } 4627 4628 static enum drm_mode_status 4629 dsi_bridge_mode_valid(struct drm_bridge *bridge, 4630 const struct drm_display_info *info, 4631 const struct drm_display_mode *mode) 4632 { 4633 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4634 struct dsi_clk_calc_ctx ctx; 4635 int r; 4636 4637 mutex_lock(&dsi->lock); 4638 r = __dsi_calc_config(dsi, mode, &ctx); 4639 mutex_unlock(&dsi->lock); 4640 4641 return r ? MODE_CLOCK_RANGE : MODE_OK; 4642 } 4643 4644 static void dsi_bridge_mode_set(struct drm_bridge *bridge, 4645 const struct drm_display_mode *mode, 4646 const struct drm_display_mode *adjusted_mode) 4647 { 4648 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4649 4650 dsi_set_config(&dsi->output, adjusted_mode); 4651 } 4652 4653 static void dsi_bridge_enable(struct drm_bridge *bridge, 4654 struct drm_atomic_commit *commit) 4655 { 4656 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4657 struct omap_dss_device *dssdev = &dsi->output; 4658 4659 cancel_delayed_work_sync(&dsi->dsi_disable_work); 4660 4661 dsi_bus_lock(dsi); 4662 4663 if (!dsi->iface_enabled) 4664 dsi_enable(dsi); 4665 4666 dsi_enable_video_output(dssdev, VC_VIDEO); 4667 4668 dsi->video_enabled = true; 4669 4670 dsi_bus_unlock(dsi); 4671 } 4672 4673 static void dsi_bridge_disable(struct drm_bridge *bridge, 4674 struct drm_atomic_commit *commit) 4675 { 4676 struct dsi_data *dsi = drm_bridge_to_dsi(bridge); 4677 struct omap_dss_device *dssdev = &dsi->output; 4678 4679 cancel_delayed_work_sync(&dsi->dsi_disable_work); 4680 4681 dsi_bus_lock(dsi); 4682 4683 dsi->video_enabled = false; 4684 4685 dsi_disable_video_output(dssdev, VC_VIDEO); 4686 4687 dsi_disable(dsi); 4688 4689 dsi_bus_unlock(dsi); 4690 } 4691 4692 static const struct drm_bridge_funcs dsi_bridge_funcs = { 4693 .atomic_create_state = drm_atomic_helper_bridge_create_state, 4694 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 4695 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 4696 .attach = dsi_bridge_attach, 4697 .mode_valid = dsi_bridge_mode_valid, 4698 .mode_set = dsi_bridge_mode_set, 4699 .atomic_enable = dsi_bridge_enable, 4700 .atomic_disable = dsi_bridge_disable, 4701 }; 4702 4703 static void dsi_bridge_init(struct dsi_data *dsi) 4704 { 4705 dsi->bridge.of_node = dsi->host.dev->of_node; 4706 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 4707 4708 drm_bridge_add(&dsi->bridge); 4709 } 4710 4711 static void dsi_bridge_cleanup(struct dsi_data *dsi) 4712 { 4713 drm_bridge_remove(&dsi->bridge); 4714 } 4715 4716 /* ----------------------------------------------------------------------------- 4717 * Probe & Remove, Suspend & Resume 4718 */ 4719 4720 static int dsi_init_output(struct dsi_data *dsi) 4721 { 4722 struct omap_dss_device *out = &dsi->output; 4723 int r; 4724 4725 dsi_bridge_init(dsi); 4726 4727 out->dev = dsi->dev; 4728 out->id = dsi->module_id == 0 ? 4729 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 4730 4731 out->type = OMAP_DISPLAY_TYPE_DSI; 4732 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 4733 out->dispc_channel = dsi_get_dispc_channel(dsi); 4734 out->dsi_ops = &dsi_ops; 4735 out->of_port = 0; 4736 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE 4737 | DRM_BUS_FLAG_DE_HIGH 4738 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 4739 4740 r = omapdss_device_init_output(out, &dsi->bridge); 4741 if (r < 0) { 4742 dsi_bridge_cleanup(dsi); 4743 return r; 4744 } 4745 4746 omapdss_device_register(out); 4747 4748 return 0; 4749 } 4750 4751 static void dsi_uninit_output(struct dsi_data *dsi) 4752 { 4753 struct omap_dss_device *out = &dsi->output; 4754 4755 omapdss_device_unregister(out); 4756 omapdss_device_cleanup_output(out); 4757 dsi_bridge_cleanup(dsi); 4758 } 4759 4760 static int dsi_probe_of(struct dsi_data *dsi) 4761 { 4762 struct device_node *node = dsi->dev->of_node; 4763 struct property *prop; 4764 u32 lane_arr[10]; 4765 int len, num_pins; 4766 int r; 4767 struct device_node *ep; 4768 4769 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 4770 if (!ep) 4771 return 0; 4772 4773 prop = of_find_property(ep, "lanes", &len); 4774 if (prop == NULL) { 4775 dev_err(dsi->dev, "failed to find lane data\n"); 4776 r = -EINVAL; 4777 goto err; 4778 } 4779 4780 num_pins = len / sizeof(u32); 4781 4782 if (num_pins < 4 || num_pins % 2 != 0 || 4783 num_pins > dsi->num_lanes_supported * 2) { 4784 dev_err(dsi->dev, "bad number of lanes\n"); 4785 r = -EINVAL; 4786 goto err; 4787 } 4788 4789 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 4790 if (r) { 4791 dev_err(dsi->dev, "failed to read lane data\n"); 4792 goto err; 4793 } 4794 4795 r = dsi_configure_pins(dsi, num_pins, lane_arr); 4796 if (r) { 4797 dev_err(dsi->dev, "failed to configure pins"); 4798 goto err; 4799 } 4800 4801 of_node_put(ep); 4802 4803 return 0; 4804 4805 err: 4806 of_node_put(ep); 4807 return r; 4808 } 4809 4810 static const struct dsi_of_data dsi_of_data_omap34xx = { 4811 .model = DSI_MODEL_OMAP3, 4812 .pll_hw = &dss_omap3_dsi_pll_hw, 4813 .modules = (const struct dsi_module_id_data[]) { 4814 { .address = 0x4804fc00, .id = 0, }, 4815 { }, 4816 }, 4817 .max_fck_freq = 173000000, 4818 .max_pll_lpdiv = (1 << 13) - 1, 4819 .quirks = DSI_QUIRK_REVERSE_TXCLKESC, 4820 }; 4821 4822 static const struct dsi_of_data dsi_of_data_omap36xx = { 4823 .model = DSI_MODEL_OMAP3, 4824 .pll_hw = &dss_omap3_dsi_pll_hw, 4825 .modules = (const struct dsi_module_id_data[]) { 4826 { .address = 0x4804fc00, .id = 0, }, 4827 { }, 4828 }, 4829 .max_fck_freq = 173000000, 4830 .max_pll_lpdiv = (1 << 13) - 1, 4831 .quirks = DSI_QUIRK_PLL_PWR_BUG, 4832 }; 4833 4834 static const struct dsi_of_data dsi_of_data_omap4 = { 4835 .model = DSI_MODEL_OMAP4, 4836 .pll_hw = &dss_omap4_dsi_pll_hw, 4837 .modules = (const struct dsi_module_id_data[]) { 4838 { .address = 0x58004000, .id = 0, }, 4839 { .address = 0x58005000, .id = 1, }, 4840 { }, 4841 }, 4842 .max_fck_freq = 170000000, 4843 .max_pll_lpdiv = (1 << 13) - 1, 4844 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 4845 | DSI_QUIRK_GNQ, 4846 }; 4847 4848 static const struct dsi_of_data dsi_of_data_omap5 = { 4849 .model = DSI_MODEL_OMAP5, 4850 .pll_hw = &dss_omap5_dsi_pll_hw, 4851 .modules = (const struct dsi_module_id_data[]) { 4852 { .address = 0x58004000, .id = 0, }, 4853 { .address = 0x58009000, .id = 1, }, 4854 { }, 4855 }, 4856 .max_fck_freq = 209250000, 4857 .max_pll_lpdiv = (1 << 13) - 1, 4858 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 4859 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC, 4860 }; 4861 4862 static const struct of_device_id dsi_of_match[] = { 4863 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, }, 4864 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, }, 4865 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, }, 4866 {}, 4867 }; 4868 4869 static const struct soc_device_attribute dsi_soc_devices[] = { 4870 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx }, 4871 { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, 4872 { /* sentinel */ } 4873 }; 4874 4875 static void omap_dsi_disable_work_callback(struct work_struct *work) 4876 { 4877 struct dsi_data *dsi = container_of(work, struct dsi_data, dsi_disable_work.work); 4878 4879 dsi_bus_lock(dsi); 4880 4881 if (dsi->iface_enabled && !dsi->video_enabled) 4882 dsi_disable(dsi); 4883 4884 dsi_bus_unlock(dsi); 4885 } 4886 4887 static int dsi_probe(struct platform_device *pdev) 4888 { 4889 const struct soc_device_attribute *soc; 4890 const struct dsi_module_id_data *d; 4891 struct device *dev = &pdev->dev; 4892 struct dsi_data *dsi; 4893 struct resource *dsi_mem; 4894 unsigned int i; 4895 int r; 4896 4897 dsi = devm_drm_bridge_alloc(dev, struct dsi_data, bridge, &dsi_bridge_funcs); 4898 if (IS_ERR(dsi)) 4899 return PTR_ERR(dsi); 4900 4901 dsi->dev = dev; 4902 dev_set_drvdata(dev, dsi); 4903 4904 spin_lock_init(&dsi->irq_lock); 4905 spin_lock_init(&dsi->errors_lock); 4906 dsi->errors = 0; 4907 4908 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 4909 spin_lock_init(&dsi->irq_stats_lock); 4910 dsi->irq_stats.last_reset = jiffies; 4911 #endif 4912 4913 mutex_init(&dsi->lock); 4914 sema_init(&dsi->bus_lock, 1); 4915 4916 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 4917 dsi_framedone_timeout_work_callback); 4918 4919 INIT_DEFERRABLE_WORK(&dsi->dsi_disable_work, omap_dsi_disable_work_callback); 4920 4921 #ifdef DSI_CATCH_MISSING_TE 4922 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); 4923 #endif 4924 4925 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto"); 4926 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem); 4927 if (IS_ERR(dsi->proto_base)) 4928 return PTR_ERR(dsi->proto_base); 4929 4930 dsi->phy_base = devm_platform_ioremap_resource_byname(pdev, "phy"); 4931 if (IS_ERR(dsi->phy_base)) 4932 return PTR_ERR(dsi->phy_base); 4933 4934 dsi->pll_base = devm_platform_ioremap_resource_byname(pdev, "pll"); 4935 if (IS_ERR(dsi->pll_base)) 4936 return PTR_ERR(dsi->pll_base); 4937 4938 dsi->irq = platform_get_irq(pdev, 0); 4939 if (dsi->irq < 0) { 4940 DSSERR("platform_get_irq failed\n"); 4941 return -ENODEV; 4942 } 4943 4944 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler, 4945 IRQF_SHARED, dev_name(dev), dsi); 4946 if (r < 0) { 4947 DSSERR("request_irq failed\n"); 4948 return r; 4949 } 4950 4951 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd"); 4952 if (IS_ERR(dsi->vdds_dsi_reg)) { 4953 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER) 4954 DSSERR("can't get DSI VDD regulator\n"); 4955 return PTR_ERR(dsi->vdds_dsi_reg); 4956 } 4957 4958 soc = soc_device_match(dsi_soc_devices); 4959 if (soc) 4960 dsi->data = soc->data; 4961 else 4962 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; 4963 4964 d = dsi->data->modules; 4965 while (d->address != 0 && d->address != dsi_mem->start) 4966 d++; 4967 4968 if (d->address == 0) { 4969 DSSERR("unsupported DSI module\n"); 4970 return -ENODEV; 4971 } 4972 4973 dsi->module_id = d->id; 4974 4975 if (dsi->data->model == DSI_MODEL_OMAP4 || 4976 dsi->data->model == DSI_MODEL_OMAP5) { 4977 struct device_node *np; 4978 4979 /* 4980 * The OMAP4/5 display DT bindings don't reference the padconf 4981 * syscon. Our only option to retrieve it is to find it by name. 4982 */ 4983 np = of_find_node_by_name(NULL, 4984 dsi->data->model == DSI_MODEL_OMAP4 ? 4985 "omap4_padconf_global" : "omap5_padconf_global"); 4986 if (!np) 4987 return -ENODEV; 4988 4989 dsi->syscon = syscon_node_to_regmap(np); 4990 of_node_put(np); 4991 } 4992 4993 /* DSI VCs initialization */ 4994 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) 4995 dsi->vc[i].source = DSI_VC_SOURCE_L4; 4996 4997 r = dsi_get_clocks(dsi); 4998 if (r) 4999 return r; 5000 5001 pm_runtime_enable(dev); 5002 5003 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5004 * of data to 3 by default */ 5005 if (dsi->data->quirks & DSI_QUIRK_GNQ) { 5006 dsi_runtime_get(dsi); 5007 /* NB_DATA_LANES */ 5008 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); 5009 dsi_runtime_put(dsi); 5010 } else { 5011 dsi->num_lanes_supported = 3; 5012 } 5013 5014 dsi->host.ops = &omap_dsi_host_ops; 5015 dsi->host.dev = &pdev->dev; 5016 5017 r = dsi_probe_of(dsi); 5018 if (r) { 5019 DSSERR("Invalid DSI DT data\n"); 5020 goto err_pm_disable; 5021 } 5022 5023 r = mipi_dsi_host_register(&dsi->host); 5024 if (r < 0) { 5025 dev_err(&pdev->dev, "failed to register DSI host: %d\n", r); 5026 goto err_pm_disable; 5027 } 5028 5029 r = dsi_init_output(dsi); 5030 if (r) 5031 goto err_dsi_host_unregister; 5032 5033 r = component_add(&pdev->dev, &dsi_component_ops); 5034 if (r) 5035 goto err_uninit_output; 5036 5037 return 0; 5038 5039 err_uninit_output: 5040 dsi_uninit_output(dsi); 5041 err_dsi_host_unregister: 5042 mipi_dsi_host_unregister(&dsi->host); 5043 err_pm_disable: 5044 pm_runtime_disable(dev); 5045 return r; 5046 } 5047 5048 static void dsi_remove(struct platform_device *pdev) 5049 { 5050 struct dsi_data *dsi = platform_get_drvdata(pdev); 5051 5052 component_del(&pdev->dev, &dsi_component_ops); 5053 5054 dsi_uninit_output(dsi); 5055 5056 mipi_dsi_host_unregister(&dsi->host); 5057 5058 pm_runtime_disable(&pdev->dev); 5059 5060 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5061 regulator_disable(dsi->vdds_dsi_reg); 5062 dsi->vdds_dsi_enabled = false; 5063 } 5064 } 5065 5066 static __maybe_unused int dsi_runtime_suspend(struct device *dev) 5067 { 5068 struct dsi_data *dsi = dev_get_drvdata(dev); 5069 5070 dsi->is_enabled = false; 5071 /* ensure the irq handler sees the is_enabled value */ 5072 smp_wmb(); 5073 /* wait for current handler to finish before turning the DSI off */ 5074 synchronize_irq(dsi->irq); 5075 5076 return 0; 5077 } 5078 5079 static __maybe_unused int dsi_runtime_resume(struct device *dev) 5080 { 5081 struct dsi_data *dsi = dev_get_drvdata(dev); 5082 5083 dsi->is_enabled = true; 5084 /* ensure the irq handler sees the is_enabled value */ 5085 smp_wmb(); 5086 5087 return 0; 5088 } 5089 5090 static const struct dev_pm_ops dsi_pm_ops = { 5091 SET_RUNTIME_PM_OPS(dsi_runtime_suspend, dsi_runtime_resume, NULL) 5092 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 5093 }; 5094 5095 struct platform_driver omap_dsihw_driver = { 5096 .probe = dsi_probe, 5097 .remove = dsi_remove, 5098 .driver = { 5099 .name = "omapdss_dsi", 5100 .pm = &dsi_pm_ops, 5101 .of_match_table = dsi_of_match, 5102 .suppress_bind_attrs = true, 5103 }, 5104 }; 5105