1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 * 6 * Some code and ideas taken from drivers/video/omap/ driver 7 * by Imre Deak. 8 */ 9 10 #define DSS_SUBSYS_NAME "DPI" 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/export.h> 17 #include <linux/kernel.h> 18 #include <linux/of.h> 19 #include <linux/of_graph.h> 20 #include <linux/platform_device.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/string.h> 23 #include <linux/sys_soc.h> 24 25 #include <drm/drm_bridge.h> 26 27 #include "dss.h" 28 #include "omapdss.h" 29 30 struct dpi_data { 31 struct platform_device *pdev; 32 enum dss_model dss_model; 33 struct dss_device *dss; 34 unsigned int id; 35 36 struct regulator *vdds_dsi_reg; 37 enum dss_clk_source clk_src; 38 struct dss_pll *pll; 39 40 struct dss_lcd_mgr_config mgr_config; 41 unsigned long pixelclock; 42 int data_lines; 43 44 struct omap_dss_device output; 45 struct drm_bridge bridge; 46 }; 47 48 #define drm_bridge_to_dpi(bridge) container_of(bridge, struct dpi_data, bridge) 49 50 /* ----------------------------------------------------------------------------- 51 * Clock Handling and PLL 52 */ 53 54 static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi, 55 enum omap_channel channel) 56 { 57 /* 58 * Possible clock sources: 59 * LCD1: FCK/PLL1_1/HDMI_PLL 60 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3) 61 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1) 62 */ 63 64 switch (channel) { 65 case OMAP_DSS_CHANNEL_LCD: 66 { 67 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1)) 68 return DSS_CLK_SRC_PLL1_1; 69 break; 70 } 71 case OMAP_DSS_CHANNEL_LCD2: 72 { 73 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 74 return DSS_CLK_SRC_PLL1_3; 75 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3)) 76 return DSS_CLK_SRC_PLL2_3; 77 break; 78 } 79 case OMAP_DSS_CHANNEL_LCD3: 80 { 81 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1)) 82 return DSS_CLK_SRC_PLL2_1; 83 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) 84 return DSS_CLK_SRC_PLL1_3; 85 break; 86 } 87 default: 88 break; 89 } 90 91 return DSS_CLK_SRC_FCK; 92 } 93 94 static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi) 95 { 96 enum omap_channel channel = dpi->output.dispc_channel; 97 98 /* 99 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL 100 * would also be used for DISPC fclk. Meaning, when the DPI output is 101 * disabled, DISPC clock will be disabled, and TV out will stop. 102 */ 103 switch (dpi->dss_model) { 104 case DSS_MODEL_OMAP2: 105 case DSS_MODEL_OMAP3: 106 return DSS_CLK_SRC_FCK; 107 108 case DSS_MODEL_OMAP4: 109 switch (channel) { 110 case OMAP_DSS_CHANNEL_LCD: 111 return DSS_CLK_SRC_PLL1_1; 112 case OMAP_DSS_CHANNEL_LCD2: 113 return DSS_CLK_SRC_PLL2_1; 114 default: 115 return DSS_CLK_SRC_FCK; 116 } 117 118 case DSS_MODEL_OMAP5: 119 switch (channel) { 120 case OMAP_DSS_CHANNEL_LCD: 121 return DSS_CLK_SRC_PLL1_1; 122 case OMAP_DSS_CHANNEL_LCD3: 123 return DSS_CLK_SRC_PLL2_1; 124 case OMAP_DSS_CHANNEL_LCD2: 125 default: 126 return DSS_CLK_SRC_FCK; 127 } 128 129 case DSS_MODEL_DRA7: 130 return dpi_get_clk_src_dra7xx(dpi, channel); 131 132 default: 133 return DSS_CLK_SRC_FCK; 134 } 135 } 136 137 struct dpi_clk_calc_ctx { 138 struct dpi_data *dpi; 139 unsigned int clkout_idx; 140 141 /* inputs */ 142 143 unsigned long pck_min, pck_max; 144 145 /* outputs */ 146 147 struct dss_pll_clock_info pll_cinfo; 148 unsigned long fck; 149 struct dispc_clock_info dispc_cinfo; 150 }; 151 152 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 153 unsigned long pck, void *data) 154 { 155 struct dpi_clk_calc_ctx *ctx = data; 156 157 /* 158 * Odd dividers give us uneven duty cycle, causing problem when level 159 * shifted. So skip all odd dividers when the pixel clock is on the 160 * higher side. 161 */ 162 if (ctx->pck_min >= 100000000) { 163 if (lckd > 1 && lckd % 2 != 0) 164 return false; 165 166 if (pckd > 1 && pckd % 2 != 0) 167 return false; 168 } 169 170 ctx->dispc_cinfo.lck_div = lckd; 171 ctx->dispc_cinfo.pck_div = pckd; 172 ctx->dispc_cinfo.lck = lck; 173 ctx->dispc_cinfo.pck = pck; 174 175 return true; 176 } 177 178 179 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 180 void *data) 181 { 182 struct dpi_clk_calc_ctx *ctx = data; 183 184 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; 185 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; 186 187 return dispc_div_calc(ctx->dpi->dss->dispc, dispc, 188 ctx->pck_min, ctx->pck_max, 189 dpi_calc_dispc_cb, ctx); 190 } 191 192 193 static bool dpi_calc_pll_cb(int n, int m, unsigned long fint, 194 unsigned long clkdco, 195 void *data) 196 { 197 struct dpi_clk_calc_ctx *ctx = data; 198 199 ctx->pll_cinfo.n = n; 200 ctx->pll_cinfo.m = m; 201 ctx->pll_cinfo.fint = fint; 202 ctx->pll_cinfo.clkdco = clkdco; 203 204 return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco, 205 ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss), 206 dpi_calc_hsdiv_cb, ctx); 207 } 208 209 static bool dpi_calc_dss_cb(unsigned long fck, void *data) 210 { 211 struct dpi_clk_calc_ctx *ctx = data; 212 213 ctx->fck = fck; 214 215 return dispc_div_calc(ctx->dpi->dss->dispc, fck, 216 ctx->pck_min, ctx->pck_max, 217 dpi_calc_dispc_cb, ctx); 218 } 219 220 static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck, 221 struct dpi_clk_calc_ctx *ctx) 222 { 223 unsigned long clkin; 224 225 memset(ctx, 0, sizeof(*ctx)); 226 ctx->dpi = dpi; 227 ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src); 228 229 clkin = clk_get_rate(dpi->pll->clkin); 230 231 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) { 232 unsigned long pll_min, pll_max; 233 234 ctx->pck_min = pck - 1000; 235 ctx->pck_max = pck + 1000; 236 237 pll_min = 0; 238 pll_max = 0; 239 240 return dss_pll_calc_a(ctx->dpi->pll, clkin, 241 pll_min, pll_max, 242 dpi_calc_pll_cb, ctx); 243 } else { /* DSS_PLL_TYPE_B */ 244 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo); 245 246 ctx->dispc_cinfo.lck_div = 1; 247 ctx->dispc_cinfo.pck_div = 1; 248 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0]; 249 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck; 250 251 return true; 252 } 253 } 254 255 static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck, 256 struct dpi_clk_calc_ctx *ctx) 257 { 258 int i; 259 260 /* 261 * DSS fck gives us very few possibilities, so finding a good pixel 262 * clock may not be possible. We try multiple times to find the clock, 263 * each time widening the pixel clock range we look for, up to 264 * +/- ~15MHz. 265 */ 266 267 for (i = 0; i < 25; ++i) { 268 bool ok; 269 270 memset(ctx, 0, sizeof(*ctx)); 271 ctx->dpi = dpi; 272 if (pck > 1000 * i * i * i) 273 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); 274 else 275 ctx->pck_min = 0; 276 ctx->pck_max = pck + 1000 * i * i * i; 277 278 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min, 279 dpi_calc_dss_cb, ctx); 280 if (ok) 281 return ok; 282 } 283 284 return false; 285 } 286 287 288 289 static int dpi_set_pll_clk(struct dpi_data *dpi, unsigned long pck_req) 290 { 291 struct dpi_clk_calc_ctx ctx; 292 int r; 293 bool ok; 294 295 ok = dpi_pll_clk_calc(dpi, pck_req, &ctx); 296 if (!ok) 297 return -EINVAL; 298 299 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); 300 if (r) 301 return r; 302 303 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel, 304 dpi->clk_src); 305 306 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 307 308 return 0; 309 } 310 311 static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req) 312 { 313 struct dpi_clk_calc_ctx ctx; 314 int r; 315 bool ok; 316 317 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx); 318 if (!ok) 319 return -EINVAL; 320 321 r = dss_set_fck_rate(dpi->dss, ctx.fck); 322 if (r) 323 return r; 324 325 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 326 327 return 0; 328 } 329 330 static int dpi_set_mode(struct dpi_data *dpi) 331 { 332 int r; 333 334 if (dpi->pll) 335 r = dpi_set_pll_clk(dpi, dpi->pixelclock); 336 else 337 r = dpi_set_dispc_clk(dpi, dpi->pixelclock); 338 339 return r; 340 } 341 342 static void dpi_config_lcd_manager(struct dpi_data *dpi) 343 { 344 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 345 346 dpi->mgr_config.stallmode = false; 347 dpi->mgr_config.fifohandcheck = false; 348 349 dpi->mgr_config.video_port_width = dpi->data_lines; 350 351 dpi->mgr_config.lcden_sig_polarity = 0; 352 353 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config); 354 } 355 356 static int dpi_clock_update(struct dpi_data *dpi, unsigned long *clock) 357 { 358 int lck_div, pck_div; 359 unsigned long fck; 360 struct dpi_clk_calc_ctx ctx; 361 362 if (dpi->pll) { 363 if (!dpi_pll_clk_calc(dpi, *clock, &ctx)) 364 return -EINVAL; 365 366 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 367 } else { 368 if (!dpi_dss_clk_calc(dpi, *clock, &ctx)) 369 return -EINVAL; 370 371 fck = ctx.fck; 372 } 373 374 lck_div = ctx.dispc_cinfo.lck_div; 375 pck_div = ctx.dispc_cinfo.pck_div; 376 377 *clock = fck / lck_div / pck_div; 378 379 return 0; 380 } 381 382 static int dpi_verify_pll(struct dss_pll *pll) 383 { 384 int r; 385 386 /* do initial setup with the PLL to see if it is operational */ 387 388 r = dss_pll_enable(pll); 389 if (r) 390 return r; 391 392 dss_pll_disable(pll); 393 394 return 0; 395 } 396 397 static void dpi_init_pll(struct dpi_data *dpi) 398 { 399 struct dss_pll *pll; 400 401 if (dpi->pll) 402 return; 403 404 dpi->clk_src = dpi_get_clk_src(dpi); 405 406 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src); 407 if (!pll) 408 return; 409 410 if (dpi_verify_pll(pll)) { 411 DSSWARN("PLL not operational\n"); 412 return; 413 } 414 415 dpi->pll = pll; 416 } 417 418 /* ----------------------------------------------------------------------------- 419 * DRM Bridge Operations 420 */ 421 422 static int dpi_bridge_attach(struct drm_bridge *bridge, 423 struct drm_encoder *encoder, 424 enum drm_bridge_attach_flags flags) 425 { 426 struct dpi_data *dpi = drm_bridge_to_dpi(bridge); 427 428 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 429 return -EINVAL; 430 431 dpi_init_pll(dpi); 432 433 return drm_bridge_attach(encoder, dpi->output.next_bridge, 434 bridge, flags); 435 } 436 437 static enum drm_mode_status 438 dpi_bridge_mode_valid(struct drm_bridge *bridge, 439 const struct drm_display_info *info, 440 const struct drm_display_mode *mode) 441 { 442 struct dpi_data *dpi = drm_bridge_to_dpi(bridge); 443 unsigned long clock = mode->clock * 1000; 444 int ret; 445 446 if (mode->hdisplay % 8 != 0) 447 return MODE_BAD_WIDTH; 448 449 if (mode->clock == 0) 450 return MODE_NOCLOCK; 451 452 ret = dpi_clock_update(dpi, &clock); 453 if (ret < 0) 454 return MODE_CLOCK_RANGE; 455 456 return MODE_OK; 457 } 458 459 static bool dpi_bridge_mode_fixup(struct drm_bridge *bridge, 460 const struct drm_display_mode *mode, 461 struct drm_display_mode *adjusted_mode) 462 { 463 struct dpi_data *dpi = drm_bridge_to_dpi(bridge); 464 unsigned long clock = mode->clock * 1000; 465 int ret; 466 467 ret = dpi_clock_update(dpi, &clock); 468 if (ret < 0) 469 return false; 470 471 adjusted_mode->clock = clock / 1000; 472 473 return true; 474 } 475 476 static void dpi_bridge_mode_set(struct drm_bridge *bridge, 477 const struct drm_display_mode *mode, 478 const struct drm_display_mode *adjusted_mode) 479 { 480 struct dpi_data *dpi = drm_bridge_to_dpi(bridge); 481 482 dpi->pixelclock = adjusted_mode->clock * 1000; 483 } 484 485 static void dpi_bridge_enable(struct drm_bridge *bridge) 486 { 487 struct dpi_data *dpi = drm_bridge_to_dpi(bridge); 488 int r; 489 490 if (dpi->vdds_dsi_reg) { 491 r = regulator_enable(dpi->vdds_dsi_reg); 492 if (r) 493 return; 494 } 495 496 r = dispc_runtime_get(dpi->dss->dispc); 497 if (r) 498 goto err_get_dispc; 499 500 r = dss_dpi_select_source(dpi->dss, dpi->id, dpi->output.dispc_channel); 501 if (r) 502 goto err_src_sel; 503 504 if (dpi->pll) { 505 r = dss_pll_enable(dpi->pll); 506 if (r) 507 goto err_pll_init; 508 } 509 510 r = dpi_set_mode(dpi); 511 if (r) 512 goto err_set_mode; 513 514 dpi_config_lcd_manager(dpi); 515 516 mdelay(2); 517 518 r = dss_mgr_enable(&dpi->output); 519 if (r) 520 goto err_mgr_enable; 521 522 return; 523 524 err_mgr_enable: 525 err_set_mode: 526 if (dpi->pll) 527 dss_pll_disable(dpi->pll); 528 err_pll_init: 529 err_src_sel: 530 dispc_runtime_put(dpi->dss->dispc); 531 err_get_dispc: 532 if (dpi->vdds_dsi_reg) 533 regulator_disable(dpi->vdds_dsi_reg); 534 } 535 536 static void dpi_bridge_disable(struct drm_bridge *bridge) 537 { 538 struct dpi_data *dpi = drm_bridge_to_dpi(bridge); 539 540 dss_mgr_disable(&dpi->output); 541 542 if (dpi->pll) { 543 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel, 544 DSS_CLK_SRC_FCK); 545 dss_pll_disable(dpi->pll); 546 } 547 548 dispc_runtime_put(dpi->dss->dispc); 549 550 if (dpi->vdds_dsi_reg) 551 regulator_disable(dpi->vdds_dsi_reg); 552 } 553 554 static const struct drm_bridge_funcs dpi_bridge_funcs = { 555 .attach = dpi_bridge_attach, 556 .mode_valid = dpi_bridge_mode_valid, 557 .mode_fixup = dpi_bridge_mode_fixup, 558 .mode_set = dpi_bridge_mode_set, 559 .enable = dpi_bridge_enable, 560 .disable = dpi_bridge_disable, 561 }; 562 563 static void dpi_bridge_init(struct dpi_data *dpi) 564 { 565 dpi->bridge.funcs = &dpi_bridge_funcs; 566 dpi->bridge.of_node = dpi->pdev->dev.of_node; 567 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI; 568 569 drm_bridge_add(&dpi->bridge); 570 } 571 572 static void dpi_bridge_cleanup(struct dpi_data *dpi) 573 { 574 drm_bridge_remove(&dpi->bridge); 575 } 576 577 /* ----------------------------------------------------------------------------- 578 * Initialisation and Cleanup 579 */ 580 581 /* 582 * Return a hardcoded channel for the DPI output. This should work for 583 * current use cases, but this can be later expanded to either resolve 584 * the channel in some more dynamic manner, or get the channel as a user 585 * parameter. 586 */ 587 static enum omap_channel dpi_get_channel(struct dpi_data *dpi) 588 { 589 switch (dpi->dss_model) { 590 case DSS_MODEL_OMAP2: 591 case DSS_MODEL_OMAP3: 592 return OMAP_DSS_CHANNEL_LCD; 593 594 case DSS_MODEL_DRA7: 595 switch (dpi->id) { 596 case 2: 597 return OMAP_DSS_CHANNEL_LCD3; 598 case 1: 599 return OMAP_DSS_CHANNEL_LCD2; 600 case 0: 601 default: 602 return OMAP_DSS_CHANNEL_LCD; 603 } 604 605 case DSS_MODEL_OMAP4: 606 return OMAP_DSS_CHANNEL_LCD2; 607 608 case DSS_MODEL_OMAP5: 609 return OMAP_DSS_CHANNEL_LCD3; 610 611 default: 612 DSSWARN("unsupported DSS version\n"); 613 return OMAP_DSS_CHANNEL_LCD; 614 } 615 } 616 617 static int dpi_init_output_port(struct dpi_data *dpi, struct device_node *port) 618 { 619 struct omap_dss_device *out = &dpi->output; 620 u32 port_num = 0; 621 int r; 622 623 dpi_bridge_init(dpi); 624 625 of_property_read_u32(port, "reg", &port_num); 626 dpi->id = port_num <= 2 ? port_num : 0; 627 628 switch (port_num) { 629 case 2: 630 out->name = "dpi.2"; 631 break; 632 case 1: 633 out->name = "dpi.1"; 634 break; 635 case 0: 636 default: 637 out->name = "dpi.0"; 638 break; 639 } 640 641 out->dev = &dpi->pdev->dev; 642 out->id = OMAP_DSS_OUTPUT_DPI; 643 out->type = OMAP_DISPLAY_TYPE_DPI; 644 out->dispc_channel = dpi_get_channel(dpi); 645 out->of_port = port_num; 646 647 r = omapdss_device_init_output(out, &dpi->bridge); 648 if (r < 0) { 649 dpi_bridge_cleanup(dpi); 650 return r; 651 } 652 653 omapdss_device_register(out); 654 655 return 0; 656 } 657 658 static void dpi_uninit_output_port(struct device_node *port) 659 { 660 struct dpi_data *dpi = port->data; 661 struct omap_dss_device *out = &dpi->output; 662 663 omapdss_device_unregister(out); 664 omapdss_device_cleanup_output(out); 665 666 dpi_bridge_cleanup(dpi); 667 } 668 669 /* ----------------------------------------------------------------------------- 670 * Initialisation and Cleanup 671 */ 672 673 static const struct soc_device_attribute dpi_soc_devices[] = { 674 { .machine = "OMAP3[456]*" }, 675 { .machine = "[AD]M37*" }, 676 { /* sentinel */ } 677 }; 678 679 static int dpi_init_regulator(struct dpi_data *dpi) 680 { 681 struct regulator *vdds_dsi; 682 683 /* 684 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and 685 * DM37xx only. 686 */ 687 if (!soc_device_match(dpi_soc_devices)) 688 return 0; 689 690 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi"); 691 if (IS_ERR(vdds_dsi)) { 692 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 693 DSSERR("can't get VDDS_DSI regulator\n"); 694 return PTR_ERR(vdds_dsi); 695 } 696 697 dpi->vdds_dsi_reg = vdds_dsi; 698 699 return 0; 700 } 701 702 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev, 703 struct device_node *port, enum dss_model dss_model) 704 { 705 struct dpi_data *dpi; 706 struct device_node *ep; 707 u32 datalines; 708 int r; 709 710 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL); 711 if (!dpi) 712 return -ENOMEM; 713 714 ep = of_graph_get_next_port_endpoint(port, NULL); 715 if (!ep) 716 return 0; 717 718 r = of_property_read_u32(ep, "data-lines", &datalines); 719 of_node_put(ep); 720 if (r) { 721 DSSERR("failed to parse datalines\n"); 722 return r; 723 } 724 725 dpi->data_lines = datalines; 726 727 dpi->pdev = pdev; 728 dpi->dss_model = dss_model; 729 dpi->dss = dss; 730 port->data = dpi; 731 732 r = dpi_init_regulator(dpi); 733 if (r) 734 return r; 735 736 return dpi_init_output_port(dpi, port); 737 } 738 739 void dpi_uninit_port(struct device_node *port) 740 { 741 struct dpi_data *dpi = port->data; 742 743 if (!dpi) 744 return; 745 746 dpi_uninit_output_port(port); 747 } 748