1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 * Martin Peres 24 */ 25 #include "priv.h" 26 27 #include <core/device.h> 28 29 struct nv40_therm_priv { 30 struct nvkm_therm_priv base; 31 }; 32 33 enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 }; 34 35 static enum nv40_sensor_style 36 nv40_sensor_style(struct nvkm_therm *therm) 37 { 38 struct nvkm_device *device = nv_device(therm); 39 40 switch (device->chipset) { 41 case 0x43: 42 case 0x44: 43 case 0x4a: 44 case 0x47: 45 return OLD_STYLE; 46 47 case 0x46: 48 case 0x49: 49 case 0x4b: 50 case 0x4e: 51 case 0x4c: 52 case 0x67: 53 case 0x68: 54 case 0x63: 55 return NEW_STYLE; 56 default: 57 return INVALID_STYLE; 58 } 59 } 60 61 static int 62 nv40_sensor_setup(struct nvkm_therm *therm) 63 { 64 enum nv40_sensor_style style = nv40_sensor_style(therm); 65 66 /* enable ADC readout and disable the ALARM threshold */ 67 if (style == NEW_STYLE) { 68 nv_mask(therm, 0x15b8, 0x80000000, 0); 69 nv_wr32(therm, 0x15b0, 0x80003fff); 70 mdelay(20); /* wait for the temperature to stabilize */ 71 return nv_rd32(therm, 0x15b4) & 0x3fff; 72 } else if (style == OLD_STYLE) { 73 nv_wr32(therm, 0x15b0, 0xff); 74 mdelay(20); /* wait for the temperature to stabilize */ 75 return nv_rd32(therm, 0x15b4) & 0xff; 76 } else 77 return -ENODEV; 78 } 79 80 static int 81 nv40_temp_get(struct nvkm_therm *therm) 82 { 83 struct nvkm_therm_priv *priv = (void *)therm; 84 struct nvbios_therm_sensor *sensor = &priv->bios_sensor; 85 enum nv40_sensor_style style = nv40_sensor_style(therm); 86 int core_temp; 87 88 if (style == NEW_STYLE) { 89 nv_wr32(therm, 0x15b0, 0x80003fff); 90 core_temp = nv_rd32(therm, 0x15b4) & 0x3fff; 91 } else if (style == OLD_STYLE) { 92 nv_wr32(therm, 0x15b0, 0xff); 93 core_temp = nv_rd32(therm, 0x15b4) & 0xff; 94 } else 95 return -ENODEV; 96 97 /* if the slope or the offset is unset, do no use the sensor */ 98 if (!sensor->slope_div || !sensor->slope_mult || 99 !sensor->offset_num || !sensor->offset_den) 100 return -ENODEV; 101 102 core_temp = core_temp * sensor->slope_mult / sensor->slope_div; 103 core_temp = core_temp + sensor->offset_num / sensor->offset_den; 104 core_temp = core_temp + sensor->offset_constant - 8; 105 106 /* reserve negative temperatures for errors */ 107 if (core_temp < 0) 108 core_temp = 0; 109 110 return core_temp; 111 } 112 113 static int 114 nv40_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable) 115 { 116 u32 mask = enable ? 0x80000000 : 0x0000000; 117 if (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask); 118 else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask); 119 else { 120 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line); 121 return -ENODEV; 122 } 123 return 0; 124 } 125 126 static int 127 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) 128 { 129 if (line == 2) { 130 u32 reg = nv_rd32(therm, 0x0010f0); 131 if (reg & 0x80000000) { 132 *duty = (reg & 0x7fff0000) >> 16; 133 *divs = (reg & 0x00007fff); 134 return 0; 135 } 136 } else 137 if (line == 9) { 138 u32 reg = nv_rd32(therm, 0x0015f4); 139 if (reg & 0x80000000) { 140 *divs = nv_rd32(therm, 0x0015f8); 141 *duty = (reg & 0x7fffffff); 142 return 0; 143 } 144 } else { 145 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line); 146 return -ENODEV; 147 } 148 149 return -EINVAL; 150 } 151 152 static int 153 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) 154 { 155 if (line == 2) { 156 nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); 157 } else 158 if (line == 9) { 159 nv_wr32(therm, 0x0015f8, divs); 160 nv_mask(therm, 0x0015f4, 0x7fffffff, duty); 161 } else { 162 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line); 163 return -ENODEV; 164 } 165 166 return 0; 167 } 168 169 void 170 nv40_therm_intr(struct nvkm_subdev *subdev) 171 { 172 struct nvkm_therm *therm = nvkm_therm(subdev); 173 uint32_t stat = nv_rd32(therm, 0x1100); 174 175 /* traitement */ 176 177 /* ack all IRQs */ 178 nv_wr32(therm, 0x1100, 0x70000); 179 180 nv_error(therm, "THERM received an IRQ: stat = %x\n", stat); 181 } 182 183 static int 184 nv40_therm_ctor(struct nvkm_object *parent, 185 struct nvkm_object *engine, 186 struct nvkm_oclass *oclass, void *data, u32 size, 187 struct nvkm_object **pobject) 188 { 189 struct nv40_therm_priv *priv; 190 int ret; 191 192 ret = nvkm_therm_create(parent, engine, oclass, &priv); 193 *pobject = nv_object(priv); 194 if (ret) 195 return ret; 196 197 priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl; 198 priv->base.base.pwm_get = nv40_fan_pwm_get; 199 priv->base.base.pwm_set = nv40_fan_pwm_set; 200 priv->base.base.temp_get = nv40_temp_get; 201 priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling; 202 nv_subdev(priv)->intr = nv40_therm_intr; 203 return nvkm_therm_preinit(&priv->base.base); 204 } 205 206 static int 207 nv40_therm_init(struct nvkm_object *object) 208 { 209 struct nvkm_therm *therm = (void *)object; 210 211 nv40_sensor_setup(therm); 212 213 return _nvkm_therm_init(object); 214 } 215 216 struct nvkm_oclass 217 nv40_therm_oclass = { 218 .handle = NV_SUBDEV(THERM, 0x40), 219 .ofuncs = &(struct nvkm_ofuncs) { 220 .ctor = nv40_therm_ctor, 221 .dtor = _nvkm_therm_dtor, 222 .init = nv40_therm_init, 223 .fini = _nvkm_therm_fini, 224 }, 225 }; 226