1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv04.h" 25 26 #include <core/gpuobj.h> 27 28 #define NV04_PDMA_SIZE (128 * 1024 * 1024) 29 #define NV04_PDMA_PAGE ( 4 * 1024) 30 31 /******************************************************************************* 32 * VM map/unmap callbacks 33 ******************************************************************************/ 34 35 static void 36 nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 37 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 38 { 39 pte = 0x00008 + (pte * 4); 40 nvkm_kmap(pgt); 41 while (cnt) { 42 u32 page = PAGE_SIZE / NV04_PDMA_PAGE; 43 u32 phys = (u32)*list++; 44 while (cnt && page--) { 45 nvkm_wo32(pgt, pte, phys | 3); 46 phys += NV04_PDMA_PAGE; 47 pte += 4; 48 cnt -= 1; 49 } 50 } 51 nvkm_done(pgt); 52 } 53 54 static void 55 nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) 56 { 57 pte = 0x00008 + (pte * 4); 58 nvkm_kmap(pgt); 59 while (cnt--) { 60 nvkm_wo32(pgt, pte, 0x00000000); 61 pte += 4; 62 } 63 nvkm_done(pgt); 64 } 65 66 static void 67 nv04_vm_flush(struct nvkm_vm *vm) 68 { 69 } 70 71 /******************************************************************************* 72 * VM object 73 ******************************************************************************/ 74 75 int 76 nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart, 77 struct nvkm_vm **pvm) 78 { 79 return -EINVAL; 80 } 81 82 /******************************************************************************* 83 * MMU subdev 84 ******************************************************************************/ 85 86 static int 87 nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 88 struct nvkm_oclass *oclass, void *data, u32 size, 89 struct nvkm_object **pobject) 90 { 91 struct nv04_mmu *mmu; 92 struct nvkm_gpuobj *dma; 93 int ret; 94 95 ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART", 96 "mmu", &mmu); 97 *pobject = nv_object(mmu); 98 if (ret) 99 return ret; 100 101 mmu->base.create = nv04_vm_create; 102 mmu->base.limit = NV04_PDMA_SIZE; 103 mmu->base.dma_bits = 32; 104 mmu->base.pgt_bits = 32 - 12; 105 mmu->base.spg_shift = 12; 106 mmu->base.lpg_shift = 12; 107 mmu->base.map_sg = nv04_vm_map_sg; 108 mmu->base.unmap = nv04_vm_unmap; 109 mmu->base.flush = nv04_vm_flush; 110 111 ret = nvkm_vm_create(&mmu->base, 0, NV04_PDMA_SIZE, 0, 4096, 112 &mmu->vm); 113 if (ret) 114 return ret; 115 116 ret = nvkm_gpuobj_new(nv_object(mmu), NULL, 117 (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8, 118 16, NVOBJ_FLAG_ZERO_ALLOC, 119 &mmu->vm->pgt[0].obj[0]); 120 dma = mmu->vm->pgt[0].obj[0]; 121 mmu->vm->pgt[0].refcount[0] = 1; 122 if (ret) 123 return ret; 124 125 nvkm_kmap(dma); 126 nvkm_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ 127 nvkm_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1); 128 nvkm_done(dma); 129 return 0; 130 } 131 132 void 133 nv04_mmu_dtor(struct nvkm_object *object) 134 { 135 struct nv04_mmu *mmu = (void *)object; 136 if (mmu->vm) { 137 nvkm_gpuobj_ref(NULL, &mmu->vm->pgt[0].obj[0]); 138 nvkm_vm_ref(NULL, &mmu->vm, NULL); 139 } 140 if (mmu->nullp) { 141 pci_free_consistent(nv_device(mmu)->pdev, 16 * 1024, 142 mmu->nullp, mmu->null); 143 } 144 nvkm_mmu_destroy(&mmu->base); 145 } 146 147 struct nvkm_oclass 148 nv04_mmu_oclass = { 149 .handle = NV_SUBDEV(MMU, 0x04), 150 .ofuncs = &(struct nvkm_ofuncs) { 151 .ctor = nv04_mmu_ctor, 152 .dtor = nv04_mmu_dtor, 153 .init = _nvkm_mmu_init, 154 .fini = _nvkm_mmu_fini, 155 }, 156 }; 157