1 /* 2 * Copyright 2010 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/mmu.h> 25 #include <subdev/bar.h> 26 #include <subdev/fb.h> 27 #include <subdev/ltc.h> 28 #include <subdev/timer.h> 29 30 #include <core/gpuobj.h> 31 32 /* Map from compressed to corresponding uncompressed storage type. 33 * The value 0xff represents an invalid storage type. 34 */ 35 const u8 gf100_pte_storage_type_map[256] = 36 { 37 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ 38 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 39 0xff, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, 0x11, /* 0x10 */ 40 0x11, 0x11, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, 41 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x26, 0x27, /* 0x20 */ 42 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 43 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 */ 44 0xff, 0xff, 0x26, 0x27, 0x28, 0x29, 0x26, 0x27, 45 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0x46, 0xff, /* 0x40 */ 46 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 47 0xff, 0x46, 0x46, 0x46, 0x46, 0xff, 0xff, 0xff, /* 0x50 */ 48 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 49 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x60 */ 50 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 51 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x70 */ 52 0xff, 0xff, 0xff, 0x7b, 0xff, 0xff, 0xff, 0xff, 53 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x7b, /* 0x80 */ 54 0x7b, 0x7b, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xff, 55 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x90 */ 56 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 57 0xff, 0xff, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xa7, /* 0xa0 */ 58 0xa8, 0xa9, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, 59 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */ 60 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, 61 0xa8, 0xa9, 0xaa, 0xc3, 0xff, 0xff, 0xff, 0xff, /* 0xc0 */ 62 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfe, 0xc3, 0xc3, 63 0xc3, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xd0 */ 64 0xfe, 0xff, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 65 0xfe, 0xff, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xff, /* 0xe0 */ 66 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xfe, 0xff, 67 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, /* 0xf0 */ 68 0xfe, 0xfe, 0xfe, 0xfe, 0xff, 0xfd, 0xfe, 0xff 69 }; 70 71 72 static void 73 gf100_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 index, struct nvkm_gpuobj *pgt[2]) 74 { 75 u32 pde[2] = { 0, 0 }; 76 77 if (pgt[0]) 78 pde[1] = 0x00000001 | (pgt[0]->addr >> 8); 79 if (pgt[1]) 80 pde[0] = 0x00000001 | (pgt[1]->addr >> 8); 81 82 nv_wo32(pgd, (index * 8) + 0, pde[0]); 83 nv_wo32(pgd, (index * 8) + 4, pde[1]); 84 } 85 86 static inline u64 87 gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) 88 { 89 phys >>= 8; 90 91 phys |= 0x00000001; /* present */ 92 if (vma->access & NV_MEM_ACCESS_SYS) 93 phys |= 0x00000002; 94 95 phys |= ((u64)target << 32); 96 phys |= ((u64)memtype << 36); 97 return phys; 98 } 99 100 static void 101 gf100_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 102 struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) 103 { 104 u64 next = 1 << (vma->node->type - 8); 105 106 phys = gf100_vm_addr(vma, phys, mem->memtype, 0); 107 pte <<= 3; 108 109 if (mem->tag) { 110 struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu); 111 u32 tag = mem->tag->offset + (delta >> 17); 112 phys |= (u64)tag << (32 + 12); 113 next |= (u64)1 << (32 + 12); 114 ltc->tags_clear(ltc, tag, cnt); 115 } 116 117 while (cnt--) { 118 nv_wo32(pgt, pte + 0, lower_32_bits(phys)); 119 nv_wo32(pgt, pte + 4, upper_32_bits(phys)); 120 phys += next; 121 pte += 8; 122 } 123 } 124 125 static void 126 gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, 127 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 128 { 129 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; 130 /* compressed storage types are invalid for system memory */ 131 u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff]; 132 133 pte <<= 3; 134 while (cnt--) { 135 u64 phys = gf100_vm_addr(vma, *list++, memtype, target); 136 nv_wo32(pgt, pte + 0, lower_32_bits(phys)); 137 nv_wo32(pgt, pte + 4, upper_32_bits(phys)); 138 pte += 8; 139 } 140 } 141 142 static void 143 gf100_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) 144 { 145 pte <<= 3; 146 while (cnt--) { 147 nv_wo32(pgt, pte + 0, 0x00000000); 148 nv_wo32(pgt, pte + 4, 0x00000000); 149 pte += 8; 150 } 151 } 152 153 static void 154 gf100_vm_flush(struct nvkm_vm *vm) 155 { 156 struct nvkm_mmu *mmu = (void *)vm->mmu; 157 struct nvkm_bar *bar = nvkm_bar(mmu); 158 struct nvkm_vm_pgd *vpgd; 159 u32 type; 160 161 bar->flush(bar); 162 163 type = 0x00000001; /* PAGE_ALL */ 164 if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR])) 165 type |= 0x00000004; /* HUB_ONLY */ 166 167 mutex_lock(&nv_subdev(mmu)->mutex); 168 list_for_each_entry(vpgd, &vm->pgd_list, head) { 169 /* looks like maybe a "free flush slots" counter, the 170 * faster you write to 0x100cbc to more it decreases 171 */ 172 if (!nv_wait_ne(mmu, 0x100c80, 0x00ff0000, 0x00000000)) { 173 nv_error(mmu, "vm timeout 0: 0x%08x %d\n", 174 nv_rd32(mmu, 0x100c80), type); 175 } 176 177 nv_wr32(mmu, 0x100cb8, vpgd->obj->addr >> 8); 178 nv_wr32(mmu, 0x100cbc, 0x80000000 | type); 179 180 /* wait for flush to be queued? */ 181 if (!nv_wait(mmu, 0x100c80, 0x00008000, 0x00008000)) { 182 nv_error(mmu, "vm timeout 1: 0x%08x %d\n", 183 nv_rd32(mmu, 0x100c80), type); 184 } 185 } 186 mutex_unlock(&nv_subdev(mmu)->mutex); 187 } 188 189 static int 190 gf100_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset, 191 struct nvkm_vm **pvm) 192 { 193 return nvkm_vm_create(mmu, offset, length, mm_offset, 4096, pvm); 194 } 195 196 static int 197 gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 198 struct nvkm_oclass *oclass, void *data, u32 size, 199 struct nvkm_object **pobject) 200 { 201 struct nvkm_mmu *mmu; 202 int ret; 203 204 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "mmu", &mmu); 205 *pobject = nv_object(mmu); 206 if (ret) 207 return ret; 208 209 mmu->limit = 1ULL << 40; 210 mmu->dma_bits = 40; 211 mmu->pgt_bits = 27 - 12; 212 mmu->spg_shift = 12; 213 mmu->lpg_shift = 17; 214 mmu->create = gf100_vm_create; 215 mmu->map_pgt = gf100_vm_map_pgt; 216 mmu->map = gf100_vm_map; 217 mmu->map_sg = gf100_vm_map_sg; 218 mmu->unmap = gf100_vm_unmap; 219 mmu->flush = gf100_vm_flush; 220 return 0; 221 } 222 223 struct nvkm_oclass 224 gf100_mmu_oclass = { 225 .handle = NV_SUBDEV(MMU, 0xc0), 226 .ofuncs = &(struct nvkm_ofuncs) { 227 .ctor = gf100_mmu_ctor, 228 .dtor = _nvkm_mmu_dtor, 229 .init = _nvkm_mmu_init, 230 .fini = _nvkm_mmu_fini, 231 }, 232 }; 233