xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 
26 const struct nvkm_mc_intr
27 nv04_mc_intr[] = {
28 	{ 0x00000001, NVKM_ENGINE_MPEG },	/* NV17- MPEG/ME */
29 	{ 0x00000100, NVKM_ENGINE_FIFO },
30 	{ 0x00001000, NVKM_ENGINE_GR },
31 	{ 0x00010000, NVKM_ENGINE_DISP },
32 	{ 0x00020000, NVKM_ENGINE_VP },	/* NV40- */
33 	{ 0x00100000, NVKM_SUBDEV_TIMER },
34 	{ 0x01000000, NVKM_ENGINE_DISP },	/* NV04- PCRTC0 */
35 	{ 0x02000000, NVKM_ENGINE_DISP },	/* NV11- PCRTC1 */
36 	{ 0x10000000, NVKM_SUBDEV_BUS },
37 	{ 0x80000000, NVKM_ENGINE_SW },
38 	{}
39 };
40 
41 void
42 nv04_mc_intr_unarm(struct nvkm_mc *mc)
43 {
44 	struct nvkm_device *device = mc->subdev.device;
45 	nvkm_wr32(device, 0x000140, 0x00000000);
46 	nvkm_rd32(device, 0x000140);
47 }
48 
49 void
50 nv04_mc_intr_rearm(struct nvkm_mc *mc)
51 {
52 	struct nvkm_device *device = mc->subdev.device;
53 	nvkm_wr32(device, 0x000140, 0x00000001);
54 }
55 
56 u32
57 nv04_mc_intr_mask(struct nvkm_mc *mc)
58 {
59 	return nvkm_rd32(mc->subdev.device, 0x000100);
60 }
61 
62 void
63 nv04_mc_init(struct nvkm_mc *mc)
64 {
65 	struct nvkm_device *device = mc->subdev.device;
66 	nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */
67 	nvkm_wr32(device, 0x001850, 0x00000001); /* disable rom access */
68 }
69 
70 static const struct nvkm_mc_func
71 nv04_mc = {
72 	.init = nv04_mc_init,
73 	.intr = nv04_mc_intr,
74 	.intr_unarm = nv04_mc_intr_unarm,
75 	.intr_rearm = nv04_mc_intr_rearm,
76 	.intr_mask = nv04_mc_intr_mask,
77 };
78 
79 int
80 nv04_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
81 {
82 	return nvkm_mc_new_(&nv04_mc, device, index, pmc);
83 }
84