xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c (revision ebb195dbb3390324100cb85c22129f6334064b5f)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include "priv.h"
25 
26 static const struct nvkm_mc_map
27 g98_mc_reset[] = {
28 	{ 0x04008000, NVKM_ENGINE_MSVLD },
29 	{ 0x02004000, NVKM_ENGINE_SEC },
30 	{ 0x01020000, NVKM_ENGINE_MSPDEC },
31 	{ 0x00400002, NVKM_ENGINE_MSPPP },
32 	{ 0x00201000, NVKM_ENGINE_GR },
33 	{ 0x00000100, NVKM_ENGINE_FIFO },
34 	{}
35 };
36 
37 static const struct nvkm_intr_data
38 g98_mc_intrs[] = {
39 	{ NVKM_ENGINE_DISP  , 0, 0, 0x04000000, true },
40 	{ NVKM_ENGINE_MSPDEC, 0, 0, 0x00020000, true },
41 	{ NVKM_ENGINE_MSVLD , 0, 0, 0x00008000, true },
42 	{ NVKM_ENGINE_SEC   , 0, 0, 0x00004000, true },
43 	{ NVKM_ENGINE_GR    , 0, 0, 0x00001000, true },
44 	{ NVKM_ENGINE_FIFO  , 0, 0, 0x00000100, true },
45 	{ NVKM_ENGINE_MSPPP , 0, 0, 0x00000001, true },
46 	{ NVKM_SUBDEV_FB    , 0, 0, 0x0002d101, true },
47 	{ NVKM_SUBDEV_BUS   , 0, 0, 0x10000000, true },
48 	{ NVKM_SUBDEV_GPIO  , 0, 0, 0x00200000, true },
49 	{ NVKM_SUBDEV_I2C   , 0, 0, 0x00200000, true },
50 	{ NVKM_SUBDEV_TIMER , 0, 0, 0x00100000, true },
51 	{},
52 };
53 
54 static const struct nvkm_mc_func
55 g98_mc = {
56 	.init = nv50_mc_init,
57 	.intr = &nv04_mc_intr,
58 	.intrs = g98_mc_intrs,
59 	.device = &nv04_mc_device,
60 	.reset = g98_mc_reset,
61 };
62 
63 int
64 g98_mc_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_mc **pmc)
65 {
66 	return nvkm_mc_new_(&g98_mc, device, type, inst, pmc);
67 }
68