1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "priv.h" 25 26 #include <core/enum.h> 27 #include <subdev/fb.h> 28 #include <subdev/timer.h> 29 30 void 31 gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) 32 { 33 nv_wr32(priv, 0x17e8cc, start); 34 nv_wr32(priv, 0x17e8d0, limit); 35 nv_wr32(priv, 0x17e8c8, 0x00000004); 36 } 37 38 void 39 gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv) 40 { 41 int c, s; 42 for (c = 0; c < priv->ltc_nr; c++) { 43 for (s = 0; s < priv->lts_nr; s++) 44 nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0); 45 } 46 } 47 48 void 49 gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4]) 50 { 51 nv_mask(priv, 0x17ea44, 0x0000000f, i); 52 nv_wr32(priv, 0x17ea48, color[0]); 53 nv_wr32(priv, 0x17ea4c, color[1]); 54 nv_wr32(priv, 0x17ea50, color[2]); 55 nv_wr32(priv, 0x17ea54, color[3]); 56 } 57 58 void 59 gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) 60 { 61 nv_mask(priv, 0x17ea44, 0x0000000f, i); 62 nv_wr32(priv, 0x17ea58, depth); 63 } 64 65 static const struct nvkm_bitfield 66 gf100_ltc_lts_intr_name[] = { 67 { 0x00000001, "IDLE_ERROR_IQ" }, 68 { 0x00000002, "IDLE_ERROR_CBC" }, 69 { 0x00000004, "IDLE_ERROR_TSTG" }, 70 { 0x00000008, "IDLE_ERROR_DSTG" }, 71 { 0x00000010, "EVICTED_CB" }, 72 { 0x00000020, "ILLEGAL_COMPSTAT" }, 73 { 0x00000040, "BLOCKLINEAR_CB" }, 74 { 0x00000100, "ECC_SEC_ERROR" }, 75 { 0x00000200, "ECC_DED_ERROR" }, 76 { 0x00000400, "DEBUG" }, 77 { 0x00000800, "ATOMIC_TO_Z" }, 78 { 0x00001000, "ILLEGAL_ATOMIC" }, 79 { 0x00002000, "BLKACTIVITY_ERR" }, 80 {} 81 }; 82 83 static void 84 gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts) 85 { 86 u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400); 87 u32 intr = nv_rd32(priv, base + 0x020); 88 u32 stat = intr & 0x0000ffff; 89 90 if (stat) { 91 nv_info(priv, "LTC%d_LTS%d:", ltc, lts); 92 nvkm_bitfield_print(gf100_ltc_lts_intr_name, stat); 93 pr_cont("\n"); 94 } 95 96 nv_wr32(priv, base + 0x020, intr); 97 } 98 99 void 100 gf100_ltc_intr(struct nvkm_subdev *subdev) 101 { 102 struct nvkm_ltc_priv *priv = (void *)subdev; 103 u32 mask; 104 105 mask = nv_rd32(priv, 0x00017c); 106 while (mask) { 107 u32 lts, ltc = __ffs(mask); 108 for (lts = 0; lts < priv->lts_nr; lts++) 109 gf100_ltc_lts_intr(priv, ltc, lts); 110 mask &= ~(1 << ltc); 111 } 112 } 113 114 static int 115 gf100_ltc_init(struct nvkm_object *object) 116 { 117 struct nvkm_ltc_priv *priv = (void *)object; 118 u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); 119 int ret; 120 121 ret = nvkm_ltc_init(priv); 122 if (ret) 123 return ret; 124 125 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ 126 nv_wr32(priv, 0x17e8d8, priv->ltc_nr); 127 nv_wr32(priv, 0x17e8d4, priv->tag_base); 128 nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); 129 return 0; 130 } 131 132 void 133 gf100_ltc_dtor(struct nvkm_object *object) 134 { 135 struct nvkm_fb *pfb = nvkm_fb(object); 136 struct nvkm_ltc_priv *priv = (void *)object; 137 138 nvkm_mm_fini(&priv->tags); 139 nvkm_mm_free(&pfb->vram, &priv->tag_ram); 140 141 nvkm_ltc_destroy(priv); 142 } 143 144 /* TODO: Figure out tag memory details and drop the over-cautious allocation. 145 */ 146 int 147 gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv) 148 { 149 u32 tag_size, tag_margin, tag_align; 150 int ret; 151 152 /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ 153 priv->num_tags = (pfb->ram->size >> 17) / 4; 154 if (priv->num_tags > (1 << 17)) 155 priv->num_tags = 1 << 17; /* we have 17 bits in PTE */ 156 priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */ 157 158 tag_align = priv->ltc_nr * 0x800; 159 tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align; 160 161 /* 4 part 4 sub: 0x2000 bytes for 56 tags */ 162 /* 3 part 4 sub: 0x6000 bytes for 168 tags */ 163 /* 164 * About 147 bytes per tag. Let's be safe and allocate x2, which makes 165 * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags. 166 * 167 * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %. 168 */ 169 tag_size = (priv->num_tags / 64) * 0x6000 + tag_margin; 170 tag_size += tag_align; 171 tag_size = (tag_size + 0xfff) >> 12; /* round up */ 172 173 ret = nvkm_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, 174 &priv->tag_ram); 175 if (ret) { 176 priv->num_tags = 0; 177 } else { 178 u64 tag_base = ((u64)priv->tag_ram->offset << 12) + tag_margin; 179 180 tag_base += tag_align - 1; 181 ret = do_div(tag_base, tag_align); 182 183 priv->tag_base = tag_base; 184 } 185 186 ret = nvkm_mm_init(&priv->tags, 0, priv->num_tags, 1); 187 return ret; 188 } 189 190 int 191 gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 192 struct nvkm_oclass *oclass, void *data, u32 size, 193 struct nvkm_object **pobject) 194 { 195 struct nvkm_fb *pfb = nvkm_fb(parent); 196 struct nvkm_ltc_priv *priv; 197 u32 parts, mask; 198 int ret, i; 199 200 ret = nvkm_ltc_create(parent, engine, oclass, &priv); 201 *pobject = nv_object(priv); 202 if (ret) 203 return ret; 204 205 parts = nv_rd32(priv, 0x022438); 206 mask = nv_rd32(priv, 0x022554); 207 for (i = 0; i < parts; i++) { 208 if (!(mask & (1 << i))) 209 priv->ltc_nr++; 210 } 211 priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28; 212 213 ret = gf100_ltc_init_tag_ram(pfb, priv); 214 if (ret) 215 return ret; 216 217 nv_subdev(priv)->intr = gf100_ltc_intr; 218 return 0; 219 } 220 221 struct nvkm_oclass * 222 gf100_ltc_oclass = &(struct nvkm_ltc_impl) { 223 .base.handle = NV_SUBDEV(LTC, 0xc0), 224 .base.ofuncs = &(struct nvkm_ofuncs) { 225 .ctor = gf100_ltc_ctor, 226 .dtor = gf100_ltc_dtor, 227 .init = gf100_ltc_init, 228 .fini = _nvkm_ltc_fini, 229 }, 230 .intr = gf100_ltc_intr, 231 .cbc_clear = gf100_ltc_cbc_clear, 232 .cbc_wait = gf100_ltc_cbc_wait, 233 .zbc = 16, 234 .zbc_clear_color = gf100_ltc_zbc_clear_color, 235 .zbc_clear_depth = gf100_ltc_zbc_clear_depth, 236 }.base; 237