1*44f93b20SBen Skeggs /* SPDX-License-Identifier: MIT 2*44f93b20SBen Skeggs * 3*44f93b20SBen Skeggs * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4*44f93b20SBen Skeggs */ 5*44f93b20SBen Skeggs #include "priv.h" 6*44f93b20SBen Skeggs 7*44f93b20SBen Skeggs #include <nvhw/ref/gh100/pri_nv_xal_ep.h> 8*44f93b20SBen Skeggs 9*44f93b20SBen Skeggs static void 10*44f93b20SBen Skeggs gh100_instmem_set_bar0_window_addr(struct nvkm_device *device, u64 addr) 11*44f93b20SBen Skeggs { 12*44f93b20SBen Skeggs nvkm_wr32(device, NV_XAL_EP_BAR0_WINDOW, addr >> NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT); 13*44f93b20SBen Skeggs } 14*44f93b20SBen Skeggs 15*44f93b20SBen Skeggs static const struct nvkm_instmem_func 16*44f93b20SBen Skeggs gh100_instmem = { 17*44f93b20SBen Skeggs .fini = nv50_instmem_fini, 18*44f93b20SBen Skeggs .memory_new = nv50_instobj_new, 19*44f93b20SBen Skeggs .memory_wrap = nv50_instobj_wrap, 20*44f93b20SBen Skeggs .set_bar0_window_addr = gh100_instmem_set_bar0_window_addr, 21*44f93b20SBen Skeggs }; 22*44f93b20SBen Skeggs 23*44f93b20SBen Skeggs int 24*44f93b20SBen Skeggs gh100_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 25*44f93b20SBen Skeggs struct nvkm_instmem **pimem) 26*44f93b20SBen Skeggs { 27*44f93b20SBen Skeggs return r535_instmem_new(&gh100_instmem, device, type, inst, pimem); 28*44f93b20SBen Skeggs } 29