1 /* 2 * Copyright 2022 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 24 #include <subdev/fb.h> 25 #include <engine/sec2.h> 26 27 #include <rm/r535/nvrm/gsp.h> 28 29 #include <nvfw/flcn.h> 30 #include <nvfw/fw.h> 31 #include <nvfw/hs.h> 32 33 int 34 tu102_gsp_fwsec_sb_ctor(struct nvkm_gsp *gsp) 35 { 36 return nvkm_gsp_fwsec_sb_init(gsp); 37 } 38 39 void 40 tu102_gsp_fwsec_sb_dtor(struct nvkm_gsp *gsp) 41 { 42 nvkm_falcon_fw_dtor(&gsp->fws.falcon.sb); 43 } 44 45 static int 46 tu102_gsp_booter_unload(struct nvkm_gsp *gsp, u32 mbox0, u32 mbox1) 47 { 48 struct nvkm_subdev *subdev = &gsp->subdev; 49 struct nvkm_device *device = subdev->device; 50 u32 wpr2_hi; 51 int ret; 52 53 wpr2_hi = nvkm_rd32(device, 0x1fa828); 54 if (!wpr2_hi) { 55 nvkm_debug(subdev, "WPR2 not set - skipping booter unload\n"); 56 return 0; 57 } 58 59 ret = nvkm_falcon_fw_boot(&gsp->booter.unload, &gsp->subdev, true, &mbox0, &mbox1, 0, 0); 60 if (WARN_ON(ret)) 61 return ret; 62 63 wpr2_hi = nvkm_rd32(device, 0x1fa828); 64 if (WARN_ON(wpr2_hi)) 65 return -EIO; 66 67 return 0; 68 } 69 70 static int 71 tu102_gsp_booter_load(struct nvkm_gsp *gsp, u32 mbox0, u32 mbox1) 72 { 73 return nvkm_falcon_fw_boot(&gsp->booter.load, &gsp->subdev, true, &mbox0, &mbox1, 0, 0); 74 } 75 76 int 77 tu102_gsp_booter_ctor(struct nvkm_gsp *gsp, const char *name, const struct firmware *blob, 78 struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw) 79 { 80 struct nvkm_subdev *subdev = &gsp->subdev; 81 const struct nvkm_falcon_fw_func *func = &gm200_flcn_fw; 82 const struct nvfw_bin_hdr *hdr; 83 const struct nvfw_hs_header_v2 *hshdr; 84 const struct nvfw_hs_load_header_v2 *lhdr; 85 u32 loc, sig, cnt; 86 int ret; 87 88 hdr = nvfw_bin_hdr(subdev, blob->data); 89 hshdr = nvfw_hs_header_v2(subdev, blob->data + hdr->header_offset); 90 loc = *(u32 *)(blob->data + hshdr->patch_loc); 91 sig = *(u32 *)(blob->data + hshdr->patch_sig); 92 cnt = *(u32 *)(blob->data + hshdr->num_sig); 93 94 ret = nvkm_falcon_fw_ctor(func, name, subdev->device, true, 95 blob->data + hdr->data_offset, hdr->data_size, falcon, fw); 96 if (ret) 97 goto done; 98 99 ret = nvkm_falcon_fw_sign(fw, loc, hshdr->sig_prod_size / cnt, blob->data, 100 cnt, hshdr->sig_prod_offset + sig, 0, 0); 101 if (ret) 102 goto done; 103 104 lhdr = nvfw_hs_load_header_v2(subdev, blob->data + hshdr->header_offset); 105 106 fw->nmem_base_img = 0; 107 fw->nmem_base = lhdr->os_code_offset; 108 fw->nmem_size = lhdr->os_code_size; 109 fw->imem_base_img = fw->nmem_size; 110 fw->imem_base = lhdr->app[0].offset; 111 fw->imem_size = lhdr->app[0].size; 112 fw->dmem_base_img = lhdr->os_data_offset; 113 fw->dmem_base = 0; 114 fw->dmem_size = lhdr->os_data_size; 115 fw->dmem_sign = loc - fw->dmem_base_img; 116 fw->boot_addr = lhdr->os_code_offset; 117 118 done: 119 if (ret) 120 nvkm_falcon_fw_dtor(fw); 121 122 return ret; 123 } 124 125 static int 126 tu102_gsp_fwsec_load_bld(struct nvkm_falcon_fw *fw) 127 { 128 struct flcn_bl_dmem_desc_v2 desc = { 129 .ctx_dma = FALCON_DMAIDX_PHYS_SYS_NCOH, 130 .code_dma_base = fw->fw.phys, 131 .non_sec_code_off = fw->nmem_base, 132 .non_sec_code_size = fw->nmem_size, 133 .sec_code_off = fw->imem_base, 134 .sec_code_size = fw->imem_size, 135 .code_entry_point = 0, 136 .data_dma_base = fw->fw.phys + fw->dmem_base_img, 137 .data_size = fw->dmem_size, 138 .argc = 0, 139 .argv = 0, 140 }; 141 142 flcn_bl_dmem_desc_v2_dump(fw->falcon->user, &desc); 143 144 nvkm_falcon_mask(fw->falcon, 0x600 + desc.ctx_dma * 4, 0x00000007, 0x00000005); 145 146 return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&desc, 0, 0, DMEM, 0, sizeof(desc), 0, 0); 147 } 148 149 const struct nvkm_falcon_fw_func 150 tu102_gsp_fwsec = { 151 .reset = gm200_flcn_fw_reset, 152 .load = gm200_flcn_fw_load, 153 .load_bld = tu102_gsp_fwsec_load_bld, 154 .boot = gm200_flcn_fw_boot, 155 }; 156 157 int 158 tu102_gsp_reset(struct nvkm_gsp *gsp) 159 { 160 return gsp->falcon.func->reset_eng(&gsp->falcon); 161 } 162 163 int 164 tu102_gsp_fini(struct nvkm_gsp *gsp, enum nvkm_suspend_state suspend) 165 { 166 u32 mbox0 = 0xff, mbox1 = 0xff; 167 int ret; 168 169 ret = r535_gsp_fini(gsp, suspend); 170 if (ret && suspend) 171 return ret; 172 173 nvkm_falcon_reset(&gsp->falcon); 174 175 ret = nvkm_gsp_fwsec_sb(gsp); 176 WARN_ON(ret); 177 178 if (suspend) { 179 mbox0 = lower_32_bits(gsp->sr.meta.addr); 180 mbox1 = upper_32_bits(gsp->sr.meta.addr); 181 } 182 183 ret = tu102_gsp_booter_unload(gsp, mbox0, mbox1); 184 WARN_ON(ret); 185 return 0; 186 } 187 188 int 189 tu102_gsp_init(struct nvkm_gsp *gsp) 190 { 191 u32 mbox0, mbox1; 192 int ret; 193 194 if (!gsp->sr.meta.data) { 195 mbox0 = lower_32_bits(gsp->wpr_meta.addr); 196 mbox1 = upper_32_bits(gsp->wpr_meta.addr); 197 } else { 198 gsp->rm->api->gsp->set_rmargs(gsp, true); 199 200 mbox0 = lower_32_bits(gsp->sr.meta.addr); 201 mbox1 = upper_32_bits(gsp->sr.meta.addr); 202 } 203 204 /* Execute booter to handle (eventually...) booting GSP-RM. */ 205 ret = tu102_gsp_booter_load(gsp, mbox0, mbox1); 206 if (WARN_ON(ret)) 207 return ret; 208 209 return r535_gsp_init(gsp); 210 } 211 212 static int 213 tu102_gsp_wpr_meta_init(struct nvkm_gsp *gsp) 214 { 215 GspFwWprMeta *meta; 216 int ret; 217 218 ret = nvkm_gsp_mem_ctor(gsp, sizeof(*meta), &gsp->wpr_meta); 219 if (ret) 220 return ret; 221 222 meta = gsp->wpr_meta.data; 223 224 meta->magic = GSP_FW_WPR_META_MAGIC; 225 meta->revision = GSP_FW_WPR_META_REVISION; 226 227 meta->sysmemAddrOfRadix3Elf = gsp->radix3.lvl0.addr; 228 meta->sizeOfRadix3Elf = gsp->fb.wpr2.elf.size; 229 230 meta->sysmemAddrOfBootloader = gsp->boot.fw.addr; 231 meta->sizeOfBootloader = gsp->boot.fw.size; 232 meta->bootloaderCodeOffset = gsp->boot.code_offset; 233 meta->bootloaderDataOffset = gsp->boot.data_offset; 234 meta->bootloaderManifestOffset = gsp->boot.manifest_offset; 235 236 meta->sysmemAddrOfSignature = gsp->sig.addr; 237 meta->sizeOfSignature = gsp->sig.size; 238 239 meta->gspFwRsvdStart = gsp->fb.heap.addr; 240 meta->nonWprHeapOffset = gsp->fb.heap.addr; 241 meta->nonWprHeapSize = gsp->fb.heap.size; 242 meta->gspFwWprStart = gsp->fb.wpr2.addr; 243 meta->gspFwHeapOffset = gsp->fb.wpr2.heap.addr; 244 meta->gspFwHeapSize = gsp->fb.wpr2.heap.size; 245 meta->gspFwOffset = gsp->fb.wpr2.elf.addr; 246 meta->bootBinOffset = gsp->fb.wpr2.boot.addr; 247 meta->frtsOffset = gsp->fb.wpr2.frts.addr; 248 meta->frtsSize = gsp->fb.wpr2.frts.size; 249 meta->gspFwWprEnd = ALIGN_DOWN(gsp->fb.bios.vga_workspace.addr, 0x20000); 250 meta->fbSize = gsp->fb.size; 251 meta->vgaWorkspaceOffset = gsp->fb.bios.vga_workspace.addr; 252 meta->vgaWorkspaceSize = gsp->fb.bios.vga_workspace.size; 253 meta->bootCount = 0; 254 meta->partitionRpcAddr = 0; 255 meta->partitionRpcRequestOffset = 0; 256 meta->partitionRpcReplyOffset = 0; 257 meta->verified = 0; 258 return 0; 259 } 260 261 u64 262 tu102_gsp_wpr_heap_size(struct nvkm_gsp *gsp) 263 { 264 u32 fb_size_gb = DIV_ROUND_UP_ULL(gsp->fb.size, 1 << 30); 265 u64 heap_size; 266 267 heap_size = gsp->rm->wpr->os_carveout_size + 268 gsp->rm->wpr->base_size + 269 ALIGN(GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB * fb_size_gb, 1 << 20) + 270 ALIGN(GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE, 1 << 20); 271 272 return max(heap_size, gsp->rm->wpr->heap_size_min); 273 } 274 275 static u64 276 tu102_gsp_vga_workspace_addr(struct nvkm_gsp *gsp, u64 fb_size) 277 { 278 struct nvkm_device *device = gsp->subdev.device; 279 const u64 base = fb_size - 0x100000; 280 u64 addr = 0; 281 282 if (device->disp) 283 addr = nvkm_rd32(gsp->subdev.device, 0x625f04); 284 if (!(addr & 0x00000008)) 285 return base; 286 287 addr = (addr & 0xffffff00) << 8; 288 if (addr < base) 289 return fb_size - 0x20000; 290 291 return addr; 292 } 293 294 int 295 tu102_gsp_oneinit(struct nvkm_gsp *gsp) 296 { 297 struct nvkm_device *device = gsp->subdev.device; 298 int ret; 299 300 gsp->fb.size = nvkm_fb_vidmem_size(device); 301 302 gsp->fb.bios.vga_workspace.addr = tu102_gsp_vga_workspace_addr(gsp, gsp->fb.size); 303 gsp->fb.bios.vga_workspace.size = gsp->fb.size - gsp->fb.bios.vga_workspace.addr; 304 gsp->fb.bios.addr = gsp->fb.bios.vga_workspace.addr; 305 gsp->fb.bios.size = gsp->fb.bios.vga_workspace.size; 306 307 ret = gsp->func->booter.ctor(gsp, "booter-load", gsp->fws.booter.load, 308 &device->sec2->falcon, &gsp->booter.load); 309 if (ret) 310 return ret; 311 312 ret = gsp->func->booter.ctor(gsp, "booter-unload", gsp->fws.booter.unload, 313 &device->sec2->falcon, &gsp->booter.unload); 314 if (ret) 315 return ret; 316 317 ret = r535_gsp_oneinit(gsp); 318 if (ret) 319 return ret; 320 321 /* Calculate FB layout. */ 322 gsp->fb.wpr2.frts.size = 0x100000; 323 gsp->fb.wpr2.frts.addr = ALIGN_DOWN(gsp->fb.bios.addr, 0x20000) - gsp->fb.wpr2.frts.size; 324 325 gsp->fb.wpr2.boot.size = gsp->boot.fw.size; 326 gsp->fb.wpr2.boot.addr = ALIGN_DOWN(gsp->fb.wpr2.frts.addr - gsp->fb.wpr2.boot.size, 0x1000); 327 328 gsp->fb.wpr2.elf.size = gsp->fw.len; 329 gsp->fb.wpr2.elf.addr = ALIGN_DOWN(gsp->fb.wpr2.boot.addr - gsp->fb.wpr2.elf.size, 0x10000); 330 331 gsp->fb.wpr2.heap.size = tu102_gsp_wpr_heap_size(gsp); 332 333 gsp->fb.wpr2.heap.addr = ALIGN_DOWN(gsp->fb.wpr2.elf.addr - gsp->fb.wpr2.heap.size, 0x100000); 334 gsp->fb.wpr2.heap.size = ALIGN_DOWN(gsp->fb.wpr2.elf.addr - gsp->fb.wpr2.heap.addr, 0x100000); 335 336 gsp->fb.wpr2.addr = ALIGN_DOWN(gsp->fb.wpr2.heap.addr - sizeof(GspFwWprMeta), 0x100000); 337 gsp->fb.wpr2.size = gsp->fb.wpr2.frts.addr + gsp->fb.wpr2.frts.size - gsp->fb.wpr2.addr; 338 339 gsp->fb.heap.size = 0x100000; 340 gsp->fb.heap.addr = gsp->fb.wpr2.addr - gsp->fb.heap.size; 341 342 ret = tu102_gsp_wpr_meta_init(gsp); 343 if (ret) 344 return ret; 345 346 ret = nvkm_gsp_fwsec_frts(gsp); 347 if (WARN_ON(ret)) 348 return ret; 349 350 /* Reset GSP into RISC-V mode. */ 351 ret = gsp->func->reset(gsp); 352 if (ret) 353 return ret; 354 355 nvkm_falcon_wr32(&gsp->falcon, 0x040, lower_32_bits(gsp->libos.addr)); 356 nvkm_falcon_wr32(&gsp->falcon, 0x044, upper_32_bits(gsp->libos.addr)); 357 return 0; 358 } 359 360 const struct nvkm_falcon_func 361 tu102_gsp_flcn = { 362 .disable = gm200_flcn_disable, 363 .enable = gm200_flcn_enable, 364 .addr2 = 0x1000, 365 .riscv_irqmask = 0x2b4, 366 .reset_eng = gp102_flcn_reset_eng, 367 .reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing, 368 .bind_inst = gm200_flcn_bind_inst, 369 .bind_stat = gm200_flcn_bind_stat, 370 .bind_intr = true, 371 .imem_pio = &gm200_flcn_imem_pio, 372 .dmem_pio = &gm200_flcn_dmem_pio, 373 .riscv_active = tu102_flcn_riscv_active, 374 }; 375 376 static const struct nvkm_gsp_func 377 tu102_gsp = { 378 .flcn = &tu102_gsp_flcn, 379 .fwsec = &tu102_gsp_fwsec, 380 381 .sig_section = ".fwsignature_tu10x", 382 383 .booter.ctor = tu102_gsp_booter_ctor, 384 385 .fwsec_sb.ctor = tu102_gsp_fwsec_sb_ctor, 386 .fwsec_sb.dtor = tu102_gsp_fwsec_sb_dtor, 387 388 .dtor = r535_gsp_dtor, 389 .oneinit = tu102_gsp_oneinit, 390 .init = tu102_gsp_init, 391 .fini = tu102_gsp_fini, 392 .reset = tu102_gsp_reset, 393 394 .rm.gpu = &tu1xx_gpu, 395 }; 396 397 int 398 tu102_gsp_load_rm(struct nvkm_gsp *gsp, const struct nvkm_gsp_fwif *fwif) 399 { 400 struct nvkm_subdev *subdev = &gsp->subdev; 401 int ret; 402 403 if (!nvkm_boolopt(subdev->device->cfgopt, "NvGspRm", true)) 404 return -EINVAL; 405 406 ret = nvkm_gsp_load_fw(gsp, "gsp", fwif->ver, &gsp->fws.rm); 407 if (ret) 408 return ret; 409 410 ret = nvkm_gsp_load_fw(gsp, "bootloader", fwif->ver, &gsp->fws.bl); 411 if (ret) 412 return ret; 413 414 return 0; 415 } 416 417 int 418 tu102_gsp_load(struct nvkm_gsp *gsp, int ver, const struct nvkm_gsp_fwif *fwif) 419 { 420 int ret; 421 422 ret = tu102_gsp_load_rm(gsp, fwif); 423 if (ret) 424 goto done; 425 426 ret = nvkm_gsp_load_fw(gsp, "booter_load", fwif->ver, &gsp->fws.booter.load); 427 if (ret) 428 goto done; 429 430 ret = nvkm_gsp_load_fw(gsp, "booter_unload", fwif->ver, &gsp->fws.booter.unload); 431 432 done: 433 if (ret) 434 nvkm_gsp_dtor_fws(gsp); 435 436 return ret; 437 } 438 439 static struct nvkm_gsp_fwif 440 tu102_gsps[] = { 441 { 1, tu102_gsp_load, &tu102_gsp, &r570_rm_tu102, "570.144" }, 442 { 0, tu102_gsp_load, &tu102_gsp, &r535_rm_tu102, "535.113.01" }, 443 { -1, gv100_gsp_nofw, &gv100_gsp }, 444 {} 445 }; 446 447 int 448 tu102_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 449 struct nvkm_gsp **pgsp) 450 { 451 return nvkm_gsp_new_(tu102_gsps, device, type, inst, pgsp); 452 } 453 454 NVKM_GSP_FIRMWARE_BOOTER(tu102, 535.113.01); 455 NVKM_GSP_FIRMWARE_BOOTER(tu104, 535.113.01); 456 NVKM_GSP_FIRMWARE_BOOTER(tu106, 535.113.01); 457 458 NVKM_GSP_FIRMWARE_BOOTER(tu102, 570.144); 459 NVKM_GSP_FIRMWARE_BOOTER(tu104, 570.144); 460 NVKM_GSP_FIRMWARE_BOOTER(tu106, 570.144); 461