1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #include "gr.h" 6 7 #include <engine/fifo.h> 8 #include <engine/gr/priv.h> 9 10 static int 11 nvkm_rm_gr_obj_ctor(const struct nvkm_oclass *oclass, void *argv, u32 argc, 12 struct nvkm_object **pobject) 13 { 14 struct r535_gr_chan *chan = container_of(oclass->parent, typeof(*chan), object); 15 16 return nvkm_rm_engine_obj_new(&chan->chan->rm.object, chan->chan->id, oclass, pobject); 17 } 18 19 static int 20 nvkm_rm_gr_fini(struct nvkm_gr *base, bool suspend) 21 { 22 struct nvkm_rm *rm = base->engine.subdev.device->gsp->rm; 23 struct r535_gr *gr = container_of(base, typeof(*gr), base); 24 25 if (rm->api->gr->scrubber.fini) 26 rm->api->gr->scrubber.fini(gr); 27 28 return 0; 29 } 30 31 static int 32 nvkm_rm_gr_init(struct nvkm_gr *base) 33 { 34 struct nvkm_rm *rm = base->engine.subdev.device->gsp->rm; 35 struct r535_gr *gr = container_of(base, typeof(*gr), base); 36 int ret; 37 38 if (rm->api->gr->scrubber.init) { 39 ret = rm->api->gr->scrubber.init(gr); 40 if (ret) 41 return ret; 42 } 43 44 return 0; 45 } 46 47 int 48 nvkm_rm_gr_new(struct nvkm_rm *rm) 49 { 50 const u32 classes[] = { 51 rm->gpu->gr.class.i2m, 52 rm->gpu->gr.class.twod, 53 rm->gpu->gr.class.threed, 54 rm->gpu->gr.class.compute, 55 }; 56 struct nvkm_gr_func *func; 57 struct r535_gr *gr; 58 59 func = kzalloc(struct_size(func, sclass, ARRAY_SIZE(classes) + 1), GFP_KERNEL); 60 if (!func) 61 return -ENOMEM; 62 63 func->dtor = r535_gr_dtor; 64 func->oneinit = r535_gr_oneinit; 65 func->init = nvkm_rm_gr_init; 66 func->fini = nvkm_rm_gr_fini; 67 func->units = r535_gr_units; 68 func->chan_new = r535_gr_chan_new; 69 70 for (int i = 0; i < ARRAY_SIZE(classes); i++) { 71 func->sclass[i].oclass = classes[i]; 72 func->sclass[i].minver = -1; 73 func->sclass[i].maxver = 0; 74 func->sclass[i].ctor = nvkm_rm_gr_obj_ctor; 75 } 76 77 gr = kzalloc(sizeof(*gr), GFP_KERNEL); 78 if (!gr) { 79 kfree(func); 80 return -ENOMEM; 81 } 82 83 nvkm_gr_ctor(func, rm->device, NVKM_ENGINE_GR, 0, true, &gr->base); 84 gr->scrubber.chid = -1; 85 rm->device->gr = &gr->base; 86 return 0; 87 } 88