xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gr.c (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce)
17c2d25f1SBen Skeggs /* SPDX-License-Identifier: MIT
27c2d25f1SBen Skeggs  *
37c2d25f1SBen Skeggs  * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
47c2d25f1SBen Skeggs  */
57c2d25f1SBen Skeggs #include "gr.h"
67c2d25f1SBen Skeggs 
77c2d25f1SBen Skeggs #include <engine/fifo.h>
87c2d25f1SBen Skeggs #include <engine/gr/priv.h>
97c2d25f1SBen Skeggs 
107c2d25f1SBen Skeggs static int
117c2d25f1SBen Skeggs nvkm_rm_gr_obj_ctor(const struct nvkm_oclass *oclass, void *argv, u32 argc,
127c2d25f1SBen Skeggs 		    struct nvkm_object **pobject)
137c2d25f1SBen Skeggs {
147c2d25f1SBen Skeggs 	struct r535_gr_chan *chan = container_of(oclass->parent, typeof(*chan), object);
157c2d25f1SBen Skeggs 
167c2d25f1SBen Skeggs 	return nvkm_rm_engine_obj_new(&chan->chan->rm.object, chan->chan->id, oclass, pobject);
177c2d25f1SBen Skeggs }
187c2d25f1SBen Skeggs 
19*53dac062SBen Skeggs static int
20*53dac062SBen Skeggs nvkm_rm_gr_fini(struct nvkm_gr *base, bool suspend)
21*53dac062SBen Skeggs {
22*53dac062SBen Skeggs 	struct nvkm_rm *rm = base->engine.subdev.device->gsp->rm;
23*53dac062SBen Skeggs 	struct r535_gr *gr = container_of(base, typeof(*gr), base);
24*53dac062SBen Skeggs 
25*53dac062SBen Skeggs 	if (rm->api->gr->scrubber.fini)
26*53dac062SBen Skeggs 		rm->api->gr->scrubber.fini(gr);
27*53dac062SBen Skeggs 
28*53dac062SBen Skeggs 	return 0;
29*53dac062SBen Skeggs }
30*53dac062SBen Skeggs 
31*53dac062SBen Skeggs static int
32*53dac062SBen Skeggs nvkm_rm_gr_init(struct nvkm_gr *base)
33*53dac062SBen Skeggs {
34*53dac062SBen Skeggs 	struct nvkm_rm *rm = base->engine.subdev.device->gsp->rm;
35*53dac062SBen Skeggs 	struct r535_gr *gr = container_of(base, typeof(*gr), base);
36*53dac062SBen Skeggs 	int ret;
37*53dac062SBen Skeggs 
38*53dac062SBen Skeggs 	if (rm->api->gr->scrubber.init) {
39*53dac062SBen Skeggs 		ret = rm->api->gr->scrubber.init(gr);
40*53dac062SBen Skeggs 		if (ret)
41*53dac062SBen Skeggs 			return ret;
42*53dac062SBen Skeggs 	}
43*53dac062SBen Skeggs 
44*53dac062SBen Skeggs 	return 0;
45*53dac062SBen Skeggs }
46*53dac062SBen Skeggs 
477c2d25f1SBen Skeggs int
487c2d25f1SBen Skeggs nvkm_rm_gr_new(struct nvkm_rm *rm)
497c2d25f1SBen Skeggs {
507c2d25f1SBen Skeggs 	const u32 classes[] = {
517c2d25f1SBen Skeggs 		rm->gpu->gr.class.i2m,
527c2d25f1SBen Skeggs 		rm->gpu->gr.class.twod,
537c2d25f1SBen Skeggs 		rm->gpu->gr.class.threed,
547c2d25f1SBen Skeggs 		rm->gpu->gr.class.compute,
557c2d25f1SBen Skeggs 	};
567c2d25f1SBen Skeggs 	struct nvkm_gr_func *func;
577c2d25f1SBen Skeggs 	struct r535_gr *gr;
587c2d25f1SBen Skeggs 
597c2d25f1SBen Skeggs 	func = kzalloc(struct_size(func, sclass, ARRAY_SIZE(classes) + 1), GFP_KERNEL);
607c2d25f1SBen Skeggs 	if (!func)
617c2d25f1SBen Skeggs 		return -ENOMEM;
627c2d25f1SBen Skeggs 
637c2d25f1SBen Skeggs 	func->dtor = r535_gr_dtor;
647c2d25f1SBen Skeggs 	func->oneinit = r535_gr_oneinit;
65*53dac062SBen Skeggs 	func->init = nvkm_rm_gr_init;
66*53dac062SBen Skeggs 	func->fini = nvkm_rm_gr_fini;
677c2d25f1SBen Skeggs 	func->units = r535_gr_units;
687c2d25f1SBen Skeggs 	func->chan_new = r535_gr_chan_new;
697c2d25f1SBen Skeggs 
707c2d25f1SBen Skeggs 	for (int i = 0; i < ARRAY_SIZE(classes); i++) {
717c2d25f1SBen Skeggs 		func->sclass[i].oclass = classes[i];
727c2d25f1SBen Skeggs 		func->sclass[i].minver = -1;
737c2d25f1SBen Skeggs 		func->sclass[i].maxver = 0;
747c2d25f1SBen Skeggs 		func->sclass[i].ctor = nvkm_rm_gr_obj_ctor;
757c2d25f1SBen Skeggs 	}
767c2d25f1SBen Skeggs 
777c2d25f1SBen Skeggs 	gr = kzalloc(sizeof(*gr), GFP_KERNEL);
787c2d25f1SBen Skeggs 	if (!gr) {
797c2d25f1SBen Skeggs 		kfree(func);
807c2d25f1SBen Skeggs 		return -ENOMEM;
817c2d25f1SBen Skeggs 	}
827c2d25f1SBen Skeggs 
837c2d25f1SBen Skeggs 	nvkm_gr_ctor(func, rm->device, NVKM_ENGINE_GR, 0, true, &gr->base);
84*53dac062SBen Skeggs 	gr->scrubber.chid = -1;
857c2d25f1SBen Skeggs 	rm->device->gr = &gr->base;
867c2d25f1SBen Skeggs 	return 0;
877c2d25f1SBen Skeggs }
88