1befe75aeSBen Skeggs /* SPDX-License-Identifier: MIT 2befe75aeSBen Skeggs * 3befe75aeSBen Skeggs * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4befe75aeSBen Skeggs */ 5befe75aeSBen Skeggs #include "gpu.h" 6befe75aeSBen Skeggs 7*56c36f59SBen Skeggs #include <engine/fifo/priv.h> 8*56c36f59SBen Skeggs 9cd3c6228SBen Skeggs #include <nvif/class.h> 10cd3c6228SBen Skeggs 11befe75aeSBen Skeggs const struct nvkm_rm_gpu 12befe75aeSBen Skeggs ga100_gpu = { 13cd3c6228SBen Skeggs .usermode.class = AMPERE_USERMODE_A, 14678bb27eSBen Skeggs 15678bb27eSBen Skeggs .fifo.chan = { 16678bb27eSBen Skeggs .class = AMPERE_CHANNEL_GPFIFO_A, 17*56c36f59SBen Skeggs .doorbell_handle = tu102_chan_doorbell_handle, 18678bb27eSBen Skeggs }, 197c2d25f1SBen Skeggs 207c2d25f1SBen Skeggs .ce.class = AMPERE_DMA_COPY_A, 217c2d25f1SBen Skeggs .gr.class = { 227c2d25f1SBen Skeggs .i2m = KEPLER_INLINE_TO_MEMORY_B, 237c2d25f1SBen Skeggs .twod = FERMI_TWOD_A, 247c2d25f1SBen Skeggs .threed = AMPERE_A, 257c2d25f1SBen Skeggs .compute = AMPERE_COMPUTE_A, 267c2d25f1SBen Skeggs }, 277c2d25f1SBen Skeggs .nvdec.class = NVC6B0_VIDEO_DECODER, 28befe75aeSBen Skeggs }; 29