144f93b20SBen Skeggs /* SPDX-License-Identifier: MIT 244f93b20SBen Skeggs * 344f93b20SBen Skeggs * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 444f93b20SBen Skeggs */ 544f93b20SBen Skeggs #ifndef __NVKM_FSP_PRIV_H__ 644f93b20SBen Skeggs #define __NVKM_FSP_PRIV_H__ 744f93b20SBen Skeggs #define nvkm_fsp(p) container_of((p), struct nvkm_fsp, subdev) 844f93b20SBen Skeggs #include <subdev/fsp.h> 944f93b20SBen Skeggs 1044f93b20SBen Skeggs struct nvkm_fsp_func { 1144f93b20SBen Skeggs int (*wait_secure_boot)(struct nvkm_fsp *); 1244f93b20SBen Skeggs 1344f93b20SBen Skeggs struct { 1444f93b20SBen Skeggs u32 version; 1544f93b20SBen Skeggs u32 size_hash; 1644f93b20SBen Skeggs u32 size_pkey; 1744f93b20SBen Skeggs u32 size_sig; 1844f93b20SBen Skeggs int (*boot_gsp_fmc)(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool resume, 1944f93b20SBen Skeggs u64 img_addr, const u8 *hash, const u8 *pkey, const u8 *sig); 2044f93b20SBen Skeggs } cot; 2144f93b20SBen Skeggs }; 2244f93b20SBen Skeggs 2344f93b20SBen Skeggs int nvkm_fsp_new_(const struct nvkm_fsp_func *, 2444f93b20SBen Skeggs struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **); 2544f93b20SBen Skeggs 26*32cb1cc3SBen Skeggs int gh100_fsp_wait_secure_boot(struct nvkm_fsp *); 2744f93b20SBen Skeggs int gh100_fsp_boot_gsp_fmc(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool resume, 2844f93b20SBen Skeggs u64 img_addr, const u8 *hash, const u8 *pkey, const u8 *sig); 2944f93b20SBen Skeggs #endif 30