xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c (revision e8d235d4d8fb8957bae5f6ed4521115203a00d8b)
1 /*
2  * Copyright (C) 2010 Francisco Jerez.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26 #include "nv04.h"
27 
28 void
29 nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
30 		  u32 flags, struct nvkm_fb_tile *tile)
31 {
32 	tile->addr  = 0x80000000 | addr;
33 	tile->limit = max(1u, addr + size) - 1;
34 	tile->pitch = pitch;
35 }
36 
37 void
38 nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
39 {
40 	tile->addr  = 0;
41 	tile->limit = 0;
42 	tile->pitch = 0;
43 	tile->zcomp = 0;
44 }
45 
46 void
47 nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile)
48 {
49 	nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
50 	nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch);
51 	nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr);
52 	nv_rd32(pfb, 0x100240 + (i * 0x10));
53 }
54 
55 struct nvkm_oclass *
56 nv10_fb_oclass = &(struct nv04_fb_impl) {
57 	.base.base.handle = NV_SUBDEV(FB, 0x10),
58 	.base.base.ofuncs = &(struct nvkm_ofuncs) {
59 		.ctor = nv04_fb_ctor,
60 		.dtor = _nvkm_fb_dtor,
61 		.init = _nvkm_fb_init,
62 		.fini = _nvkm_fb_fini,
63 	},
64 	.base.memtype = nv04_fb_memtype_valid,
65 	.base.ram = &nv10_ram_oclass,
66 	.tile.regions = 8,
67 	.tile.init = nv10_fb_tile_init,
68 	.tile.fini = nv10_fb_tile_fini,
69 	.tile.prog = nv10_fb_tile_prog,
70 }.base.base;
71