xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.h (revision d0034a7a4ac7fae708146ac0059b9c47a1543f0d)
1b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */
2151abd44SBen Skeggs #ifndef __NV04_DEVINIT_H__
3151abd44SBen Skeggs #define __NV04_DEVINIT_H__
4151abd44SBen Skeggs #define nv04_devinit(p) container_of((p), struct nv04_devinit, base)
5c39f472eSBen Skeggs #include "priv.h"
6a8c4362bSBen Skeggs struct nvkm_pll_vals;
7c39f472eSBen Skeggs 
8266f8b5eSBen Skeggs struct nv04_devinit {
9a8c4362bSBen Skeggs 	struct nvkm_devinit base;
1030489c23SBen Skeggs 	int owner;
11c39f472eSBen Skeggs };
12c39f472eSBen Skeggs 
13151abd44SBen Skeggs int nv04_devinit_new_(const struct nvkm_devinit_func *, struct nvkm_device *,
14*4a34fd0eSBen Skeggs 		      enum nvkm_subdev_type, int, struct nvkm_devinit **);
15151abd44SBen Skeggs void *nv04_devinit_dtor(struct nvkm_devinit *);
16151abd44SBen Skeggs void nv04_devinit_preinit(struct nvkm_devinit *);
17151abd44SBen Skeggs void nv04_devinit_fini(struct nvkm_devinit *);
18a8c4362bSBen Skeggs int  nv04_devinit_pll_set(struct nvkm_devinit *, u32, u32);
19c39f472eSBen Skeggs 
20a8c4362bSBen Skeggs void setPLL_single(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
21a8c4362bSBen Skeggs void setPLL_double_highregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
22a8c4362bSBen Skeggs void setPLL_double_lowregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
23c39f472eSBen Skeggs #endif
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