1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 #include "pll.h" 26 #include "seq.h" 27 28 #include <subdev/bios.h> 29 #include <subdev/bios/pll.h> 30 31 static u32 32 read_div(struct nv50_clk *clk) 33 { 34 switch (nv_device(clk)->chipset) { 35 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ 36 case 0x84: 37 case 0x86: 38 case 0x98: 39 case 0xa0: 40 return nv_rd32(clk, 0x004700); 41 case 0x92: 42 case 0x94: 43 case 0x96: 44 return nv_rd32(clk, 0x004800); 45 default: 46 return 0x00000000; 47 } 48 } 49 50 static u32 51 read_pll_src(struct nv50_clk *clk, u32 base) 52 { 53 u32 coef, ref = clk->base.read(&clk->base, nv_clk_src_crystal); 54 u32 rsel = nv_rd32(clk, 0x00e18c); 55 int P, N, M, id; 56 57 switch (nv_device(clk)->chipset) { 58 case 0x50: 59 case 0xa0: 60 switch (base) { 61 case 0x4020: 62 case 0x4028: id = !!(rsel & 0x00000004); break; 63 case 0x4008: id = !!(rsel & 0x00000008); break; 64 case 0x4030: id = 0; break; 65 default: 66 nv_error(clk, "ref: bad pll 0x%06x\n", base); 67 return 0; 68 } 69 70 coef = nv_rd32(clk, 0x00e81c + (id * 0x0c)); 71 ref *= (coef & 0x01000000) ? 2 : 4; 72 P = (coef & 0x00070000) >> 16; 73 N = ((coef & 0x0000ff00) >> 8) + 1; 74 M = ((coef & 0x000000ff) >> 0) + 1; 75 break; 76 case 0x84: 77 case 0x86: 78 case 0x92: 79 coef = nv_rd32(clk, 0x00e81c); 80 P = (coef & 0x00070000) >> 16; 81 N = (coef & 0x0000ff00) >> 8; 82 M = (coef & 0x000000ff) >> 0; 83 break; 84 case 0x94: 85 case 0x96: 86 case 0x98: 87 rsel = nv_rd32(clk, 0x00c050); 88 switch (base) { 89 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; 90 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; 91 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; 92 case 0x4030: rsel = 3; break; 93 default: 94 nv_error(clk, "ref: bad pll 0x%06x\n", base); 95 return 0; 96 } 97 98 switch (rsel) { 99 case 0: id = 1; break; 100 case 1: return clk->base.read(&clk->base, nv_clk_src_crystal); 101 case 2: return clk->base.read(&clk->base, nv_clk_src_href); 102 case 3: id = 0; break; 103 } 104 105 coef = nv_rd32(clk, 0x00e81c + (id * 0x28)); 106 P = (nv_rd32(clk, 0x00e824 + (id * 0x28)) >> 16) & 7; 107 P += (coef & 0x00070000) >> 16; 108 N = (coef & 0x0000ff00) >> 8; 109 M = (coef & 0x000000ff) >> 0; 110 break; 111 default: 112 BUG_ON(1); 113 } 114 115 if (M) 116 return (ref * N / M) >> P; 117 118 return 0; 119 } 120 121 static u32 122 read_pll_ref(struct nv50_clk *clk, u32 base) 123 { 124 u32 src, mast = nv_rd32(clk, 0x00c040); 125 126 switch (base) { 127 case 0x004028: 128 src = !!(mast & 0x00200000); 129 break; 130 case 0x004020: 131 src = !!(mast & 0x00400000); 132 break; 133 case 0x004008: 134 src = !!(mast & 0x00010000); 135 break; 136 case 0x004030: 137 src = !!(mast & 0x02000000); 138 break; 139 case 0x00e810: 140 return clk->base.read(&clk->base, nv_clk_src_crystal); 141 default: 142 nv_error(clk, "bad pll 0x%06x\n", base); 143 return 0; 144 } 145 146 if (src) 147 return clk->base.read(&clk->base, nv_clk_src_href); 148 149 return read_pll_src(clk, base); 150 } 151 152 static u32 153 read_pll(struct nv50_clk *clk, u32 base) 154 { 155 u32 mast = nv_rd32(clk, 0x00c040); 156 u32 ctrl = nv_rd32(clk, base + 0); 157 u32 coef = nv_rd32(clk, base + 4); 158 u32 ref = read_pll_ref(clk, base); 159 u32 freq = 0; 160 int N1, N2, M1, M2; 161 162 if (base == 0x004028 && (mast & 0x00100000)) { 163 /* wtf, appears to only disable post-divider on gt200 */ 164 if (nv_device(clk)->chipset != 0xa0) 165 return clk->base.read(&clk->base, nv_clk_src_dom6); 166 } 167 168 N2 = (coef & 0xff000000) >> 24; 169 M2 = (coef & 0x00ff0000) >> 16; 170 N1 = (coef & 0x0000ff00) >> 8; 171 M1 = (coef & 0x000000ff); 172 if ((ctrl & 0x80000000) && M1) { 173 freq = ref * N1 / M1; 174 if ((ctrl & 0x40000100) == 0x40000000) { 175 if (M2) 176 freq = freq * N2 / M2; 177 else 178 freq = 0; 179 } 180 } 181 182 return freq; 183 } 184 185 static int 186 nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src) 187 { 188 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 189 u32 mast = nv_rd32(clk, 0x00c040); 190 u32 P = 0; 191 192 switch (src) { 193 case nv_clk_src_crystal: 194 return nv_device(clk)->crystal; 195 case nv_clk_src_href: 196 return 100000; /* PCIE reference clock */ 197 case nv_clk_src_hclk: 198 return div_u64((u64)clk->base.read(&clk->base, nv_clk_src_href) * 27778, 10000); 199 case nv_clk_src_hclkm3: 200 return clk->base.read(&clk->base, nv_clk_src_hclk) * 3; 201 case nv_clk_src_hclkm3d2: 202 return clk->base.read(&clk->base, nv_clk_src_hclk) * 3 / 2; 203 case nv_clk_src_host: 204 switch (mast & 0x30000000) { 205 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_href); 206 case 0x10000000: break; 207 case 0x20000000: /* !0x50 */ 208 case 0x30000000: return clk->base.read(&clk->base, nv_clk_src_hclk); 209 } 210 break; 211 case nv_clk_src_core: 212 if (!(mast & 0x00100000)) 213 P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16; 214 switch (mast & 0x00000003) { 215 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 216 case 0x00000001: return clk->base.read(&clk->base, nv_clk_src_dom6); 217 case 0x00000002: return read_pll(clk, 0x004020) >> P; 218 case 0x00000003: return read_pll(clk, 0x004028) >> P; 219 } 220 break; 221 case nv_clk_src_shader: 222 P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16; 223 switch (mast & 0x00000030) { 224 case 0x00000000: 225 if (mast & 0x00000080) 226 return clk->base.read(&clk->base, nv_clk_src_host) >> P; 227 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 228 case 0x00000010: break; 229 case 0x00000020: return read_pll(clk, 0x004028) >> P; 230 case 0x00000030: return read_pll(clk, 0x004020) >> P; 231 } 232 break; 233 case nv_clk_src_mem: 234 P = (nv_rd32(clk, 0x004008) & 0x00070000) >> 16; 235 if (nv_rd32(clk, 0x004008) & 0x00000200) { 236 switch (mast & 0x0000c000) { 237 case 0x00000000: 238 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 239 case 0x00008000: 240 case 0x0000c000: 241 return clk->base.read(&clk->base, nv_clk_src_href) >> P; 242 } 243 } else { 244 return read_pll(clk, 0x004008) >> P; 245 } 246 break; 247 case nv_clk_src_vdec: 248 P = (read_div(clk) & 0x00000700) >> 8; 249 switch (nv_device(clk)->chipset) { 250 case 0x84: 251 case 0x86: 252 case 0x92: 253 case 0x94: 254 case 0x96: 255 case 0xa0: 256 switch (mast & 0x00000c00) { 257 case 0x00000000: 258 if (nv_device(clk)->chipset == 0xa0) /* wtf?? */ 259 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 260 return clk->base.read(&clk->base, nv_clk_src_crystal) >> P; 261 case 0x00000400: 262 return 0; 263 case 0x00000800: 264 if (mast & 0x01000000) 265 return read_pll(clk, 0x004028) >> P; 266 return read_pll(clk, 0x004030) >> P; 267 case 0x00000c00: 268 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 269 } 270 break; 271 case 0x98: 272 switch (mast & 0x00000c00) { 273 case 0x00000000: 274 return clk->base.read(&clk->base, nv_clk_src_core) >> P; 275 case 0x00000400: 276 return 0; 277 case 0x00000800: 278 return clk->base.read(&clk->base, nv_clk_src_hclkm3d2) >> P; 279 case 0x00000c00: 280 return clk->base.read(&clk->base, nv_clk_src_mem) >> P; 281 } 282 break; 283 } 284 break; 285 case nv_clk_src_dom6: 286 switch (nv_device(clk)->chipset) { 287 case 0x50: 288 case 0xa0: 289 return read_pll(clk, 0x00e810) >> 2; 290 case 0x84: 291 case 0x86: 292 case 0x92: 293 case 0x94: 294 case 0x96: 295 case 0x98: 296 P = (read_div(clk) & 0x00000007) >> 0; 297 switch (mast & 0x0c000000) { 298 case 0x00000000: return clk->base.read(&clk->base, nv_clk_src_href); 299 case 0x04000000: break; 300 case 0x08000000: return clk->base.read(&clk->base, nv_clk_src_hclk); 301 case 0x0c000000: 302 return clk->base.read(&clk->base, nv_clk_src_hclkm3) >> P; 303 } 304 break; 305 default: 306 break; 307 } 308 default: 309 break; 310 } 311 312 nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast); 313 return -EINVAL; 314 } 315 316 static u32 317 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P) 318 { 319 struct nvkm_bios *bios = nvkm_bios(clk); 320 struct nvbios_pll pll; 321 int ret; 322 323 ret = nvbios_pll_parse(bios, reg, &pll); 324 if (ret) 325 return 0; 326 327 pll.vco2.max_freq = 0; 328 pll.refclk = read_pll_ref(clk, reg); 329 if (!pll.refclk) 330 return 0; 331 332 return nv04_pll_calc(nv_subdev(clk), &pll, idx, N, M, NULL, NULL, P); 333 } 334 335 static inline u32 336 calc_div(u32 src, u32 target, int *div) 337 { 338 u32 clk0 = src, clk1 = src; 339 for (*div = 0; *div <= 7; (*div)++) { 340 if (clk0 <= target) { 341 clk1 = clk0 << (*div ? 1 : 0); 342 break; 343 } 344 clk0 >>= 1; 345 } 346 347 if (target - clk0 <= clk1 - target) 348 return clk0; 349 (*div)--; 350 return clk1; 351 } 352 353 static inline u32 354 clk_same(u32 a, u32 b) 355 { 356 return ((a / 1000) == (b / 1000)); 357 } 358 359 static int 360 nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate) 361 { 362 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 363 struct nv50_clk_hwsq *hwsq = &clk->hwsq; 364 const int shader = cstate->domain[nv_clk_src_shader]; 365 const int core = cstate->domain[nv_clk_src_core]; 366 const int vdec = cstate->domain[nv_clk_src_vdec]; 367 const int dom6 = cstate->domain[nv_clk_src_dom6]; 368 u32 mastm = 0, mastv = 0; 369 u32 divsm = 0, divsv = 0; 370 int N, M, P1, P2; 371 int freq, out; 372 373 /* prepare a hwsq script from which we'll perform the reclock */ 374 out = clk_init(hwsq, nv_subdev(clk)); 375 if (out) 376 return out; 377 378 clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ 379 clk_nsec(hwsq, 8000); 380 clk_setf(hwsq, 0x10, 0x00); /* disable fb */ 381 clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 382 383 /* vdec: avoid modifying xpll until we know exactly how the other 384 * clock domains work, i suspect at least some of them can also be 385 * tied to xpll... 386 */ 387 if (vdec) { 388 /* see how close we can get using nvclk as a source */ 389 freq = calc_div(core, vdec, &P1); 390 391 /* see how close we can get using xpll/hclk as a source */ 392 if (nv_device(clk)->chipset != 0x98) 393 out = read_pll(clk, 0x004030); 394 else 395 out = clk->base.read(&clk->base, nv_clk_src_hclkm3d2); 396 out = calc_div(out, vdec, &P2); 397 398 /* select whichever gets us closest */ 399 if (abs(vdec - freq) <= abs(vdec - out)) { 400 if (nv_device(clk)->chipset != 0x98) 401 mastv |= 0x00000c00; 402 divsv |= P1 << 8; 403 } else { 404 mastv |= 0x00000800; 405 divsv |= P2 << 8; 406 } 407 408 mastm |= 0x00000c00; 409 divsm |= 0x00000700; 410 } 411 412 /* dom6: nfi what this is, but we're limited to various combinations 413 * of the host clock frequency 414 */ 415 if (dom6) { 416 if (clk_same(dom6, clk->base.read(&clk->base, nv_clk_src_href))) { 417 mastv |= 0x00000000; 418 } else 419 if (clk_same(dom6, clk->base.read(&clk->base, nv_clk_src_hclk))) { 420 mastv |= 0x08000000; 421 } else { 422 freq = clk->base.read(&clk->base, nv_clk_src_hclk) * 3; 423 calc_div(freq, dom6, &P1); 424 425 mastv |= 0x0c000000; 426 divsv |= P1; 427 } 428 429 mastm |= 0x0c000000; 430 divsm |= 0x00000007; 431 } 432 433 /* vdec/dom6: switch to "safe" clocks temporarily, update dividers 434 * and then switch to target clocks 435 */ 436 clk_mask(hwsq, mast, mastm, 0x00000000); 437 clk_mask(hwsq, divs, divsm, divsv); 438 clk_mask(hwsq, mast, mastm, mastv); 439 440 /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, 441 * sclk to hclk) before reprogramming 442 */ 443 if (nv_device(clk)->chipset < 0x92) 444 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); 445 else 446 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); 447 448 /* core: for the moment at least, always use nvpll */ 449 freq = calc_pll(clk, 0x4028, core, &N, &M, &P1); 450 if (freq == 0) 451 return -ERANGE; 452 453 clk_mask(hwsq, nvpll[0], 0xc03f0100, 454 0x80000000 | (P1 << 19) | (P1 << 16)); 455 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); 456 457 /* shader: tie to nvclk if possible, otherwise use spll. have to be 458 * very careful that the shader clock is at least twice the core, or 459 * some chipsets will be very unhappy. i expect most or all of these 460 * cases will be handled by tying to nvclk, but it's possible there's 461 * corners 462 */ 463 if (P1-- && shader == (core << 1)) { 464 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); 465 clk_mask(hwsq, mast, 0x00100033, 0x00000023); 466 } else { 467 freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1); 468 if (freq == 0) 469 return -ERANGE; 470 471 clk_mask(hwsq, spll[0], 0xc03f0100, 472 0x80000000 | (P1 << 19) | (P1 << 16)); 473 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); 474 clk_mask(hwsq, mast, 0x00100033, 0x00000033); 475 } 476 477 /* restore normal operation */ 478 clk_setf(hwsq, 0x10, 0x01); /* enable fb */ 479 clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 480 clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ 481 return 0; 482 } 483 484 static int 485 nv50_clk_prog(struct nvkm_clk *obj) 486 { 487 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 488 return clk_exec(&clk->hwsq, true); 489 } 490 491 static void 492 nv50_clk_tidy(struct nvkm_clk *obj) 493 { 494 struct nv50_clk *clk = container_of(obj, typeof(*clk), base); 495 clk_exec(&clk->hwsq, false); 496 } 497 498 int 499 nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 500 struct nvkm_oclass *oclass, void *data, u32 size, 501 struct nvkm_object **pobject) 502 { 503 struct nv50_clk_oclass *pclass = (void *)oclass; 504 struct nv50_clk *clk; 505 int ret; 506 507 ret = nvkm_clk_create(parent, engine, oclass, pclass->domains, 508 NULL, 0, nv_device(parent)->chipset == 0xa0, 509 &clk); 510 *pobject = nv_object(clk); 511 if (ret) 512 return ret; 513 514 clk->hwsq.r_fifo = hwsq_reg(0x002504); 515 clk->hwsq.r_spll[0] = hwsq_reg(0x004020); 516 clk->hwsq.r_spll[1] = hwsq_reg(0x004024); 517 clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028); 518 clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); 519 switch (nv_device(clk)->chipset) { 520 case 0x92: 521 case 0x94: 522 case 0x96: 523 clk->hwsq.r_divs = hwsq_reg(0x004800); 524 break; 525 default: 526 clk->hwsq.r_divs = hwsq_reg(0x004700); 527 break; 528 } 529 clk->hwsq.r_mast = hwsq_reg(0x00c040); 530 531 clk->base.read = nv50_clk_read; 532 clk->base.calc = nv50_clk_calc; 533 clk->base.prog = nv50_clk_prog; 534 clk->base.tidy = nv50_clk_tidy; 535 return 0; 536 } 537 538 static struct nvkm_domain 539 nv50_domains[] = { 540 { nv_clk_src_crystal, 0xff }, 541 { nv_clk_src_href , 0xff }, 542 { nv_clk_src_core , 0xff, 0, "core", 1000 }, 543 { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, 544 { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, 545 { nv_clk_src_max } 546 }; 547 548 struct nvkm_oclass * 549 nv50_clk_oclass = &(struct nv50_clk_oclass) { 550 .base.handle = NV_SUBDEV(CLK, 0x50), 551 .base.ofuncs = &(struct nvkm_ofuncs) { 552 .ctor = nv50_clk_ctor, 553 .dtor = _nvkm_clk_dtor, 554 .init = _nvkm_clk_init, 555 .fini = _nvkm_clk_fini, 556 }, 557 .domains = nv50_domains, 558 }.base; 559