1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 * Roy Spliet 24 */ 25 #include "gt215.h" 26 #include "pll.h" 27 28 #include <core/device.h> 29 #include <engine/fifo.h> 30 #include <subdev/bios.h> 31 #include <subdev/bios/pll.h> 32 #include <subdev/timer.h> 33 34 struct gt215_clk_priv { 35 struct nvkm_clk base; 36 struct gt215_clk_info eng[nv_clk_src_max]; 37 }; 38 39 static u32 read_clk(struct gt215_clk_priv *, int, bool); 40 static u32 read_pll(struct gt215_clk_priv *, int, u32); 41 42 static u32 43 read_vco(struct gt215_clk_priv *priv, int clk) 44 { 45 u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); 46 47 switch (sctl & 0x00000030) { 48 case 0x00000000: 49 return nv_device(priv)->crystal; 50 case 0x00000020: 51 return read_pll(priv, 0x41, 0x00e820); 52 case 0x00000030: 53 return read_pll(priv, 0x42, 0x00e8a0); 54 default: 55 return 0; 56 } 57 } 58 59 static u32 60 read_clk(struct gt215_clk_priv *priv, int clk, bool ignore_en) 61 { 62 u32 sctl, sdiv, sclk; 63 64 /* refclk for the 0xe8xx plls is a fixed frequency */ 65 if (clk >= 0x40) { 66 if (nv_device(priv)->chipset == 0xaf) { 67 /* no joke.. seriously.. sigh.. */ 68 return nv_rd32(priv, 0x00471c) * 1000; 69 } 70 71 return nv_device(priv)->crystal; 72 } 73 74 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); 75 if (!ignore_en && !(sctl & 0x00000100)) 76 return 0; 77 78 /* out_alt */ 79 if (sctl & 0x00000400) 80 return 108000; 81 82 /* vco_out */ 83 switch (sctl & 0x00003000) { 84 case 0x00000000: 85 if (!(sctl & 0x00000200)) 86 return nv_device(priv)->crystal; 87 return 0; 88 case 0x00002000: 89 if (sctl & 0x00000040) 90 return 108000; 91 return 100000; 92 case 0x00003000: 93 /* vco_enable */ 94 if (!(sctl & 0x00000001)) 95 return 0; 96 97 sclk = read_vco(priv, clk); 98 sdiv = ((sctl & 0x003f0000) >> 16) + 2; 99 return (sclk * 2) / sdiv; 100 default: 101 return 0; 102 } 103 } 104 105 static u32 106 read_pll(struct gt215_clk_priv *priv, int clk, u32 pll) 107 { 108 u32 ctrl = nv_rd32(priv, pll + 0); 109 u32 sclk = 0, P = 1, N = 1, M = 1; 110 111 if (!(ctrl & 0x00000008)) { 112 if (ctrl & 0x00000001) { 113 u32 coef = nv_rd32(priv, pll + 4); 114 M = (coef & 0x000000ff) >> 0; 115 N = (coef & 0x0000ff00) >> 8; 116 P = (coef & 0x003f0000) >> 16; 117 118 /* no post-divider on these.. 119 * XXX: it looks more like two post-"dividers" that 120 * cross each other out in the default RPLL config */ 121 if ((pll & 0x00ff00) == 0x00e800) 122 P = 1; 123 124 sclk = read_clk(priv, 0x00 + clk, false); 125 } 126 } else { 127 sclk = read_clk(priv, 0x10 + clk, false); 128 } 129 130 if (M * P) 131 return sclk * N / (M * P); 132 133 return 0; 134 } 135 136 static int 137 gt215_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) 138 { 139 struct gt215_clk_priv *priv = (void *)clk; 140 u32 hsrc; 141 142 switch (src) { 143 case nv_clk_src_crystal: 144 return nv_device(priv)->crystal; 145 case nv_clk_src_core: 146 case nv_clk_src_core_intm: 147 return read_pll(priv, 0x00, 0x4200); 148 case nv_clk_src_shader: 149 return read_pll(priv, 0x01, 0x4220); 150 case nv_clk_src_mem: 151 return read_pll(priv, 0x02, 0x4000); 152 case nv_clk_src_disp: 153 return read_clk(priv, 0x20, false); 154 case nv_clk_src_vdec: 155 return read_clk(priv, 0x21, false); 156 case nv_clk_src_daemon: 157 return read_clk(priv, 0x25, false); 158 case nv_clk_src_host: 159 hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; 160 switch (hsrc) { 161 case 0: 162 return read_clk(priv, 0x1d, false); 163 case 2: 164 case 3: 165 return 277000; 166 default: 167 nv_error(clk, "unknown HOST clock source %d\n", hsrc); 168 return -EINVAL; 169 } 170 default: 171 nv_error(clk, "invalid clock source %d\n", src); 172 return -EINVAL; 173 } 174 175 return 0; 176 } 177 178 int 179 gt215_clk_info(struct nvkm_clk *clock, int clk, u32 khz, 180 struct gt215_clk_info *info) 181 { 182 struct gt215_clk_priv *priv = (void *)clock; 183 u32 oclk, sclk, sdiv, diff; 184 185 info->clk = 0; 186 187 switch (khz) { 188 case 27000: 189 info->clk = 0x00000100; 190 return khz; 191 case 100000: 192 info->clk = 0x00002100; 193 return khz; 194 case 108000: 195 info->clk = 0x00002140; 196 return khz; 197 default: 198 sclk = read_vco(priv, clk); 199 sdiv = min((sclk * 2) / khz, (u32)65); 200 oclk = (sclk * 2) / sdiv; 201 diff = ((khz + 3000) - oclk); 202 203 /* When imprecise, play it safe and aim for a clock lower than 204 * desired rather than higher */ 205 if (diff < 0) { 206 sdiv++; 207 oclk = (sclk * 2) / sdiv; 208 } 209 210 /* divider can go as low as 2, limited here because NVIDIA 211 * and the VBIOS on my NVA8 seem to prefer using the PLL 212 * for 810MHz - is there a good reason? 213 * XXX: PLLs with refclk 810MHz? */ 214 if (sdiv > 4) { 215 info->clk = (((sdiv - 2) << 16) | 0x00003100); 216 return oclk; 217 } 218 219 break; 220 } 221 222 return -ERANGE; 223 } 224 225 int 226 gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz, 227 struct gt215_clk_info *info) 228 { 229 struct nvkm_bios *bios = nvkm_bios(clock); 230 struct gt215_clk_priv *priv = (void *)clock; 231 struct nvbios_pll limits; 232 int P, N, M, diff; 233 int ret; 234 235 info->pll = 0; 236 237 /* If we can get a within [-2, 3) MHz of a divider, we'll disable the 238 * PLL and use the divider instead. */ 239 ret = gt215_clk_info(clock, clk, khz, info); 240 diff = khz - ret; 241 if (!pll || (diff >= -2000 && diff < 3000)) { 242 goto out; 243 } 244 245 /* Try with PLL */ 246 ret = nvbios_pll_parse(bios, pll, &limits); 247 if (ret) 248 return ret; 249 250 ret = gt215_clk_info(clock, clk - 0x10, limits.refclk, info); 251 if (ret != limits.refclk) 252 return -EINVAL; 253 254 ret = gt215_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); 255 if (ret >= 0) { 256 info->pll = (P << 16) | (N << 8) | M; 257 } 258 259 out: 260 info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); 261 return ret ? ret : -ERANGE; 262 } 263 264 static int 265 calc_clk(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate, 266 int clk, u32 pll, int idx) 267 { 268 int ret = gt215_pll_info(&priv->base, clk, pll, cstate->domain[idx], 269 &priv->eng[idx]); 270 if (ret >= 0) 271 return 0; 272 return ret; 273 } 274 275 static int 276 calc_host(struct gt215_clk_priv *priv, struct nvkm_cstate *cstate) 277 { 278 int ret = 0; 279 u32 kHz = cstate->domain[nv_clk_src_host]; 280 struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; 281 282 if (kHz == 277000) { 283 info->clk = 0; 284 info->host_out = NVA3_HOST_277; 285 return 0; 286 } 287 288 info->host_out = NVA3_HOST_CLK; 289 290 ret = gt215_clk_info(&priv->base, 0x1d, kHz, info); 291 if (ret >= 0) 292 return 0; 293 294 return ret; 295 } 296 297 int 298 gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) 299 { 300 struct nvkm_fifo *pfifo = nvkm_fifo(clk); 301 302 /* halt and idle execution engines */ 303 nv_mask(clk, 0x020060, 0x00070000, 0x00000000); 304 nv_mask(clk, 0x002504, 0x00000001, 0x00000001); 305 /* Wait until the interrupt handler is finished */ 306 if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) 307 return -EBUSY; 308 309 if (pfifo) 310 pfifo->pause(pfifo, flags); 311 312 if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) 313 return -EIO; 314 if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) 315 return -EIO; 316 317 return 0; 318 } 319 320 void 321 gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) 322 { 323 struct nvkm_fifo *pfifo = nvkm_fifo(clk); 324 325 if (pfifo && flags) 326 pfifo->start(pfifo, flags); 327 328 nv_mask(clk, 0x002504, 0x00000001, 0x00000000); 329 nv_mask(clk, 0x020060, 0x00070000, 0x00040000); 330 } 331 332 static void 333 disable_clk_src(struct gt215_clk_priv *priv, u32 src) 334 { 335 nv_mask(priv, src, 0x00000100, 0x00000000); 336 nv_mask(priv, src, 0x00000001, 0x00000000); 337 } 338 339 static void 340 prog_pll(struct gt215_clk_priv *priv, int clk, u32 pll, int idx) 341 { 342 struct gt215_clk_info *info = &priv->eng[idx]; 343 const u32 src0 = 0x004120 + (clk * 4); 344 const u32 src1 = 0x004160 + (clk * 4); 345 const u32 ctrl = pll + 0; 346 const u32 coef = pll + 4; 347 u32 bypass; 348 349 if (info->pll) { 350 /* Always start from a non-PLL clock */ 351 bypass = nv_rd32(priv, ctrl) & 0x00000008; 352 if (!bypass) { 353 nv_mask(priv, src1, 0x00000101, 0x00000101); 354 nv_mask(priv, ctrl, 0x00000008, 0x00000008); 355 udelay(20); 356 } 357 358 nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); 359 nv_wr32(priv, coef, info->pll); 360 nv_mask(priv, ctrl, 0x00000015, 0x00000015); 361 nv_mask(priv, ctrl, 0x00000010, 0x00000000); 362 if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) { 363 nv_mask(priv, ctrl, 0x00000010, 0x00000010); 364 nv_mask(priv, src0, 0x00000101, 0x00000000); 365 return; 366 } 367 nv_mask(priv, ctrl, 0x00000010, 0x00000010); 368 nv_mask(priv, ctrl, 0x00000008, 0x00000000); 369 disable_clk_src(priv, src1); 370 } else { 371 nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); 372 nv_mask(priv, ctrl, 0x00000018, 0x00000018); 373 udelay(20); 374 nv_mask(priv, ctrl, 0x00000001, 0x00000000); 375 disable_clk_src(priv, src0); 376 } 377 } 378 379 static void 380 prog_clk(struct gt215_clk_priv *priv, int clk, int idx) 381 { 382 struct gt215_clk_info *info = &priv->eng[idx]; 383 nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); 384 } 385 386 static void 387 prog_host(struct gt215_clk_priv *priv) 388 { 389 struct gt215_clk_info *info = &priv->eng[nv_clk_src_host]; 390 u32 hsrc = (nv_rd32(priv, 0xc040)); 391 392 switch (info->host_out) { 393 case NVA3_HOST_277: 394 if ((hsrc & 0x30000000) == 0) { 395 nv_wr32(priv, 0xc040, hsrc | 0x20000000); 396 disable_clk_src(priv, 0x4194); 397 } 398 break; 399 case NVA3_HOST_CLK: 400 prog_clk(priv, 0x1d, nv_clk_src_host); 401 if ((hsrc & 0x30000000) >= 0x20000000) { 402 nv_wr32(priv, 0xc040, hsrc & ~0x30000000); 403 } 404 break; 405 default: 406 break; 407 } 408 409 /* This seems to be a clock gating factor on idle, always set to 64 */ 410 nv_wr32(priv, 0xc044, 0x3e); 411 } 412 413 static void 414 prog_core(struct gt215_clk_priv *priv, int idx) 415 { 416 struct gt215_clk_info *info = &priv->eng[idx]; 417 u32 fb_delay = nv_rd32(priv, 0x10002c); 418 419 if (fb_delay < info->fb_delay) 420 nv_wr32(priv, 0x10002c, info->fb_delay); 421 422 prog_pll(priv, 0x00, 0x004200, idx); 423 424 if (fb_delay > info->fb_delay) 425 nv_wr32(priv, 0x10002c, info->fb_delay); 426 } 427 428 static int 429 gt215_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) 430 { 431 struct gt215_clk_priv *priv = (void *)clk; 432 struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; 433 int ret; 434 435 if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || 436 (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || 437 (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || 438 (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || 439 (ret = calc_host(priv, cstate))) 440 return ret; 441 442 /* XXX: Should be reading the highest bit in the VBIOS clock to decide 443 * whether to use a PLL or not... but using a PLL defeats the purpose */ 444 if (core->pll) { 445 ret = gt215_clk_info(clk, 0x10, 446 cstate->domain[nv_clk_src_core_intm], 447 &priv->eng[nv_clk_src_core_intm]); 448 if (ret < 0) 449 return ret; 450 } 451 452 return 0; 453 } 454 455 static int 456 gt215_clk_prog(struct nvkm_clk *clk) 457 { 458 struct gt215_clk_priv *priv = (void *)clk; 459 struct gt215_clk_info *core = &priv->eng[nv_clk_src_core]; 460 int ret = 0; 461 unsigned long flags; 462 unsigned long *f = &flags; 463 464 ret = gt215_clk_pre(clk, f); 465 if (ret) 466 goto out; 467 468 if (core->pll) 469 prog_core(priv, nv_clk_src_core_intm); 470 471 prog_core(priv, nv_clk_src_core); 472 prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); 473 prog_clk(priv, 0x20, nv_clk_src_disp); 474 prog_clk(priv, 0x21, nv_clk_src_vdec); 475 prog_host(priv); 476 477 out: 478 if (ret == -EBUSY) 479 f = NULL; 480 481 gt215_clk_post(clk, f); 482 return ret; 483 } 484 485 static void 486 gt215_clk_tidy(struct nvkm_clk *clk) 487 { 488 } 489 490 static struct nvkm_domain 491 gt215_domain[] = { 492 { nv_clk_src_crystal , 0xff }, 493 { nv_clk_src_core , 0x00, 0, "core", 1000 }, 494 { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, 495 { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, 496 { nv_clk_src_vdec , 0x03 }, 497 { nv_clk_src_disp , 0x04 }, 498 { nv_clk_src_host , 0x05 }, 499 { nv_clk_src_core_intm, 0x06 }, 500 { nv_clk_src_max } 501 }; 502 503 static int 504 gt215_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 505 struct nvkm_oclass *oclass, void *data, u32 size, 506 struct nvkm_object **pobject) 507 { 508 struct gt215_clk_priv *priv; 509 int ret; 510 511 ret = nvkm_clk_create(parent, engine, oclass, gt215_domain, 512 NULL, 0, true, &priv); 513 *pobject = nv_object(priv); 514 if (ret) 515 return ret; 516 517 priv->base.read = gt215_clk_read; 518 priv->base.calc = gt215_clk_calc; 519 priv->base.prog = gt215_clk_prog; 520 priv->base.tidy = gt215_clk_tidy; 521 return 0; 522 } 523 524 struct nvkm_oclass 525 gt215_clk_oclass = { 526 .handle = NV_SUBDEV(CLK, 0xa3), 527 .ofuncs = &(struct nvkm_ofuncs) { 528 .ctor = gt215_clk_ctor, 529 .dtor = _nvkm_clk_dtor, 530 .init = _nvkm_clk_init, 531 .fini = _nvkm_clk_fini, 532 }, 533 }; 534