1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #define gf100_clk(p) container_of((p), struct gf100_clk, base) 25 #include "priv.h" 26 #include "pll.h" 27 28 #include <subdev/bios.h> 29 #include <subdev/bios/pll.h> 30 #include <subdev/timer.h> 31 32 struct gf100_clk_info { 33 u32 freq; 34 u32 ssel; 35 u32 mdiv; 36 u32 dsrc; 37 u32 ddiv; 38 u32 coef; 39 }; 40 41 struct gf100_clk { 42 struct nvkm_clk base; 43 struct gf100_clk_info eng[16]; 44 }; 45 46 static u32 read_div(struct gf100_clk *, int, u32, u32); 47 48 static u32 49 read_vco(struct gf100_clk *clk, u32 dsrc) 50 { 51 struct nvkm_device *device = clk->base.subdev.device; 52 u32 ssrc = nvkm_rd32(device, dsrc); 53 if (!(ssrc & 0x00000100)) 54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); 55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); 56 } 57 58 static u32 59 read_pll(struct gf100_clk *clk, u32 pll) 60 { 61 struct nvkm_device *device = clk->base.subdev.device; 62 u32 ctrl = nvkm_rd32(device, pll + 0x00); 63 u32 coef = nvkm_rd32(device, pll + 0x04); 64 u32 P = (coef & 0x003f0000) >> 16; 65 u32 N = (coef & 0x0000ff00) >> 8; 66 u32 M = (coef & 0x000000ff) >> 0; 67 u32 sclk; 68 69 if (!(ctrl & 0x00000001)) 70 return 0; 71 72 switch (pll) { 73 case 0x00e800: 74 case 0x00e820: 75 sclk = device->crystal; 76 P = 1; 77 break; 78 case 0x132000: 79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); 80 break; 81 case 0x132020: 82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); 83 break; 84 case 0x137000: 85 case 0x137020: 86 case 0x137040: 87 case 0x1370e0: 88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); 89 break; 90 default: 91 return 0; 92 } 93 94 return sclk * N / M / P; 95 } 96 97 static u32 98 read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl) 99 { 100 struct nvkm_device *device = clk->base.subdev.device; 101 u32 ssrc = nvkm_rd32(device, dsrc + (doff * 4)); 102 u32 sctl = nvkm_rd32(device, dctl + (doff * 4)); 103 104 switch (ssrc & 0x00000003) { 105 case 0: 106 if ((ssrc & 0x00030000) != 0x00030000) 107 return device->crystal; 108 return 108000; 109 case 2: 110 return 100000; 111 case 3: 112 if (sctl & 0x80000000) { 113 u32 sclk = read_vco(clk, dsrc + (doff * 4)); 114 u32 sdiv = (sctl & 0x0000003f) + 2; 115 return (sclk * 2) / sdiv; 116 } 117 118 return read_vco(clk, dsrc + (doff * 4)); 119 default: 120 return 0; 121 } 122 } 123 124 static u32 125 read_clk(struct gf100_clk *clk, int idx) 126 { 127 struct nvkm_device *device = clk->base.subdev.device; 128 u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); 129 u32 ssel = nvkm_rd32(device, 0x137100); 130 u32 sclk, sdiv; 131 132 if (ssel & (1 << idx)) { 133 if (idx < 7) 134 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); 135 else 136 sclk = read_pll(clk, 0x1370e0); 137 sdiv = ((sctl & 0x00003f00) >> 8) + 2; 138 } else { 139 sclk = read_div(clk, idx, 0x137160, 0x1371d0); 140 sdiv = ((sctl & 0x0000003f) >> 0) + 2; 141 } 142 143 if (sctl & 0x80000000) 144 return (sclk * 2) / sdiv; 145 146 return sclk; 147 } 148 149 static int 150 gf100_clk_read(struct nvkm_clk *base, enum nv_clk_src src) 151 { 152 struct gf100_clk *clk = gf100_clk(base); 153 struct nvkm_subdev *subdev = &clk->base.subdev; 154 struct nvkm_device *device = subdev->device; 155 156 switch (src) { 157 case nv_clk_src_crystal: 158 return device->crystal; 159 case nv_clk_src_href: 160 return 100000; 161 case nv_clk_src_sppll0: 162 return read_pll(clk, 0x00e800); 163 case nv_clk_src_sppll1: 164 return read_pll(clk, 0x00e820); 165 166 case nv_clk_src_mpllsrcref: 167 return read_div(clk, 0, 0x137320, 0x137330); 168 case nv_clk_src_mpllsrc: 169 return read_pll(clk, 0x132020); 170 case nv_clk_src_mpll: 171 return read_pll(clk, 0x132000); 172 case nv_clk_src_mdiv: 173 return read_div(clk, 0, 0x137300, 0x137310); 174 case nv_clk_src_mem: 175 if (nvkm_rd32(device, 0x1373f0) & 0x00000002) 176 return nvkm_clk_read(&clk->base, nv_clk_src_mpll); 177 return nvkm_clk_read(&clk->base, nv_clk_src_mdiv); 178 179 case nv_clk_src_gpc: 180 return read_clk(clk, 0x00); 181 case nv_clk_src_rop: 182 return read_clk(clk, 0x01); 183 case nv_clk_src_hubk07: 184 return read_clk(clk, 0x02); 185 case nv_clk_src_hubk06: 186 return read_clk(clk, 0x07); 187 case nv_clk_src_hubk01: 188 return read_clk(clk, 0x08); 189 case nv_clk_src_copy: 190 return read_clk(clk, 0x09); 191 case nv_clk_src_daemon: 192 return read_clk(clk, 0x0c); 193 case nv_clk_src_vdec: 194 return read_clk(clk, 0x0e); 195 default: 196 nvkm_error(subdev, "invalid clock source %d\n", src); 197 return -EINVAL; 198 } 199 } 200 201 static u32 202 calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) 203 { 204 u32 div = min((ref * 2) / freq, (u32)65); 205 if (div < 2) 206 div = 2; 207 208 *ddiv = div - 2; 209 return (ref * 2) / div; 210 } 211 212 static u32 213 calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) 214 { 215 u32 sclk; 216 217 /* use one of the fixed frequencies if possible */ 218 *ddiv = 0x00000000; 219 switch (freq) { 220 case 27000: 221 case 108000: 222 *dsrc = 0x00000000; 223 if (freq == 108000) 224 *dsrc |= 0x00030000; 225 return freq; 226 case 100000: 227 *dsrc = 0x00000002; 228 return freq; 229 default: 230 *dsrc = 0x00000003; 231 break; 232 } 233 234 /* otherwise, calculate the closest divider */ 235 sclk = read_vco(clk, 0x137160 + (idx * 4)); 236 if (idx < 7) 237 sclk = calc_div(clk, idx, sclk, freq, ddiv); 238 return sclk; 239 } 240 241 static u32 242 calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef) 243 { 244 struct nvkm_subdev *subdev = &clk->base.subdev; 245 struct nvkm_bios *bios = subdev->device->bios; 246 struct nvbios_pll limits; 247 int N, M, P, ret; 248 249 ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits); 250 if (ret) 251 return 0; 252 253 limits.refclk = read_div(clk, idx, 0x137120, 0x137140); 254 if (!limits.refclk) 255 return 0; 256 257 ret = gt215_pll_calc(subdev, &limits, freq, &N, NULL, &M, &P); 258 if (ret <= 0) 259 return 0; 260 261 *coef = (P << 16) | (N << 8) | M; 262 return ret; 263 } 264 265 static int 266 calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom) 267 { 268 struct gf100_clk_info *info = &clk->eng[idx]; 269 u32 freq = cstate->domain[dom]; 270 u32 src0, div0, div1D, div1P = 0; 271 u32 clk0, clk1 = 0; 272 273 /* invalid clock domain */ 274 if (!freq) 275 return 0; 276 277 /* first possible path, using only dividers */ 278 clk0 = calc_src(clk, idx, freq, &src0, &div0); 279 clk0 = calc_div(clk, idx, clk0, freq, &div1D); 280 281 /* see if we can get any closer using PLLs */ 282 if (clk0 != freq && (0x00004387 & (1 << idx))) { 283 if (idx <= 7) 284 clk1 = calc_pll(clk, idx, freq, &info->coef); 285 else 286 clk1 = cstate->domain[nv_clk_src_hubk06]; 287 clk1 = calc_div(clk, idx, clk1, freq, &div1P); 288 } 289 290 /* select the method which gets closest to target freq */ 291 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { 292 info->dsrc = src0; 293 if (div0) { 294 info->ddiv |= 0x80000000; 295 info->ddiv |= div0 << 8; 296 info->ddiv |= div0; 297 } 298 if (div1D) { 299 info->mdiv |= 0x80000000; 300 info->mdiv |= div1D; 301 } 302 info->ssel = info->coef = 0; 303 info->freq = clk0; 304 } else { 305 if (div1P) { 306 info->mdiv |= 0x80000000; 307 info->mdiv |= div1P << 8; 308 } 309 info->ssel = (1 << idx); 310 info->freq = clk1; 311 } 312 313 return 0; 314 } 315 316 static int 317 gf100_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate) 318 { 319 struct gf100_clk *clk = gf100_clk(base); 320 int ret; 321 322 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || 323 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || 324 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || 325 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || 326 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || 327 (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) || 328 (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) || 329 (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) 330 return ret; 331 332 return 0; 333 } 334 335 static void 336 gf100_clk_prog_0(struct gf100_clk *clk, int idx) 337 { 338 struct gf100_clk_info *info = &clk->eng[idx]; 339 struct nvkm_device *device = clk->base.subdev.device; 340 if (idx < 7 && !info->ssel) { 341 nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv); 342 nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc); 343 } 344 } 345 346 static void 347 gf100_clk_prog_1(struct gf100_clk *clk, int idx) 348 { 349 struct nvkm_device *device = clk->base.subdev.device; 350 nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); 351 nvkm_msec(device, 2000, 352 if (!(nvkm_rd32(device, 0x137100) & (1 << idx))) 353 break; 354 ); 355 } 356 357 static void 358 gf100_clk_prog_2(struct gf100_clk *clk, int idx) 359 { 360 struct gf100_clk_info *info = &clk->eng[idx]; 361 struct nvkm_device *device = clk->base.subdev.device; 362 const u32 addr = 0x137000 + (idx * 0x20); 363 if (idx <= 7) { 364 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); 365 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); 366 if (info->coef) { 367 nvkm_wr32(device, addr + 0x04, info->coef); 368 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); 369 nvkm_msec(device, 2000, 370 if (nvkm_rd32(device, addr + 0x00) & 0x00020000) 371 break; 372 ); 373 nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); 374 } 375 } 376 } 377 378 static void 379 gf100_clk_prog_3(struct gf100_clk *clk, int idx) 380 { 381 struct gf100_clk_info *info = &clk->eng[idx]; 382 struct nvkm_device *device = clk->base.subdev.device; 383 if (info->ssel) { 384 nvkm_mask(device, 0x137100, (1 << idx), info->ssel); 385 nvkm_msec(device, 2000, 386 u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx); 387 if (tmp == info->ssel) 388 break; 389 ); 390 } 391 } 392 393 static void 394 gf100_clk_prog_4(struct gf100_clk *clk, int idx) 395 { 396 struct gf100_clk_info *info = &clk->eng[idx]; 397 struct nvkm_device *device = clk->base.subdev.device; 398 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv); 399 } 400 401 static int 402 gf100_clk_prog(struct nvkm_clk *base) 403 { 404 struct gf100_clk *clk = gf100_clk(base); 405 struct { 406 void (*exec)(struct gf100_clk *, int); 407 } stage[] = { 408 { gf100_clk_prog_0 }, /* div programming */ 409 { gf100_clk_prog_1 }, /* select div mode */ 410 { gf100_clk_prog_2 }, /* (maybe) program pll */ 411 { gf100_clk_prog_3 }, /* (maybe) select pll mode */ 412 { gf100_clk_prog_4 }, /* final divider */ 413 }; 414 int i, j; 415 416 for (i = 0; i < ARRAY_SIZE(stage); i++) { 417 for (j = 0; j < ARRAY_SIZE(clk->eng); j++) { 418 if (!clk->eng[j].freq) 419 continue; 420 stage[i].exec(clk, j); 421 } 422 } 423 424 return 0; 425 } 426 427 static void 428 gf100_clk_tidy(struct nvkm_clk *base) 429 { 430 struct gf100_clk *clk = gf100_clk(base); 431 memset(clk->eng, 0x00, sizeof(clk->eng)); 432 } 433 434 static const struct nvkm_clk_func 435 gf100_clk = { 436 .read = gf100_clk_read, 437 .calc = gf100_clk_calc, 438 .prog = gf100_clk_prog, 439 .tidy = gf100_clk_tidy, 440 .domains = { 441 { nv_clk_src_crystal, 0xff }, 442 { nv_clk_src_href , 0xff }, 443 { nv_clk_src_hubk06 , 0x00 }, 444 { nv_clk_src_hubk01 , 0x01 }, 445 { nv_clk_src_copy , 0x02 }, 446 { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, 447 { nv_clk_src_rop , 0x04 }, 448 { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, 449 { nv_clk_src_vdec , 0x06 }, 450 { nv_clk_src_daemon , 0x0a }, 451 { nv_clk_src_hubk07 , 0x0b }, 452 { nv_clk_src_max } 453 } 454 }; 455 456 int 457 gf100_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) 458 { 459 struct gf100_clk *clk; 460 461 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) 462 return -ENOMEM; 463 *pclk = &clk->base; 464 465 return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base); 466 } 467