1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/clk.h> 25 #include <subdev/bios.h> 26 #include <subdev/bios/boost.h> 27 #include <subdev/bios/cstep.h> 28 #include <subdev/bios/perf.h> 29 #include <subdev/fb.h> 30 #include <subdev/therm.h> 31 #include <subdev/volt.h> 32 33 #include <core/option.h> 34 35 /****************************************************************************** 36 * misc 37 *****************************************************************************/ 38 static u32 39 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, 40 u8 pstate, u8 domain, u32 input) 41 { 42 struct nvkm_bios *bios = nvkm_bios(clk); 43 struct nvbios_boostE boostE; 44 u8 ver, hdr, cnt, len; 45 u16 data; 46 47 data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE); 48 if (data) { 49 struct nvbios_boostS boostS; 50 u8 idx = 0, sver, shdr; 51 u16 subd; 52 53 input = max(boostE.min, input); 54 input = min(boostE.max, input); 55 do { 56 sver = ver; 57 shdr = hdr; 58 subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr, 59 cnt, len, &boostS); 60 if (subd && boostS.domain == domain) { 61 if (adjust) 62 input = input * boostS.percent / 100; 63 input = max(boostS.min, input); 64 input = min(boostS.max, input); 65 break; 66 } 67 } while (subd); 68 } 69 70 return input; 71 } 72 73 /****************************************************************************** 74 * C-States 75 *****************************************************************************/ 76 static int 77 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) 78 { 79 struct nvkm_therm *therm = nvkm_therm(clk); 80 struct nvkm_volt *volt = nvkm_volt(clk); 81 struct nvkm_cstate *cstate; 82 int ret; 83 84 if (!list_empty(&pstate->list)) { 85 cstate = list_entry(pstate->list.prev, typeof(*cstate), head); 86 } else { 87 cstate = &pstate->base; 88 } 89 90 if (therm) { 91 ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1); 92 if (ret && ret != -ENODEV) { 93 nv_error(clk, "failed to raise fan speed: %d\n", ret); 94 return ret; 95 } 96 } 97 98 if (volt) { 99 ret = volt->set_id(volt, cstate->voltage, +1); 100 if (ret && ret != -ENODEV) { 101 nv_error(clk, "failed to raise voltage: %d\n", ret); 102 return ret; 103 } 104 } 105 106 ret = clk->calc(clk, cstate); 107 if (ret == 0) { 108 ret = clk->prog(clk); 109 clk->tidy(clk); 110 } 111 112 if (volt) { 113 ret = volt->set_id(volt, cstate->voltage, -1); 114 if (ret && ret != -ENODEV) 115 nv_error(clk, "failed to lower voltage: %d\n", ret); 116 } 117 118 if (therm) { 119 ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1); 120 if (ret && ret != -ENODEV) 121 nv_error(clk, "failed to lower fan speed: %d\n", ret); 122 } 123 124 return ret; 125 } 126 127 static void 128 nvkm_cstate_del(struct nvkm_cstate *cstate) 129 { 130 list_del(&cstate->head); 131 kfree(cstate); 132 } 133 134 static int 135 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) 136 { 137 struct nvkm_bios *bios = nvkm_bios(clk); 138 struct nvkm_domain *domain = clk->domains; 139 struct nvkm_cstate *cstate = NULL; 140 struct nvbios_cstepX cstepX; 141 u8 ver, hdr; 142 u16 data; 143 144 data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX); 145 if (!data) 146 return -ENOENT; 147 148 cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); 149 if (!cstate) 150 return -ENOMEM; 151 152 *cstate = pstate->base; 153 cstate->voltage = cstepX.voltage; 154 155 while (domain && domain->name != nv_clk_src_max) { 156 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { 157 u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, 158 domain->bios, cstepX.freq); 159 cstate->domain[domain->name] = freq; 160 } 161 domain++; 162 } 163 164 list_add(&cstate->head, &pstate->list); 165 return 0; 166 } 167 168 /****************************************************************************** 169 * P-States 170 *****************************************************************************/ 171 static int 172 nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) 173 { 174 struct nvkm_fb *fb = nvkm_fb(clk); 175 struct nvkm_pstate *pstate; 176 int ret, idx = 0; 177 178 list_for_each_entry(pstate, &clk->states, head) { 179 if (idx++ == pstatei) 180 break; 181 } 182 183 nv_debug(clk, "setting performance state %d\n", pstatei); 184 clk->pstate = pstatei; 185 186 if (fb->ram && fb->ram->calc) { 187 int khz = pstate->base.domain[nv_clk_src_mem]; 188 do { 189 ret = fb->ram->calc(fb, khz); 190 if (ret == 0) 191 ret = fb->ram->prog(fb); 192 } while (ret > 0); 193 fb->ram->tidy(fb); 194 } 195 196 return nvkm_cstate_prog(clk, pstate, 0); 197 } 198 199 static void 200 nvkm_pstate_work(struct work_struct *work) 201 { 202 struct nvkm_clk *clk = container_of(work, typeof(*clk), work); 203 int pstate; 204 205 if (!atomic_xchg(&clk->waiting, 0)) 206 return; 207 clk->pwrsrc = power_supply_is_system_supplied(); 208 209 nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", 210 clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, 211 clk->astate, clk->tstate, clk->dstate); 212 213 pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; 214 if (clk->state_nr && pstate != -1) { 215 pstate = (pstate < 0) ? clk->astate : pstate; 216 pstate = min(pstate, clk->state_nr - 1 + clk->tstate); 217 pstate = max(pstate, clk->dstate); 218 } else { 219 pstate = clk->pstate = -1; 220 } 221 222 nv_trace(clk, "-> %d\n", pstate); 223 if (pstate != clk->pstate) { 224 int ret = nvkm_pstate_prog(clk, pstate); 225 if (ret) { 226 nv_error(clk, "error setting pstate %d: %d\n", 227 pstate, ret); 228 } 229 } 230 231 wake_up_all(&clk->wait); 232 nvkm_notify_get(&clk->pwrsrc_ntfy); 233 } 234 235 static int 236 nvkm_pstate_calc(struct nvkm_clk *clk, bool wait) 237 { 238 atomic_set(&clk->waiting, 1); 239 schedule_work(&clk->work); 240 if (wait) 241 wait_event(clk->wait, !atomic_read(&clk->waiting)); 242 return 0; 243 } 244 245 static void 246 nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) 247 { 248 struct nvkm_domain *clock = clk->domains - 1; 249 struct nvkm_cstate *cstate; 250 char info[3][32] = { "", "", "" }; 251 char name[4] = "--"; 252 int i = -1; 253 254 if (pstate->pstate != 0xff) 255 snprintf(name, sizeof(name), "%02x", pstate->pstate); 256 257 while ((++clock)->name != nv_clk_src_max) { 258 u32 lo = pstate->base.domain[clock->name]; 259 u32 hi = lo; 260 if (hi == 0) 261 continue; 262 263 nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo); 264 list_for_each_entry(cstate, &pstate->list, head) { 265 u32 freq = cstate->domain[clock->name]; 266 lo = min(lo, freq); 267 hi = max(hi, freq); 268 nv_debug(clk, "%10d KHz\n", freq); 269 } 270 271 if (clock->mname && ++i < ARRAY_SIZE(info)) { 272 lo /= clock->mdiv; 273 hi /= clock->mdiv; 274 if (lo == hi) { 275 snprintf(info[i], sizeof(info[i]), "%s %d MHz", 276 clock->mname, lo); 277 } else { 278 snprintf(info[i], sizeof(info[i]), 279 "%s %d-%d MHz", clock->mname, lo, hi); 280 } 281 } 282 } 283 284 nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]); 285 } 286 287 static void 288 nvkm_pstate_del(struct nvkm_pstate *pstate) 289 { 290 struct nvkm_cstate *cstate, *temp; 291 292 list_for_each_entry_safe(cstate, temp, &pstate->list, head) { 293 nvkm_cstate_del(cstate); 294 } 295 296 list_del(&pstate->head); 297 kfree(pstate); 298 } 299 300 static int 301 nvkm_pstate_new(struct nvkm_clk *clk, int idx) 302 { 303 struct nvkm_bios *bios = nvkm_bios(clk); 304 struct nvkm_domain *domain = clk->domains - 1; 305 struct nvkm_pstate *pstate; 306 struct nvkm_cstate *cstate; 307 struct nvbios_cstepE cstepE; 308 struct nvbios_perfE perfE; 309 u8 ver, hdr, cnt, len; 310 u16 data; 311 312 data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE); 313 if (!data) 314 return -EINVAL; 315 if (perfE.pstate == 0xff) 316 return 0; 317 318 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); 319 cstate = &pstate->base; 320 if (!pstate) 321 return -ENOMEM; 322 323 INIT_LIST_HEAD(&pstate->list); 324 325 pstate->pstate = perfE.pstate; 326 pstate->fanspeed = perfE.fanspeed; 327 cstate->voltage = perfE.voltage; 328 cstate->domain[nv_clk_src_core] = perfE.core; 329 cstate->domain[nv_clk_src_shader] = perfE.shader; 330 cstate->domain[nv_clk_src_mem] = perfE.memory; 331 cstate->domain[nv_clk_src_vdec] = perfE.vdec; 332 cstate->domain[nv_clk_src_dom6] = perfE.disp; 333 334 while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) { 335 struct nvbios_perfS perfS; 336 u8 sver = ver, shdr = hdr; 337 u32 perfSe = nvbios_perfSp(bios, data, domain->bios, 338 &sver, &shdr, cnt, len, &perfS); 339 if (perfSe == 0 || sver != 0x40) 340 continue; 341 342 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { 343 perfS.v40.freq = nvkm_clk_adjust(clk, false, 344 pstate->pstate, 345 domain->bios, 346 perfS.v40.freq); 347 } 348 349 cstate->domain[domain->name] = perfS.v40.freq; 350 } 351 352 data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE); 353 if (data) { 354 int idx = cstepE.index; 355 do { 356 nvkm_cstate_new(clk, idx, pstate); 357 } while(idx--); 358 } 359 360 nvkm_pstate_info(clk, pstate); 361 list_add_tail(&pstate->head, &clk->states); 362 clk->state_nr++; 363 return 0; 364 } 365 366 /****************************************************************************** 367 * Adjustment triggers 368 *****************************************************************************/ 369 static int 370 nvkm_clk_ustate_update(struct nvkm_clk *clk, int req) 371 { 372 struct nvkm_pstate *pstate; 373 int i = 0; 374 375 if (!clk->allow_reclock) 376 return -ENOSYS; 377 378 if (req != -1 && req != -2) { 379 list_for_each_entry(pstate, &clk->states, head) { 380 if (pstate->pstate == req) 381 break; 382 i++; 383 } 384 385 if (pstate->pstate != req) 386 return -EINVAL; 387 req = i; 388 } 389 390 return req + 2; 391 } 392 393 static int 394 nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) 395 { 396 int ret = 1; 397 398 if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) 399 return -2; 400 401 if (strncasecmpz(mode, "disabled", arglen)) { 402 char save = mode[arglen]; 403 long v; 404 405 ((char *)mode)[arglen] = '\0'; 406 if (!kstrtol(mode, 0, &v)) { 407 ret = nvkm_clk_ustate_update(clk, v); 408 if (ret < 0) 409 ret = 1; 410 } 411 ((char *)mode)[arglen] = save; 412 } 413 414 return ret - 2; 415 } 416 417 int 418 nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr) 419 { 420 int ret = nvkm_clk_ustate_update(clk, req); 421 if (ret >= 0) { 422 if (ret -= 2, pwr) clk->ustate_ac = ret; 423 else clk->ustate_dc = ret; 424 return nvkm_pstate_calc(clk, true); 425 } 426 return ret; 427 } 428 429 int 430 nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait) 431 { 432 if (!rel) clk->astate = req; 433 if ( rel) clk->astate += rel; 434 clk->astate = min(clk->astate, clk->state_nr - 1); 435 clk->astate = max(clk->astate, 0); 436 return nvkm_pstate_calc(clk, wait); 437 } 438 439 int 440 nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel) 441 { 442 if (!rel) clk->tstate = req; 443 if ( rel) clk->tstate += rel; 444 clk->tstate = min(clk->tstate, 0); 445 clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); 446 return nvkm_pstate_calc(clk, true); 447 } 448 449 int 450 nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel) 451 { 452 if (!rel) clk->dstate = req; 453 if ( rel) clk->dstate += rel; 454 clk->dstate = min(clk->dstate, clk->state_nr - 1); 455 clk->dstate = max(clk->dstate, 0); 456 return nvkm_pstate_calc(clk, true); 457 } 458 459 static int 460 nvkm_clk_pwrsrc(struct nvkm_notify *notify) 461 { 462 struct nvkm_clk *clk = 463 container_of(notify, typeof(*clk), pwrsrc_ntfy); 464 nvkm_pstate_calc(clk, false); 465 return NVKM_NOTIFY_DROP; 466 } 467 468 /****************************************************************************** 469 * subdev base class implementation 470 *****************************************************************************/ 471 472 int 473 _nvkm_clk_fini(struct nvkm_object *object, bool suspend) 474 { 475 struct nvkm_clk *clk = (void *)object; 476 nvkm_notify_put(&clk->pwrsrc_ntfy); 477 return nvkm_subdev_fini(&clk->subdev, suspend); 478 } 479 480 int 481 _nvkm_clk_init(struct nvkm_object *object) 482 { 483 struct nvkm_clk *clk = (void *)object; 484 struct nvkm_domain *clock = clk->domains; 485 int ret; 486 487 ret = nvkm_subdev_init(&clk->subdev); 488 if (ret) 489 return ret; 490 491 memset(&clk->bstate, 0x00, sizeof(clk->bstate)); 492 INIT_LIST_HEAD(&clk->bstate.list); 493 clk->bstate.pstate = 0xff; 494 495 while (clock->name != nv_clk_src_max) { 496 ret = clk->read(clk, clock->name); 497 if (ret < 0) { 498 nv_error(clk, "%02x freq unknown\n", clock->name); 499 return ret; 500 } 501 clk->bstate.base.domain[clock->name] = ret; 502 clock++; 503 } 504 505 nvkm_pstate_info(clk, &clk->bstate); 506 507 clk->astate = clk->state_nr - 1; 508 clk->tstate = 0; 509 clk->dstate = 0; 510 clk->pstate = -1; 511 nvkm_pstate_calc(clk, true); 512 return 0; 513 } 514 515 void 516 _nvkm_clk_dtor(struct nvkm_object *object) 517 { 518 struct nvkm_clk *clk = (void *)object; 519 struct nvkm_pstate *pstate, *temp; 520 521 nvkm_notify_fini(&clk->pwrsrc_ntfy); 522 523 list_for_each_entry_safe(pstate, temp, &clk->states, head) { 524 nvkm_pstate_del(pstate); 525 } 526 527 nvkm_subdev_destroy(&clk->subdev); 528 } 529 530 int 531 nvkm_clk_create_(struct nvkm_object *parent, struct nvkm_object *engine, 532 struct nvkm_oclass *oclass, struct nvkm_domain *clocks, 533 struct nvkm_pstate *pstates, int nb_pstates, 534 bool allow_reclock, int length, void **object) 535 { 536 struct nvkm_device *device = nv_device(parent); 537 struct nvkm_clk *clk; 538 int ret, idx, arglen; 539 const char *mode; 540 541 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "CLK", 542 "clock", length, object); 543 clk = *object; 544 if (ret) 545 return ret; 546 547 INIT_LIST_HEAD(&clk->states); 548 clk->domains = clocks; 549 clk->ustate_ac = -1; 550 clk->ustate_dc = -1; 551 552 INIT_WORK(&clk->work, nvkm_pstate_work); 553 init_waitqueue_head(&clk->wait); 554 atomic_set(&clk->waiting, 0); 555 556 /* If no pstates are provided, try and fetch them from the BIOS */ 557 if (!pstates) { 558 idx = 0; 559 do { 560 ret = nvkm_pstate_new(clk, idx++); 561 } while (ret == 0); 562 } else { 563 for (idx = 0; idx < nb_pstates; idx++) 564 list_add_tail(&pstates[idx].head, &clk->states); 565 clk->state_nr = nb_pstates; 566 } 567 568 clk->allow_reclock = allow_reclock; 569 570 ret = nvkm_notify_init(NULL, &device->event, nvkm_clk_pwrsrc, true, 571 NULL, 0, 0, &clk->pwrsrc_ntfy); 572 if (ret) 573 return ret; 574 575 mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen); 576 if (mode) { 577 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); 578 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); 579 } 580 581 mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen); 582 if (mode) 583 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); 584 585 mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen); 586 if (mode) 587 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); 588 589 return 0; 590 } 591