xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c (revision 4de93a086eb0315f0bd8e1d6da40186842670b57)
1 /*
2  * Copyright 2012 Nouveau Community
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Martin Peres <martin.peres@labri.fr>
23  *          Ben Skeggs
24  */
25 #include "nv04.h"
26 
27 static void
28 nv04_bus_intr(struct nvkm_subdev *subdev)
29 {
30 	struct nvkm_bus *bus = nvkm_bus(subdev);
31 	struct nvkm_device *device = bus->subdev.device;
32 	u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140);
33 
34 	if (stat & 0x00000001) {
35 		nv_error(bus, "BUS ERROR\n");
36 		stat &= ~0x00000001;
37 		nvkm_wr32(device, 0x001100, 0x00000001);
38 	}
39 
40 	if (stat & 0x00000110) {
41 		subdev = nvkm_subdev(subdev, NVDEV_SUBDEV_GPIO);
42 		if (subdev && subdev->intr)
43 			subdev->intr(subdev);
44 		stat &= ~0x00000110;
45 		nvkm_wr32(device, 0x001100, 0x00000110);
46 	}
47 
48 	if (stat) {
49 		nv_error(bus, "unknown intr 0x%08x\n", stat);
50 		nvkm_mask(device, 0x001140, stat, 0x00000000);
51 	}
52 }
53 
54 static int
55 nv04_bus_init(struct nvkm_object *object)
56 {
57 	struct nvkm_bus *bus = (void *)object;
58 	struct nvkm_device *device = bus->subdev.device;
59 
60 	nvkm_wr32(device, 0x001100, 0xffffffff);
61 	nvkm_wr32(device, 0x001140, 0x00000111);
62 
63 	return nvkm_bus_init(bus);
64 }
65 
66 int
67 nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
68 	      struct nvkm_oclass *oclass, void *data, u32 size,
69 	      struct nvkm_object **pobject)
70 {
71 	struct nv04_bus_impl *impl = (void *)oclass;
72 	struct nvkm_bus *bus;
73 	int ret;
74 
75 	ret = nvkm_bus_create(parent, engine, oclass, &bus);
76 	*pobject = nv_object(bus);
77 	if (ret)
78 		return ret;
79 
80 	nv_subdev(bus)->intr = impl->intr;
81 	bus->hwsq_exec = impl->hwsq_exec;
82 	bus->hwsq_size = impl->hwsq_size;
83 	return 0;
84 }
85 
86 struct nvkm_oclass *
87 nv04_bus_oclass = &(struct nv04_bus_impl) {
88 	.base.handle = NV_SUBDEV(BUS, 0x04),
89 	.base.ofuncs = &(struct nvkm_ofuncs) {
90 		.ctor = nv04_bus_ctor,
91 		.dtor = _nvkm_bus_dtor,
92 		.init = nv04_bus_init,
93 		.fini = _nvkm_bus_fini,
94 	},
95 	.intr = nv04_bus_intr,
96 }.base;
97