1 /* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/pll.h> 28 #include <subdev/vga.h> 29 30 31 struct pll_mapping { 32 u8 type; 33 u32 reg; 34 }; 35 36 static struct pll_mapping 37 nv04_pll_mapping[] = { 38 { PLL_CORE , 0x680500 }, 39 { PLL_MEMORY, 0x680504 }, 40 { PLL_VPLL0 , 0x680508 }, 41 { PLL_VPLL1 , 0x680520 }, 42 {} 43 }; 44 45 static struct pll_mapping 46 nv40_pll_mapping[] = { 47 { PLL_CORE , 0x004000 }, 48 { PLL_MEMORY, 0x004020 }, 49 { PLL_VPLL0 , 0x680508 }, 50 { PLL_VPLL1 , 0x680520 }, 51 {} 52 }; 53 54 static struct pll_mapping 55 nv50_pll_mapping[] = { 56 { PLL_CORE , 0x004028 }, 57 { PLL_SHADER, 0x004020 }, 58 { PLL_UNK03 , 0x004000 }, 59 { PLL_MEMORY, 0x004008 }, 60 { PLL_UNK40 , 0x00e810 }, 61 { PLL_UNK41 , 0x00e818 }, 62 { PLL_UNK42 , 0x00e824 }, 63 { PLL_VPLL0 , 0x614100 }, 64 { PLL_VPLL1 , 0x614900 }, 65 {} 66 }; 67 68 static struct pll_mapping 69 g84_pll_mapping[] = { 70 { PLL_CORE , 0x004028 }, 71 { PLL_SHADER, 0x004020 }, 72 { PLL_MEMORY, 0x004008 }, 73 { PLL_VDEC , 0x004030 }, 74 { PLL_UNK41 , 0x00e818 }, 75 { PLL_VPLL0 , 0x614100 }, 76 { PLL_VPLL1 , 0x614900 }, 77 {} 78 }; 79 80 static u32 81 pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 82 { 83 struct bit_entry bit_C; 84 u32 data = 0x0000; 85 86 if (!bit_entry(bios, 'C', &bit_C)) { 87 if (bit_C.version == 1 && bit_C.length >= 10) 88 data = nvbios_rd16(bios, bit_C.offset + 8); 89 if (bit_C.version == 2 && bit_C.length >= 4) 90 data = nvbios_rd32(bios, bit_C.offset + 0); 91 if (data) { 92 *ver = nvbios_rd08(bios, data + 0); 93 *hdr = nvbios_rd08(bios, data + 1); 94 *len = nvbios_rd08(bios, data + 2); 95 *cnt = nvbios_rd08(bios, data + 3); 96 return data; 97 } 98 } 99 100 if (bmp_version(bios) >= 0x0524) { 101 data = nvbios_rd16(bios, bios->bmp_offset + 142); 102 if (data) { 103 *ver = nvbios_rd08(bios, data + 0); 104 *hdr = 1; 105 *cnt = 1; 106 *len = 0x18; 107 return data; 108 } 109 } 110 111 *ver = 0x00; 112 return data; 113 } 114 115 static struct pll_mapping * 116 pll_map(struct nvkm_bios *bios) 117 { 118 struct nvkm_device *device = bios->subdev.device; 119 switch (device->card_type) { 120 case NV_04: 121 case NV_10: 122 case NV_11: 123 case NV_20: 124 case NV_30: 125 return nv04_pll_mapping; 126 break; 127 case NV_40: 128 return nv40_pll_mapping; 129 case NV_50: 130 if (device->chipset == 0x50) 131 return nv50_pll_mapping; 132 else 133 if (device->chipset < 0xa3 || 134 device->chipset == 0xaa || 135 device->chipset == 0xac) 136 return g84_pll_mapping; 137 default: 138 return NULL; 139 } 140 } 141 142 static u32 143 pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) 144 { 145 struct pll_mapping *map; 146 u8 hdr, cnt; 147 u32 data; 148 149 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 150 if (data && *ver >= 0x30) { 151 data += hdr; 152 while (cnt--) { 153 if (nvbios_rd32(bios, data + 3) == reg) { 154 *type = nvbios_rd08(bios, data + 0); 155 return data; 156 } 157 data += *len; 158 } 159 return 0x0000; 160 } 161 162 map = pll_map(bios); 163 while (map && map->reg) { 164 if (map->reg == reg && *ver >= 0x20) { 165 u32 addr = (data += hdr); 166 *type = map->type; 167 while (cnt--) { 168 if (nvbios_rd32(bios, data) == map->reg) 169 return data; 170 data += *len; 171 } 172 return addr; 173 } else 174 if (map->reg == reg) { 175 *type = map->type; 176 return data + 1; 177 } 178 map++; 179 } 180 181 return 0x0000; 182 } 183 184 static u32 185 pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) 186 { 187 struct pll_mapping *map; 188 u8 hdr, cnt; 189 u32 data; 190 191 data = pll_limits_table(bios, ver, &hdr, &cnt, len); 192 if (data && *ver >= 0x30) { 193 data += hdr; 194 while (cnt--) { 195 if (nvbios_rd08(bios, data + 0) == type) { 196 *reg = nvbios_rd32(bios, data + 3); 197 return data; 198 } 199 data += *len; 200 } 201 return 0x0000; 202 } 203 204 map = pll_map(bios); 205 while (map && map->reg) { 206 if (map->type == type && *ver >= 0x20) { 207 u32 addr = (data += hdr); 208 *reg = map->reg; 209 while (cnt--) { 210 if (nvbios_rd32(bios, data) == map->reg) 211 return data; 212 data += *len; 213 } 214 return addr; 215 } else 216 if (map->type == type) { 217 *reg = map->reg; 218 return data + 1; 219 } 220 map++; 221 } 222 223 return 0x0000; 224 } 225 226 int 227 nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info) 228 { 229 struct nvkm_subdev *subdev = &bios->subdev; 230 struct nvkm_device *device = subdev->device; 231 u8 ver, len; 232 u32 reg = type; 233 u32 data; 234 235 if (type > PLL_MAX) { 236 reg = type; 237 data = pll_map_reg(bios, reg, &type, &ver, &len); 238 } else { 239 data = pll_map_type(bios, type, ®, &ver, &len); 240 } 241 242 if (ver && !data) 243 return -ENOENT; 244 245 memset(info, 0, sizeof(*info)); 246 info->type = type; 247 info->reg = reg; 248 249 switch (ver) { 250 case 0x00: 251 break; 252 case 0x10: 253 case 0x11: 254 info->vco1.min_freq = nvbios_rd32(bios, data + 0); 255 info->vco1.max_freq = nvbios_rd32(bios, data + 4); 256 info->vco2.min_freq = nvbios_rd32(bios, data + 8); 257 info->vco2.max_freq = nvbios_rd32(bios, data + 12); 258 info->vco1.min_inputfreq = nvbios_rd32(bios, data + 16); 259 info->vco2.min_inputfreq = nvbios_rd32(bios, data + 20); 260 info->vco1.max_inputfreq = INT_MAX; 261 info->vco2.max_inputfreq = INT_MAX; 262 263 info->max_p = 0x7; 264 info->max_p_usable = 0x6; 265 266 /* these values taken from nv30/31/36 */ 267 switch (bios->version.chip) { 268 case 0x36: 269 info->vco1.min_n = 0x5; 270 break; 271 default: 272 info->vco1.min_n = 0x1; 273 break; 274 } 275 info->vco1.max_n = 0xff; 276 info->vco1.min_m = 0x1; 277 info->vco1.max_m = 0xd; 278 279 /* 280 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 281 * table version (apart from nv35)), N2 is compared to 282 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 283 * save a comparison 284 */ 285 info->vco2.min_n = 0x4; 286 switch (bios->version.chip) { 287 case 0x30: 288 case 0x35: 289 info->vco2.max_n = 0x1f; 290 break; 291 default: 292 info->vco2.max_n = 0x28; 293 break; 294 } 295 info->vco2.min_m = 0x1; 296 info->vco2.max_m = 0x4; 297 break; 298 case 0x20: 299 case 0x21: 300 info->vco1.min_freq = nvbios_rd16(bios, data + 4) * 1000; 301 info->vco1.max_freq = nvbios_rd16(bios, data + 6) * 1000; 302 info->vco2.min_freq = nvbios_rd16(bios, data + 8) * 1000; 303 info->vco2.max_freq = nvbios_rd16(bios, data + 10) * 1000; 304 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 12) * 1000; 305 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 14) * 1000; 306 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 16) * 1000; 307 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 18) * 1000; 308 info->vco1.min_n = nvbios_rd08(bios, data + 20); 309 info->vco1.max_n = nvbios_rd08(bios, data + 21); 310 info->vco1.min_m = nvbios_rd08(bios, data + 22); 311 info->vco1.max_m = nvbios_rd08(bios, data + 23); 312 info->vco2.min_n = nvbios_rd08(bios, data + 24); 313 info->vco2.max_n = nvbios_rd08(bios, data + 25); 314 info->vco2.min_m = nvbios_rd08(bios, data + 26); 315 info->vco2.max_m = nvbios_rd08(bios, data + 27); 316 317 info->max_p = nvbios_rd08(bios, data + 29); 318 info->max_p_usable = info->max_p; 319 if (bios->version.chip < 0x60) 320 info->max_p_usable = 0x6; 321 info->bias_p = nvbios_rd08(bios, data + 30); 322 323 if (len > 0x22) 324 info->refclk = nvbios_rd32(bios, data + 31); 325 break; 326 case 0x30: 327 data = nvbios_rd16(bios, data + 1); 328 329 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000; 330 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000; 331 info->vco2.min_freq = nvbios_rd16(bios, data + 4) * 1000; 332 info->vco2.max_freq = nvbios_rd16(bios, data + 6) * 1000; 333 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 8) * 1000; 334 info->vco2.min_inputfreq = nvbios_rd16(bios, data + 10) * 1000; 335 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 12) * 1000; 336 info->vco2.max_inputfreq = nvbios_rd16(bios, data + 14) * 1000; 337 info->vco1.min_n = nvbios_rd08(bios, data + 16); 338 info->vco1.max_n = nvbios_rd08(bios, data + 17); 339 info->vco1.min_m = nvbios_rd08(bios, data + 18); 340 info->vco1.max_m = nvbios_rd08(bios, data + 19); 341 info->vco2.min_n = nvbios_rd08(bios, data + 20); 342 info->vco2.max_n = nvbios_rd08(bios, data + 21); 343 info->vco2.min_m = nvbios_rd08(bios, data + 22); 344 info->vco2.max_m = nvbios_rd08(bios, data + 23); 345 info->max_p_usable = info->max_p = nvbios_rd08(bios, data + 25); 346 info->bias_p = nvbios_rd08(bios, data + 27); 347 info->refclk = nvbios_rd32(bios, data + 28); 348 break; 349 case 0x40: 350 info->refclk = nvbios_rd16(bios, data + 9) * 1000; 351 data = nvbios_rd16(bios, data + 1); 352 353 info->vco1.min_freq = nvbios_rd16(bios, data + 0) * 1000; 354 info->vco1.max_freq = nvbios_rd16(bios, data + 2) * 1000; 355 info->vco1.min_inputfreq = nvbios_rd16(bios, data + 4) * 1000; 356 info->vco1.max_inputfreq = nvbios_rd16(bios, data + 6) * 1000; 357 info->vco1.min_m = nvbios_rd08(bios, data + 8); 358 info->vco1.max_m = nvbios_rd08(bios, data + 9); 359 info->vco1.min_n = nvbios_rd08(bios, data + 10); 360 info->vco1.max_n = nvbios_rd08(bios, data + 11); 361 info->min_p = nvbios_rd08(bios, data + 12); 362 info->max_p = nvbios_rd08(bios, data + 13); 363 break; 364 default: 365 nvkm_error(subdev, "unknown pll limits version 0x%02x\n", ver); 366 return -EINVAL; 367 } 368 369 if (!info->refclk) { 370 info->refclk = device->crystal; 371 if (bios->version.chip == 0x51) { 372 u32 sel_clk = nvkm_rd32(device, 0x680524); 373 if ((info->reg == 0x680508 && sel_clk & 0x20) || 374 (info->reg == 0x680520 && sel_clk & 0x80)) { 375 if (nvkm_rdvgac(device, 0, 0x27) < 0xa3) 376 info->refclk = 200000; 377 else 378 info->refclk = 25000; 379 } 380 } 381 } 382 383 /* 384 * By now any valid limit table ought to have set a max frequency for 385 * vco1, so if it's zero it's either a pre limit table bios, or one 386 * with an empty limit table (seen on nv18) 387 */ 388 if (!info->vco1.max_freq) { 389 info->vco1.max_freq = nvbios_rd32(bios, bios->bmp_offset + 67); 390 info->vco1.min_freq = nvbios_rd32(bios, bios->bmp_offset + 71); 391 if (bmp_version(bios) < 0x0506) { 392 info->vco1.max_freq = 256000; 393 info->vco1.min_freq = 128000; 394 } 395 396 info->vco1.min_inputfreq = 0; 397 info->vco1.max_inputfreq = INT_MAX; 398 info->vco1.min_n = 0x1; 399 info->vco1.max_n = 0xff; 400 info->vco1.min_m = 0x1; 401 402 if (device->crystal == 13500) { 403 /* nv05 does this, nv11 doesn't, nv10 unknown */ 404 if (bios->version.chip < 0x11) 405 info->vco1.min_m = 0x7; 406 info->vco1.max_m = 0xd; 407 } else { 408 if (bios->version.chip < 0x11) 409 info->vco1.min_m = 0x8; 410 info->vco1.max_m = 0xe; 411 } 412 413 if (bios->version.chip < 0x17 || 414 bios->version.chip == 0x1a || 415 bios->version.chip == 0x20) 416 info->max_p = 4; 417 else 418 info->max_p = 5; 419 info->max_p_usable = info->max_p; 420 } 421 422 return 0; 423 } 424