1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/mxm.h> 27 28 u16 29 mxm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr) 30 { 31 struct bit_entry x; 32 33 if (bit_entry(bios, 'x', &x)) { 34 nv_debug(bios, "BIT 'x' table not present\n"); 35 return 0x0000; 36 } 37 38 *ver = x.version; 39 *hdr = x.length; 40 if (*ver != 1 || *hdr < 3) { 41 nv_warn(bios, "BIT 'x' table %d/%d unknown\n", *ver, *hdr); 42 return 0x0000; 43 } 44 45 return x.offset; 46 } 47 48 /* These map MXM v2.x digital connection values to the appropriate SOR/link, 49 * hopefully they're correct for all boards within the same chipset... 50 * 51 * MXM v3.x VBIOS are nicer and provide pointers to these tables. 52 */ 53 static u8 g84_sor_map[16] = { 54 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, 55 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 56 }; 57 58 static u8 g92_sor_map[16] = { 59 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, 60 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 61 }; 62 63 static u8 g94_sor_map[16] = { 64 0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31, 65 0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00 66 }; 67 68 static u8 g98_sor_map[16] = { 69 0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31, 70 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 71 }; 72 73 u8 74 mxm_sor_map(struct nvkm_bios *bios, u8 conn) 75 { 76 u8 ver, hdr; 77 u16 mxm = mxm_table(bios, &ver, &hdr); 78 if (mxm && hdr >= 6) { 79 u16 map = nv_ro16(bios, mxm + 4); 80 if (map) { 81 ver = nv_ro08(bios, map); 82 if (ver == 0x10) { 83 if (conn < nv_ro08(bios, map + 3)) { 84 map += nv_ro08(bios, map + 1); 85 map += conn; 86 return nv_ro08(bios, map); 87 } 88 89 return 0x00; 90 } 91 92 nv_warn(bios, "unknown sor map v%02x\n", ver); 93 } 94 } 95 96 if (bios->version.chip == 0x84 || bios->version.chip == 0x86) 97 return g84_sor_map[conn]; 98 if (bios->version.chip == 0x92) 99 return g92_sor_map[conn]; 100 if (bios->version.chip == 0x94 || bios->version.chip == 0x96) 101 return g94_sor_map[conn]; 102 if (bios->version.chip == 0x98) 103 return g98_sor_map[conn]; 104 105 nv_warn(bios, "missing sor map\n"); 106 return 0x00; 107 } 108 109 u8 110 mxm_ddc_map(struct nvkm_bios *bios, u8 port) 111 { 112 u8 ver, hdr; 113 u16 mxm = mxm_table(bios, &ver, &hdr); 114 if (mxm && hdr >= 8) { 115 u16 map = nv_ro16(bios, mxm + 6); 116 if (map) { 117 ver = nv_ro08(bios, map); 118 if (ver == 0x10) { 119 if (port < nv_ro08(bios, map + 3)) { 120 map += nv_ro08(bios, map + 1); 121 map += port; 122 return nv_ro08(bios, map); 123 } 124 125 return 0x00; 126 } 127 128 nv_warn(bios, "unknown ddc map v%02x\n", ver); 129 } 130 } 131 132 /* v2.x: directly write port as dcb i2cidx */ 133 return (port << 4) | port; 134 } 135