1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 #include <core/gpuobj.h> 27 #include <subdev/fb.h> 28 #include <subdev/mmu.h> 29 #include <subdev/timer.h> 30 31 static void 32 nv50_bar_flush(struct nvkm_bar *base) 33 { 34 struct nv50_bar *bar = nv50_bar(base); 35 struct nvkm_device *device = bar->base.subdev.device; 36 unsigned long flags; 37 spin_lock_irqsave(&bar->base.lock, flags); 38 nvkm_wr32(device, 0x00330c, 0x00000001); 39 nvkm_msec(device, 2000, 40 if (!(nvkm_rd32(device, 0x00330c) & 0x00000002)) 41 break; 42 ); 43 spin_unlock_irqrestore(&bar->base.lock, flags); 44 } 45 46 struct nvkm_vmm * 47 nv50_bar_bar1_vmm(struct nvkm_bar *base) 48 { 49 return nv50_bar(base)->bar1_vmm; 50 } 51 52 void 53 nv50_bar_bar1_wait(struct nvkm_bar *base) 54 { 55 nvkm_bar_flush(base); 56 } 57 58 void 59 nv50_bar_bar1_fini(struct nvkm_bar *bar) 60 { 61 nvkm_wr32(bar->subdev.device, 0x001708, 0x00000000); 62 } 63 64 void 65 nv50_bar_bar1_init(struct nvkm_bar *base) 66 { 67 struct nvkm_device *device = base->subdev.device; 68 struct nv50_bar *bar = nv50_bar(base); 69 nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4); 70 } 71 72 struct nvkm_vmm * 73 nv50_bar_bar2_vmm(struct nvkm_bar *base) 74 { 75 return nv50_bar(base)->bar2_vmm; 76 } 77 78 void 79 nv50_bar_bar2_fini(struct nvkm_bar *bar) 80 { 81 nvkm_wr32(bar->subdev.device, 0x00170c, 0x00000000); 82 } 83 84 void 85 nv50_bar_bar2_init(struct nvkm_bar *base) 86 { 87 struct nvkm_device *device = base->subdev.device; 88 struct nv50_bar *bar = nv50_bar(base); 89 nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12); 90 nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12); 91 nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4); 92 } 93 94 void 95 nv50_bar_init(struct nvkm_bar *base) 96 { 97 struct nv50_bar *bar = nv50_bar(base); 98 struct nvkm_device *device = bar->base.subdev.device; 99 int i; 100 101 for (i = 0; i < 8; i++) 102 nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000); 103 } 104 105 int 106 nv50_bar_oneinit(struct nvkm_bar *base) 107 { 108 struct nv50_bar *bar = nv50_bar(base); 109 struct nvkm_device *device = bar->base.subdev.device; 110 static struct lock_class_key bar1_lock; 111 static struct lock_class_key bar2_lock; 112 u64 start, limit; 113 int ret; 114 115 ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem); 116 if (ret) 117 return ret; 118 119 ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem, 120 &bar->pad); 121 if (ret) 122 return ret; 123 124 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, bar->mem, &bar->pgd); 125 if (ret) 126 return ret; 127 128 /* BAR2 */ 129 start = 0x0100000000ULL; 130 limit = start + device->func->resource_size(device, 3); 131 132 ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0, 133 &bar2_lock, "bar2", &bar->bar2_vmm); 134 if (ret) 135 return ret; 136 137 atomic_inc(&bar->bar2_vmm->engref[NVKM_SUBDEV_BAR]); 138 bar->bar2_vmm->debug = bar->base.subdev.debug; 139 140 ret = nvkm_vmm_boot(bar->bar2_vmm); 141 if (ret) 142 return ret; 143 144 ret = nvkm_vmm_join(bar->bar2_vmm, bar->mem->memory); 145 if (ret) 146 return ret; 147 148 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar2); 149 if (ret) 150 return ret; 151 152 nvkm_kmap(bar->bar2); 153 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000); 154 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); 155 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); 156 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | 157 upper_32_bits(start)); 158 nvkm_wo32(bar->bar2, 0x10, 0x00000000); 159 nvkm_wo32(bar->bar2, 0x14, 0x00000000); 160 nvkm_done(bar->bar2); 161 162 bar->base.subdev.oneinit = true; 163 nvkm_bar_bar2_init(device); 164 165 /* BAR1 */ 166 start = 0x0000000000ULL; 167 limit = start + device->func->resource_size(device, 1); 168 169 ret = nvkm_vmm_new(device, start, limit-- - start, NULL, 0, 170 &bar1_lock, "bar1", &bar->bar1_vmm); 171 172 atomic_inc(&bar->bar1_vmm->engref[NVKM_SUBDEV_BAR]); 173 bar->bar1_vmm->debug = bar->base.subdev.debug; 174 175 ret = nvkm_vmm_join(bar->bar1_vmm, bar->mem->memory); 176 if (ret) 177 return ret; 178 179 ret = nvkm_gpuobj_new(device, 24, 16, false, bar->mem, &bar->bar1); 180 if (ret) 181 return ret; 182 183 nvkm_kmap(bar->bar1); 184 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000); 185 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); 186 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); 187 nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24 | 188 upper_32_bits(start)); 189 nvkm_wo32(bar->bar1, 0x10, 0x00000000); 190 nvkm_wo32(bar->bar1, 0x14, 0x00000000); 191 nvkm_done(bar->bar1); 192 return 0; 193 } 194 195 void * 196 nv50_bar_dtor(struct nvkm_bar *base) 197 { 198 struct nv50_bar *bar = nv50_bar(base); 199 if (bar->mem) { 200 nvkm_gpuobj_del(&bar->bar1); 201 nvkm_vmm_part(bar->bar1_vmm, bar->mem->memory); 202 nvkm_vmm_unref(&bar->bar1_vmm); 203 nvkm_gpuobj_del(&bar->bar2); 204 nvkm_vmm_part(bar->bar2_vmm, bar->mem->memory); 205 nvkm_vmm_unref(&bar->bar2_vmm); 206 nvkm_gpuobj_del(&bar->pgd); 207 nvkm_gpuobj_del(&bar->pad); 208 nvkm_gpuobj_del(&bar->mem); 209 } 210 return bar; 211 } 212 213 int 214 nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device, 215 int index, u32 pgd_addr, struct nvkm_bar **pbar) 216 { 217 struct nv50_bar *bar; 218 if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL))) 219 return -ENOMEM; 220 nvkm_bar_ctor(func, device, index, &bar->base); 221 bar->pgd_addr = pgd_addr; 222 *pbar = &bar->base; 223 return 0; 224 } 225 226 static const struct nvkm_bar_func 227 nv50_bar_func = { 228 .dtor = nv50_bar_dtor, 229 .oneinit = nv50_bar_oneinit, 230 .init = nv50_bar_init, 231 .bar1.init = nv50_bar_bar1_init, 232 .bar1.fini = nv50_bar_bar1_fini, 233 .bar1.wait = nv50_bar_bar1_wait, 234 .bar1.vmm = nv50_bar_bar1_vmm, 235 .bar2.init = nv50_bar_bar2_init, 236 .bar2.fini = nv50_bar_bar2_fini, 237 .bar2.wait = nv50_bar_bar1_wait, 238 .bar2.vmm = nv50_bar_bar2_vmm, 239 .flush = nv50_bar_flush, 240 }; 241 242 int 243 nv50_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar) 244 { 245 return nv50_bar_new_(&nv50_bar_func, device, index, 0x1400, pbar); 246 } 247