1 /* 2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 * DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 24 #include <core/gpuobj.h> 25 #include <core/memory.h> 26 #include <subdev/timer.h> 27 28 void 29 nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start, 30 u32 size, u16 tag, u8 port, bool secure) 31 { 32 u8 rem = size % 4; 33 u32 reg; 34 int i; 35 36 size -= rem; 37 38 reg = start | BIT(24) | (secure ? BIT(28) : 0); 39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); 40 for (i = 0; i < size / 4; i++) { 41 /* write new tag every 256B */ 42 if ((i & 0x3f) == 0) 43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); 44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); 45 } 46 47 /* 48 * If size is not a multiple of 4, mask the last work to ensure garbage 49 * does not get written 50 */ 51 if (rem) { 52 u32 extra = ((u32 *)data)[i]; 53 54 /* write new tag every 256B */ 55 if ((i & 0x3f) == 0) 56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); 57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 58 extra & (BIT(rem * 8) - 1)); 59 ++i; 60 } 61 62 /* code must be padded to 0x40 words */ 63 for (; i & 0x3f; i++) 64 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), 0); 65 } 66 67 void 68 nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start, 69 u32 size, u8 port) 70 { 71 u8 rem = size % 4; 72 int i; 73 74 size -= rem; 75 76 nvkm_falcon_wr32(falcon, 0x1c0 + (port * 8), start | (0x1 << 24)); 77 for (i = 0; i < size / 4; i++) 78 nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), ((u32 *)data)[i]); 79 80 /* 81 * If size is not a multiple of 4, mask the last word to ensure garbage 82 * does not get written 83 */ 84 if (rem) { 85 u32 extra = ((u32 *)data)[i]; 86 87 nvkm_falcon_wr32(falcon, 0x1c4 + (port * 8), 88 extra & (BIT(rem * 8) - 1)); 89 } 90 } 91 92 void 93 nvkm_falcon_v1_start(struct nvkm_falcon *falcon) 94 { 95 u32 reg = nvkm_falcon_rd32(falcon, 0x100); 96 97 if (reg & BIT(6)) 98 nvkm_falcon_wr32(falcon, 0x130, 0x2); 99 else 100 nvkm_falcon_wr32(falcon, 0x100, 0x2); 101 } 102