xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h (revision 4b660dbd9ee2059850fd30e0df420ca7a38a1856)
1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVKM_SEC2_PRIV_H__
3 #define __NVKM_SEC2_PRIV_H__
4 #include <engine/sec2.h>
5 struct nvkm_acr_lsfw;
6 
7 int r535_sec2_new(const struct nvkm_sec2_func *,
8 		  struct nvkm_device *, enum nvkm_subdev_type, int, u32 addr, struct nvkm_sec2 **);
9 
10 struct nvkm_sec2_func {
11 	const struct nvkm_falcon_func *flcn;
12 	u8 unit_unload;
13 	u8 unit_acr;
14 	struct nvkm_intr *(*intr_vector)(struct nvkm_sec2 *, enum nvkm_intr_type *);
15 	irqreturn_t (*intr)(struct nvkm_inth *);
16 	int (*initmsg)(struct nvkm_sec2 *);
17 };
18 
19 irqreturn_t gp102_sec2_intr(struct nvkm_inth *);
20 int gp102_sec2_initmsg(struct nvkm_sec2 *);
21 
22 struct nvkm_sec2_fwif {
23 	int version;
24 	int (*load)(struct nvkm_sec2 *, int ver, const struct nvkm_sec2_fwif *);
25 	const struct nvkm_sec2_func *func;
26 	const struct nvkm_acr_lsf_func *acr;
27 };
28 
29 int gp102_sec2_nofw(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *);
30 int gp102_sec2_load(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *);
31 extern const struct nvkm_sec2_func gp102_sec2;
32 extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1;
33 void gp102_sec2_acr_bld_write_1(struct nvkm_acr *, u32, struct nvkm_acr_lsfw *);
34 void gp102_sec2_acr_bld_patch_1(struct nvkm_acr *, u32, s64);
35 
36 int nvkm_sec2_new_(const struct nvkm_sec2_fwif *, struct nvkm_device *, enum nvkm_subdev_type,
37 		   int, u32 addr, struct nvkm_sec2 **);
38 #endif
39