xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c (revision 3a8c3400f3e74638bedd0d2410416aa8b794c0fd)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 #include <engine/mpeg.h>
25 
26 #include <core/client.h>
27 #include <core/handle.h>
28 #include <engine/fifo.h>
29 
30 struct nv44_mpeg_chan {
31 	struct nvkm_mpeg_chan base;
32 };
33 
34 /*******************************************************************************
35  * PMPEG context
36  ******************************************************************************/
37 
38 static int
39 nv44_mpeg_context_ctor(struct nvkm_object *parent,
40 		       struct nvkm_object *engine,
41 		       struct nvkm_oclass *oclass, void *data, u32 size,
42 		       struct nvkm_object **pobject)
43 {
44 	struct nv44_mpeg_chan *chan;
45 	int ret;
46 
47 	ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 264 * 4,
48 				       16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
49 	*pobject = nv_object(chan);
50 	if (ret)
51 		return ret;
52 
53 	nvkm_kmap(&chan->base.base.gpuobj);
54 	nvkm_wo32(&chan->base.base.gpuobj, 0x78, 0x02001ec1);
55 	nvkm_done(&chan->base.base.gpuobj);
56 	return 0;
57 }
58 
59 static int
60 nv44_mpeg_context_fini(struct nvkm_object *object, bool suspend)
61 {
62 
63 	struct nvkm_mpeg *mpeg = (void *)object->engine;
64 	struct nv44_mpeg_chan *chan = (void *)object;
65 	struct nvkm_device *device = mpeg->engine.subdev.device;
66 	u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
67 
68 	nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000000);
69 	if (nvkm_rd32(device, 0x00b318) == inst)
70 		nvkm_mask(device, 0x00b318, 0x80000000, 0x00000000);
71 	nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001);
72 	return 0;
73 }
74 
75 static struct nvkm_oclass
76 nv44_mpeg_cclass = {
77 	.handle = NV_ENGCTX(MPEG, 0x44),
78 	.ofuncs = &(struct nvkm_ofuncs) {
79 		.ctor = nv44_mpeg_context_ctor,
80 		.dtor = _nvkm_mpeg_context_dtor,
81 		.init = _nvkm_mpeg_context_init,
82 		.fini = nv44_mpeg_context_fini,
83 		.rd32 = _nvkm_mpeg_context_rd32,
84 		.wr32 = _nvkm_mpeg_context_wr32,
85 	},
86 };
87 
88 /*******************************************************************************
89  * PMPEG engine/subdev functions
90  ******************************************************************************/
91 
92 static void
93 nv44_mpeg_intr(struct nvkm_subdev *subdev)
94 {
95 	struct nvkm_mpeg *mpeg = (void *)subdev;
96 	struct nvkm_device *device = mpeg->engine.subdev.device;
97 	struct nvkm_fifo *fifo = device->fifo;
98 	struct nvkm_engine *engine = nv_engine(subdev);
99 	struct nvkm_object *engctx;
100 	struct nvkm_handle *handle;
101 	u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff;
102 	u32 stat = nvkm_rd32(device, 0x00b100);
103 	u32 type = nvkm_rd32(device, 0x00b230);
104 	u32 mthd = nvkm_rd32(device, 0x00b234);
105 	u32 data = nvkm_rd32(device, 0x00b238);
106 	u32 show = stat;
107 	int chid;
108 
109 	engctx = nvkm_engctx_get(engine, inst);
110 	chid   = fifo->chid(fifo, engctx);
111 
112 	if (stat & 0x01000000) {
113 		/* happens on initial binding of the object */
114 		if (type == 0x00000020 && mthd == 0x0000) {
115 			nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000);
116 			show &= ~0x01000000;
117 		}
118 
119 		if (type == 0x00000010) {
120 			handle = nvkm_handle_get_class(engctx, 0x3174);
121 			if (handle && !nv_call(handle->object, mthd, data))
122 				show &= ~0x01000000;
123 			nvkm_handle_put(handle);
124 		}
125 	}
126 
127 	nvkm_wr32(device, 0x00b100, stat);
128 	nvkm_wr32(device, 0x00b230, 0x00000001);
129 
130 	if (show) {
131 		nvkm_error(subdev,
132 			   "ch %d [%08x %s] %08x %08x %08x %08x\n",
133 			   chid, inst << 4, nvkm_client_name(engctx), stat,
134 			   type, mthd, data);
135 	}
136 
137 	nvkm_engctx_put(engctx);
138 }
139 
140 static void
141 nv44_mpeg_me_intr(struct nvkm_subdev *subdev)
142 {
143 	struct nvkm_mpeg *mpeg = (void *)subdev;
144 	struct nvkm_device *device = mpeg->engine.subdev.device;
145 	u32 stat;
146 
147 	if ((stat = nvkm_rd32(device, 0x00b100)))
148 		nv44_mpeg_intr(subdev);
149 
150 	if ((stat = nvkm_rd32(device, 0x00b800))) {
151 		nvkm_error(subdev, "PMSRCH %08x\n", stat);
152 		nvkm_wr32(device, 0x00b800, stat);
153 	}
154 }
155 
156 static int
157 nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
158 	       struct nvkm_oclass *oclass, void *data, u32 size,
159 	       struct nvkm_object **pobject)
160 {
161 	struct nvkm_mpeg *mpeg;
162 	int ret;
163 
164 	ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
165 	*pobject = nv_object(mpeg);
166 	if (ret)
167 		return ret;
168 
169 	nv_subdev(mpeg)->unit = 0x00000002;
170 	nv_subdev(mpeg)->intr = nv44_mpeg_me_intr;
171 	nv_engine(mpeg)->cclass = &nv44_mpeg_cclass;
172 	nv_engine(mpeg)->sclass = nv40_mpeg_sclass;
173 	nv_engine(mpeg)->tile_prog = nv31_mpeg_tile_prog;
174 	return 0;
175 }
176 
177 struct nvkm_oclass
178 nv44_mpeg_oclass = {
179 	.handle = NV_ENGINE(MPEG, 0x44),
180 	.ofuncs = &(struct nvkm_ofuncs) {
181 		.ctor = nv44_mpeg_ctor,
182 		.dtor = _nvkm_mpeg_dtor,
183 		.init = nv31_mpeg_init,
184 		.fini = _nvkm_mpeg_fini,
185 	},
186 };
187