1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv31.h" 25 26 #include <core/client.h> 27 #include <core/gpuobj.h> 28 #include <subdev/fb.h> 29 #include <subdev/timer.h> 30 #include <engine/fifo.h> 31 32 #include <nvif/class.h> 33 34 /******************************************************************************* 35 * MPEG object classes 36 ******************************************************************************/ 37 38 static int 39 nv31_mpeg_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, 40 int align, struct nvkm_gpuobj **pgpuobj) 41 { 42 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align, 43 false, parent, pgpuobj); 44 if (ret == 0) { 45 nvkm_kmap(*pgpuobj); 46 nvkm_wo32(*pgpuobj, 0x00, object->oclass); 47 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); 48 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); 49 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); 50 nvkm_done(*pgpuobj); 51 } 52 return ret; 53 } 54 55 const struct nvkm_object_func 56 nv31_mpeg_object = { 57 .bind = nv31_mpeg_object_bind, 58 }; 59 60 /******************************************************************************* 61 * PMPEG context 62 ******************************************************************************/ 63 64 static void * 65 nv31_mpeg_chan_dtor(struct nvkm_object *object) 66 { 67 struct nv31_mpeg_chan *chan = nv31_mpeg_chan(object); 68 struct nv31_mpeg *mpeg = chan->mpeg; 69 unsigned long flags; 70 71 spin_lock_irqsave(&mpeg->engine.lock, flags); 72 if (mpeg->chan == chan) 73 mpeg->chan = NULL; 74 spin_unlock_irqrestore(&mpeg->engine.lock, flags); 75 return chan; 76 } 77 78 static const struct nvkm_object_func 79 nv31_mpeg_chan = { 80 .dtor = nv31_mpeg_chan_dtor, 81 }; 82 83 int 84 nv31_mpeg_chan_new(struct nvkm_chan *fifoch, const struct nvkm_oclass *oclass, 85 struct nvkm_object **pobject) 86 { 87 struct nv31_mpeg *mpeg = nv31_mpeg(oclass->engine); 88 struct nv31_mpeg_chan *chan; 89 unsigned long flags; 90 int ret = -EBUSY; 91 92 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) 93 return -ENOMEM; 94 nvkm_object_ctor(&nv31_mpeg_chan, oclass, &chan->object); 95 chan->mpeg = mpeg; 96 chan->fifo = fifoch; 97 *pobject = &chan->object; 98 99 spin_lock_irqsave(&mpeg->engine.lock, flags); 100 if (!mpeg->chan) { 101 mpeg->chan = chan; 102 ret = 0; 103 } 104 spin_unlock_irqrestore(&mpeg->engine.lock, flags); 105 return ret; 106 } 107 108 /******************************************************************************* 109 * PMPEG engine/subdev functions 110 ******************************************************************************/ 111 112 void 113 nv31_mpeg_tile(struct nvkm_engine *engine, int i, struct nvkm_fb_tile *tile) 114 { 115 struct nv31_mpeg *mpeg = nv31_mpeg(engine); 116 struct nvkm_device *device = mpeg->engine.subdev.device; 117 118 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); 119 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); 120 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); 121 } 122 123 static bool 124 nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) 125 { 126 struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg); 127 struct nvkm_subdev *subdev = &mpeg->engine.subdev; 128 u32 inst = data << 4; 129 u32 dma0 = nvkm_rd32(device, 0x700000 + inst); 130 u32 dma1 = nvkm_rd32(device, 0x700004 + inst); 131 u32 dma2 = nvkm_rd32(device, 0x700008 + inst); 132 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); 133 u32 size = dma1 + 1; 134 135 /* only allow linear DMA objects */ 136 if (!(dma0 & 0x00002000)) { 137 nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n", 138 inst, dma0, dma1, dma2); 139 return false; 140 } 141 142 if (mthd == 0x0190) { 143 /* DMA_CMD */ 144 nvkm_mask(device, 0x00b300, 0x00010000, 145 (dma0 & 0x00030000) ? 0x00010000 : 0); 146 nvkm_wr32(device, 0x00b334, base); 147 nvkm_wr32(device, 0x00b324, size); 148 } else 149 if (mthd == 0x01a0) { 150 /* DMA_DATA */ 151 nvkm_mask(device, 0x00b300, 0x00020000, 152 (dma0 & 0x00030000) ? 0x00020000 : 0); 153 nvkm_wr32(device, 0x00b360, base); 154 nvkm_wr32(device, 0x00b364, size); 155 } else { 156 /* DMA_IMAGE, VRAM only */ 157 if (dma0 & 0x00030000) 158 return false; 159 160 nvkm_wr32(device, 0x00b370, base); 161 nvkm_wr32(device, 0x00b374, size); 162 } 163 164 return true; 165 } 166 167 static bool 168 nv31_mpeg_mthd(struct nv31_mpeg *mpeg, u32 mthd, u32 data) 169 { 170 struct nvkm_device *device = mpeg->engine.subdev.device; 171 switch (mthd) { 172 case 0x190: 173 case 0x1a0: 174 case 0x1b0: 175 return mpeg->func->mthd_dma(device, mthd, data); 176 default: 177 break; 178 } 179 return false; 180 } 181 182 static void 183 nv31_mpeg_intr(struct nvkm_engine *engine) 184 { 185 struct nv31_mpeg *mpeg = nv31_mpeg(engine); 186 struct nvkm_subdev *subdev = &mpeg->engine.subdev; 187 struct nvkm_device *device = subdev->device; 188 u32 stat = nvkm_rd32(device, 0x00b100); 189 u32 type = nvkm_rd32(device, 0x00b230); 190 u32 mthd = nvkm_rd32(device, 0x00b234); 191 u32 data = nvkm_rd32(device, 0x00b238); 192 u32 show = stat; 193 unsigned long flags; 194 195 spin_lock_irqsave(&mpeg->engine.lock, flags); 196 197 if (stat & 0x01000000) { 198 /* happens on initial binding of the object */ 199 if (type == 0x00000020 && mthd == 0x0000) { 200 nvkm_mask(device, 0x00b308, 0x00000000, 0x00000000); 201 show &= ~0x01000000; 202 } 203 204 if (type == 0x00000010) { 205 if (nv31_mpeg_mthd(mpeg, mthd, data)) 206 show &= ~0x01000000; 207 } 208 } 209 210 nvkm_wr32(device, 0x00b100, stat); 211 nvkm_wr32(device, 0x00b230, 0x00000001); 212 213 if (show) { 214 nvkm_error(subdev, "ch %d [%s] %08x %08x %08x %08x\n", 215 mpeg->chan ? mpeg->chan->fifo->id : -1, 216 mpeg->chan ? mpeg->chan->fifo->name : 217 "unknown", stat, type, mthd, data); 218 } 219 220 spin_unlock_irqrestore(&mpeg->engine.lock, flags); 221 } 222 223 int 224 nv31_mpeg_init(struct nvkm_engine *mpeg) 225 { 226 struct nvkm_subdev *subdev = &mpeg->subdev; 227 struct nvkm_device *device = subdev->device; 228 229 /* VPE init */ 230 nvkm_wr32(device, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ 231 nvkm_wr32(device, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ 232 233 /* PMPEG init */ 234 nvkm_wr32(device, 0x00b32c, 0x00000000); 235 nvkm_wr32(device, 0x00b314, 0x00000100); 236 nvkm_wr32(device, 0x00b220, 0x00000031); 237 nvkm_wr32(device, 0x00b300, 0x02001ec1); 238 nvkm_mask(device, 0x00b32c, 0x00000001, 0x00000001); 239 240 nvkm_wr32(device, 0x00b100, 0xffffffff); 241 nvkm_wr32(device, 0x00b140, 0xffffffff); 242 243 if (nvkm_msec(device, 2000, 244 if (!(nvkm_rd32(device, 0x00b200) & 0x00000001)) 245 break; 246 ) < 0) { 247 nvkm_error(subdev, "timeout %08x\n", 248 nvkm_rd32(device, 0x00b200)); 249 return -EBUSY; 250 } 251 252 return 0; 253 } 254 255 static void * 256 nv31_mpeg_dtor(struct nvkm_engine *engine) 257 { 258 return nv31_mpeg(engine); 259 } 260 261 static const struct nvkm_engine_func 262 nv31_mpeg_ = { 263 .dtor = nv31_mpeg_dtor, 264 .init = nv31_mpeg_init, 265 .intr = nv31_mpeg_intr, 266 .tile = nv31_mpeg_tile, 267 .fifo.cclass = nv31_mpeg_chan_new, 268 .sclass = { 269 { -1, -1, NV31_MPEG, &nv31_mpeg_object }, 270 {} 271 } 272 }; 273 274 int 275 nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device, 276 enum nvkm_subdev_type type, int inst, struct nvkm_engine **pmpeg) 277 { 278 struct nv31_mpeg *mpeg; 279 280 if (!(mpeg = kzalloc(sizeof(*mpeg), GFP_KERNEL))) 281 return -ENOMEM; 282 mpeg->func = func; 283 *pmpeg = &mpeg->engine; 284 285 return nvkm_engine_ctor(&nv31_mpeg_, device, type, inst, true, &mpeg->engine); 286 } 287 288 static const struct nv31_mpeg_func 289 nv31_mpeg = { 290 .mthd_dma = nv31_mpeg_mthd_dma, 291 }; 292 293 int 294 nv31_mpeg_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 295 struct nvkm_engine **pmpeg) 296 { 297 return nv31_mpeg_new_(&nv31_mpeg, device, type, inst, pmpeg); 298 } 299